1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_TPC4_RTR_REGS_H_ 14 #define ASIC_REG_TPC4_RTR_REGS_H_ 15 16 /* 17 ***************************************** 18 * TPC4_RTR (Prototype: TPC_RTR) 19 ***************************************** 20 */ 21 22 #define mmTPC4_RTR_HBW_RD_RQ_E_ARB 0xF00100 23 24 #define mmTPC4_RTR_HBW_RD_RQ_W_ARB 0xF00104 25 26 #define mmTPC4_RTR_HBW_RD_RQ_N_ARB 0xF00108 27 28 #define mmTPC4_RTR_HBW_RD_RQ_S_ARB 0xF0010C 29 30 #define mmTPC4_RTR_HBW_RD_RQ_L_ARB 0xF00110 31 32 #define mmTPC4_RTR_HBW_E_ARB_MAX 0xF00120 33 34 #define mmTPC4_RTR_HBW_W_ARB_MAX 0xF00124 35 36 #define mmTPC4_RTR_HBW_N_ARB_MAX 0xF00128 37 38 #define mmTPC4_RTR_HBW_S_ARB_MAX 0xF0012C 39 40 #define mmTPC4_RTR_HBW_L_ARB_MAX 0xF00130 41 42 #define mmTPC4_RTR_HBW_RD_RS_E_ARB 0xF00140 43 44 #define mmTPC4_RTR_HBW_RD_RS_W_ARB 0xF00144 45 46 #define mmTPC4_RTR_HBW_RD_RS_N_ARB 0xF00148 47 48 #define mmTPC4_RTR_HBW_RD_RS_S_ARB 0xF0014C 49 50 #define mmTPC4_RTR_HBW_RD_RS_L_ARB 0xF00150 51 52 #define mmTPC4_RTR_HBW_WR_RQ_E_ARB 0xF00170 53 54 #define mmTPC4_RTR_HBW_WR_RQ_W_ARB 0xF00174 55 56 #define mmTPC4_RTR_HBW_WR_RQ_N_ARB 0xF00178 57 58 #define mmTPC4_RTR_HBW_WR_RQ_S_ARB 0xF0017C 59 60 #define mmTPC4_RTR_HBW_WR_RQ_L_ARB 0xF00180 61 62 #define mmTPC4_RTR_HBW_WR_RS_E_ARB 0xF00190 63 64 #define mmTPC4_RTR_HBW_WR_RS_W_ARB 0xF00194 65 66 #define mmTPC4_RTR_HBW_WR_RS_N_ARB 0xF00198 67 68 #define mmTPC4_RTR_HBW_WR_RS_S_ARB 0xF0019C 69 70 #define mmTPC4_RTR_HBW_WR_RS_L_ARB 0xF001A0 71 72 #define mmTPC4_RTR_LBW_RD_RQ_E_ARB 0xF00200 73 74 #define mmTPC4_RTR_LBW_RD_RQ_W_ARB 0xF00204 75 76 #define mmTPC4_RTR_LBW_RD_RQ_N_ARB 0xF00208 77 78 #define mmTPC4_RTR_LBW_RD_RQ_S_ARB 0xF0020C 79 80 #define mmTPC4_RTR_LBW_RD_RQ_L_ARB 0xF00210 81 82 #define mmTPC4_RTR_LBW_E_ARB_MAX 0xF00220 83 84 #define mmTPC4_RTR_LBW_W_ARB_MAX 0xF00224 85 86 #define mmTPC4_RTR_LBW_N_ARB_MAX 0xF00228 87 88 #define mmTPC4_RTR_LBW_S_ARB_MAX 0xF0022C 89 90 #define mmTPC4_RTR_LBW_L_ARB_MAX 0xF00230 91 92 #define mmTPC4_RTR_LBW_RD_RS_E_ARB 0xF00250 93 94 #define mmTPC4_RTR_LBW_RD_RS_W_ARB 0xF00254 95 96 #define mmTPC4_RTR_LBW_RD_RS_N_ARB 0xF00258 97 98 #define mmTPC4_RTR_LBW_RD_RS_S_ARB 0xF0025C 99 100 #define mmTPC4_RTR_LBW_RD_RS_L_ARB 0xF00260 101 102 #define mmTPC4_RTR_LBW_WR_RQ_E_ARB 0xF00270 103 104 #define mmTPC4_RTR_LBW_WR_RQ_W_ARB 0xF00274 105 106 #define mmTPC4_RTR_LBW_WR_RQ_N_ARB 0xF00278 107 108 #define mmTPC4_RTR_LBW_WR_RQ_S_ARB 0xF0027C 109 110 #define mmTPC4_RTR_LBW_WR_RQ_L_ARB 0xF00280 111 112 #define mmTPC4_RTR_LBW_WR_RS_E_ARB 0xF00290 113 114 #define mmTPC4_RTR_LBW_WR_RS_W_ARB 0xF00294 115 116 #define mmTPC4_RTR_LBW_WR_RS_N_ARB 0xF00298 117 118 #define mmTPC4_RTR_LBW_WR_RS_S_ARB 0xF0029C 119 120 #define mmTPC4_RTR_LBW_WR_RS_L_ARB 0xF002A0 121 122 #define mmTPC4_RTR_DBG_E_ARB 0xF00300 123 124 #define mmTPC4_RTR_DBG_W_ARB 0xF00304 125 126 #define mmTPC4_RTR_DBG_N_ARB 0xF00308 127 128 #define mmTPC4_RTR_DBG_S_ARB 0xF0030C 129 130 #define mmTPC4_RTR_DBG_L_ARB 0xF00310 131 132 #define mmTPC4_RTR_DBG_E_ARB_MAX 0xF00320 133 134 #define mmTPC4_RTR_DBG_W_ARB_MAX 0xF00324 135 136 #define mmTPC4_RTR_DBG_N_ARB_MAX 0xF00328 137 138 #define mmTPC4_RTR_DBG_S_ARB_MAX 0xF0032C 139 140 #define mmTPC4_RTR_DBG_L_ARB_MAX 0xF00330 141 142 #define mmTPC4_RTR_SPLIT_COEF_0 0xF00400 143 144 #define mmTPC4_RTR_SPLIT_COEF_1 0xF00404 145 146 #define mmTPC4_RTR_SPLIT_COEF_2 0xF00408 147 148 #define mmTPC4_RTR_SPLIT_COEF_3 0xF0040C 149 150 #define mmTPC4_RTR_SPLIT_COEF_4 0xF00410 151 152 #define mmTPC4_RTR_SPLIT_COEF_5 0xF00414 153 154 #define mmTPC4_RTR_SPLIT_COEF_6 0xF00418 155 156 #define mmTPC4_RTR_SPLIT_COEF_7 0xF0041C 157 158 #define mmTPC4_RTR_SPLIT_COEF_8 0xF00420 159 160 #define mmTPC4_RTR_SPLIT_COEF_9 0xF00424 161 162 #define mmTPC4_RTR_SPLIT_CFG 0xF00440 163 164 #define mmTPC4_RTR_SPLIT_RD_SAT 0xF00444 165 166 #define mmTPC4_RTR_SPLIT_RD_RST_TOKEN 0xF00448 167 168 #define mmTPC4_RTR_SPLIT_RD_TIMEOUT_0 0xF0044C 169 170 #define mmTPC4_RTR_SPLIT_RD_TIMEOUT_1 0xF00450 171 172 #define mmTPC4_RTR_SPLIT_WR_SAT 0xF00454 173 174 #define mmTPC4_RTR_WPLIT_WR_TST_TOLEN 0xF00458 175 176 #define mmTPC4_RTR_SPLIT_WR_TIMEOUT_0 0xF0045C 177 178 #define mmTPC4_RTR_SPLIT_WR_TIMEOUT_1 0xF00460 179 180 #define mmTPC4_RTR_HBW_RANGE_HIT 0xF00470 181 182 #define mmTPC4_RTR_HBW_RANGE_MASK_L_0 0xF00480 183 184 #define mmTPC4_RTR_HBW_RANGE_MASK_L_1 0xF00484 185 186 #define mmTPC4_RTR_HBW_RANGE_MASK_L_2 0xF00488 187 188 #define mmTPC4_RTR_HBW_RANGE_MASK_L_3 0xF0048C 189 190 #define mmTPC4_RTR_HBW_RANGE_MASK_L_4 0xF00490 191 192 #define mmTPC4_RTR_HBW_RANGE_MASK_L_5 0xF00494 193 194 #define mmTPC4_RTR_HBW_RANGE_MASK_L_6 0xF00498 195 196 #define mmTPC4_RTR_HBW_RANGE_MASK_L_7 0xF0049C 197 198 #define mmTPC4_RTR_HBW_RANGE_MASK_H_0 0xF004A0 199 200 #define mmTPC4_RTR_HBW_RANGE_MASK_H_1 0xF004A4 201 202 #define mmTPC4_RTR_HBW_RANGE_MASK_H_2 0xF004A8 203 204 #define mmTPC4_RTR_HBW_RANGE_MASK_H_3 0xF004AC 205 206 #define mmTPC4_RTR_HBW_RANGE_MASK_H_4 0xF004B0 207 208 #define mmTPC4_RTR_HBW_RANGE_MASK_H_5 0xF004B4 209 210 #define mmTPC4_RTR_HBW_RANGE_MASK_H_6 0xF004B8 211 212 #define mmTPC4_RTR_HBW_RANGE_MASK_H_7 0xF004BC 213 214 #define mmTPC4_RTR_HBW_RANGE_BASE_L_0 0xF004C0 215 216 #define mmTPC4_RTR_HBW_RANGE_BASE_L_1 0xF004C4 217 218 #define mmTPC4_RTR_HBW_RANGE_BASE_L_2 0xF004C8 219 220 #define mmTPC4_RTR_HBW_RANGE_BASE_L_3 0xF004CC 221 222 #define mmTPC4_RTR_HBW_RANGE_BASE_L_4 0xF004D0 223 224 #define mmTPC4_RTR_HBW_RANGE_BASE_L_5 0xF004D4 225 226 #define mmTPC4_RTR_HBW_RANGE_BASE_L_6 0xF004D8 227 228 #define mmTPC4_RTR_HBW_RANGE_BASE_L_7 0xF004DC 229 230 #define mmTPC4_RTR_HBW_RANGE_BASE_H_0 0xF004E0 231 232 #define mmTPC4_RTR_HBW_RANGE_BASE_H_1 0xF004E4 233 234 #define mmTPC4_RTR_HBW_RANGE_BASE_H_2 0xF004E8 235 236 #define mmTPC4_RTR_HBW_RANGE_BASE_H_3 0xF004EC 237 238 #define mmTPC4_RTR_HBW_RANGE_BASE_H_4 0xF004F0 239 240 #define mmTPC4_RTR_HBW_RANGE_BASE_H_5 0xF004F4 241 242 #define mmTPC4_RTR_HBW_RANGE_BASE_H_6 0xF004F8 243 244 #define mmTPC4_RTR_HBW_RANGE_BASE_H_7 0xF004FC 245 246 #define mmTPC4_RTR_LBW_RANGE_HIT 0xF00500 247 248 #define mmTPC4_RTR_LBW_RANGE_MASK_0 0xF00510 249 250 #define mmTPC4_RTR_LBW_RANGE_MASK_1 0xF00514 251 252 #define mmTPC4_RTR_LBW_RANGE_MASK_2 0xF00518 253 254 #define mmTPC4_RTR_LBW_RANGE_MASK_3 0xF0051C 255 256 #define mmTPC4_RTR_LBW_RANGE_MASK_4 0xF00520 257 258 #define mmTPC4_RTR_LBW_RANGE_MASK_5 0xF00524 259 260 #define mmTPC4_RTR_LBW_RANGE_MASK_6 0xF00528 261 262 #define mmTPC4_RTR_LBW_RANGE_MASK_7 0xF0052C 263 264 #define mmTPC4_RTR_LBW_RANGE_MASK_8 0xF00530 265 266 #define mmTPC4_RTR_LBW_RANGE_MASK_9 0xF00534 267 268 #define mmTPC4_RTR_LBW_RANGE_MASK_10 0xF00538 269 270 #define mmTPC4_RTR_LBW_RANGE_MASK_11 0xF0053C 271 272 #define mmTPC4_RTR_LBW_RANGE_MASK_12 0xF00540 273 274 #define mmTPC4_RTR_LBW_RANGE_MASK_13 0xF00544 275 276 #define mmTPC4_RTR_LBW_RANGE_MASK_14 0xF00548 277 278 #define mmTPC4_RTR_LBW_RANGE_MASK_15 0xF0054C 279 280 #define mmTPC4_RTR_LBW_RANGE_BASE_0 0xF00550 281 282 #define mmTPC4_RTR_LBW_RANGE_BASE_1 0xF00554 283 284 #define mmTPC4_RTR_LBW_RANGE_BASE_2 0xF00558 285 286 #define mmTPC4_RTR_LBW_RANGE_BASE_3 0xF0055C 287 288 #define mmTPC4_RTR_LBW_RANGE_BASE_4 0xF00560 289 290 #define mmTPC4_RTR_LBW_RANGE_BASE_5 0xF00564 291 292 #define mmTPC4_RTR_LBW_RANGE_BASE_6 0xF00568 293 294 #define mmTPC4_RTR_LBW_RANGE_BASE_7 0xF0056C 295 296 #define mmTPC4_RTR_LBW_RANGE_BASE_8 0xF00570 297 298 #define mmTPC4_RTR_LBW_RANGE_BASE_9 0xF00574 299 300 #define mmTPC4_RTR_LBW_RANGE_BASE_10 0xF00578 301 302 #define mmTPC4_RTR_LBW_RANGE_BASE_11 0xF0057C 303 304 #define mmTPC4_RTR_LBW_RANGE_BASE_12 0xF00580 305 306 #define mmTPC4_RTR_LBW_RANGE_BASE_13 0xF00584 307 308 #define mmTPC4_RTR_LBW_RANGE_BASE_14 0xF00588 309 310 #define mmTPC4_RTR_LBW_RANGE_BASE_15 0xF0058C 311 312 #define mmTPC4_RTR_RGLTR 0xF00590 313 314 #define mmTPC4_RTR_RGLTR_WR_RESULT 0xF00594 315 316 #define mmTPC4_RTR_RGLTR_RD_RESULT 0xF00598 317 318 #define mmTPC4_RTR_SCRAMB_EN 0xF00600 319 320 #define mmTPC4_RTR_NON_LIN_SCRAMB 0xF00604 321 322 #endif /* ASIC_REG_TPC4_RTR_REGS_H_ */ 323