xref: /linux/drivers/accel/habanalabs/include/goya/asic_reg/tpc2_cmdq_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_TPC2_CMDQ_REGS_H_
14 #define ASIC_REG_TPC2_CMDQ_REGS_H_
15 
16 /*
17  *****************************************
18  *   TPC2_CMDQ (Prototype: CMDQ)
19  *****************************************
20  */
21 
22 #define mmTPC2_CMDQ_GLBL_CFG0                                        0xE89000
23 
24 #define mmTPC2_CMDQ_GLBL_CFG1                                        0xE89004
25 
26 #define mmTPC2_CMDQ_GLBL_PROT                                        0xE89008
27 
28 #define mmTPC2_CMDQ_GLBL_ERR_CFG                                     0xE8900C
29 
30 #define mmTPC2_CMDQ_GLBL_ERR_ADDR_LO                                 0xE89010
31 
32 #define mmTPC2_CMDQ_GLBL_ERR_ADDR_HI                                 0xE89014
33 
34 #define mmTPC2_CMDQ_GLBL_ERR_WDATA                                   0xE89018
35 
36 #define mmTPC2_CMDQ_GLBL_SECURE_PROPS                                0xE8901C
37 
38 #define mmTPC2_CMDQ_GLBL_NON_SECURE_PROPS                            0xE89020
39 
40 #define mmTPC2_CMDQ_GLBL_STS0                                        0xE89024
41 
42 #define mmTPC2_CMDQ_GLBL_STS1                                        0xE89028
43 
44 #define mmTPC2_CMDQ_CQ_CFG0                                          0xE890B0
45 
46 #define mmTPC2_CMDQ_CQ_CFG1                                          0xE890B4
47 
48 #define mmTPC2_CMDQ_CQ_ARUSER                                        0xE890B8
49 
50 #define mmTPC2_CMDQ_CQ_PTR_LO                                        0xE890C0
51 
52 #define mmTPC2_CMDQ_CQ_PTR_HI                                        0xE890C4
53 
54 #define mmTPC2_CMDQ_CQ_TSIZE                                         0xE890C8
55 
56 #define mmTPC2_CMDQ_CQ_CTL                                           0xE890CC
57 
58 #define mmTPC2_CMDQ_CQ_PTR_LO_STS                                    0xE890D4
59 
60 #define mmTPC2_CMDQ_CQ_PTR_HI_STS                                    0xE890D8
61 
62 #define mmTPC2_CMDQ_CQ_TSIZE_STS                                     0xE890DC
63 
64 #define mmTPC2_CMDQ_CQ_CTL_STS                                       0xE890E0
65 
66 #define mmTPC2_CMDQ_CQ_STS0                                          0xE890E4
67 
68 #define mmTPC2_CMDQ_CQ_STS1                                          0xE890E8
69 
70 #define mmTPC2_CMDQ_CQ_RD_RATE_LIM_EN                                0xE890F0
71 
72 #define mmTPC2_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN                         0xE890F4
73 
74 #define mmTPC2_CMDQ_CQ_RD_RATE_LIM_SAT                               0xE890F8
75 
76 #define mmTPC2_CMDQ_CQ_RD_RATE_LIM_TOUT                              0xE890FC
77 
78 #define mmTPC2_CMDQ_CQ_IFIFO_CNT                                     0xE89108
79 
80 #define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_LO                             0xE89120
81 
82 #define mmTPC2_CMDQ_CP_MSG_BASE0_ADDR_HI                             0xE89124
83 
84 #define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_LO                             0xE89128
85 
86 #define mmTPC2_CMDQ_CP_MSG_BASE1_ADDR_HI                             0xE8912C
87 
88 #define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_LO                             0xE89130
89 
90 #define mmTPC2_CMDQ_CP_MSG_BASE2_ADDR_HI                             0xE89134
91 
92 #define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_LO                             0xE89138
93 
94 #define mmTPC2_CMDQ_CP_MSG_BASE3_ADDR_HI                             0xE8913C
95 
96 #define mmTPC2_CMDQ_CP_LDMA_TSIZE_OFFSET                             0xE89140
97 
98 #define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET                       0xE89144
99 
100 #define mmTPC2_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET                       0xE89148
101 
102 #define mmTPC2_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET                       0xE8914C
103 
104 #define mmTPC2_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET                       0xE89150
105 
106 #define mmTPC2_CMDQ_CP_LDMA_COMMIT_OFFSET                            0xE89154
107 
108 #define mmTPC2_CMDQ_CP_FENCE0_RDATA                                  0xE89158
109 
110 #define mmTPC2_CMDQ_CP_FENCE1_RDATA                                  0xE8915C
111 
112 #define mmTPC2_CMDQ_CP_FENCE2_RDATA                                  0xE89160
113 
114 #define mmTPC2_CMDQ_CP_FENCE3_RDATA                                  0xE89164
115 
116 #define mmTPC2_CMDQ_CP_FENCE0_CNT                                    0xE89168
117 
118 #define mmTPC2_CMDQ_CP_FENCE1_CNT                                    0xE8916C
119 
120 #define mmTPC2_CMDQ_CP_FENCE2_CNT                                    0xE89170
121 
122 #define mmTPC2_CMDQ_CP_FENCE3_CNT                                    0xE89174
123 
124 #define mmTPC2_CMDQ_CP_STS                                           0xE89178
125 
126 #define mmTPC2_CMDQ_CP_CURRENT_INST_LO                               0xE8917C
127 
128 #define mmTPC2_CMDQ_CP_CURRENT_INST_HI                               0xE89180
129 
130 #define mmTPC2_CMDQ_CP_BARRIER_CFG                                   0xE89184
131 
132 #define mmTPC2_CMDQ_CP_DBG_0                                         0xE89188
133 
134 #define mmTPC2_CMDQ_CQ_BUF_ADDR                                      0xE89308
135 
136 #define mmTPC2_CMDQ_CQ_BUF_RDATA                                     0xE8930C
137 
138 #endif /* ASIC_REG_TPC2_CMDQ_REGS_H_ */
139