xref: /linux/drivers/accel/habanalabs/include/goya/asic_reg/tpc0_nrtr_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2018 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_TPC0_NRTR_REGS_H_
14 #define ASIC_REG_TPC0_NRTR_REGS_H_
15 
16 /*
17  *****************************************
18  *   TPC0_NRTR (Prototype: IF_NRTR)
19  *****************************************
20  */
21 
22 #define mmTPC0_NRTR_HBW_MAX_CRED                                     0xE00100
23 
24 #define mmTPC0_NRTR_LBW_MAX_CRED                                     0xE00120
25 
26 #define mmTPC0_NRTR_DBG_E_ARB                                        0xE00300
27 
28 #define mmTPC0_NRTR_DBG_W_ARB                                        0xE00304
29 
30 #define mmTPC0_NRTR_DBG_N_ARB                                        0xE00308
31 
32 #define mmTPC0_NRTR_DBG_S_ARB                                        0xE0030C
33 
34 #define mmTPC0_NRTR_DBG_L_ARB                                        0xE00310
35 
36 #define mmTPC0_NRTR_DBG_E_ARB_MAX                                    0xE00320
37 
38 #define mmTPC0_NRTR_DBG_W_ARB_MAX                                    0xE00324
39 
40 #define mmTPC0_NRTR_DBG_N_ARB_MAX                                    0xE00328
41 
42 #define mmTPC0_NRTR_DBG_S_ARB_MAX                                    0xE0032C
43 
44 #define mmTPC0_NRTR_DBG_L_ARB_MAX                                    0xE00330
45 
46 #define mmTPC0_NRTR_SPLIT_COEF_0                                     0xE00400
47 
48 #define mmTPC0_NRTR_SPLIT_COEF_1                                     0xE00404
49 
50 #define mmTPC0_NRTR_SPLIT_COEF_2                                     0xE00408
51 
52 #define mmTPC0_NRTR_SPLIT_COEF_3                                     0xE0040C
53 
54 #define mmTPC0_NRTR_SPLIT_COEF_4                                     0xE00410
55 
56 #define mmTPC0_NRTR_SPLIT_COEF_5                                     0xE00414
57 
58 #define mmTPC0_NRTR_SPLIT_COEF_6                                     0xE00418
59 
60 #define mmTPC0_NRTR_SPLIT_COEF_7                                     0xE0041C
61 
62 #define mmTPC0_NRTR_SPLIT_COEF_8                                     0xE00420
63 
64 #define mmTPC0_NRTR_SPLIT_COEF_9                                     0xE00424
65 
66 #define mmTPC0_NRTR_SPLIT_CFG                                        0xE00440
67 
68 #define mmTPC0_NRTR_SPLIT_RD_SAT                                     0xE00444
69 
70 #define mmTPC0_NRTR_SPLIT_RD_RST_TOKEN                               0xE00448
71 
72 #define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_0                               0xE0044C
73 
74 #define mmTPC0_NRTR_SPLIT_RD_TIMEOUT_1                               0xE00450
75 
76 #define mmTPC0_NRTR_SPLIT_WR_SAT                                     0xE00454
77 
78 #define mmTPC0_NRTR_WPLIT_WR_TST_TOLEN                               0xE00458
79 
80 #define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_0                               0xE0045C
81 
82 #define mmTPC0_NRTR_SPLIT_WR_TIMEOUT_1                               0xE00460
83 
84 #define mmTPC0_NRTR_HBW_RANGE_HIT                                    0xE00470
85 
86 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_0                               0xE00480
87 
88 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_1                               0xE00484
89 
90 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_2                               0xE00488
91 
92 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_3                               0xE0048C
93 
94 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_4                               0xE00490
95 
96 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_5                               0xE00494
97 
98 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_6                               0xE00498
99 
100 #define mmTPC0_NRTR_HBW_RANGE_MASK_L_7                               0xE0049C
101 
102 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_0                               0xE004A0
103 
104 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_1                               0xE004A4
105 
106 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_2                               0xE004A8
107 
108 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_3                               0xE004AC
109 
110 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_4                               0xE004B0
111 
112 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_5                               0xE004B4
113 
114 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_6                               0xE004B8
115 
116 #define mmTPC0_NRTR_HBW_RANGE_MASK_H_7                               0xE004BC
117 
118 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_0                               0xE004C0
119 
120 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_1                               0xE004C4
121 
122 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_2                               0xE004C8
123 
124 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_3                               0xE004CC
125 
126 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_4                               0xE004D0
127 
128 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_5                               0xE004D4
129 
130 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_6                               0xE004D8
131 
132 #define mmTPC0_NRTR_HBW_RANGE_BASE_L_7                               0xE004DC
133 
134 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_0                               0xE004E0
135 
136 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_1                               0xE004E4
137 
138 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_2                               0xE004E8
139 
140 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_3                               0xE004EC
141 
142 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_4                               0xE004F0
143 
144 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_5                               0xE004F4
145 
146 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_6                               0xE004F8
147 
148 #define mmTPC0_NRTR_HBW_RANGE_BASE_H_7                               0xE004FC
149 
150 #define mmTPC0_NRTR_LBW_RANGE_HIT                                    0xE00500
151 
152 #define mmTPC0_NRTR_LBW_RANGE_MASK_0                                 0xE00510
153 
154 #define mmTPC0_NRTR_LBW_RANGE_MASK_1                                 0xE00514
155 
156 #define mmTPC0_NRTR_LBW_RANGE_MASK_2                                 0xE00518
157 
158 #define mmTPC0_NRTR_LBW_RANGE_MASK_3                                 0xE0051C
159 
160 #define mmTPC0_NRTR_LBW_RANGE_MASK_4                                 0xE00520
161 
162 #define mmTPC0_NRTR_LBW_RANGE_MASK_5                                 0xE00524
163 
164 #define mmTPC0_NRTR_LBW_RANGE_MASK_6                                 0xE00528
165 
166 #define mmTPC0_NRTR_LBW_RANGE_MASK_7                                 0xE0052C
167 
168 #define mmTPC0_NRTR_LBW_RANGE_MASK_8                                 0xE00530
169 
170 #define mmTPC0_NRTR_LBW_RANGE_MASK_9                                 0xE00534
171 
172 #define mmTPC0_NRTR_LBW_RANGE_MASK_10                                0xE00538
173 
174 #define mmTPC0_NRTR_LBW_RANGE_MASK_11                                0xE0053C
175 
176 #define mmTPC0_NRTR_LBW_RANGE_MASK_12                                0xE00540
177 
178 #define mmTPC0_NRTR_LBW_RANGE_MASK_13                                0xE00544
179 
180 #define mmTPC0_NRTR_LBW_RANGE_MASK_14                                0xE00548
181 
182 #define mmTPC0_NRTR_LBW_RANGE_MASK_15                                0xE0054C
183 
184 #define mmTPC0_NRTR_LBW_RANGE_BASE_0                                 0xE00550
185 
186 #define mmTPC0_NRTR_LBW_RANGE_BASE_1                                 0xE00554
187 
188 #define mmTPC0_NRTR_LBW_RANGE_BASE_2                                 0xE00558
189 
190 #define mmTPC0_NRTR_LBW_RANGE_BASE_3                                 0xE0055C
191 
192 #define mmTPC0_NRTR_LBW_RANGE_BASE_4                                 0xE00560
193 
194 #define mmTPC0_NRTR_LBW_RANGE_BASE_5                                 0xE00564
195 
196 #define mmTPC0_NRTR_LBW_RANGE_BASE_6                                 0xE00568
197 
198 #define mmTPC0_NRTR_LBW_RANGE_BASE_7                                 0xE0056C
199 
200 #define mmTPC0_NRTR_LBW_RANGE_BASE_8                                 0xE00570
201 
202 #define mmTPC0_NRTR_LBW_RANGE_BASE_9                                 0xE00574
203 
204 #define mmTPC0_NRTR_LBW_RANGE_BASE_10                                0xE00578
205 
206 #define mmTPC0_NRTR_LBW_RANGE_BASE_11                                0xE0057C
207 
208 #define mmTPC0_NRTR_LBW_RANGE_BASE_12                                0xE00580
209 
210 #define mmTPC0_NRTR_LBW_RANGE_BASE_13                                0xE00584
211 
212 #define mmTPC0_NRTR_LBW_RANGE_BASE_14                                0xE00588
213 
214 #define mmTPC0_NRTR_LBW_RANGE_BASE_15                                0xE0058C
215 
216 #define mmTPC0_NRTR_RGLTR                                            0xE00590
217 
218 #define mmTPC0_NRTR_RGLTR_WR_RESULT                                  0xE00594
219 
220 #define mmTPC0_NRTR_RGLTR_RD_RESULT                                  0xE00598
221 
222 #define mmTPC0_NRTR_SCRAMB_EN                                        0xE00600
223 
224 #define mmTPC0_NRTR_NON_LIN_SCRAMB                                   0xE00604
225 
226 #endif /* ASIC_REG_TPC0_NRTR_REGS_H_ */
227