1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PDMA0_QM_REGS_H_ 14 #define ASIC_REG_PDMA0_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * PDMA0_QM 19 * (Prototype: QMAN) 20 ***************************************** 21 */ 22 23 #define mmPDMA0_QM_GLBL_CFG0 0x4C8A000 24 25 #define mmPDMA0_QM_GLBL_CFG1 0x4C8A004 26 27 #define mmPDMA0_QM_GLBL_CFG2 0x4C8A008 28 29 #define mmPDMA0_QM_GLBL_ERR_CFG 0x4C8A00C 30 31 #define mmPDMA0_QM_GLBL_ERR_CFG1 0x4C8A010 32 33 #define mmPDMA0_QM_GLBL_ERR_ARC_HALT_EN 0x4C8A014 34 35 #define mmPDMA0_QM_GLBL_AXCACHE 0x4C8A018 36 37 #define mmPDMA0_QM_GLBL_STS0 0x4C8A01C 38 39 #define mmPDMA0_QM_GLBL_STS1 0x4C8A020 40 41 #define mmPDMA0_QM_GLBL_ERR_STS_0 0x4C8A024 42 43 #define mmPDMA0_QM_GLBL_ERR_STS_1 0x4C8A028 44 45 #define mmPDMA0_QM_GLBL_ERR_STS_2 0x4C8A02C 46 47 #define mmPDMA0_QM_GLBL_ERR_STS_3 0x4C8A030 48 49 #define mmPDMA0_QM_GLBL_ERR_STS_4 0x4C8A034 50 51 #define mmPDMA0_QM_GLBL_ERR_MSG_EN_0 0x4C8A038 52 53 #define mmPDMA0_QM_GLBL_ERR_MSG_EN_1 0x4C8A03C 54 55 #define mmPDMA0_QM_GLBL_ERR_MSG_EN_2 0x4C8A040 56 57 #define mmPDMA0_QM_GLBL_ERR_MSG_EN_3 0x4C8A044 58 59 #define mmPDMA0_QM_GLBL_ERR_MSG_EN_4 0x4C8A048 60 61 #define mmPDMA0_QM_GLBL_PROT 0x4C8A04C 62 63 #define mmPDMA0_QM_PQ_BASE_LO_0 0x4C8A050 64 65 #define mmPDMA0_QM_PQ_BASE_LO_1 0x4C8A054 66 67 #define mmPDMA0_QM_PQ_BASE_LO_2 0x4C8A058 68 69 #define mmPDMA0_QM_PQ_BASE_LO_3 0x4C8A05C 70 71 #define mmPDMA0_QM_PQ_BASE_HI_0 0x4C8A060 72 73 #define mmPDMA0_QM_PQ_BASE_HI_1 0x4C8A064 74 75 #define mmPDMA0_QM_PQ_BASE_HI_2 0x4C8A068 76 77 #define mmPDMA0_QM_PQ_BASE_HI_3 0x4C8A06C 78 79 #define mmPDMA0_QM_PQ_SIZE_0 0x4C8A070 80 81 #define mmPDMA0_QM_PQ_SIZE_1 0x4C8A074 82 83 #define mmPDMA0_QM_PQ_SIZE_2 0x4C8A078 84 85 #define mmPDMA0_QM_PQ_SIZE_3 0x4C8A07C 86 87 #define mmPDMA0_QM_PQ_PI_0 0x4C8A080 88 89 #define mmPDMA0_QM_PQ_PI_1 0x4C8A084 90 91 #define mmPDMA0_QM_PQ_PI_2 0x4C8A088 92 93 #define mmPDMA0_QM_PQ_PI_3 0x4C8A08C 94 95 #define mmPDMA0_QM_PQ_CI_0 0x4C8A090 96 97 #define mmPDMA0_QM_PQ_CI_1 0x4C8A094 98 99 #define mmPDMA0_QM_PQ_CI_2 0x4C8A098 100 101 #define mmPDMA0_QM_PQ_CI_3 0x4C8A09C 102 103 #define mmPDMA0_QM_PQ_CFG0_0 0x4C8A0A0 104 105 #define mmPDMA0_QM_PQ_CFG0_1 0x4C8A0A4 106 107 #define mmPDMA0_QM_PQ_CFG0_2 0x4C8A0A8 108 109 #define mmPDMA0_QM_PQ_CFG0_3 0x4C8A0AC 110 111 #define mmPDMA0_QM_PQ_CFG1_0 0x4C8A0B0 112 113 #define mmPDMA0_QM_PQ_CFG1_1 0x4C8A0B4 114 115 #define mmPDMA0_QM_PQ_CFG1_2 0x4C8A0B8 116 117 #define mmPDMA0_QM_PQ_CFG1_3 0x4C8A0BC 118 119 #define mmPDMA0_QM_PQ_STS0_0 0x4C8A0C0 120 121 #define mmPDMA0_QM_PQ_STS0_1 0x4C8A0C4 122 123 #define mmPDMA0_QM_PQ_STS0_2 0x4C8A0C8 124 125 #define mmPDMA0_QM_PQ_STS0_3 0x4C8A0CC 126 127 #define mmPDMA0_QM_PQ_STS1_0 0x4C8A0D0 128 129 #define mmPDMA0_QM_PQ_STS1_1 0x4C8A0D4 130 131 #define mmPDMA0_QM_PQ_STS1_2 0x4C8A0D8 132 133 #define mmPDMA0_QM_PQ_STS1_3 0x4C8A0DC 134 135 #define mmPDMA0_QM_CQ_CFG0_0 0x4C8A0E0 136 137 #define mmPDMA0_QM_CQ_CFG0_1 0x4C8A0E4 138 139 #define mmPDMA0_QM_CQ_CFG0_2 0x4C8A0E8 140 141 #define mmPDMA0_QM_CQ_CFG0_3 0x4C8A0EC 142 143 #define mmPDMA0_QM_CQ_CFG0_4 0x4C8A0F0 144 145 #define mmPDMA0_QM_CQ_STS0_0 0x4C8A0F4 146 147 #define mmPDMA0_QM_CQ_STS0_1 0x4C8A0F8 148 149 #define mmPDMA0_QM_CQ_STS0_2 0x4C8A0FC 150 151 #define mmPDMA0_QM_CQ_STS0_3 0x4C8A100 152 153 #define mmPDMA0_QM_CQ_STS0_4 0x4C8A104 154 155 #define mmPDMA0_QM_CQ_CFG1_0 0x4C8A108 156 157 #define mmPDMA0_QM_CQ_CFG1_1 0x4C8A10C 158 159 #define mmPDMA0_QM_CQ_CFG1_2 0x4C8A110 160 161 #define mmPDMA0_QM_CQ_CFG1_3 0x4C8A114 162 163 #define mmPDMA0_QM_CQ_CFG1_4 0x4C8A118 164 165 #define mmPDMA0_QM_CQ_STS1_0 0x4C8A11C 166 167 #define mmPDMA0_QM_CQ_STS1_1 0x4C8A120 168 169 #define mmPDMA0_QM_CQ_STS1_2 0x4C8A124 170 171 #define mmPDMA0_QM_CQ_STS1_3 0x4C8A128 172 173 #define mmPDMA0_QM_CQ_STS1_4 0x4C8A12C 174 175 #define mmPDMA0_QM_CQ_PTR_LO_0 0x4C8A150 176 177 #define mmPDMA0_QM_CQ_PTR_HI_0 0x4C8A154 178 179 #define mmPDMA0_QM_CQ_TSIZE_0 0x4C8A158 180 181 #define mmPDMA0_QM_CQ_CTL_0 0x4C8A15C 182 183 #define mmPDMA0_QM_CQ_PTR_LO_1 0x4C8A160 184 185 #define mmPDMA0_QM_CQ_PTR_HI_1 0x4C8A164 186 187 #define mmPDMA0_QM_CQ_TSIZE_1 0x4C8A168 188 189 #define mmPDMA0_QM_CQ_CTL_1 0x4C8A16C 190 191 #define mmPDMA0_QM_CQ_PTR_LO_2 0x4C8A170 192 193 #define mmPDMA0_QM_CQ_PTR_HI_2 0x4C8A174 194 195 #define mmPDMA0_QM_CQ_TSIZE_2 0x4C8A178 196 197 #define mmPDMA0_QM_CQ_CTL_2 0x4C8A17C 198 199 #define mmPDMA0_QM_CQ_PTR_LO_3 0x4C8A180 200 201 #define mmPDMA0_QM_CQ_PTR_HI_3 0x4C8A184 202 203 #define mmPDMA0_QM_CQ_TSIZE_3 0x4C8A188 204 205 #define mmPDMA0_QM_CQ_CTL_3 0x4C8A18C 206 207 #define mmPDMA0_QM_CQ_PTR_LO_4 0x4C8A190 208 209 #define mmPDMA0_QM_CQ_PTR_HI_4 0x4C8A194 210 211 #define mmPDMA0_QM_CQ_TSIZE_4 0x4C8A198 212 213 #define mmPDMA0_QM_CQ_CTL_4 0x4C8A19C 214 215 #define mmPDMA0_QM_CQ_TSIZE_STS_0 0x4C8A1A0 216 217 #define mmPDMA0_QM_CQ_TSIZE_STS_1 0x4C8A1A4 218 219 #define mmPDMA0_QM_CQ_TSIZE_STS_2 0x4C8A1A8 220 221 #define mmPDMA0_QM_CQ_TSIZE_STS_3 0x4C8A1AC 222 223 #define mmPDMA0_QM_CQ_TSIZE_STS_4 0x4C8A1B0 224 225 #define mmPDMA0_QM_CQ_PTR_LO_STS_0 0x4C8A1B4 226 227 #define mmPDMA0_QM_CQ_PTR_LO_STS_1 0x4C8A1B8 228 229 #define mmPDMA0_QM_CQ_PTR_LO_STS_2 0x4C8A1BC 230 231 #define mmPDMA0_QM_CQ_PTR_LO_STS_3 0x4C8A1C0 232 233 #define mmPDMA0_QM_CQ_PTR_LO_STS_4 0x4C8A1C4 234 235 #define mmPDMA0_QM_CQ_PTR_HI_STS_0 0x4C8A1C8 236 237 #define mmPDMA0_QM_CQ_PTR_HI_STS_1 0x4C8A1CC 238 239 #define mmPDMA0_QM_CQ_PTR_HI_STS_2 0x4C8A1D0 240 241 #define mmPDMA0_QM_CQ_PTR_HI_STS_3 0x4C8A1D4 242 243 #define mmPDMA0_QM_CQ_PTR_HI_STS_4 0x4C8A1D8 244 245 #define mmPDMA0_QM_CQ_IFIFO_STS_0 0x4C8A1DC 246 247 #define mmPDMA0_QM_CQ_IFIFO_STS_1 0x4C8A1E0 248 249 #define mmPDMA0_QM_CQ_IFIFO_STS_2 0x4C8A1E4 250 251 #define mmPDMA0_QM_CQ_IFIFO_STS_3 0x4C8A1E8 252 253 #define mmPDMA0_QM_CQ_IFIFO_STS_4 0x4C8A1EC 254 255 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 0x4C8A1F0 256 257 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1 0x4C8A1F4 258 259 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2 0x4C8A1F8 260 261 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3 0x4C8A1FC 262 263 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4 0x4C8A200 264 265 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 0x4C8A204 266 267 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1 0x4C8A208 268 269 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2 0x4C8A20C 270 271 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3 0x4C8A210 272 273 #define mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4 0x4C8A214 274 275 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 0x4C8A218 276 277 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1 0x4C8A21C 278 279 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2 0x4C8A220 280 281 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3 0x4C8A224 282 283 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4 0x4C8A228 284 285 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 0x4C8A22C 286 287 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1 0x4C8A230 288 289 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2 0x4C8A234 290 291 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3 0x4C8A238 292 293 #define mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4 0x4C8A23C 294 295 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0 0x4C8A240 296 297 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1 0x4C8A244 298 299 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2 0x4C8A248 300 301 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3 0x4C8A24C 302 303 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4 0x4C8A250 304 305 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0 0x4C8A254 306 307 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1 0x4C8A258 308 309 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2 0x4C8A25C 310 311 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3 0x4C8A260 312 313 #define mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4 0x4C8A264 314 315 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0 0x4C8A268 316 317 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1 0x4C8A26C 318 319 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2 0x4C8A270 320 321 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3 0x4C8A274 322 323 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4 0x4C8A278 324 325 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0 0x4C8A27C 326 327 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1 0x4C8A280 328 329 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2 0x4C8A284 330 331 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3 0x4C8A288 332 333 #define mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4 0x4C8A28C 334 335 #define mmPDMA0_QM_CP_FENCE0_RDATA_0 0x4C8A290 336 337 #define mmPDMA0_QM_CP_FENCE0_RDATA_1 0x4C8A294 338 339 #define mmPDMA0_QM_CP_FENCE0_RDATA_2 0x4C8A298 340 341 #define mmPDMA0_QM_CP_FENCE0_RDATA_3 0x4C8A29C 342 343 #define mmPDMA0_QM_CP_FENCE0_RDATA_4 0x4C8A2A0 344 345 #define mmPDMA0_QM_CP_FENCE1_RDATA_0 0x4C8A2A4 346 347 #define mmPDMA0_QM_CP_FENCE1_RDATA_1 0x4C8A2A8 348 349 #define mmPDMA0_QM_CP_FENCE1_RDATA_2 0x4C8A2AC 350 351 #define mmPDMA0_QM_CP_FENCE1_RDATA_3 0x4C8A2B0 352 353 #define mmPDMA0_QM_CP_FENCE1_RDATA_4 0x4C8A2B4 354 355 #define mmPDMA0_QM_CP_FENCE2_RDATA_0 0x4C8A2B8 356 357 #define mmPDMA0_QM_CP_FENCE2_RDATA_1 0x4C8A2BC 358 359 #define mmPDMA0_QM_CP_FENCE2_RDATA_2 0x4C8A2C0 360 361 #define mmPDMA0_QM_CP_FENCE2_RDATA_3 0x4C8A2C4 362 363 #define mmPDMA0_QM_CP_FENCE2_RDATA_4 0x4C8A2C8 364 365 #define mmPDMA0_QM_CP_FENCE3_RDATA_0 0x4C8A2CC 366 367 #define mmPDMA0_QM_CP_FENCE3_RDATA_1 0x4C8A2D0 368 369 #define mmPDMA0_QM_CP_FENCE3_RDATA_2 0x4C8A2D4 370 371 #define mmPDMA0_QM_CP_FENCE3_RDATA_3 0x4C8A2D8 372 373 #define mmPDMA0_QM_CP_FENCE3_RDATA_4 0x4C8A2DC 374 375 #define mmPDMA0_QM_CP_FENCE0_CNT_0 0x4C8A2E0 376 377 #define mmPDMA0_QM_CP_FENCE0_CNT_1 0x4C8A2E4 378 379 #define mmPDMA0_QM_CP_FENCE0_CNT_2 0x4C8A2E8 380 381 #define mmPDMA0_QM_CP_FENCE0_CNT_3 0x4C8A2EC 382 383 #define mmPDMA0_QM_CP_FENCE0_CNT_4 0x4C8A2F0 384 385 #define mmPDMA0_QM_CP_FENCE1_CNT_0 0x4C8A2F4 386 387 #define mmPDMA0_QM_CP_FENCE1_CNT_1 0x4C8A2F8 388 389 #define mmPDMA0_QM_CP_FENCE1_CNT_2 0x4C8A2FC 390 391 #define mmPDMA0_QM_CP_FENCE1_CNT_3 0x4C8A300 392 393 #define mmPDMA0_QM_CP_FENCE1_CNT_4 0x4C8A304 394 395 #define mmPDMA0_QM_CP_FENCE2_CNT_0 0x4C8A308 396 397 #define mmPDMA0_QM_CP_FENCE2_CNT_1 0x4C8A30C 398 399 #define mmPDMA0_QM_CP_FENCE2_CNT_2 0x4C8A310 400 401 #define mmPDMA0_QM_CP_FENCE2_CNT_3 0x4C8A314 402 403 #define mmPDMA0_QM_CP_FENCE2_CNT_4 0x4C8A318 404 405 #define mmPDMA0_QM_CP_FENCE3_CNT_0 0x4C8A31C 406 407 #define mmPDMA0_QM_CP_FENCE3_CNT_1 0x4C8A320 408 409 #define mmPDMA0_QM_CP_FENCE3_CNT_2 0x4C8A324 410 411 #define mmPDMA0_QM_CP_FENCE3_CNT_3 0x4C8A328 412 413 #define mmPDMA0_QM_CP_FENCE3_CNT_4 0x4C8A32C 414 415 #define mmPDMA0_QM_CP_BARRIER_CFG 0x4C8A330 416 417 #define mmPDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x4C8A334 418 419 #define mmPDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x4C8A338 420 421 #define mmPDMA0_QM_CP_LDMA_TSIZE_OFFSET 0x4C8A33C 422 423 #define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 0x4C8A340 424 425 #define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 0x4C8A344 426 427 #define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 0x4C8A348 428 429 #define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 0x4C8A34C 430 431 #define mmPDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 0x4C8A350 432 433 #define mmPDMA0_QM_CP_STS_0 0x4C8A368 434 435 #define mmPDMA0_QM_CP_STS_1 0x4C8A36C 436 437 #define mmPDMA0_QM_CP_STS_2 0x4C8A370 438 439 #define mmPDMA0_QM_CP_STS_3 0x4C8A374 440 441 #define mmPDMA0_QM_CP_STS_4 0x4C8A378 442 443 #define mmPDMA0_QM_CP_CURRENT_INST_LO_0 0x4C8A37C 444 445 #define mmPDMA0_QM_CP_CURRENT_INST_LO_1 0x4C8A380 446 447 #define mmPDMA0_QM_CP_CURRENT_INST_LO_2 0x4C8A384 448 449 #define mmPDMA0_QM_CP_CURRENT_INST_LO_3 0x4C8A388 450 451 #define mmPDMA0_QM_CP_CURRENT_INST_LO_4 0x4C8A38C 452 453 #define mmPDMA0_QM_CP_CURRENT_INST_HI_0 0x4C8A390 454 455 #define mmPDMA0_QM_CP_CURRENT_INST_HI_1 0x4C8A394 456 457 #define mmPDMA0_QM_CP_CURRENT_INST_HI_2 0x4C8A398 458 459 #define mmPDMA0_QM_CP_CURRENT_INST_HI_3 0x4C8A39C 460 461 #define mmPDMA0_QM_CP_CURRENT_INST_HI_4 0x4C8A3A0 462 463 #define mmPDMA0_QM_CP_PRED_0 0x4C8A3A4 464 465 #define mmPDMA0_QM_CP_PRED_1 0x4C8A3A8 466 467 #define mmPDMA0_QM_CP_PRED_2 0x4C8A3AC 468 469 #define mmPDMA0_QM_CP_PRED_3 0x4C8A3B0 470 471 #define mmPDMA0_QM_CP_PRED_4 0x4C8A3B4 472 473 #define mmPDMA0_QM_CP_PRED_UPEN_0 0x4C8A3B8 474 475 #define mmPDMA0_QM_CP_PRED_UPEN_1 0x4C8A3BC 476 477 #define mmPDMA0_QM_CP_PRED_UPEN_2 0x4C8A3C0 478 479 #define mmPDMA0_QM_CP_PRED_UPEN_3 0x4C8A3C4 480 481 #define mmPDMA0_QM_CP_PRED_UPEN_4 0x4C8A3C8 482 483 #define mmPDMA0_QM_CP_DBG_0_0 0x4C8A3CC 484 485 #define mmPDMA0_QM_CP_DBG_0_1 0x4C8A3D0 486 487 #define mmPDMA0_QM_CP_DBG_0_2 0x4C8A3D4 488 489 #define mmPDMA0_QM_CP_DBG_0_3 0x4C8A3D8 490 491 #define mmPDMA0_QM_CP_DBG_0_4 0x4C8A3DC 492 493 #define mmPDMA0_QM_CP_CPDMA_UP_CRED_0 0x4C8A3E0 494 495 #define mmPDMA0_QM_CP_CPDMA_UP_CRED_1 0x4C8A3E4 496 497 #define mmPDMA0_QM_CP_CPDMA_UP_CRED_2 0x4C8A3E8 498 499 #define mmPDMA0_QM_CP_CPDMA_UP_CRED_3 0x4C8A3EC 500 501 #define mmPDMA0_QM_CP_CPDMA_UP_CRED_4 0x4C8A3F0 502 503 #define mmPDMA0_QM_CP_IN_DATA_LO_0 0x4C8A3F4 504 505 #define mmPDMA0_QM_CP_IN_DATA_LO_1 0x4C8A3F8 506 507 #define mmPDMA0_QM_CP_IN_DATA_LO_2 0x4C8A3FC 508 509 #define mmPDMA0_QM_CP_IN_DATA_LO_3 0x4C8A400 510 511 #define mmPDMA0_QM_CP_IN_DATA_LO_4 0x4C8A404 512 513 #define mmPDMA0_QM_CP_IN_DATA_HI_0 0x4C8A408 514 515 #define mmPDMA0_QM_CP_IN_DATA_HI_1 0x4C8A40C 516 517 #define mmPDMA0_QM_CP_IN_DATA_HI_2 0x4C8A410 518 519 #define mmPDMA0_QM_CP_IN_DATA_HI_3 0x4C8A414 520 521 #define mmPDMA0_QM_CP_IN_DATA_HI_4 0x4C8A418 522 523 #define mmPDMA0_QM_PQC_HBW_BASE_LO_0 0x4C8A41C 524 525 #define mmPDMA0_QM_PQC_HBW_BASE_LO_1 0x4C8A420 526 527 #define mmPDMA0_QM_PQC_HBW_BASE_LO_2 0x4C8A424 528 529 #define mmPDMA0_QM_PQC_HBW_BASE_LO_3 0x4C8A428 530 531 #define mmPDMA0_QM_PQC_HBW_BASE_HI_0 0x4C8A42C 532 533 #define mmPDMA0_QM_PQC_HBW_BASE_HI_1 0x4C8A430 534 535 #define mmPDMA0_QM_PQC_HBW_BASE_HI_2 0x4C8A434 536 537 #define mmPDMA0_QM_PQC_HBW_BASE_HI_3 0x4C8A438 538 539 #define mmPDMA0_QM_PQC_SIZE_0 0x4C8A43C 540 541 #define mmPDMA0_QM_PQC_SIZE_1 0x4C8A440 542 543 #define mmPDMA0_QM_PQC_SIZE_2 0x4C8A444 544 545 #define mmPDMA0_QM_PQC_SIZE_3 0x4C8A448 546 547 #define mmPDMA0_QM_PQC_PI_0 0x4C8A44C 548 549 #define mmPDMA0_QM_PQC_PI_1 0x4C8A450 550 551 #define mmPDMA0_QM_PQC_PI_2 0x4C8A454 552 553 #define mmPDMA0_QM_PQC_PI_3 0x4C8A458 554 555 #define mmPDMA0_QM_PQC_LBW_WDATA_0 0x4C8A45C 556 557 #define mmPDMA0_QM_PQC_LBW_WDATA_1 0x4C8A460 558 559 #define mmPDMA0_QM_PQC_LBW_WDATA_2 0x4C8A464 560 561 #define mmPDMA0_QM_PQC_LBW_WDATA_3 0x4C8A468 562 563 #define mmPDMA0_QM_PQC_LBW_BASE_LO_0 0x4C8A46C 564 565 #define mmPDMA0_QM_PQC_LBW_BASE_LO_1 0x4C8A470 566 567 #define mmPDMA0_QM_PQC_LBW_BASE_LO_2 0x4C8A474 568 569 #define mmPDMA0_QM_PQC_LBW_BASE_LO_3 0x4C8A478 570 571 #define mmPDMA0_QM_PQC_LBW_BASE_HI_0 0x4C8A47C 572 573 #define mmPDMA0_QM_PQC_LBW_BASE_HI_1 0x4C8A480 574 575 #define mmPDMA0_QM_PQC_LBW_BASE_HI_2 0x4C8A484 576 577 #define mmPDMA0_QM_PQC_LBW_BASE_HI_3 0x4C8A488 578 579 #define mmPDMA0_QM_PQC_CFG 0x4C8A48C 580 581 #define mmPDMA0_QM_PQC_SECURE_PUSH_IND 0x4C8A490 582 583 #define mmPDMA0_QM_ARB_MASK 0x4C8A4A0 584 585 #define mmPDMA0_QM_ARB_CFG_0 0x4C8A4A4 586 587 #define mmPDMA0_QM_ARB_CHOICE_Q_PUSH 0x4C8A4A8 588 589 #define mmPDMA0_QM_ARB_WRR_WEIGHT_0 0x4C8A4AC 590 591 #define mmPDMA0_QM_ARB_WRR_WEIGHT_1 0x4C8A4B0 592 593 #define mmPDMA0_QM_ARB_WRR_WEIGHT_2 0x4C8A4B4 594 595 #define mmPDMA0_QM_ARB_WRR_WEIGHT_3 0x4C8A4B8 596 597 #define mmPDMA0_QM_ARB_CFG_1 0x4C8A4BC 598 599 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_0 0x4C8A4C0 600 601 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_1 0x4C8A4C4 602 603 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_2 0x4C8A4C8 604 605 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_3 0x4C8A4CC 606 607 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_4 0x4C8A4D0 608 609 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_5 0x4C8A4D4 610 611 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_6 0x4C8A4D8 612 613 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_7 0x4C8A4DC 614 615 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_8 0x4C8A4E0 616 617 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_9 0x4C8A4E4 618 619 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_10 0x4C8A4E8 620 621 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_11 0x4C8A4EC 622 623 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_12 0x4C8A4F0 624 625 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_13 0x4C8A4F4 626 627 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_14 0x4C8A4F8 628 629 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_15 0x4C8A4FC 630 631 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_16 0x4C8A500 632 633 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_17 0x4C8A504 634 635 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_18 0x4C8A508 636 637 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_19 0x4C8A50C 638 639 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_20 0x4C8A510 640 641 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_21 0x4C8A514 642 643 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_22 0x4C8A518 644 645 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_23 0x4C8A51C 646 647 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_24 0x4C8A520 648 649 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_25 0x4C8A524 650 651 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_26 0x4C8A528 652 653 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_27 0x4C8A52C 654 655 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_28 0x4C8A530 656 657 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_29 0x4C8A534 658 659 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_30 0x4C8A538 660 661 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_31 0x4C8A53C 662 663 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_32 0x4C8A540 664 665 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_33 0x4C8A544 666 667 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_34 0x4C8A548 668 669 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_35 0x4C8A54C 670 671 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_36 0x4C8A550 672 673 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_37 0x4C8A554 674 675 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_38 0x4C8A558 676 677 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_39 0x4C8A55C 678 679 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_40 0x4C8A560 680 681 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_41 0x4C8A564 682 683 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_42 0x4C8A568 684 685 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_43 0x4C8A56C 686 687 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_44 0x4C8A570 688 689 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_45 0x4C8A574 690 691 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_46 0x4C8A578 692 693 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_47 0x4C8A57C 694 695 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_48 0x4C8A580 696 697 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_49 0x4C8A584 698 699 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_50 0x4C8A588 700 701 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_51 0x4C8A58C 702 703 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_52 0x4C8A590 704 705 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_53 0x4C8A594 706 707 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_54 0x4C8A598 708 709 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_55 0x4C8A59C 710 711 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_56 0x4C8A5A0 712 713 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_57 0x4C8A5A4 714 715 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_58 0x4C8A5A8 716 717 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_59 0x4C8A5AC 718 719 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_60 0x4C8A5B0 720 721 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_61 0x4C8A5B4 722 723 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_62 0x4C8A5B8 724 725 #define mmPDMA0_QM_ARB_MST_AVAIL_CRED_63 0x4C8A5BC 726 727 #define mmPDMA0_QM_ARB_MST_CRED_INC 0x4C8A5E0 728 729 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x4C8A5E4 730 731 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x4C8A5E8 732 733 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x4C8A5EC 734 735 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x4C8A5F0 736 737 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x4C8A5F4 738 739 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x4C8A5F8 740 741 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x4C8A5FC 742 743 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x4C8A600 744 745 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x4C8A604 746 747 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x4C8A608 748 749 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x4C8A60C 750 751 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x4C8A610 752 753 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x4C8A614 754 755 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x4C8A618 756 757 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x4C8A61C 758 759 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x4C8A620 760 761 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x4C8A624 762 763 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x4C8A628 764 765 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x4C8A62C 766 767 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x4C8A630 768 769 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x4C8A634 770 771 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x4C8A638 772 773 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x4C8A63C 774 775 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x4C8A640 776 777 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x4C8A644 778 779 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x4C8A648 780 781 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x4C8A64C 782 783 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x4C8A650 784 785 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x4C8A654 786 787 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x4C8A658 788 789 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x4C8A65C 790 791 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x4C8A660 792 793 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x4C8A664 794 795 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x4C8A668 796 797 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x4C8A66C 798 799 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x4C8A670 800 801 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x4C8A674 802 803 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x4C8A678 804 805 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x4C8A67C 806 807 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x4C8A680 808 809 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x4C8A684 810 811 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x4C8A688 812 813 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x4C8A68C 814 815 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x4C8A690 816 817 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x4C8A694 818 819 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x4C8A698 820 821 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x4C8A69C 822 823 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x4C8A6A0 824 825 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x4C8A6A4 826 827 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x4C8A6A8 828 829 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x4C8A6AC 830 831 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x4C8A6B0 832 833 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x4C8A6B4 834 835 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x4C8A6B8 836 837 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x4C8A6BC 838 839 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x4C8A6C0 840 841 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x4C8A6C4 842 843 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x4C8A6C8 844 845 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x4C8A6CC 846 847 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x4C8A6D0 848 849 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x4C8A6D4 850 851 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x4C8A6D8 852 853 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x4C8A6DC 854 855 #define mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x4C8A6E0 856 857 #define mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x4C8A704 858 859 #define mmPDMA0_QM_ARB_MST_SLAVE_EN 0x4C8A708 860 861 #define mmPDMA0_QM_ARB_MST_SLAVE_EN_1 0x4C8A70C 862 863 #define mmPDMA0_QM_ARB_SLV_CHOICE_WDT 0x4C8A710 864 865 #define mmPDMA0_QM_ARB_SLV_ID 0x4C8A714 866 867 #define mmPDMA0_QM_ARB_MST_QUIET_PER 0x4C8A718 868 869 #define mmPDMA0_QM_ARB_MSG_MAX_INFLIGHT 0x4C8A744 870 871 #define mmPDMA0_QM_ARB_BASE_LO 0x4C8A754 872 873 #define mmPDMA0_QM_ARB_BASE_HI 0x4C8A758 874 875 #define mmPDMA0_QM_ARB_STATE_STS 0x4C8A780 876 877 #define mmPDMA0_QM_ARB_CHOICE_FULLNESS_STS 0x4C8A784 878 879 #define mmPDMA0_QM_ARB_MSG_STS 0x4C8A788 880 881 #define mmPDMA0_QM_ARB_SLV_CHOICE_Q_HEAD 0x4C8A78C 882 883 #define mmPDMA0_QM_ARB_ERR_CAUSE 0x4C8A79C 884 885 #define mmPDMA0_QM_ARB_ERR_MSG_EN 0x4C8A7A0 886 887 #define mmPDMA0_QM_ARB_ERR_STS_DRP 0x4C8A7A8 888 889 #define mmPDMA0_QM_ARB_MST_CRED_STS 0x4C8A7B0 890 891 #define mmPDMA0_QM_ARB_MST_CRED_STS_1 0x4C8A7B4 892 893 #define mmPDMA0_QM_CSMR_STRICT_PRIO_CFG 0x4C8A7FC 894 895 #define mmPDMA0_QM_ARC_CQ_CFG0 0x4C8A800 896 897 #define mmPDMA0_QM_ARC_CQ_CFG1 0x4C8A804 898 899 #define mmPDMA0_QM_ARC_CQ_PTR_LO 0x4C8A808 900 901 #define mmPDMA0_QM_ARC_CQ_PTR_HI 0x4C8A80C 902 903 #define mmPDMA0_QM_ARC_CQ_TSIZE 0x4C8A810 904 905 #define mmPDMA0_QM_ARC_CQ_CTL 0x4C8A814 906 907 #define mmPDMA0_QM_ARC_CQ_IFIFO_STS 0x4C8A81C 908 909 #define mmPDMA0_QM_ARC_CQ_STS0 0x4C8A820 910 911 #define mmPDMA0_QM_ARC_CQ_STS1 0x4C8A824 912 913 #define mmPDMA0_QM_ARC_CQ_TSIZE_STS 0x4C8A828 914 915 #define mmPDMA0_QM_ARC_CQ_PTR_LO_STS 0x4C8A82C 916 917 #define mmPDMA0_QM_ARC_CQ_PTR_HI_STS 0x4C8A830 918 919 #define mmPDMA0_QM_CP_WR_ARC_ADDR_HI 0x4C8A834 920 921 #define mmPDMA0_QM_CP_WR_ARC_ADDR_LO 0x4C8A838 922 923 #define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x4C8A83C 924 925 #define mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x4C8A840 926 927 #define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x4C8A844 928 929 #define mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x4C8A848 930 931 #define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_HI 0x4C8A84C 932 933 #define mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO 0x4C8A850 934 935 #define mmPDMA0_QM_CQ_CTL_MSG_BASE_HI 0x4C8A854 936 937 #define mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 0x4C8A858 938 939 #define mmPDMA0_QM_ADDR_OVRD 0x4C8A85C 940 941 #define mmPDMA0_QM_CQ_IFIFO_CI_0 0x4C8A860 942 943 #define mmPDMA0_QM_CQ_IFIFO_CI_1 0x4C8A864 944 945 #define mmPDMA0_QM_CQ_IFIFO_CI_2 0x4C8A868 946 947 #define mmPDMA0_QM_CQ_IFIFO_CI_3 0x4C8A86C 948 949 #define mmPDMA0_QM_CQ_IFIFO_CI_4 0x4C8A870 950 951 #define mmPDMA0_QM_ARC_CQ_IFIFO_CI 0x4C8A874 952 953 #define mmPDMA0_QM_CQ_CTL_CI_0 0x4C8A878 954 955 #define mmPDMA0_QM_CQ_CTL_CI_1 0x4C8A87C 956 957 #define mmPDMA0_QM_CQ_CTL_CI_2 0x4C8A880 958 959 #define mmPDMA0_QM_CQ_CTL_CI_3 0x4C8A884 960 961 #define mmPDMA0_QM_CQ_CTL_CI_4 0x4C8A888 962 963 #define mmPDMA0_QM_ARC_CQ_CTL_CI 0x4C8A88C 964 965 #define mmPDMA0_QM_CP_CFG 0x4C8A890 966 967 #define mmPDMA0_QM_CP_EXT_SWITCH 0x4C8A894 968 969 #define mmPDMA0_QM_CP_SWITCH_WD_SET 0x4C8A898 970 971 #define mmPDMA0_QM_CP_SWITCH_WD 0x4C8A89C 972 973 #define mmPDMA0_QM_ARC_LB_ADDR_BASE_LO 0x4C8A8A4 974 975 #define mmPDMA0_QM_ARC_LB_ADDR_BASE_HI 0x4C8A8A8 976 977 #define mmPDMA0_QM_ENGINE_BASE_ADDR_HI 0x4C8A8AC 978 979 #define mmPDMA0_QM_ENGINE_BASE_ADDR_LO 0x4C8A8B0 980 981 #define mmPDMA0_QM_ENGINE_ADDR_RANGE_SIZE 0x4C8A8B4 982 983 #define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x4C8A8B8 984 985 #define mmPDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x4C8A8BC 986 987 #define mmPDMA0_QM_QM_BASE_ADDR_HI 0x4C8A8C0 988 989 #define mmPDMA0_QM_QM_BASE_ADDR_LO 0x4C8A8C4 990 991 #define mmPDMA0_QM_ARC_PQC_SECURE_PUSH_IND 0x4C8A8C8 992 993 #define mmPDMA0_QM_PQC_STS_0_0 0x4C8A8D0 994 995 #define mmPDMA0_QM_PQC_STS_0_1 0x4C8A8D4 996 997 #define mmPDMA0_QM_PQC_STS_0_2 0x4C8A8D8 998 999 #define mmPDMA0_QM_PQC_STS_0_3 0x4C8A8DC 1000 1001 #define mmPDMA0_QM_PQC_STS_1_0 0x4C8A8E0 1002 1003 #define mmPDMA0_QM_PQC_STS_1_1 0x4C8A8E4 1004 1005 #define mmPDMA0_QM_PQC_STS_1_2 0x4C8A8E8 1006 1007 #define mmPDMA0_QM_PQC_STS_1_3 0x4C8A8EC 1008 1009 #define mmPDMA0_QM_SEI_STATUS 0x4C8A8F0 1010 1011 #define mmPDMA0_QM_SEI_MASK 0x4C8A8F4 1012 1013 #define mmPDMA0_QM_GLBL_ERR_ADDR_LO 0x4C8AD00 1014 1015 #define mmPDMA0_QM_GLBL_ERR_ADDR_HI 0x4C8AD04 1016 1017 #define mmPDMA0_QM_GLBL_ERR_WDATA 0x4C8AD08 1018 1019 #define mmPDMA0_QM_L2H_MASK_LO 0x4C8AD14 1020 1021 #define mmPDMA0_QM_L2H_MASK_HI 0x4C8AD18 1022 1023 #define mmPDMA0_QM_L2H_CMPR_LO 0x4C8AD1C 1024 1025 #define mmPDMA0_QM_L2H_CMPR_HI 0x4C8AD20 1026 1027 #define mmPDMA0_QM_LOCAL_RANGE_BASE 0x4C8AD24 1028 1029 #define mmPDMA0_QM_LOCAL_RANGE_SIZE 0x4C8AD28 1030 1031 #define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_1 0x4C8AD30 1032 1033 #define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_0 0x4C8AD34 1034 1035 #define mmPDMA0_QM_LBW_WR_RATE_LIM_CFG_1 0x4C8AD38 1036 1037 #define mmPDMA0_QM_HBW_RD_RATE_LIM_CFG_0 0x4C8AD3C 1038 1039 #define mmPDMA0_QM_IND_GW_APB_CFG 0x4C8AD40 1040 1041 #define mmPDMA0_QM_IND_GW_APB_WDATA 0x4C8AD44 1042 1043 #define mmPDMA0_QM_IND_GW_APB_RDATA 0x4C8AD48 1044 1045 #define mmPDMA0_QM_IND_GW_APB_STATUS 0x4C8AD4C 1046 1047 #define mmPDMA0_QM_PERF_CNT_FREE_LO 0x4C8AD60 1048 1049 #define mmPDMA0_QM_PERF_CNT_FREE_HI 0x4C8AD64 1050 1051 #define mmPDMA0_QM_PERF_CNT_IDLE_LO 0x4C8AD68 1052 1053 #define mmPDMA0_QM_PERF_CNT_IDLE_HI 0x4C8AD6C 1054 1055 #define mmPDMA0_QM_PERF_CNT_CFG 0x4C8AD70 1056 1057 #endif /* ASIC_REG_PDMA0_QM_REGS_H_ */ 1058