| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | smu9_smumgr.c | 76 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
123 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
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| H A D | smu10_smumgr.c | 54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
85 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc()
103 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc_with_parameter()
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| H A D | vega20_smumgr.c | 75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
80 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
112 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc()
138 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc_with_parameter()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_12_0_0_offset.h | 298 #define mmMP1_SMN_C2PMSG_90 … macro
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| H A D | mp_10_0_offset.h | 298 #define mmMP1_SMN_C2PMSG_90 … macro
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| H A D | mp_9_0_offset.h | 310 #define mmMP1_SMN_C2PMSG_90 0x029a macro
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| H A D | mp_11_0_offset.h | 300 #define mmMP1_SMN_C2PMSG_90 … macro
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| H A D | mp_11_0_8_offset.h | 298 #define mmMP1_SMN_C2PMSG_90 … macro
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| H A D | mp_11_5_0_offset.h | 298 #define mmMP1_SMN_C2PMSG_90 … macro
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_4_ppt.c | 52 #define mmMP1_SMN_C2PMSG_90 0x029a macro
1129 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v13_0_4_set_smu_mailbox_registers()
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| H A D | smu_v13_0.c | 70 #define mmMP1_SMN_C2PMSG_90 … macro
2476 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v13_0_set_smu_mailbox_registers()
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| H A D | smu_v13_0_0_ppt.c | 79 #define mmMP1_SMN_C2PMSG_90 … macro
2986 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v13_0_0_set_smu_mailbox_registers()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
| H A D | renoir_ppt.c | 50 #define mmMP1_SMN_C2PMSG_90 … macro
1503 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in renoir_set_ppt_funcs()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 52 #define mmMP1_SMN_C2PMSG_90 0x029a macro
1683 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v14_0_0_set_smu_mailbox_registers()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 2216 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v11_0_set_smu_mailbox_registers()
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