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Searched refs:mmMP1_SMN_C2PMSG_90 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c76 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
83 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu9_wait_for_response()
123 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
H A Dsmu10_smumgr.c54 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
59 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu10_wait_for_response()
85 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc()
103 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu10_send_msg_to_smc_with_parameter()
H A Dvega20_smumgr.c75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
80 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
112 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc()
138 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in vega20_send_msg_to_smc_with_parameter()
/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h298 #define mmMP1_SMN_C2PMSG_90 … macro
H A Dmp_10_0_offset.h298 #define mmMP1_SMN_C2PMSG_90 … macro
H A Dmp_9_0_offset.h310 #define mmMP1_SMN_C2PMSG_90 0x029a macro
H A Dmp_11_0_offset.h300 #define mmMP1_SMN_C2PMSG_90 … macro
H A Dmp_11_0_8_offset.h298 #define mmMP1_SMN_C2PMSG_90 … macro
H A Dmp_11_5_0_offset.h298 #define mmMP1_SMN_C2PMSG_90 … macro
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c381 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v12_0_init_msg_ctl()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c2105 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in smu_v11_0_init_msg_ctl()