1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "gc/gc_9_0_sh_mask.h"
35 #include "dce/dce_12_0_offset.h"
36 #include "dce/dce_12_0_sh_mask.h"
37 #include "vega10_enum.h"
38 #include "mmhub/mmhub_1_0_offset.h"
39 #include "athub/athub_1_0_sh_mask.h"
40 #include "athub/athub_1_0_offset.h"
41 #include "oss/osssys_4_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15d.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
47
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "gfxhub_v1_2.h"
53 #include "mmhub_v9_4.h"
54 #include "mmhub_v1_7.h"
55 #include "mmhub_v1_8.h"
56 #include "umc_v6_1.h"
57 #include "umc_v6_0.h"
58 #include "umc_v6_7.h"
59 #include "umc_v12_0.h"
60 #include "hdp_v4_0.h"
61 #include "mca_v3_0.h"
62
63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
64
65 #include "amdgpu_ras.h"
66 #include "amdgpu_xgmi.h"
67
68 /* add these here since we already include dce12 headers and these are for DCN */
69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
77
78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
80
81 #define MAX_MEM_RANGES 8
82
83 static const char * const gfxhub_client_ids[] = {
84 "CB",
85 "DB",
86 "IA",
87 "WD",
88 "CPF",
89 "CPC",
90 "CPG",
91 "RLC",
92 "TCP",
93 "SQC (inst)",
94 "SQC (data)",
95 "SQG",
96 "PA",
97 };
98
99 static const char *mmhub_client_ids_raven[][2] = {
100 [0][0] = "MP1",
101 [1][0] = "MP0",
102 [2][0] = "VCN",
103 [3][0] = "VCNU",
104 [4][0] = "HDP",
105 [5][0] = "DCE",
106 [13][0] = "UTCL2",
107 [19][0] = "TLS",
108 [26][0] = "OSS",
109 [27][0] = "SDMA0",
110 [0][1] = "MP1",
111 [1][1] = "MP0",
112 [2][1] = "VCN",
113 [3][1] = "VCNU",
114 [4][1] = "HDP",
115 [5][1] = "XDP",
116 [6][1] = "DBGU0",
117 [7][1] = "DCE",
118 [8][1] = "DCEDWB0",
119 [9][1] = "DCEDWB1",
120 [26][1] = "OSS",
121 [27][1] = "SDMA0",
122 };
123
124 static const char *mmhub_client_ids_renoir[][2] = {
125 [0][0] = "MP1",
126 [1][0] = "MP0",
127 [2][0] = "HDP",
128 [4][0] = "DCEDMC",
129 [5][0] = "DCEVGA",
130 [13][0] = "UTCL2",
131 [19][0] = "TLS",
132 [26][0] = "OSS",
133 [27][0] = "SDMA0",
134 [28][0] = "VCN",
135 [29][0] = "VCNU",
136 [30][0] = "JPEG",
137 [0][1] = "MP1",
138 [1][1] = "MP0",
139 [2][1] = "HDP",
140 [3][1] = "XDP",
141 [6][1] = "DBGU0",
142 [7][1] = "DCEDMC",
143 [8][1] = "DCEVGA",
144 [9][1] = "DCEDWB",
145 [26][1] = "OSS",
146 [27][1] = "SDMA0",
147 [28][1] = "VCN",
148 [29][1] = "VCNU",
149 [30][1] = "JPEG",
150 };
151
152 static const char *mmhub_client_ids_vega10[][2] = {
153 [0][0] = "MP0",
154 [1][0] = "UVD",
155 [2][0] = "UVDU",
156 [3][0] = "HDP",
157 [13][0] = "UTCL2",
158 [14][0] = "OSS",
159 [15][0] = "SDMA1",
160 [32+0][0] = "VCE0",
161 [32+1][0] = "VCE0U",
162 [32+2][0] = "XDMA",
163 [32+3][0] = "DCE",
164 [32+4][0] = "MP1",
165 [32+14][0] = "SDMA0",
166 [0][1] = "MP0",
167 [1][1] = "UVD",
168 [2][1] = "UVDU",
169 [3][1] = "DBGU0",
170 [4][1] = "HDP",
171 [5][1] = "XDP",
172 [14][1] = "OSS",
173 [15][1] = "SDMA0",
174 [32+0][1] = "VCE0",
175 [32+1][1] = "VCE0U",
176 [32+2][1] = "XDMA",
177 [32+3][1] = "DCE",
178 [32+4][1] = "DCEDWB",
179 [32+5][1] = "MP1",
180 [32+6][1] = "DBGU1",
181 [32+14][1] = "SDMA1",
182 };
183
184 static const char *mmhub_client_ids_vega12[][2] = {
185 [0][0] = "MP0",
186 [1][0] = "VCE0",
187 [2][0] = "VCE0U",
188 [3][0] = "HDP",
189 [13][0] = "UTCL2",
190 [14][0] = "OSS",
191 [15][0] = "SDMA1",
192 [32+0][0] = "DCE",
193 [32+1][0] = "XDMA",
194 [32+2][0] = "UVD",
195 [32+3][0] = "UVDU",
196 [32+4][0] = "MP1",
197 [32+15][0] = "SDMA0",
198 [0][1] = "MP0",
199 [1][1] = "VCE0",
200 [2][1] = "VCE0U",
201 [3][1] = "DBGU0",
202 [4][1] = "HDP",
203 [5][1] = "XDP",
204 [14][1] = "OSS",
205 [15][1] = "SDMA0",
206 [32+0][1] = "DCE",
207 [32+1][1] = "DCEDWB",
208 [32+2][1] = "XDMA",
209 [32+3][1] = "UVD",
210 [32+4][1] = "UVDU",
211 [32+5][1] = "MP1",
212 [32+6][1] = "DBGU1",
213 [32+15][1] = "SDMA1",
214 };
215
216 static const char *mmhub_client_ids_vega20[][2] = {
217 [0][0] = "XDMA",
218 [1][0] = "DCE",
219 [2][0] = "VCE0",
220 [3][0] = "VCE0U",
221 [4][0] = "UVD",
222 [5][0] = "UVD1U",
223 [13][0] = "OSS",
224 [14][0] = "HDP",
225 [15][0] = "SDMA0",
226 [32+0][0] = "UVD",
227 [32+1][0] = "UVDU",
228 [32+2][0] = "MP1",
229 [32+3][0] = "MP0",
230 [32+12][0] = "UTCL2",
231 [32+14][0] = "SDMA1",
232 [0][1] = "XDMA",
233 [1][1] = "DCE",
234 [2][1] = "DCEDWB",
235 [3][1] = "VCE0",
236 [4][1] = "VCE0U",
237 [5][1] = "UVD1",
238 [6][1] = "UVD1U",
239 [7][1] = "DBGU0",
240 [8][1] = "XDP",
241 [13][1] = "OSS",
242 [14][1] = "HDP",
243 [15][1] = "SDMA0",
244 [32+0][1] = "UVD",
245 [32+1][1] = "UVDU",
246 [32+2][1] = "DBGU1",
247 [32+3][1] = "MP1",
248 [32+4][1] = "MP0",
249 [32+14][1] = "SDMA1",
250 };
251
252 static const char *mmhub_client_ids_arcturus[][2] = {
253 [0][0] = "DBGU1",
254 [1][0] = "XDP",
255 [2][0] = "MP1",
256 [14][0] = "HDP",
257 [171][0] = "JPEG",
258 [172][0] = "VCN",
259 [173][0] = "VCNU",
260 [203][0] = "JPEG1",
261 [204][0] = "VCN1",
262 [205][0] = "VCN1U",
263 [256][0] = "SDMA0",
264 [257][0] = "SDMA1",
265 [258][0] = "SDMA2",
266 [259][0] = "SDMA3",
267 [260][0] = "SDMA4",
268 [261][0] = "SDMA5",
269 [262][0] = "SDMA6",
270 [263][0] = "SDMA7",
271 [384][0] = "OSS",
272 [0][1] = "DBGU1",
273 [1][1] = "XDP",
274 [2][1] = "MP1",
275 [14][1] = "HDP",
276 [171][1] = "JPEG",
277 [172][1] = "VCN",
278 [173][1] = "VCNU",
279 [203][1] = "JPEG1",
280 [204][1] = "VCN1",
281 [205][1] = "VCN1U",
282 [256][1] = "SDMA0",
283 [257][1] = "SDMA1",
284 [258][1] = "SDMA2",
285 [259][1] = "SDMA3",
286 [260][1] = "SDMA4",
287 [261][1] = "SDMA5",
288 [262][1] = "SDMA6",
289 [263][1] = "SDMA7",
290 [384][1] = "OSS",
291 };
292
293 static const char *mmhub_client_ids_aldebaran[][2] = {
294 [2][0] = "MP1",
295 [3][0] = "MP0",
296 [32+1][0] = "DBGU_IO0",
297 [32+2][0] = "DBGU_IO2",
298 [32+4][0] = "MPIO",
299 [96+11][0] = "JPEG0",
300 [96+12][0] = "VCN0",
301 [96+13][0] = "VCNU0",
302 [128+11][0] = "JPEG1",
303 [128+12][0] = "VCN1",
304 [128+13][0] = "VCNU1",
305 [160+1][0] = "XDP",
306 [160+14][0] = "HDP",
307 [256+0][0] = "SDMA0",
308 [256+1][0] = "SDMA1",
309 [256+2][0] = "SDMA2",
310 [256+3][0] = "SDMA3",
311 [256+4][0] = "SDMA4",
312 [384+0][0] = "OSS",
313 [2][1] = "MP1",
314 [3][1] = "MP0",
315 [32+1][1] = "DBGU_IO0",
316 [32+2][1] = "DBGU_IO2",
317 [32+4][1] = "MPIO",
318 [96+11][1] = "JPEG0",
319 [96+12][1] = "VCN0",
320 [96+13][1] = "VCNU0",
321 [128+11][1] = "JPEG1",
322 [128+12][1] = "VCN1",
323 [128+13][1] = "VCNU1",
324 [160+1][1] = "XDP",
325 [160+14][1] = "HDP",
326 [256+0][1] = "SDMA0",
327 [256+1][1] = "SDMA1",
328 [256+2][1] = "SDMA2",
329 [256+3][1] = "SDMA3",
330 [256+4][1] = "SDMA4",
331 [384+0][1] = "OSS",
332 };
333
334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
337 };
338
339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
342 };
343
344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
345 (0x000143c0 + 0x00000000),
346 (0x000143c0 + 0x00000800),
347 (0x000143c0 + 0x00001000),
348 (0x000143c0 + 0x00001800),
349 (0x000543c0 + 0x00000000),
350 (0x000543c0 + 0x00000800),
351 (0x000543c0 + 0x00001000),
352 (0x000543c0 + 0x00001800),
353 (0x000943c0 + 0x00000000),
354 (0x000943c0 + 0x00000800),
355 (0x000943c0 + 0x00001000),
356 (0x000943c0 + 0x00001800),
357 (0x000d43c0 + 0x00000000),
358 (0x000d43c0 + 0x00000800),
359 (0x000d43c0 + 0x00001000),
360 (0x000d43c0 + 0x00001800),
361 (0x001143c0 + 0x00000000),
362 (0x001143c0 + 0x00000800),
363 (0x001143c0 + 0x00001000),
364 (0x001143c0 + 0x00001800),
365 (0x001543c0 + 0x00000000),
366 (0x001543c0 + 0x00000800),
367 (0x001543c0 + 0x00001000),
368 (0x001543c0 + 0x00001800),
369 (0x001943c0 + 0x00000000),
370 (0x001943c0 + 0x00000800),
371 (0x001943c0 + 0x00001000),
372 (0x001943c0 + 0x00001800),
373 (0x001d43c0 + 0x00000000),
374 (0x001d43c0 + 0x00000800),
375 (0x001d43c0 + 0x00001000),
376 (0x001d43c0 + 0x00001800),
377 };
378
379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
380 (0x000143e0 + 0x00000000),
381 (0x000143e0 + 0x00000800),
382 (0x000143e0 + 0x00001000),
383 (0x000143e0 + 0x00001800),
384 (0x000543e0 + 0x00000000),
385 (0x000543e0 + 0x00000800),
386 (0x000543e0 + 0x00001000),
387 (0x000543e0 + 0x00001800),
388 (0x000943e0 + 0x00000000),
389 (0x000943e0 + 0x00000800),
390 (0x000943e0 + 0x00001000),
391 (0x000943e0 + 0x00001800),
392 (0x000d43e0 + 0x00000000),
393 (0x000d43e0 + 0x00000800),
394 (0x000d43e0 + 0x00001000),
395 (0x000d43e0 + 0x00001800),
396 (0x001143e0 + 0x00000000),
397 (0x001143e0 + 0x00000800),
398 (0x001143e0 + 0x00001000),
399 (0x001143e0 + 0x00001800),
400 (0x001543e0 + 0x00000000),
401 (0x001543e0 + 0x00000800),
402 (0x001543e0 + 0x00001000),
403 (0x001543e0 + 0x00001800),
404 (0x001943e0 + 0x00000000),
405 (0x001943e0 + 0x00000800),
406 (0x001943e0 + 0x00001000),
407 (0x001943e0 + 0x00001800),
408 (0x001d43e0 + 0x00000000),
409 (0x001d43e0 + 0x00000800),
410 (0x001d43e0 + 0x00001000),
411 (0x001d43e0 + 0x00001800),
412 };
413
gmc_v9_0_is_multi_chiplet(struct amdgpu_device * adev)414 static inline bool gmc_v9_0_is_multi_chiplet(struct amdgpu_device *adev)
415 {
416 return !!adev->aid_mask;
417 }
418
gmc_v9_0_ecc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)419 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
420 struct amdgpu_irq_src *src,
421 unsigned int type,
422 enum amdgpu_interrupt_state state)
423 {
424 u32 bits, i, tmp, reg;
425
426 /* Devices newer then VEGA10/12 shall have these programming
427 * sequences performed by PSP BL
428 */
429 if (adev->asic_type >= CHIP_VEGA20)
430 return 0;
431
432 bits = 0x7f;
433
434 switch (state) {
435 case AMDGPU_IRQ_STATE_DISABLE:
436 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
437 reg = ecc_umc_mcumc_ctrl_addrs[i];
438 tmp = RREG32(reg);
439 tmp &= ~bits;
440 WREG32(reg, tmp);
441 }
442 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
443 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
444 tmp = RREG32(reg);
445 tmp &= ~bits;
446 WREG32(reg, tmp);
447 }
448 break;
449 case AMDGPU_IRQ_STATE_ENABLE:
450 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
451 reg = ecc_umc_mcumc_ctrl_addrs[i];
452 tmp = RREG32(reg);
453 tmp |= bits;
454 WREG32(reg, tmp);
455 }
456 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
457 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
458 tmp = RREG32(reg);
459 tmp |= bits;
460 WREG32(reg, tmp);
461 }
462 break;
463 default:
464 break;
465 }
466
467 return 0;
468 }
469
gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)470 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
471 struct amdgpu_irq_src *src,
472 unsigned int type,
473 enum amdgpu_interrupt_state state)
474 {
475 struct amdgpu_vmhub *hub;
476 u32 tmp, reg, bits, i, j;
477
478 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
479 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
480 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
481 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
482 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
483 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
484 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
485
486 switch (state) {
487 case AMDGPU_IRQ_STATE_DISABLE:
488 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
489 hub = &adev->vmhub[j];
490 for (i = 0; i < 16; i++) {
491 reg = hub->vm_context0_cntl + i;
492
493 /* This works because this interrupt is only
494 * enabled at init/resume and disabled in
495 * fini/suspend, so the overall state doesn't
496 * change over the course of suspend/resume.
497 */
498 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
499 continue;
500
501 if (j >= AMDGPU_MMHUB0(0))
502 tmp = RREG32_SOC15_IP(MMHUB, reg);
503 else
504 tmp = RREG32_XCC(reg, j);
505
506 tmp &= ~bits;
507
508 if (j >= AMDGPU_MMHUB0(0))
509 WREG32_SOC15_IP(MMHUB, reg, tmp);
510 else
511 WREG32_XCC(reg, tmp, j);
512 }
513 }
514 break;
515 case AMDGPU_IRQ_STATE_ENABLE:
516 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
517 hub = &adev->vmhub[j];
518 for (i = 0; i < 16; i++) {
519 reg = hub->vm_context0_cntl + i;
520
521 /* This works because this interrupt is only
522 * enabled at init/resume and disabled in
523 * fini/suspend, so the overall state doesn't
524 * change over the course of suspend/resume.
525 */
526 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
527 continue;
528
529 if (j >= AMDGPU_MMHUB0(0))
530 tmp = RREG32_SOC15_IP(MMHUB, reg);
531 else
532 tmp = RREG32_XCC(reg, j);
533
534 tmp |= bits;
535
536 if (j >= AMDGPU_MMHUB0(0))
537 WREG32_SOC15_IP(MMHUB, reg, tmp);
538 else
539 WREG32_XCC(reg, tmp, j);
540 }
541 }
542 break;
543 default:
544 break;
545 }
546
547 return 0;
548 }
549
gmc_v9_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)550 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 struct amdgpu_iv_entry *entry)
553 {
554 bool retry_fault = !!(entry->src_data[1] & 0x80);
555 bool write_fault = !!(entry->src_data[1] & 0x20);
556 uint32_t status = 0, cid = 0, rw = 0, fed = 0;
557 struct amdgpu_task_info *task_info;
558 struct amdgpu_vmhub *hub;
559 const char *mmhub_cid;
560 const char *hub_name;
561 unsigned int vmhub;
562 u64 addr;
563 uint32_t cam_index = 0;
564 int ret, xcc_id = 0;
565 uint32_t node_id;
566
567 node_id = entry->node_id;
568
569 addr = (u64)entry->src_data[0] << 12;
570 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
571
572 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
573 hub_name = "mmhub0";
574 vmhub = AMDGPU_MMHUB0(node_id / 4);
575 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
576 hub_name = "mmhub1";
577 vmhub = AMDGPU_MMHUB1(0);
578 } else {
579 hub_name = "gfxhub0";
580 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
581 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
582 node_id);
583 if (xcc_id < 0)
584 xcc_id = 0;
585 }
586 vmhub = xcc_id;
587 }
588 hub = &adev->vmhub[vmhub];
589
590 if (retry_fault) {
591 if (adev->irq.retry_cam_enabled) {
592 /* Delegate it to a different ring if the hardware hasn't
593 * already done it.
594 */
595 if (entry->ih == &adev->irq.ih) {
596 amdgpu_irq_delegate(adev, entry, 8);
597 return 1;
598 }
599
600 cam_index = entry->src_data[2] & 0x3ff;
601
602 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
603 addr, entry->timestamp, write_fault);
604 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
605 if (ret)
606 return 1;
607 } else {
608 /* Process it onyl if it's the first fault for this address */
609 if (entry->ih != &adev->irq.ih_soft &&
610 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
611 entry->timestamp))
612 return 1;
613
614 /* Delegate it to a different ring if the hardware hasn't
615 * already done it.
616 */
617 if (entry->ih == &adev->irq.ih) {
618 amdgpu_irq_delegate(adev, entry, 8);
619 return 1;
620 }
621
622 /* Try to handle the recoverable page faults by filling page
623 * tables
624 */
625 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
626 addr, entry->timestamp, write_fault))
627 return 1;
628 }
629 }
630
631 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault))
632 return 1;
633
634 if (!printk_ratelimit())
635 return 0;
636
637 dev_err(adev->dev,
638 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
639 retry_fault ? "retry" : "no-retry",
640 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
641
642 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
643 if (task_info) {
644 dev_err(adev->dev,
645 " for process %s pid %d thread %s pid %d)\n",
646 task_info->process_name, task_info->tgid,
647 task_info->task_name, task_info->pid);
648 amdgpu_vm_put_task_info(task_info);
649 }
650
651 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
652 addr, entry->client_id,
653 soc15_ih_clientid_name[entry->client_id]);
654
655 if (gmc_v9_0_is_multi_chiplet(adev))
656 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n",
657 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
658 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
659
660 if (amdgpu_sriov_vf(adev))
661 return 0;
662
663 /*
664 * Issue a dummy read to wait for the status register to
665 * be updated to avoid reading an incorrect value due to
666 * the new fast GRBM interface.
667 */
668 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
669 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
670 RREG32(hub->vm_l2_pro_fault_status);
671
672 status = RREG32(hub->vm_l2_pro_fault_status);
673 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
674 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
675 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
676
677 /* for fed error, kfd will handle it, return directly */
678 if (fed && amdgpu_ras_is_poison_mode_supported(adev) &&
679 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2)))
680 return 0;
681
682 /* Only print L2 fault status if the status register could be read and
683 * contains useful information
684 */
685 if (!status)
686 return 0;
687
688 if (!amdgpu_sriov_vf(adev))
689 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
690
691 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
692
693 dev_err(adev->dev,
694 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
695 status);
696 if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
697 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
698 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
699 gfxhub_client_ids[cid],
700 cid);
701 } else {
702 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
703 case IP_VERSION(9, 0, 0):
704 mmhub_cid = mmhub_client_ids_vega10[cid][rw];
705 break;
706 case IP_VERSION(9, 3, 0):
707 mmhub_cid = mmhub_client_ids_vega12[cid][rw];
708 break;
709 case IP_VERSION(9, 4, 0):
710 mmhub_cid = mmhub_client_ids_vega20[cid][rw];
711 break;
712 case IP_VERSION(9, 4, 1):
713 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
714 break;
715 case IP_VERSION(9, 1, 0):
716 case IP_VERSION(9, 2, 0):
717 mmhub_cid = mmhub_client_ids_raven[cid][rw];
718 break;
719 case IP_VERSION(1, 5, 0):
720 case IP_VERSION(2, 4, 0):
721 mmhub_cid = mmhub_client_ids_renoir[cid][rw];
722 break;
723 case IP_VERSION(1, 8, 0):
724 case IP_VERSION(9, 4, 2):
725 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
726 break;
727 default:
728 mmhub_cid = NULL;
729 break;
730 }
731 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
732 mmhub_cid ? mmhub_cid : "unknown", cid);
733 }
734 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
735 REG_GET_FIELD(status,
736 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
737 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
738 REG_GET_FIELD(status,
739 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
740 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
741 REG_GET_FIELD(status,
742 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
743 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
744 REG_GET_FIELD(status,
745 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
746 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
747 return 0;
748 }
749
750 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
751 .set = gmc_v9_0_vm_fault_interrupt_state,
752 .process = gmc_v9_0_process_interrupt,
753 };
754
755
756 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
757 .set = gmc_v9_0_ecc_interrupt_state,
758 .process = amdgpu_umc_process_ecc_irq,
759 };
760
gmc_v9_0_set_irq_funcs(struct amdgpu_device * adev)761 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
762 {
763 adev->gmc.vm_fault.num_types = 1;
764 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
765
766 if (!amdgpu_sriov_vf(adev) &&
767 !adev->gmc.xgmi.connected_to_cpu &&
768 !adev->gmc.is_app_apu) {
769 adev->gmc.ecc_irq.num_types = 1;
770 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
771 }
772 }
773
gmc_v9_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)774 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
775 uint32_t flush_type)
776 {
777 u32 req = 0;
778
779 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
780 PER_VMID_INVALIDATE_REQ, 1 << vmid);
781 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
782 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
783 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
784 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
785 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
786 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
787 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
788 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
789
790 return req;
791 }
792
793 /**
794 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
795 *
796 * @adev: amdgpu_device pointer
797 * @vmhub: vmhub type
798 *
799 */
gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device * adev,uint32_t vmhub)800 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
801 uint32_t vmhub)
802 {
803 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
804 gmc_v9_0_is_multi_chiplet(adev))
805 return false;
806
807 return ((vmhub == AMDGPU_MMHUB0(0) ||
808 vmhub == AMDGPU_MMHUB1(0)) &&
809 (!amdgpu_sriov_vf(adev)) &&
810 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
811 (adev->apu_flags & AMD_APU_IS_PICASSO))));
812 }
813
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device * adev,uint8_t vmid,uint16_t * p_pasid)814 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
815 uint8_t vmid, uint16_t *p_pasid)
816 {
817 uint32_t value;
818
819 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
820 + vmid);
821 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
822
823 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
824 }
825
826 /*
827 * GART
828 * VMID 0 is the physical GPU addresses as used by the kernel.
829 * VMIDs 1-15 are used for userspace clients and are handled
830 * by the amdgpu vm/hsa code.
831 */
832
833 /**
834 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
835 *
836 * @adev: amdgpu_device pointer
837 * @vmid: vm instance to flush
838 * @vmhub: which hub to flush
839 * @flush_type: the flush type
840 *
841 * Flush the TLB for the requested page table using certain type.
842 */
gmc_v9_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)843 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
844 uint32_t vmhub, uint32_t flush_type)
845 {
846 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
847 u32 j, inv_req, tmp, sem, req, ack, inst;
848 const unsigned int eng = 17;
849 struct amdgpu_vmhub *hub;
850
851 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
852
853 hub = &adev->vmhub[vmhub];
854 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
855 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
856 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
857 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
858
859 if (vmhub >= AMDGPU_MMHUB0(0))
860 inst = 0;
861 else
862 inst = vmhub;
863
864 /* This is necessary for SRIOV as well as for GFXOFF to function
865 * properly under bare metal
866 */
867 if (adev->gfx.kiq[inst].ring.sched.ready &&
868 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
869 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
870 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
871
872 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
873 1 << vmid, inst);
874 return;
875 }
876
877 /* This path is needed before KIQ/MES/GFXOFF are set up */
878 spin_lock(&adev->gmc.invalidate_lock);
879
880 /*
881 * It may lose gpuvm invalidate acknowldege state across power-gating
882 * off cycle, add semaphore acquire before invalidation and semaphore
883 * release after invalidation to avoid entering power gated state
884 * to WA the Issue
885 */
886
887 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
888 if (use_semaphore) {
889 for (j = 0; j < adev->usec_timeout; j++) {
890 /* a read return value of 1 means semaphore acquire */
891 if (vmhub >= AMDGPU_MMHUB0(0))
892 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
893 else
894 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
895 if (tmp & 0x1)
896 break;
897 udelay(1);
898 }
899
900 if (j >= adev->usec_timeout)
901 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
902 }
903
904 if (vmhub >= AMDGPU_MMHUB0(0))
905 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));
906 else
907 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));
908
909 /*
910 * Issue a dummy read to wait for the ACK register to
911 * be cleared to avoid a false ACK due to the new fast
912 * GRBM interface.
913 */
914 if ((vmhub == AMDGPU_GFXHUB(0)) &&
915 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
916 RREG32_NO_KIQ(req);
917
918 for (j = 0; j < adev->usec_timeout; j++) {
919 if (vmhub >= AMDGPU_MMHUB0(0))
920 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
921 else
922 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
923 if (tmp & (1 << vmid))
924 break;
925 udelay(1);
926 }
927
928 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
929 if (use_semaphore) {
930 /*
931 * add semaphore release after invalidation,
932 * write with 0 means semaphore release
933 */
934 if (vmhub >= AMDGPU_MMHUB0(0))
935 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));
936 else
937 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));
938 }
939
940 spin_unlock(&adev->gmc.invalidate_lock);
941
942 if (j < adev->usec_timeout)
943 return;
944
945 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
946 }
947
948 /**
949 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
950 *
951 * @adev: amdgpu_device pointer
952 * @pasid: pasid to be flush
953 * @flush_type: the flush type
954 * @all_hub: flush all hubs
955 * @inst: is used to select which instance of KIQ to use for the invalidation
956 *
957 * Flush the TLB for the requested pasid.
958 */
gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub,uint32_t inst)959 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
960 uint16_t pasid, uint32_t flush_type,
961 bool all_hub, uint32_t inst)
962 {
963 uint16_t queried;
964 int i, vmid;
965
966 for (vmid = 1; vmid < 16; vmid++) {
967 bool valid;
968
969 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
970 &queried);
971 if (!valid || queried != pasid)
972 continue;
973
974 if (all_hub) {
975 for_each_set_bit(i, adev->vmhubs_mask,
976 AMDGPU_MAX_VMHUBS)
977 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
978 flush_type);
979 } else {
980 gmc_v9_0_flush_gpu_tlb(adev, vmid,
981 AMDGPU_GFXHUB(0),
982 flush_type);
983 }
984 }
985 }
986
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)987 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
988 unsigned int vmid, uint64_t pd_addr)
989 {
990 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
991 struct amdgpu_device *adev = ring->adev;
992 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
993 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
994 unsigned int eng = ring->vm_inv_eng;
995
996 /*
997 * It may lose gpuvm invalidate acknowldege state across power-gating
998 * off cycle, add semaphore acquire before invalidation and semaphore
999 * release after invalidation to avoid entering power gated state
1000 * to WA the Issue
1001 */
1002
1003 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1004 if (use_semaphore)
1005 /* a read return value of 1 means semaphore acuqire */
1006 amdgpu_ring_emit_reg_wait(ring,
1007 hub->vm_inv_eng0_sem +
1008 hub->eng_distance * eng, 0x1, 0x1);
1009
1010 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1011 (hub->ctx_addr_distance * vmid),
1012 lower_32_bits(pd_addr));
1013
1014 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1015 (hub->ctx_addr_distance * vmid),
1016 upper_32_bits(pd_addr));
1017
1018 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1019 hub->eng_distance * eng,
1020 hub->vm_inv_eng0_ack +
1021 hub->eng_distance * eng,
1022 req, 1 << vmid);
1023
1024 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1025 if (use_semaphore)
1026 /*
1027 * add semaphore release after invalidation,
1028 * write with 0 means semaphore release
1029 */
1030 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1031 hub->eng_distance * eng, 0);
1032
1033 return pd_addr;
1034 }
1035
gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned int vmid,unsigned int pasid)1036 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
1037 unsigned int pasid)
1038 {
1039 struct amdgpu_device *adev = ring->adev;
1040 uint32_t reg;
1041
1042 /* Do nothing because there's no lut register for mmhub1. */
1043 if (ring->vm_hub == AMDGPU_MMHUB1(0))
1044 return;
1045
1046 if (ring->vm_hub == AMDGPU_GFXHUB(0))
1047 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1048 else
1049 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1050
1051 amdgpu_ring_emit_wreg(ring, reg, pasid);
1052 }
1053
1054 /*
1055 * PTE format on VEGA 10:
1056 * 63:59 reserved
1057 * 58:57 mtype
1058 * 56 F
1059 * 55 L
1060 * 54 P
1061 * 53 SW
1062 * 52 T
1063 * 50:48 reserved
1064 * 47:12 4k physical page base address
1065 * 11:7 fragment
1066 * 6 write
1067 * 5 read
1068 * 4 exe
1069 * 3 Z
1070 * 2 snooped
1071 * 1 system
1072 * 0 valid
1073 *
1074 * PDE format on VEGA 10:
1075 * 63:59 block fragment size
1076 * 58:55 reserved
1077 * 54 P
1078 * 53:48 reserved
1079 * 47:6 physical base address of PD or PTE
1080 * 5:3 reserved
1081 * 2 C
1082 * 1 system
1083 * 0 valid
1084 */
1085
gmc_v9_0_map_mtype(struct amdgpu_device * adev,uint32_t flags)1086 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1087
1088 {
1089 switch (flags) {
1090 case AMDGPU_VM_MTYPE_DEFAULT:
1091 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1092 case AMDGPU_VM_MTYPE_NC:
1093 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1094 case AMDGPU_VM_MTYPE_WC:
1095 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_WC);
1096 case AMDGPU_VM_MTYPE_RW:
1097 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_RW);
1098 case AMDGPU_VM_MTYPE_CC:
1099 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_CC);
1100 case AMDGPU_VM_MTYPE_UC:
1101 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC);
1102 default:
1103 return AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC);
1104 }
1105 }
1106
gmc_v9_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)1107 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1108 uint64_t *addr, uint64_t *flags)
1109 {
1110 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1111 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1112 BUG_ON(*addr & 0xFFFF00000000003FULL);
1113
1114 if (!adev->gmc.translate_further)
1115 return;
1116
1117 if (level == AMDGPU_VM_PDB1) {
1118 /* Set the block fragment size */
1119 if (!(*flags & AMDGPU_PDE_PTE))
1120 *flags |= AMDGPU_PDE_BFS(0x9);
1121
1122 } else if (level == AMDGPU_VM_PDB0) {
1123 if (*flags & AMDGPU_PDE_PTE) {
1124 *flags &= ~AMDGPU_PDE_PTE;
1125 if (!(*flags & AMDGPU_PTE_VALID))
1126 *addr |= 1 << PAGE_SHIFT;
1127 } else {
1128 *flags |= AMDGPU_PTE_TF;
1129 }
1130 }
1131 }
1132
gmc_v9_0_get_coherence_flags(struct amdgpu_device * adev,struct amdgpu_bo * bo,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)1133 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1134 struct amdgpu_bo *bo,
1135 struct amdgpu_bo_va_mapping *mapping,
1136 uint64_t *flags)
1137 {
1138 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1139 bool is_vram = bo->tbo.resource &&
1140 bo->tbo.resource->mem_type == TTM_PL_VRAM;
1141 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1142 AMDGPU_GEM_CREATE_EXT_COHERENT);
1143 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1144 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1145 struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1146 unsigned int mtype_local, mtype;
1147 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);
1148 bool snoop = false;
1149 bool is_local;
1150
1151 dma_resv_assert_held(bo->tbo.base.resv);
1152
1153 switch (gc_ip_version) {
1154 case IP_VERSION(9, 4, 1):
1155 case IP_VERSION(9, 4, 2):
1156 if (is_vram) {
1157 if (bo_adev == adev) {
1158 if (uncached)
1159 mtype = MTYPE_UC;
1160 else if (coherent)
1161 mtype = MTYPE_CC;
1162 else
1163 mtype = MTYPE_RW;
1164 /* FIXME: is this still needed? Or does
1165 * amdgpu_ttm_tt_pde_flags already handle this?
1166 */
1167 if (gc_ip_version == IP_VERSION(9, 4, 2) &&
1168 adev->gmc.xgmi.connected_to_cpu)
1169 snoop = true;
1170 } else {
1171 if (uncached || coherent)
1172 mtype = MTYPE_UC;
1173 else
1174 mtype = MTYPE_NC;
1175 if (mapping->bo_va->is_xgmi)
1176 snoop = true;
1177 }
1178 } else {
1179 if (uncached || coherent)
1180 mtype = MTYPE_UC;
1181 else
1182 mtype = MTYPE_NC;
1183 /* FIXME: is this still needed? Or does
1184 * amdgpu_ttm_tt_pde_flags already handle this?
1185 */
1186 snoop = true;
1187 }
1188 break;
1189 case IP_VERSION(9, 4, 3):
1190 case IP_VERSION(9, 4, 4):
1191 case IP_VERSION(9, 5, 0):
1192 /* Only local VRAM BOs or system memory on non-NUMA APUs
1193 * can be assumed to be local in their entirety. Choose
1194 * MTYPE_NC as safe fallback for all system memory BOs on
1195 * NUMA systems. Their MTYPE can be overridden per-page in
1196 * gmc_v9_0_override_vm_pte_flags.
1197 */
1198 mtype_local = MTYPE_RW;
1199 if (amdgpu_mtype_local == 1) {
1200 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
1201 mtype_local = MTYPE_NC;
1202 } else if (amdgpu_mtype_local == 2) {
1203 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n");
1204 mtype_local = MTYPE_CC;
1205 } else {
1206 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
1207 }
1208 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1209 num_possible_nodes() <= 1) ||
1210 (is_vram && adev == bo_adev &&
1211 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1212 snoop = true;
1213 if (uncached) {
1214 mtype = MTYPE_UC;
1215 } else if (ext_coherent) {
1216 if (gc_ip_version == IP_VERSION(9, 5, 0) || adev->rev_id)
1217 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1218 else
1219 mtype = MTYPE_UC;
1220 } else if (adev->flags & AMD_IS_APU) {
1221 mtype = is_local ? mtype_local : MTYPE_NC;
1222 } else {
1223 /* dGPU */
1224 if (is_local)
1225 mtype = mtype_local;
1226 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram)
1227 mtype = MTYPE_UC;
1228 else
1229 mtype = MTYPE_NC;
1230 }
1231
1232 break;
1233 default:
1234 if (uncached || coherent)
1235 mtype = MTYPE_UC;
1236 else
1237 mtype = MTYPE_NC;
1238
1239 /* FIXME: is this still needed? Or does
1240 * amdgpu_ttm_tt_pde_flags already handle this?
1241 */
1242 if (!is_vram)
1243 snoop = true;
1244 }
1245
1246 if (mtype != MTYPE_NC)
1247 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype);
1248
1249 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1250 }
1251
gmc_v9_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_bo_va_mapping * mapping,uint64_t * flags)1252 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1253 struct amdgpu_bo_va_mapping *mapping,
1254 uint64_t *flags)
1255 {
1256 struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1257
1258 *flags &= ~AMDGPU_PTE_EXECUTABLE;
1259 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1260
1261 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1262 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1263
1264 if (mapping->flags & AMDGPU_PTE_PRT) {
1265 *flags |= AMDGPU_PTE_PRT;
1266 *flags &= ~AMDGPU_PTE_VALID;
1267 }
1268
1269 if ((*flags & AMDGPU_PTE_VALID) && bo)
1270 gmc_v9_0_get_coherence_flags(adev, bo, mapping, flags);
1271 }
1272
gmc_v9_0_override_vm_pte_flags(struct amdgpu_device * adev,struct amdgpu_vm * vm,uint64_t addr,uint64_t * flags)1273 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1274 struct amdgpu_vm *vm,
1275 uint64_t addr, uint64_t *flags)
1276 {
1277 int local_node, nid;
1278
1279 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1280 * memory can use more efficient MTYPEs.
1281 */
1282 if (!(adev->flags & AMD_IS_APU) ||
1283 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))
1284 return;
1285
1286 /* Only direct-mapped memory allows us to determine the NUMA node from
1287 * the DMA address.
1288 */
1289 if (!adev->ram_is_direct_mapped) {
1290 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1291 return;
1292 }
1293
1294 /* MTYPE_NC is the same default and can be overridden.
1295 * MTYPE_UC will be present if the memory is extended-coherent
1296 * and can also be overridden.
1297 */
1298 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1299 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) &&
1300 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1301 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) {
1302 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1303 return;
1304 }
1305
1306 /* FIXME: Only supported on native mode for now. For carve-out, the
1307 * NUMA affinity of the GPU/VM needs to come from the PCI info because
1308 * memory partitions are not associated with different NUMA nodes.
1309 */
1310 if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1311 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1312 } else {
1313 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1314 return;
1315 }
1316
1317 /* Only handle real RAM. Mappings of PCIe resources don't have struct
1318 * page or NUMA nodes.
1319 */
1320 if (!page_is_ram(addr >> PAGE_SHIFT)) {
1321 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1322 return;
1323 }
1324 nid = pfn_to_nid(addr >> PAGE_SHIFT);
1325 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1326 vm->mem_id, local_node, nid);
1327 if (nid == local_node) {
1328 uint64_t old_flags = *flags;
1329 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1330 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) {
1331 unsigned int mtype_local = MTYPE_RW;
1332
1333 if (amdgpu_mtype_local == 1)
1334 mtype_local = MTYPE_NC;
1335 else if (amdgpu_mtype_local == 2)
1336 mtype_local = MTYPE_CC;
1337
1338 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local);
1339 } else if (adev->rev_id) {
1340 /* MTYPE_UC case */
1341 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);
1342 }
1343
1344 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1345 old_flags, *flags);
1346 }
1347 }
1348
gmc_v9_0_get_vbios_fb_size(struct amdgpu_device * adev)1349 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1350 {
1351 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1352 unsigned int size;
1353
1354 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1355
1356 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1357 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1358 } else {
1359 u32 viewport;
1360
1361 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1362 case IP_VERSION(1, 0, 0):
1363 case IP_VERSION(1, 0, 1):
1364 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1365 size = (REG_GET_FIELD(viewport,
1366 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1367 REG_GET_FIELD(viewport,
1368 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1369 4);
1370 break;
1371 case IP_VERSION(2, 1, 0):
1372 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1373 size = (REG_GET_FIELD(viewport,
1374 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1375 REG_GET_FIELD(viewport,
1376 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1377 4);
1378 break;
1379 default:
1380 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1381 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1382 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1383 4);
1384 break;
1385 }
1386 }
1387
1388 return size;
1389 }
1390
1391 static enum amdgpu_memory_partition
gmc_v9_0_get_memory_partition(struct amdgpu_device * adev,u32 * supp_modes)1392 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
1393 {
1394 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
1395
1396 if (adev->nbio.funcs->get_memory_partition_mode)
1397 mode = adev->nbio.funcs->get_memory_partition_mode(adev,
1398 supp_modes);
1399
1400 return mode;
1401 }
1402
1403 static enum amdgpu_memory_partition
gmc_v9_0_query_vf_memory_partition(struct amdgpu_device * adev)1404 gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev)
1405 {
1406 switch (adev->gmc.num_mem_partitions) {
1407 case 0:
1408 return UNKNOWN_MEMORY_PARTITION_MODE;
1409 case 1:
1410 return AMDGPU_NPS1_PARTITION_MODE;
1411 case 2:
1412 return AMDGPU_NPS2_PARTITION_MODE;
1413 case 4:
1414 return AMDGPU_NPS4_PARTITION_MODE;
1415 default:
1416 return AMDGPU_NPS1_PARTITION_MODE;
1417 }
1418
1419 return AMDGPU_NPS1_PARTITION_MODE;
1420 }
1421
1422 static enum amdgpu_memory_partition
gmc_v9_0_query_memory_partition(struct amdgpu_device * adev)1423 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
1424 {
1425 if (amdgpu_sriov_vf(adev))
1426 return gmc_v9_0_query_vf_memory_partition(adev);
1427
1428 return gmc_v9_0_get_memory_partition(adev, NULL);
1429 }
1430
gmc_v9_0_need_reset_on_init(struct amdgpu_device * adev)1431 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)
1432 {
1433 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested &&
1434 adev->nbio.funcs->is_nps_switch_requested(adev)) {
1435 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;
1436 return true;
1437 }
1438
1439 return false;
1440 }
1441
1442 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1443 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1444 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1445 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1446 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1447 .map_mtype = gmc_v9_0_map_mtype,
1448 .get_vm_pde = gmc_v9_0_get_vm_pde,
1449 .get_vm_pte = gmc_v9_0_get_vm_pte,
1450 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1451 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1452 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
1453 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition,
1454 .need_reset_on_init = &gmc_v9_0_need_reset_on_init,
1455 };
1456
gmc_v9_0_set_gmc_funcs(struct amdgpu_device * adev)1457 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1458 {
1459 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1460 }
1461
gmc_v9_0_set_umc_funcs(struct amdgpu_device * adev)1462 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1463 {
1464 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1465 case IP_VERSION(6, 0, 0):
1466 adev->umc.funcs = &umc_v6_0_funcs;
1467 break;
1468 case IP_VERSION(6, 1, 1):
1469 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1470 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1471 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1472 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1473 adev->umc.retire_unit = 1;
1474 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1475 adev->umc.ras = &umc_v6_1_ras;
1476 break;
1477 case IP_VERSION(6, 1, 2):
1478 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1479 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1480 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1481 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1482 adev->umc.retire_unit = 1;
1483 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1484 adev->umc.ras = &umc_v6_1_ras;
1485 break;
1486 case IP_VERSION(6, 7, 0):
1487 adev->umc.max_ras_err_cnt_per_query =
1488 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1489 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1490 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1491 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1492 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1493 if (!adev->gmc.xgmi.connected_to_cpu)
1494 adev->umc.ras = &umc_v6_7_ras;
1495 if (1 & adev->smuio.funcs->get_die_id(adev))
1496 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1497 else
1498 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1499 break;
1500 case IP_VERSION(12, 0, 0):
1501 case IP_VERSION(12, 5, 0):
1502 adev->umc.max_ras_err_cnt_per_query =
1503 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1504 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1505 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1506 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1507 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1508 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1509 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1510 adev->umc.ras = &umc_v12_0_ras;
1511 break;
1512 default:
1513 break;
1514 }
1515 }
1516
gmc_v9_0_set_mmhub_funcs(struct amdgpu_device * adev)1517 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1518 {
1519 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1520 case IP_VERSION(9, 4, 1):
1521 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1522 break;
1523 case IP_VERSION(9, 4, 2):
1524 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1525 break;
1526 case IP_VERSION(1, 8, 0):
1527 case IP_VERSION(1, 8, 1):
1528 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1529 break;
1530 default:
1531 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1532 break;
1533 }
1534 }
1535
gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device * adev)1536 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1537 {
1538 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1539 case IP_VERSION(9, 4, 0):
1540 adev->mmhub.ras = &mmhub_v1_0_ras;
1541 break;
1542 case IP_VERSION(9, 4, 1):
1543 adev->mmhub.ras = &mmhub_v9_4_ras;
1544 break;
1545 case IP_VERSION(9, 4, 2):
1546 adev->mmhub.ras = &mmhub_v1_7_ras;
1547 break;
1548 case IP_VERSION(1, 8, 0):
1549 case IP_VERSION(1, 8, 1):
1550 adev->mmhub.ras = &mmhub_v1_8_ras;
1551 break;
1552 default:
1553 /* mmhub ras is not available */
1554 break;
1555 }
1556 }
1557
gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device * adev)1558 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1559 {
1560 if (gmc_v9_0_is_multi_chiplet(adev))
1561 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1562 else
1563 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1564 }
1565
gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device * adev)1566 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1567 {
1568 adev->hdp.ras = &hdp_v4_0_ras;
1569 }
1570
gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device * adev)1571 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1572 {
1573 struct amdgpu_mca *mca = &adev->mca;
1574
1575 /* is UMC the right IP to check for MCA? Maybe DF? */
1576 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1577 case IP_VERSION(6, 7, 0):
1578 if (!adev->gmc.xgmi.connected_to_cpu) {
1579 mca->mp0.ras = &mca_v3_0_mp0_ras;
1580 mca->mp1.ras = &mca_v3_0_mp1_ras;
1581 mca->mpio.ras = &mca_v3_0_mpio_ras;
1582 }
1583 break;
1584 default:
1585 break;
1586 }
1587 }
1588
gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device * adev)1589 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1590 {
1591 if (!adev->gmc.xgmi.connected_to_cpu)
1592 adev->gmc.xgmi.ras = &xgmi_ras;
1593 }
1594
gmc_v9_0_init_nps_details(struct amdgpu_device * adev)1595 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)
1596 {
1597 enum amdgpu_memory_partition mode;
1598 uint32_t supp_modes;
1599 int i;
1600
1601 adev->gmc.supported_nps_modes = 0;
1602
1603 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
1604 return;
1605
1606 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1607
1608 /* Mode detected by hardware and supported modes available */
1609 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) {
1610 while ((i = ffs(supp_modes))) {
1611 if (AMDGPU_ALL_NPS_MASK & BIT(i))
1612 adev->gmc.supported_nps_modes |= BIT(i);
1613 supp_modes &= supp_modes - 1;
1614 }
1615 } else {
1616 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep
1617 * supported modes as 0.
1618 */
1619 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1620 case IP_VERSION(9, 4, 3):
1621 case IP_VERSION(9, 4, 4):
1622 adev->gmc.supported_nps_modes =
1623 BIT(AMDGPU_NPS1_PARTITION_MODE) |
1624 BIT(AMDGPU_NPS4_PARTITION_MODE);
1625 break;
1626 default:
1627 break;
1628 }
1629 }
1630 }
1631
gmc_v9_0_early_init(struct amdgpu_ip_block * ip_block)1632 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)
1633 {
1634 struct amdgpu_device *adev = ip_block->adev;
1635
1636 /*
1637 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1638 * in their IP discovery tables
1639 */
1640 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1641 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1642 gmc_v9_0_is_multi_chiplet(adev))
1643 adev->gmc.xgmi.supported = true;
1644
1645 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1646 adev->gmc.xgmi.supported = true;
1647 adev->gmc.xgmi.connected_to_cpu =
1648 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1649 }
1650
1651 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1652 enum amdgpu_pkg_type pkg_type =
1653 adev->smuio.funcs->get_pkg_type(adev);
1654 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1655 * and the APU, can be in used two possible modes:
1656 * - carveout mode
1657 * - native APU mode
1658 * "is_app_apu" can be used to identify the APU in the native
1659 * mode.
1660 */
1661 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1662 !pci_resource_len(adev->pdev, 0));
1663 }
1664
1665 gmc_v9_0_set_gmc_funcs(adev);
1666 gmc_v9_0_set_irq_funcs(adev);
1667 gmc_v9_0_set_umc_funcs(adev);
1668 gmc_v9_0_set_mmhub_funcs(adev);
1669 gmc_v9_0_set_mmhub_ras_funcs(adev);
1670 gmc_v9_0_set_gfxhub_funcs(adev);
1671 gmc_v9_0_set_hdp_ras_funcs(adev);
1672 gmc_v9_0_set_mca_ras_funcs(adev);
1673 gmc_v9_0_set_xgmi_ras_funcs(adev);
1674
1675 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1676 adev->gmc.shared_aperture_end =
1677 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1678 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1679 adev->gmc.private_aperture_end =
1680 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1681 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1682
1683 return 0;
1684 }
1685
gmc_v9_0_late_init(struct amdgpu_ip_block * ip_block)1686 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block)
1687 {
1688 struct amdgpu_device *adev = ip_block->adev;
1689 int r;
1690
1691 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1692 if (r)
1693 return r;
1694
1695 /*
1696 * Workaround performance drop issue with VBIOS enables partial
1697 * writes, while disables HBM ECC for vega10.
1698 */
1699 if (!amdgpu_sriov_vf(adev) &&
1700 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1701 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1702 if (adev->df.funcs &&
1703 adev->df.funcs->enable_ecc_force_par_wr_rmw)
1704 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1705 }
1706 }
1707
1708 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1709 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1710 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1711 }
1712
1713 r = amdgpu_gmc_ras_late_init(adev);
1714 if (r)
1715 return r;
1716
1717 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1718 }
1719
gmc_v9_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)1720 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1721 struct amdgpu_gmc *mc)
1722 {
1723 u64 base = adev->mmhub.funcs->get_fb_location(adev);
1724
1725 amdgpu_gmc_set_agp_default(adev, mc);
1726
1727 /* add the xgmi offset of the physical node */
1728 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1729 if (adev->gmc.xgmi.connected_to_cpu) {
1730 amdgpu_gmc_sysvm_location(adev, mc);
1731 } else {
1732 amdgpu_gmc_vram_location(adev, mc, base);
1733 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1734 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1735 amdgpu_gmc_agp_location(adev, mc);
1736 }
1737 /* base offset of vram pages */
1738 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1739
1740 /* XXX: add the xgmi offset of the physical node? */
1741 adev->vm_manager.vram_base_offset +=
1742 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1743 }
1744
1745 /**
1746 * gmc_v9_0_mc_init - initialize the memory controller driver params
1747 *
1748 * @adev: amdgpu_device pointer
1749 *
1750 * Look up the amount of vram, vram width, and decide how to place
1751 * vram and gart within the GPU's physical address space.
1752 * Returns 0 for success.
1753 */
gmc_v9_0_mc_init(struct amdgpu_device * adev)1754 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1755 {
1756 int r;
1757
1758 /* size in MB on si */
1759 if (!adev->gmc.is_app_apu) {
1760 adev->gmc.mc_vram_size =
1761 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1762 } else {
1763 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1764 adev->gmc.mc_vram_size = 0;
1765 }
1766 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1767
1768 if (!(adev->flags & AMD_IS_APU) &&
1769 !adev->gmc.xgmi.connected_to_cpu) {
1770 r = amdgpu_device_resize_fb_bar(adev);
1771 if (r)
1772 return r;
1773 }
1774 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1775 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1776
1777 #ifdef CONFIG_X86_64
1778 /*
1779 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1780 * interface can use VRAM through here as it appears system reserved
1781 * memory in host address space.
1782 *
1783 * For APUs, VRAM is just the stolen system memory and can be accessed
1784 * directly.
1785 *
1786 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1787 */
1788
1789 /* check whether both host-gpu and gpu-gpu xgmi links exist */
1790 if ((!amdgpu_sriov_vf(adev) &&
1791 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1792 (adev->gmc.xgmi.supported &&
1793 adev->gmc.xgmi.connected_to_cpu)) {
1794 adev->gmc.aper_base =
1795 adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1796 adev->gmc.xgmi.physical_node_id *
1797 adev->gmc.xgmi.node_segment_size;
1798 adev->gmc.aper_size = adev->gmc.real_vram_size;
1799 }
1800
1801 #endif
1802 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1803
1804 /* set the gart size */
1805 if (amdgpu_gart_size == -1) {
1806 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1807 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
1808 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
1809 case IP_VERSION(9, 4, 0):
1810 case IP_VERSION(9, 4, 1):
1811 case IP_VERSION(9, 4, 2):
1812 case IP_VERSION(9, 4, 3):
1813 case IP_VERSION(9, 4, 4):
1814 case IP_VERSION(9, 5, 0):
1815 default:
1816 adev->gmc.gart_size = 512ULL << 20;
1817 break;
1818 case IP_VERSION(9, 1, 0): /* DCE SG support */
1819 case IP_VERSION(9, 2, 2): /* DCE SG support */
1820 case IP_VERSION(9, 3, 0):
1821 adev->gmc.gart_size = 1024ULL << 20;
1822 break;
1823 }
1824 } else {
1825 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1826 }
1827
1828 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1829
1830 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1831
1832 return 0;
1833 }
1834
gmc_v9_0_gart_init(struct amdgpu_device * adev)1835 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1836 {
1837 int r;
1838
1839 if (adev->gart.bo) {
1840 WARN(1, "VEGA10 PCIE GART already initialized\n");
1841 return 0;
1842 }
1843
1844 if (adev->gmc.xgmi.connected_to_cpu) {
1845 adev->gmc.vmid0_page_table_depth = 1;
1846 adev->gmc.vmid0_page_table_block_size = 12;
1847 } else {
1848 adev->gmc.vmid0_page_table_depth = 0;
1849 adev->gmc.vmid0_page_table_block_size = 0;
1850 }
1851
1852 /* Initialize common gart structure */
1853 r = amdgpu_gart_init(adev);
1854 if (r)
1855 return r;
1856 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1857 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) |
1858 AMDGPU_PTE_EXECUTABLE;
1859
1860 if (!adev->gmc.real_vram_size) {
1861 dev_info(adev->dev, "Put GART in system memory for APU\n");
1862 r = amdgpu_gart_table_ram_alloc(adev);
1863 if (r)
1864 dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1865 } else {
1866 r = amdgpu_gart_table_vram_alloc(adev);
1867 if (r)
1868 return r;
1869
1870 if (adev->gmc.xgmi.connected_to_cpu)
1871 r = amdgpu_gmc_pdb0_alloc(adev);
1872 }
1873
1874 return r;
1875 }
1876
1877 /**
1878 * gmc_v9_0_save_registers - saves regs
1879 *
1880 * @adev: amdgpu_device pointer
1881 *
1882 * This saves potential register values that should be
1883 * restored upon resume
1884 */
gmc_v9_0_save_registers(struct amdgpu_device * adev)1885 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1886 {
1887 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1888 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1889 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1890 }
1891
gmc_v9_0_validate_partition_info(struct amdgpu_device * adev)1892 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
1893 {
1894 enum amdgpu_memory_partition mode;
1895 u32 supp_modes;
1896 bool valid;
1897
1898 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1899
1900 /* Mode detected by hardware not present in supported modes */
1901 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &&
1902 !(BIT(mode - 1) & supp_modes))
1903 return false;
1904
1905 switch (mode) {
1906 case UNKNOWN_MEMORY_PARTITION_MODE:
1907 case AMDGPU_NPS1_PARTITION_MODE:
1908 valid = (adev->gmc.num_mem_partitions == 1);
1909 break;
1910 case AMDGPU_NPS2_PARTITION_MODE:
1911 valid = (adev->gmc.num_mem_partitions == 2);
1912 break;
1913 case AMDGPU_NPS4_PARTITION_MODE:
1914 valid = (adev->gmc.num_mem_partitions == 3 ||
1915 adev->gmc.num_mem_partitions == 4);
1916 break;
1917 default:
1918 valid = false;
1919 }
1920
1921 return valid;
1922 }
1923
gmc_v9_0_is_node_present(int * node_ids,int num_ids,int nid)1924 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
1925 {
1926 int i;
1927
1928 /* Check if node with id 'nid' is present in 'node_ids' array */
1929 for (i = 0; i < num_ids; ++i)
1930 if (node_ids[i] == nid)
1931 return true;
1932
1933 return false;
1934 }
1935
1936 static void
gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device * adev,struct amdgpu_mem_partition_info * mem_ranges)1937 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
1938 struct amdgpu_mem_partition_info *mem_ranges)
1939 {
1940 struct amdgpu_numa_info numa_info;
1941 int node_ids[MAX_MEM_RANGES];
1942 int num_ranges = 0, ret;
1943 int num_xcc, xcc_id;
1944 uint32_t xcc_mask;
1945
1946 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1947 xcc_mask = (1U << num_xcc) - 1;
1948
1949 for_each_inst(xcc_id, xcc_mask) {
1950 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
1951 if (ret)
1952 continue;
1953
1954 if (numa_info.nid == NUMA_NO_NODE) {
1955 mem_ranges[0].size = numa_info.size;
1956 mem_ranges[0].numa.node = numa_info.nid;
1957 num_ranges = 1;
1958 break;
1959 }
1960
1961 if (gmc_v9_0_is_node_present(node_ids, num_ranges,
1962 numa_info.nid))
1963 continue;
1964
1965 node_ids[num_ranges] = numa_info.nid;
1966 mem_ranges[num_ranges].numa.node = numa_info.nid;
1967 mem_ranges[num_ranges].size = numa_info.size;
1968 ++num_ranges;
1969 }
1970
1971 adev->gmc.num_mem_partitions = num_ranges;
1972 }
1973
1974 static void
gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device * adev,struct amdgpu_mem_partition_info * mem_ranges)1975 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
1976 struct amdgpu_mem_partition_info *mem_ranges)
1977 {
1978 enum amdgpu_memory_partition mode;
1979 u32 start_addr = 0, size;
1980 int i, r, l;
1981
1982 mode = gmc_v9_0_query_memory_partition(adev);
1983
1984 switch (mode) {
1985 case UNKNOWN_MEMORY_PARTITION_MODE:
1986 adev->gmc.num_mem_partitions = 0;
1987 break;
1988 case AMDGPU_NPS1_PARTITION_MODE:
1989 adev->gmc.num_mem_partitions = 1;
1990 break;
1991 case AMDGPU_NPS2_PARTITION_MODE:
1992 adev->gmc.num_mem_partitions = 2;
1993 break;
1994 case AMDGPU_NPS4_PARTITION_MODE:
1995 if (adev->flags & AMD_IS_APU)
1996 adev->gmc.num_mem_partitions = 3;
1997 else
1998 adev->gmc.num_mem_partitions = 4;
1999 break;
2000 default:
2001 adev->gmc.num_mem_partitions = 1;
2002 break;
2003 }
2004
2005 /* Use NPS range info, if populated */
2006 r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges,
2007 &adev->gmc.num_mem_partitions);
2008 if (!r) {
2009 l = 0;
2010 for (i = 1; i < adev->gmc.num_mem_partitions; ++i) {
2011 if (mem_ranges[i].range.lpfn >
2012 mem_ranges[i - 1].range.lpfn)
2013 l = i;
2014 }
2015
2016 } else {
2017 if (!adev->gmc.num_mem_partitions) {
2018 dev_err(adev->dev,
2019 "Not able to detect NPS mode, fall back to NPS1");
2020 adev->gmc.num_mem_partitions = 1;
2021 }
2022 /* Fallback to sw based calculation */
2023 size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT;
2024 size /= adev->gmc.num_mem_partitions;
2025
2026 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
2027 mem_ranges[i].range.fpfn = start_addr;
2028 mem_ranges[i].size =
2029 ((u64)size << AMDGPU_GPU_PAGE_SHIFT);
2030 mem_ranges[i].range.lpfn = start_addr + size - 1;
2031 start_addr += size;
2032 }
2033
2034 l = adev->gmc.num_mem_partitions - 1;
2035 }
2036
2037 /* Adjust the last one */
2038 mem_ranges[l].range.lpfn =
2039 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
2040 mem_ranges[l].size =
2041 adev->gmc.real_vram_size -
2042 ((u64)mem_ranges[l].range.fpfn << AMDGPU_GPU_PAGE_SHIFT);
2043 }
2044
gmc_v9_0_init_mem_ranges(struct amdgpu_device * adev)2045 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
2046 {
2047 bool valid;
2048
2049 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,
2050 sizeof(struct amdgpu_mem_partition_info),
2051 GFP_KERNEL);
2052 if (!adev->gmc.mem_partitions)
2053 return -ENOMEM;
2054
2055 /* TODO : Get the range from PSP/Discovery for dGPU */
2056 if (adev->gmc.is_app_apu)
2057 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
2058 else
2059 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2060
2061 if (amdgpu_sriov_vf(adev))
2062 valid = true;
2063 else
2064 valid = gmc_v9_0_validate_partition_info(adev);
2065 if (!valid) {
2066 /* TODO: handle invalid case */
2067 dev_WARN(adev->dev,
2068 "Mem ranges not matching with hardware config");
2069 }
2070
2071 return 0;
2072 }
2073
gmc_v9_4_3_init_vram_info(struct amdgpu_device * adev)2074 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
2075 {
2076 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2077 adev->gmc.vram_width = 128 * 64;
2078 }
2079
gmc_v9_0_sw_init(struct amdgpu_ip_block * ip_block)2080 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
2081 {
2082 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
2083 struct amdgpu_device *adev = ip_block->adev;
2084 unsigned long inst_mask = adev->aid_mask;
2085
2086 adev->gfxhub.funcs->init(adev);
2087
2088 adev->mmhub.funcs->init(adev);
2089
2090 spin_lock_init(&adev->gmc.invalidate_lock);
2091
2092 if (gmc_v9_0_is_multi_chiplet(adev)) {
2093 gmc_v9_4_3_init_vram_info(adev);
2094 } else if (!adev->bios) {
2095 if (adev->flags & AMD_IS_APU) {
2096 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
2097 adev->gmc.vram_width = 64 * 64;
2098 } else {
2099 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
2100 adev->gmc.vram_width = 128 * 64;
2101 }
2102 } else {
2103 r = amdgpu_atomfirmware_get_vram_info(adev,
2104 &vram_width, &vram_type, &vram_vendor);
2105 if (amdgpu_sriov_vf(adev))
2106 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
2107 * and DF related registers is not readable, seems hardcord is the
2108 * only way to set the correct vram_width
2109 */
2110 adev->gmc.vram_width = 2048;
2111 else if (amdgpu_emu_mode != 1)
2112 adev->gmc.vram_width = vram_width;
2113
2114 if (!adev->gmc.vram_width) {
2115 int chansize, numchan;
2116
2117 /* hbm memory channel size */
2118 if (adev->flags & AMD_IS_APU)
2119 chansize = 64;
2120 else
2121 chansize = 128;
2122 if (adev->df.funcs &&
2123 adev->df.funcs->get_hbm_channel_number) {
2124 numchan = adev->df.funcs->get_hbm_channel_number(adev);
2125 adev->gmc.vram_width = numchan * chansize;
2126 }
2127 }
2128
2129 adev->gmc.vram_type = vram_type;
2130 adev->gmc.vram_vendor = vram_vendor;
2131 }
2132 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2133 case IP_VERSION(9, 1, 0):
2134 case IP_VERSION(9, 2, 2):
2135 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2136 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2137
2138 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
2139 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2140 } else {
2141 /* vm_size is 128TB + 512GB for legacy 3-level page support */
2142 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
2143 adev->gmc.translate_further =
2144 adev->vm_manager.num_level > 1;
2145 }
2146 break;
2147 case IP_VERSION(9, 0, 1):
2148 case IP_VERSION(9, 2, 1):
2149 case IP_VERSION(9, 4, 0):
2150 case IP_VERSION(9, 3, 0):
2151 case IP_VERSION(9, 4, 2):
2152 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2153 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2154
2155 /*
2156 * To fulfill 4-level page support,
2157 * vm size is 256TB (48bit), maximum size of Vega10,
2158 * block size 512 (9bit)
2159 */
2160
2161 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2162 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
2163 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2164 break;
2165 case IP_VERSION(9, 4, 1):
2166 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2167 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2168 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
2169
2170 /* Keep the vm size same with Vega20 */
2171 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2172 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2173 break;
2174 case IP_VERSION(9, 4, 3):
2175 case IP_VERSION(9, 4, 4):
2176 case IP_VERSION(9, 5, 0):
2177 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
2178 NUM_XCC(adev->gfx.xcc_mask));
2179
2180 inst_mask <<= AMDGPU_MMHUB0(0);
2181 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2182
2183 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2184 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2185 break;
2186 default:
2187 break;
2188 }
2189
2190 /* This interrupt is VMC page fault.*/
2191 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
2192 &adev->gmc.vm_fault);
2193 if (r)
2194 return r;
2195
2196 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
2197 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
2198 &adev->gmc.vm_fault);
2199 if (r)
2200 return r;
2201 }
2202
2203 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
2204 &adev->gmc.vm_fault);
2205
2206 if (r)
2207 return r;
2208
2209 if (!amdgpu_sriov_vf(adev) &&
2210 !adev->gmc.xgmi.connected_to_cpu &&
2211 !adev->gmc.is_app_apu) {
2212 /* interrupt sent to DF. */
2213 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
2214 &adev->gmc.ecc_irq);
2215 if (r)
2216 return r;
2217 }
2218
2219 /* Set the internal MC address mask
2220 * This is the max address of the GPU's
2221 * internal address space.
2222 */
2223 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
2224
2225 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
2226 IP_VERSION(9, 4, 2) ?
2227 48 :
2228 44;
2229 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
2230 if (r) {
2231 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
2232 return r;
2233 }
2234 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
2235
2236 r = gmc_v9_0_mc_init(adev);
2237 if (r)
2238 return r;
2239
2240 amdgpu_gmc_get_vbios_allocations(adev);
2241
2242 if (gmc_v9_0_is_multi_chiplet(adev)) {
2243 r = gmc_v9_0_init_mem_ranges(adev);
2244 if (r)
2245 return r;
2246 }
2247
2248 /* Memory manager */
2249 r = amdgpu_bo_init(adev);
2250 if (r)
2251 return r;
2252
2253 r = gmc_v9_0_gart_init(adev);
2254 if (r)
2255 return r;
2256
2257 gmc_v9_0_init_nps_details(adev);
2258 /*
2259 * number of VMs
2260 * VMID 0 is reserved for System
2261 * amdgpu graphics/compute will use VMIDs 1..n-1
2262 * amdkfd will use VMIDs n..15
2263 *
2264 * The first KFD VMID is 8 for GPUs with graphics, 3 for
2265 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2266 * for video processing.
2267 */
2268 adev->vm_manager.first_kfd_vmid =
2269 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2270 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2271 gmc_v9_0_is_multi_chiplet(adev)) ?
2272 3 :
2273 8;
2274
2275 amdgpu_vm_manager_init(adev);
2276
2277 gmc_v9_0_save_registers(adev);
2278
2279 r = amdgpu_gmc_ras_sw_init(adev);
2280 if (r)
2281 return r;
2282
2283 if (gmc_v9_0_is_multi_chiplet(adev))
2284 amdgpu_gmc_sysfs_init(adev);
2285
2286 return 0;
2287 }
2288
gmc_v9_0_sw_fini(struct amdgpu_ip_block * ip_block)2289 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)
2290 {
2291 struct amdgpu_device *adev = ip_block->adev;
2292
2293 if (gmc_v9_0_is_multi_chiplet(adev))
2294 amdgpu_gmc_sysfs_fini(adev);
2295
2296 amdgpu_gmc_ras_fini(adev);
2297 amdgpu_gem_force_release(adev);
2298 amdgpu_vm_manager_fini(adev);
2299 if (!adev->gmc.real_vram_size) {
2300 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2301 amdgpu_gart_table_ram_free(adev);
2302 } else {
2303 amdgpu_gart_table_vram_free(adev);
2304 }
2305 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2306 amdgpu_bo_fini(adev);
2307
2308 adev->gmc.num_mem_partitions = 0;
2309 kfree(adev->gmc.mem_partitions);
2310
2311 return 0;
2312 }
2313
gmc_v9_0_init_golden_registers(struct amdgpu_device * adev)2314 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2315 {
2316 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2317 case IP_VERSION(9, 0, 0):
2318 if (amdgpu_sriov_vf(adev))
2319 break;
2320 fallthrough;
2321 case IP_VERSION(9, 4, 0):
2322 soc15_program_register_sequence(adev,
2323 golden_settings_mmhub_1_0_0,
2324 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2325 soc15_program_register_sequence(adev,
2326 golden_settings_athub_1_0_0,
2327 ARRAY_SIZE(golden_settings_athub_1_0_0));
2328 break;
2329 case IP_VERSION(9, 1, 0):
2330 case IP_VERSION(9, 2, 0):
2331 /* TODO for renoir */
2332 soc15_program_register_sequence(adev,
2333 golden_settings_athub_1_0_0,
2334 ARRAY_SIZE(golden_settings_athub_1_0_0));
2335 break;
2336 default:
2337 break;
2338 }
2339 }
2340
2341 /**
2342 * gmc_v9_0_restore_registers - restores regs
2343 *
2344 * @adev: amdgpu_device pointer
2345 *
2346 * This restores register values, saved at suspend.
2347 */
gmc_v9_0_restore_registers(struct amdgpu_device * adev)2348 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2349 {
2350 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2351 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2352 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2353 WARN_ON(adev->gmc.sdpif_register !=
2354 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2355 }
2356 }
2357
2358 /**
2359 * gmc_v9_0_gart_enable - gart enable
2360 *
2361 * @adev: amdgpu_device pointer
2362 */
gmc_v9_0_gart_enable(struct amdgpu_device * adev)2363 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2364 {
2365 int r;
2366
2367 if (adev->gmc.xgmi.connected_to_cpu)
2368 amdgpu_gmc_init_pdb0(adev);
2369
2370 if (adev->gart.bo == NULL) {
2371 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2372 return -EINVAL;
2373 }
2374
2375 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2376
2377 if (!adev->in_s0ix) {
2378 r = adev->gfxhub.funcs->gart_enable(adev);
2379 if (r)
2380 return r;
2381 }
2382
2383 r = adev->mmhub.funcs->gart_enable(adev);
2384 if (r)
2385 return r;
2386
2387 DRM_INFO("PCIE GART of %uM enabled.\n",
2388 (unsigned int)(adev->gmc.gart_size >> 20));
2389 if (adev->gmc.pdb0_bo)
2390 DRM_INFO("PDB0 located at 0x%016llX\n",
2391 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2392 DRM_INFO("PTB located at 0x%016llX\n",
2393 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2394
2395 return 0;
2396 }
2397
gmc_v9_0_hw_init(struct amdgpu_ip_block * ip_block)2398 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
2399 {
2400 struct amdgpu_device *adev = ip_block->adev;
2401 bool value;
2402 int i, r;
2403
2404 adev->gmc.flush_pasid_uses_kiq = true;
2405
2406 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2407 * (type 2), which flushes both. Due to a race condition with
2408 * concurrent memory accesses using the same TLB cache line, we still
2409 * need a second TLB flush after this.
2410 */
2411 adev->gmc.flush_tlb_needs_extra_type_2 =
2412 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2413 adev->gmc.xgmi.num_physical_nodes;
2414 /*
2415 * TODO: This workaround is badly documented and had a buggy
2416 * implementation. We should probably verify what we do here.
2417 */
2418 adev->gmc.flush_tlb_needs_extra_type_0 =
2419 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &&
2420 adev->rev_id == 0;
2421
2422 /* The sequence of these two function calls matters.*/
2423 gmc_v9_0_init_golden_registers(adev);
2424
2425 if (adev->mode_info.num_crtc) {
2426 /* Lockout access through VGA aperture*/
2427 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2428 /* disable VGA render */
2429 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2430 }
2431
2432 if (adev->mmhub.funcs->update_power_gating)
2433 adev->mmhub.funcs->update_power_gating(adev, true);
2434
2435 adev->hdp.funcs->init_registers(adev);
2436
2437 /* After HDP is initialized, flush HDP.*/
2438 amdgpu_device_flush_hdp(adev, NULL);
2439
2440 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2441 value = false;
2442 else
2443 value = true;
2444
2445 if (!amdgpu_sriov_vf(adev)) {
2446 if (!adev->in_s0ix)
2447 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2448 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2449 }
2450 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2451 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2452 continue;
2453 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2454 }
2455
2456 if (adev->umc.funcs && adev->umc.funcs->init_registers)
2457 adev->umc.funcs->init_registers(adev);
2458
2459 r = gmc_v9_0_gart_enable(adev);
2460 if (r)
2461 return r;
2462
2463 if (amdgpu_emu_mode == 1)
2464 return amdgpu_gmc_vram_checking(adev);
2465
2466 return 0;
2467 }
2468
2469 /**
2470 * gmc_v9_0_gart_disable - gart disable
2471 *
2472 * @adev: amdgpu_device pointer
2473 *
2474 * This disables all VM page table.
2475 */
gmc_v9_0_gart_disable(struct amdgpu_device * adev)2476 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2477 {
2478 if (!adev->in_s0ix)
2479 adev->gfxhub.funcs->gart_disable(adev);
2480 adev->mmhub.funcs->gart_disable(adev);
2481 }
2482
gmc_v9_0_hw_fini(struct amdgpu_ip_block * ip_block)2483 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)
2484 {
2485 struct amdgpu_device *adev = ip_block->adev;
2486
2487 gmc_v9_0_gart_disable(adev);
2488
2489 if (amdgpu_sriov_vf(adev)) {
2490 /* full access mode, so don't touch any GMC register */
2491 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2492 return 0;
2493 }
2494
2495 /*
2496 * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2497 * a correct cached state for GMC. Otherwise, the "gate" again
2498 * operation on S3 resuming will fail due to wrong cached state.
2499 */
2500 if (adev->mmhub.funcs->update_power_gating)
2501 adev->mmhub.funcs->update_power_gating(adev, false);
2502
2503 /*
2504 * For minimal init, late_init is not called, hence VM fault/RAS irqs
2505 * are not enabled.
2506 */
2507 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
2508 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2509
2510 if (adev->gmc.ecc_irq.funcs &&
2511 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2512 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2513 }
2514
2515 return 0;
2516 }
2517
gmc_v9_0_suspend(struct amdgpu_ip_block * ip_block)2518 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block)
2519 {
2520 return gmc_v9_0_hw_fini(ip_block);
2521 }
2522
gmc_v9_0_resume(struct amdgpu_ip_block * ip_block)2523 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
2524 {
2525 struct amdgpu_device *adev = ip_block->adev;
2526 int r;
2527
2528 /* If a reset is done for NPS mode switch, read the memory range
2529 * information again.
2530 */
2531 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) {
2532 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2533 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS;
2534 }
2535
2536 r = gmc_v9_0_hw_init(ip_block);
2537 if (r)
2538 return r;
2539
2540 amdgpu_vmid_reset_all(ip_block->adev);
2541
2542 return 0;
2543 }
2544
gmc_v9_0_is_idle(struct amdgpu_ip_block * ip_block)2545 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
2546 {
2547 /* MC is always ready in GMC v9.*/
2548 return true;
2549 }
2550
gmc_v9_0_wait_for_idle(struct amdgpu_ip_block * ip_block)2551 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2552 {
2553 /* There is no need to wait for MC idle in GMC v9.*/
2554 return 0;
2555 }
2556
gmc_v9_0_soft_reset(struct amdgpu_ip_block * ip_block)2557 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
2558 {
2559 /* XXX for emulation.*/
2560 return 0;
2561 }
2562
gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2563 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2564 enum amd_clockgating_state state)
2565 {
2566 struct amdgpu_device *adev = ip_block->adev;
2567
2568 adev->mmhub.funcs->set_clockgating(adev, state);
2569
2570 athub_v1_0_set_clockgating(adev, state);
2571
2572 return 0;
2573 }
2574
gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)2575 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
2576 {
2577 struct amdgpu_device *adev = ip_block->adev;
2578
2579 adev->mmhub.funcs->get_clockgating(adev, flags);
2580
2581 athub_v1_0_get_clockgating(adev, flags);
2582 }
2583
gmc_v9_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2584 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
2585 enum amd_powergating_state state)
2586 {
2587 return 0;
2588 }
2589
2590 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2591 .name = "gmc_v9_0",
2592 .early_init = gmc_v9_0_early_init,
2593 .late_init = gmc_v9_0_late_init,
2594 .sw_init = gmc_v9_0_sw_init,
2595 .sw_fini = gmc_v9_0_sw_fini,
2596 .hw_init = gmc_v9_0_hw_init,
2597 .hw_fini = gmc_v9_0_hw_fini,
2598 .suspend = gmc_v9_0_suspend,
2599 .resume = gmc_v9_0_resume,
2600 .is_idle = gmc_v9_0_is_idle,
2601 .wait_for_idle = gmc_v9_0_wait_for_idle,
2602 .soft_reset = gmc_v9_0_soft_reset,
2603 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2604 .set_powergating_state = gmc_v9_0_set_powergating_state,
2605 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2606 };
2607
2608 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2609 .type = AMD_IP_BLOCK_TYPE_GMC,
2610 .major = 9,
2611 .minor = 0,
2612 .rev = 0,
2613 .funcs = &gmc_v9_0_ip_funcs,
2614 };
2615