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Searched refs:mmGRPH_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c112 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
116 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
120 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
132 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c117 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
135 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
141 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
147 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/linux/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c116 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
134 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
140 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
146 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c121 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
125 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
129 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
133 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
137 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
141 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1951 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_crtc_do_set_base()
2612 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_panic_flush()
2614 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_panic_flush()
H A Ddce_v6_0.c2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2653 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2655 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()
H A Ddce_v10_0.c2021 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2686 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_panic_flush()
2688 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_panic_flush()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3826 #define mmGRPH_CONTROL 0x1A01 macro
H A Ddce_8_0_d.h1542 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_10_0_d.h2391 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_11_0_d.h2285 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_11_2_d.h3516 #define mmGRPH_CONTROL 0x1a01 macro