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Searched refs:mmGRPH_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c1956 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_crtc_do_set_base()
2625 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_panic_flush()
2627 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_panic_flush()
H A Ddce_v10_0.c2026 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2699 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_panic_flush()
2701 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_panic_flush()
H A Ddce_v6_0.c2044 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2666 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2668 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3826 #define mmGRPH_CONTROL 0x1A01 macro
H A Ddce_8_0_d.h1542 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_10_0_d.h2391 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_11_0_d.h2285 #define mmGRPH_CONTROL 0x1a01 macro
H A Ddce_11_2_d.h3516 #define mmGRPH_CONTROL 0x1a01 macro