xref: /linux/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h (revision db5d28c0bfe566908719bec8e25443aabecbb802)
1 /*
2  * Copyright (C) 2019  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _gc_10_1_0_OFFSET_HEADER
22 #define _gc_10_1_0_OFFSET_HEADER
23 
24 #define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
26 #define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
28 
29 // addressBlock: gc_sdma0_sdma0dec
30 // base address: 0x4980
31 #define mmSDMA0_DEC_START                                                                              0x0000
32 #define mmSDMA0_DEC_START_BASE_IDX                                                                     0
33 #define mmSDMA0_PG_CNTL                                                                                0x0016
34 #define mmSDMA0_PG_CNTL_BASE_IDX                                                                       0
35 #define mmSDMA0_PG_CTX_LO                                                                              0x0017
36 #define mmSDMA0_PG_CTX_LO_BASE_IDX                                                                     0
37 #define mmSDMA0_PG_CTX_HI                                                                              0x0018
38 #define mmSDMA0_PG_CTX_HI_BASE_IDX                                                                     0
39 #define mmSDMA0_PG_CTX_CNTL                                                                            0x0019
40 #define mmSDMA0_PG_CTX_CNTL_BASE_IDX                                                                   0
41 #define mmSDMA0_POWER_CNTL                                                                             0x001a
42 #define mmSDMA0_POWER_CNTL_BASE_IDX                                                                    0
43 #define mmSDMA0_CLK_CTRL                                                                               0x001b
44 #define mmSDMA0_CLK_CTRL_BASE_IDX                                                                      0
45 #define mmSDMA0_CNTL                                                                                   0x001c
46 #define mmSDMA0_CNTL_BASE_IDX                                                                          0
47 #define mmSDMA0_CHICKEN_BITS                                                                           0x001d
48 #define mmSDMA0_CHICKEN_BITS_BASE_IDX                                                                  0
49 #define mmSDMA0_GB_ADDR_CONFIG                                                                         0x001e
50 #define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX                                                                0
51 #define mmSDMA0_GB_ADDR_CONFIG_READ                                                                    0x001f
52 #define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
53 #define mmSDMA0_RB_RPTR_FETCH_HI                                                                       0x0020
54 #define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
55 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0021
56 #define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
57 #define mmSDMA0_RB_RPTR_FETCH                                                                          0x0022
58 #define mmSDMA0_RB_RPTR_FETCH_BASE_IDX                                                                 0
59 #define mmSDMA0_IB_OFFSET_FETCH                                                                        0x0023
60 #define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX                                                               0
61 #define mmSDMA0_PROGRAM                                                                                0x0024
62 #define mmSDMA0_PROGRAM_BASE_IDX                                                                       0
63 #define mmSDMA0_STATUS_REG                                                                             0x0025
64 #define mmSDMA0_STATUS_REG_BASE_IDX                                                                    0
65 #define mmSDMA0_STATUS1_REG                                                                            0x0026
66 #define mmSDMA0_STATUS1_REG_BASE_IDX                                                                   0
67 #define mmSDMA0_RD_BURST_CNTL                                                                          0x0027
68 #define mmSDMA0_RD_BURST_CNTL_BASE_IDX                                                                 0
69 #define mmSDMA0_HBM_PAGE_CONFIG                                                                        0x0028
70 #define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX                                                               0
71 #define mmSDMA0_UCODE_CHECKSUM                                                                         0x0029
72 #define mmSDMA0_UCODE_CHECKSUM_BASE_IDX                                                                0
73 #define mmSDMA0_F32_CNTL                                                                               0x002a
74 #define mmSDMA0_F32_CNTL_BASE_IDX                                                                      0
75 #define mmSDMA0_FREEZE                                                                                 0x002b
76 #define mmSDMA0_FREEZE_BASE_IDX                                                                        0
77 #define mmSDMA0_PHASE0_QUANTUM                                                                         0x002c
78 #define mmSDMA0_PHASE0_QUANTUM_BASE_IDX                                                                0
79 #define mmSDMA0_PHASE1_QUANTUM                                                                         0x002d
80 #define mmSDMA0_PHASE1_QUANTUM_BASE_IDX                                                                0
81 #define mmSDMA_POWER_GATING                                                                            0x002e
82 #define mmSDMA_POWER_GATING_BASE_IDX                                                                   0
83 #define mmSDMA_PGFSM_CONFIG                                                                            0x002f
84 #define mmSDMA_PGFSM_CONFIG_BASE_IDX                                                                   0
85 #define mmSDMA_PGFSM_WRITE                                                                             0x0030
86 #define mmSDMA_PGFSM_WRITE_BASE_IDX                                                                    0
87 #define mmSDMA_PGFSM_READ                                                                              0x0031
88 #define mmSDMA_PGFSM_READ_BASE_IDX                                                                     0
89 #define mmSDMA0_EDC_CONFIG                                                                             0x0032
90 #define mmSDMA0_EDC_CONFIG_BASE_IDX                                                                    0
91 #define mmSDMA0_BA_THRESHOLD                                                                           0x0033
92 #define mmSDMA0_BA_THRESHOLD_BASE_IDX                                                                  0
93 #define mmSDMA0_ID                                                                                     0x0034
94 #define mmSDMA0_ID_BASE_IDX                                                                            0
95 #define mmSDMA0_VERSION                                                                                0x0035
96 #define mmSDMA0_VERSION_BASE_IDX                                                                       0
97 #define mmSDMA0_EDC_COUNTER                                                                            0x0036
98 #define mmSDMA0_EDC_COUNTER_BASE_IDX                                                                   0
99 #define mmSDMA0_EDC_COUNTER_CLEAR                                                                      0x0037
100 #define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
101 #define mmSDMA0_STATUS2_REG                                                                            0x0038
102 #define mmSDMA0_STATUS2_REG_BASE_IDX                                                                   0
103 #define mmSDMA0_ATOMIC_CNTL                                                                            0x0039
104 #define mmSDMA0_ATOMIC_CNTL_BASE_IDX                                                                   0
105 #define mmSDMA0_ATOMIC_PREOP_LO                                                                        0x003a
106 #define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX                                                               0
107 #define mmSDMA0_ATOMIC_PREOP_HI                                                                        0x003b
108 #define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX                                                               0
109 #define mmSDMA0_UTCL1_CNTL                                                                             0x003c
110 #define mmSDMA0_UTCL1_CNTL_BASE_IDX                                                                    0
111 #define mmSDMA0_UTCL1_WATERMK                                                                          0x003d
112 #define mmSDMA0_UTCL1_WATERMK_BASE_IDX                                                                 0
113 #define mmSDMA0_UTCL1_RD_STATUS                                                                        0x003e
114 #define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX                                                               0
115 #define mmSDMA0_UTCL1_WR_STATUS                                                                        0x003f
116 #define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX                                                               0
117 #define mmSDMA0_UTCL1_INV0                                                                             0x0040
118 #define mmSDMA0_UTCL1_INV0_BASE_IDX                                                                    0
119 #define mmSDMA0_UTCL1_INV1                                                                             0x0041
120 #define mmSDMA0_UTCL1_INV1_BASE_IDX                                                                    0
121 #define mmSDMA0_UTCL1_INV2                                                                             0x0042
122 #define mmSDMA0_UTCL1_INV2_BASE_IDX                                                                    0
123 #define mmSDMA0_UTCL1_RD_XNACK0                                                                        0x0043
124 #define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX                                                               0
125 #define mmSDMA0_UTCL1_RD_XNACK1                                                                        0x0044
126 #define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX                                                               0
127 #define mmSDMA0_UTCL1_WR_XNACK0                                                                        0x0045
128 #define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX                                                               0
129 #define mmSDMA0_UTCL1_WR_XNACK1                                                                        0x0046
130 #define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX                                                               0
131 #define mmSDMA0_UTCL1_TIMEOUT                                                                          0x0047
132 #define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX                                                                 0
133 #define mmSDMA0_UTCL1_PAGE                                                                             0x0048
134 #define mmSDMA0_UTCL1_PAGE_BASE_IDX                                                                    0
135 #define mmSDMA0_POWER_CNTL_IDLE                                                                        0x0049
136 #define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX                                                               0
137 #define mmSDMA0_RELAX_ORDERING_LUT                                                                     0x004a
138 #define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX                                                            0
139 #define mmSDMA0_CHICKEN_BITS_2                                                                         0x004b
140 #define mmSDMA0_CHICKEN_BITS_2_BASE_IDX                                                                0
141 #define mmSDMA0_STATUS3_REG                                                                            0x004c
142 #define mmSDMA0_STATUS3_REG_BASE_IDX                                                                   0
143 #define mmSDMA0_PHYSICAL_ADDR_LO                                                                       0x004d
144 #define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
145 #define mmSDMA0_PHYSICAL_ADDR_HI                                                                       0x004e
146 #define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
147 #define mmSDMA0_PHASE2_QUANTUM                                                                         0x004f
148 #define mmSDMA0_PHASE2_QUANTUM_BASE_IDX                                                                0
149 #define mmSDMA0_ERROR_LOG                                                                              0x0050
150 #define mmSDMA0_ERROR_LOG_BASE_IDX                                                                     0
151 #define mmSDMA0_PUB_DUMMY_REG0                                                                         0x0051
152 #define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX                                                                0
153 #define mmSDMA0_F32_COUNTER                                                                            0x0055
154 #define mmSDMA0_F32_COUNTER_BASE_IDX                                                                   0
155 #define mmSDMA0_PERFMON_CNTL                                                                           0x0057
156 #define mmSDMA0_PERFMON_CNTL_BASE_IDX                                                                  0
157 #define mmSDMA0_PERFCOUNTER0_RESULT                                                                    0x0058
158 #define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX                                                           0
159 #define mmSDMA0_PERFCOUNTER1_RESULT                                                                    0x0059
160 #define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX                                                           0
161 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x005a
162 #define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   0
163 #define mmSDMA0_CRD_CNTL                                                                               0x005b
164 #define mmSDMA0_CRD_CNTL_BASE_IDX                                                                      0
165 #define mmSDMA0_GPU_IOV_VIOLATION_LOG                                                                  0x005d
166 #define mmSDMA0_AQL_STATUS                                                                             0x005f
167 #define mmSDMA0_AQL_STATUS_BASE_IDX                                                                    0
168 #define mmSDMA0_EA_DBIT_ADDR_DATA                                                                      0x0060
169 #define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
170 #define mmSDMA0_EA_DBIT_ADDR_INDEX                                                                     0x0061
171 #define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
172 #define mmSDMA0_TLBI_GCR_CNTL                                                                          0x0062
173 #define mmSDMA0_TLBI_GCR_CNTL_BASE_IDX                                                                 0
174 #define mmSDMA0_TILING_CONFIG                                                                          0x0063
175 #define mmSDMA0_TILING_CONFIG_BASE_IDX                                                                 0
176 #define mmSDMA0_HASH                                                                                   0x0064
177 #define mmSDMA0_HASH_BASE_IDX                                                                          0
178 #define mmSDMA0_PERFCOUNTER0_SELECT                                                                    0x0068
179 #define mmSDMA0_PERFCOUNTER0_SELECT_BASE_IDX                                                           0
180 #define mmSDMA0_PERFCOUNTER0_SELECT1                                                                   0x0069
181 #define mmSDMA0_PERFCOUNTER0_SELECT1_BASE_IDX                                                          0
182 #define mmSDMA0_PERFCOUNTER0_LO                                                                        0x006a
183 #define mmSDMA0_PERFCOUNTER0_LO_BASE_IDX                                                               0
184 #define mmSDMA0_PERFCOUNTER0_HI                                                                        0x006b
185 #define mmSDMA0_PERFCOUNTER0_HI_BASE_IDX                                                               0
186 #define mmSDMA0_PERFCOUNTER1_SELECT                                                                    0x006c
187 #define mmSDMA0_PERFCOUNTER1_SELECT_BASE_IDX                                                           0
188 #define mmSDMA0_PERFCOUNTER1_SELECT1                                                                   0x006d
189 #define mmSDMA0_PERFCOUNTER1_SELECT1_BASE_IDX                                                          0
190 #define mmSDMA0_PERFCOUNTER1_LO                                                                        0x006e
191 #define mmSDMA0_PERFCOUNTER1_LO_BASE_IDX                                                               0
192 #define mmSDMA0_PERFCOUNTER1_HI                                                                        0x006f
193 #define mmSDMA0_PERFCOUNTER1_HI_BASE_IDX                                                               0
194 #define mmSDMA0_INT_STATUS                                                                             0x0070
195 #define mmSDMA0_INT_STATUS_BASE_IDX                                                                    0
196 #define mmSDMA0_GPU_IOV_VIOLATION_LOG2                                                                 0x0071
197 #define mmSDMA0_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        0
198 #define mmSDMA0_HOLE_ADDR_LO                                                                           0x0072
199 #define mmSDMA0_HOLE_ADDR_LO_BASE_IDX                                                                  0
200 #define mmSDMA0_HOLE_ADDR_HI                                                                           0x0073
201 #define mmSDMA0_HOLE_ADDR_HI_BASE_IDX                                                                  0
202 #define mmSDMA0_GFX_RB_CNTL                                                                            0x0080
203 #define mmSDMA0_GFX_RB_CNTL_BASE_IDX                                                                   0
204 #define mmSDMA0_GFX_RB_BASE                                                                            0x0081
205 #define mmSDMA0_GFX_RB_BASE_BASE_IDX                                                                   0
206 #define mmSDMA0_GFX_RB_BASE_HI                                                                         0x0082
207 #define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX                                                                0
208 #define mmSDMA0_GFX_RB_RPTR                                                                            0x0083
209 #define mmSDMA0_GFX_RB_RPTR_BASE_IDX                                                                   0
210 #define mmSDMA0_GFX_RB_RPTR_HI                                                                         0x0084
211 #define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX                                                                0
212 #define mmSDMA0_GFX_RB_WPTR                                                                            0x0085
213 #define mmSDMA0_GFX_RB_WPTR_BASE_IDX                                                                   0
214 #define mmSDMA0_GFX_RB_WPTR_HI                                                                         0x0086
215 #define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX                                                                0
216 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL                                                                  0x0087
217 #define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
218 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI                                                                    0x0088
219 #define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
220 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO                                                                    0x0089
221 #define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
222 #define mmSDMA0_GFX_IB_CNTL                                                                            0x008a
223 #define mmSDMA0_GFX_IB_CNTL_BASE_IDX                                                                   0
224 #define mmSDMA0_GFX_IB_RPTR                                                                            0x008b
225 #define mmSDMA0_GFX_IB_RPTR_BASE_IDX                                                                   0
226 #define mmSDMA0_GFX_IB_OFFSET                                                                          0x008c
227 #define mmSDMA0_GFX_IB_OFFSET_BASE_IDX                                                                 0
228 #define mmSDMA0_GFX_IB_BASE_LO                                                                         0x008d
229 #define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX                                                                0
230 #define mmSDMA0_GFX_IB_BASE_HI                                                                         0x008e
231 #define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX                                                                0
232 #define mmSDMA0_GFX_IB_SIZE                                                                            0x008f
233 #define mmSDMA0_GFX_IB_SIZE_BASE_IDX                                                                   0
234 #define mmSDMA0_GFX_SKIP_CNTL                                                                          0x0090
235 #define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX                                                                 0
236 #define mmSDMA0_GFX_CONTEXT_STATUS                                                                     0x0091
237 #define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
238 #define mmSDMA0_GFX_DOORBELL                                                                           0x0092
239 #define mmSDMA0_GFX_DOORBELL_BASE_IDX                                                                  0
240 #define mmSDMA0_GFX_CONTEXT_CNTL                                                                       0x0093
241 #define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
242 #define mmSDMA0_GFX_STATUS                                                                             0x00a8
243 #define mmSDMA0_GFX_STATUS_BASE_IDX                                                                    0
244 #define mmSDMA0_GFX_DOORBELL_LOG                                                                       0x00a9
245 #define mmSDMA0_GFX_WATERMARK                                                                          0x00aa
246 #define mmSDMA0_GFX_WATERMARK_BASE_IDX                                                                 0
247 #define mmSDMA0_GFX_DOORBELL_OFFSET                                                                    0x00ab
248 #define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
249 #define mmSDMA0_GFX_CSA_ADDR_LO                                                                        0x00ac
250 #define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
251 #define mmSDMA0_GFX_CSA_ADDR_HI                                                                        0x00ad
252 #define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
253 #define mmSDMA0_GFX_IB_SUB_REMAIN                                                                      0x00af
254 #define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
255 #define mmSDMA0_GFX_PREEMPT                                                                            0x00b0
256 #define mmSDMA0_GFX_PREEMPT_BASE_IDX                                                                   0
257 #define mmSDMA0_GFX_DUMMY_REG                                                                          0x00b1
258 #define mmSDMA0_GFX_DUMMY_REG_BASE_IDX                                                                 0
259 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x00b2
260 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
261 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x00b3
262 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
263 #define mmSDMA0_GFX_RB_AQL_CNTL                                                                        0x00b4
264 #define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
265 #define mmSDMA0_GFX_MINOR_PTR_UPDATE                                                                   0x00b5
266 #define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
267 #define mmSDMA0_GFX_MIDCMD_DATA0                                                                       0x00c0
268 #define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
269 #define mmSDMA0_GFX_MIDCMD_DATA1                                                                       0x00c1
270 #define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
271 #define mmSDMA0_GFX_MIDCMD_DATA2                                                                       0x00c2
272 #define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
273 #define mmSDMA0_GFX_MIDCMD_DATA3                                                                       0x00c3
274 #define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
275 #define mmSDMA0_GFX_MIDCMD_DATA4                                                                       0x00c4
276 #define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
277 #define mmSDMA0_GFX_MIDCMD_DATA5                                                                       0x00c5
278 #define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
279 #define mmSDMA0_GFX_MIDCMD_DATA6                                                                       0x00c6
280 #define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
281 #define mmSDMA0_GFX_MIDCMD_DATA7                                                                       0x00c7
282 #define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
283 #define mmSDMA0_GFX_MIDCMD_DATA8                                                                       0x00c8
284 #define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
285 #define mmSDMA0_GFX_MIDCMD_CNTL                                                                        0x00c9
286 #define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
287 #define mmSDMA0_PAGE_RB_CNTL                                                                           0x00e0
288 #define mmSDMA0_PAGE_RB_CNTL_BASE_IDX                                                                  0
289 #define mmSDMA0_PAGE_RB_BASE                                                                           0x00e1
290 #define mmSDMA0_PAGE_RB_BASE_BASE_IDX                                                                  0
291 #define mmSDMA0_PAGE_RB_BASE_HI                                                                        0x00e2
292 #define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX                                                               0
293 #define mmSDMA0_PAGE_RB_RPTR                                                                           0x00e3
294 #define mmSDMA0_PAGE_RB_RPTR_BASE_IDX                                                                  0
295 #define mmSDMA0_PAGE_RB_RPTR_HI                                                                        0x00e4
296 #define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
297 #define mmSDMA0_PAGE_RB_WPTR                                                                           0x00e5
298 #define mmSDMA0_PAGE_RB_WPTR_BASE_IDX                                                                  0
299 #define mmSDMA0_PAGE_RB_WPTR_HI                                                                        0x00e6
300 #define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
301 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL                                                                 0x00e7
302 #define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
303 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI                                                                   0x00e8
304 #define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
305 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO                                                                   0x00e9
306 #define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
307 #define mmSDMA0_PAGE_IB_CNTL                                                                           0x00ea
308 #define mmSDMA0_PAGE_IB_CNTL_BASE_IDX                                                                  0
309 #define mmSDMA0_PAGE_IB_RPTR                                                                           0x00eb
310 #define mmSDMA0_PAGE_IB_RPTR_BASE_IDX                                                                  0
311 #define mmSDMA0_PAGE_IB_OFFSET                                                                         0x00ec
312 #define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX                                                                0
313 #define mmSDMA0_PAGE_IB_BASE_LO                                                                        0x00ed
314 #define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX                                                               0
315 #define mmSDMA0_PAGE_IB_BASE_HI                                                                        0x00ee
316 #define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX                                                               0
317 #define mmSDMA0_PAGE_IB_SIZE                                                                           0x00ef
318 #define mmSDMA0_PAGE_IB_SIZE_BASE_IDX                                                                  0
319 #define mmSDMA0_PAGE_SKIP_CNTL                                                                         0x00f0
320 #define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX                                                                0
321 #define mmSDMA0_PAGE_CONTEXT_STATUS                                                                    0x00f1
322 #define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
323 #define mmSDMA0_PAGE_DOORBELL                                                                          0x00f2
324 #define mmSDMA0_PAGE_DOORBELL_BASE_IDX                                                                 0
325 #define mmSDMA0_PAGE_STATUS                                                                            0x0108
326 #define mmSDMA0_PAGE_STATUS_BASE_IDX                                                                   0
327 #define mmSDMA0_PAGE_DOORBELL_LOG                                                                      0x0109
328 #define mmSDMA0_PAGE_WATERMARK                                                                         0x010a
329 #define mmSDMA0_PAGE_WATERMARK_BASE_IDX                                                                0
330 #define mmSDMA0_PAGE_DOORBELL_OFFSET                                                                   0x010b
331 #define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
332 #define mmSDMA0_PAGE_CSA_ADDR_LO                                                                       0x010c
333 #define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
334 #define mmSDMA0_PAGE_CSA_ADDR_HI                                                                       0x010d
335 #define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
336 #define mmSDMA0_PAGE_IB_SUB_REMAIN                                                                     0x010f
337 #define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
338 #define mmSDMA0_PAGE_PREEMPT                                                                           0x0110
339 #define mmSDMA0_PAGE_PREEMPT_BASE_IDX                                                                  0
340 #define mmSDMA0_PAGE_DUMMY_REG                                                                         0x0111
341 #define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX                                                                0
342 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x0112
343 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
344 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x0113
345 #define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
346 #define mmSDMA0_PAGE_RB_AQL_CNTL                                                                       0x0114
347 #define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
348 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE                                                                  0x0115
349 #define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
350 #define mmSDMA0_PAGE_MIDCMD_DATA0                                                                      0x0120
351 #define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
352 #define mmSDMA0_PAGE_MIDCMD_DATA1                                                                      0x0121
353 #define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
354 #define mmSDMA0_PAGE_MIDCMD_DATA2                                                                      0x0122
355 #define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
356 #define mmSDMA0_PAGE_MIDCMD_DATA3                                                                      0x0123
357 #define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
358 #define mmSDMA0_PAGE_MIDCMD_DATA4                                                                      0x0124
359 #define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
360 #define mmSDMA0_PAGE_MIDCMD_DATA5                                                                      0x0125
361 #define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
362 #define mmSDMA0_PAGE_MIDCMD_DATA6                                                                      0x0126
363 #define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
364 #define mmSDMA0_PAGE_MIDCMD_DATA7                                                                      0x0127
365 #define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
366 #define mmSDMA0_PAGE_MIDCMD_DATA8                                                                      0x0128
367 #define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
368 #define mmSDMA0_PAGE_MIDCMD_CNTL                                                                       0x0129
369 #define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
370 #define mmSDMA0_RLC0_RB_CNTL                                                                           0x0140
371 #define mmSDMA0_RLC0_RB_CNTL_BASE_IDX                                                                  0
372 #define mmSDMA0_RLC0_RB_BASE                                                                           0x0141
373 #define mmSDMA0_RLC0_RB_BASE_BASE_IDX                                                                  0
374 #define mmSDMA0_RLC0_RB_BASE_HI                                                                        0x0142
375 #define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX                                                               0
376 #define mmSDMA0_RLC0_RB_RPTR                                                                           0x0143
377 #define mmSDMA0_RLC0_RB_RPTR_BASE_IDX                                                                  0
378 #define mmSDMA0_RLC0_RB_RPTR_HI                                                                        0x0144
379 #define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
380 #define mmSDMA0_RLC0_RB_WPTR                                                                           0x0145
381 #define mmSDMA0_RLC0_RB_WPTR_BASE_IDX                                                                  0
382 #define mmSDMA0_RLC0_RB_WPTR_HI                                                                        0x0146
383 #define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
384 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0147
385 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
386 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI                                                                   0x0148
387 #define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
388 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO                                                                   0x0149
389 #define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
390 #define mmSDMA0_RLC0_IB_CNTL                                                                           0x014a
391 #define mmSDMA0_RLC0_IB_CNTL_BASE_IDX                                                                  0
392 #define mmSDMA0_RLC0_IB_RPTR                                                                           0x014b
393 #define mmSDMA0_RLC0_IB_RPTR_BASE_IDX                                                                  0
394 #define mmSDMA0_RLC0_IB_OFFSET                                                                         0x014c
395 #define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX                                                                0
396 #define mmSDMA0_RLC0_IB_BASE_LO                                                                        0x014d
397 #define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX                                                               0
398 #define mmSDMA0_RLC0_IB_BASE_HI                                                                        0x014e
399 #define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX                                                               0
400 #define mmSDMA0_RLC0_IB_SIZE                                                                           0x014f
401 #define mmSDMA0_RLC0_IB_SIZE_BASE_IDX                                                                  0
402 #define mmSDMA0_RLC0_SKIP_CNTL                                                                         0x0150
403 #define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX                                                                0
404 #define mmSDMA0_RLC0_CONTEXT_STATUS                                                                    0x0151
405 #define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
406 #define mmSDMA0_RLC0_DOORBELL                                                                          0x0152
407 #define mmSDMA0_RLC0_DOORBELL_BASE_IDX                                                                 0
408 #define mmSDMA0_RLC0_STATUS                                                                            0x0168
409 #define mmSDMA0_RLC0_STATUS_BASE_IDX                                                                   0
410 #define mmSDMA0_RLC0_DOORBELL_LOG                                                                      0x0169
411 #define mmSDMA0_RLC0_WATERMARK                                                                         0x016a
412 #define mmSDMA0_RLC0_WATERMARK_BASE_IDX                                                                0
413 #define mmSDMA0_RLC0_DOORBELL_OFFSET                                                                   0x016b
414 #define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
415 #define mmSDMA0_RLC0_CSA_ADDR_LO                                                                       0x016c
416 #define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
417 #define mmSDMA0_RLC0_CSA_ADDR_HI                                                                       0x016d
418 #define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
419 #define mmSDMA0_RLC0_IB_SUB_REMAIN                                                                     0x016f
420 #define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
421 #define mmSDMA0_RLC0_PREEMPT                                                                           0x0170
422 #define mmSDMA0_RLC0_PREEMPT_BASE_IDX                                                                  0
423 #define mmSDMA0_RLC0_DUMMY_REG                                                                         0x0171
424 #define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX                                                                0
425 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0172
426 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
427 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0173
428 #define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
429 #define mmSDMA0_RLC0_RB_AQL_CNTL                                                                       0x0174
430 #define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
431 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE                                                                  0x0175
432 #define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
433 #define mmSDMA0_RLC0_MIDCMD_DATA0                                                                      0x0180
434 #define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
435 #define mmSDMA0_RLC0_MIDCMD_DATA1                                                                      0x0181
436 #define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
437 #define mmSDMA0_RLC0_MIDCMD_DATA2                                                                      0x0182
438 #define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
439 #define mmSDMA0_RLC0_MIDCMD_DATA3                                                                      0x0183
440 #define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
441 #define mmSDMA0_RLC0_MIDCMD_DATA4                                                                      0x0184
442 #define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
443 #define mmSDMA0_RLC0_MIDCMD_DATA5                                                                      0x0185
444 #define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
445 #define mmSDMA0_RLC0_MIDCMD_DATA6                                                                      0x0186
446 #define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
447 #define mmSDMA0_RLC0_MIDCMD_DATA7                                                                      0x0187
448 #define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
449 #define mmSDMA0_RLC0_MIDCMD_DATA8                                                                      0x0188
450 #define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
451 #define mmSDMA0_RLC0_MIDCMD_CNTL                                                                       0x0189
452 #define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
453 #define mmSDMA0_RLC1_RB_CNTL                                                                           0x01a0
454 #define mmSDMA0_RLC1_RB_CNTL_BASE_IDX                                                                  0
455 #define mmSDMA0_RLC1_RB_BASE                                                                           0x01a1
456 #define mmSDMA0_RLC1_RB_BASE_BASE_IDX                                                                  0
457 #define mmSDMA0_RLC1_RB_BASE_HI                                                                        0x01a2
458 #define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX                                                               0
459 #define mmSDMA0_RLC1_RB_RPTR                                                                           0x01a3
460 #define mmSDMA0_RLC1_RB_RPTR_BASE_IDX                                                                  0
461 #define mmSDMA0_RLC1_RB_RPTR_HI                                                                        0x01a4
462 #define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
463 #define mmSDMA0_RLC1_RB_WPTR                                                                           0x01a5
464 #define mmSDMA0_RLC1_RB_WPTR_BASE_IDX                                                                  0
465 #define mmSDMA0_RLC1_RB_WPTR_HI                                                                        0x01a6
466 #define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
467 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL                                                                 0x01a7
468 #define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
469 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI                                                                   0x01a8
470 #define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
471 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO                                                                   0x01a9
472 #define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
473 #define mmSDMA0_RLC1_IB_CNTL                                                                           0x01aa
474 #define mmSDMA0_RLC1_IB_CNTL_BASE_IDX                                                                  0
475 #define mmSDMA0_RLC1_IB_RPTR                                                                           0x01ab
476 #define mmSDMA0_RLC1_IB_RPTR_BASE_IDX                                                                  0
477 #define mmSDMA0_RLC1_IB_OFFSET                                                                         0x01ac
478 #define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX                                                                0
479 #define mmSDMA0_RLC1_IB_BASE_LO                                                                        0x01ad
480 #define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX                                                               0
481 #define mmSDMA0_RLC1_IB_BASE_HI                                                                        0x01ae
482 #define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX                                                               0
483 #define mmSDMA0_RLC1_IB_SIZE                                                                           0x01af
484 #define mmSDMA0_RLC1_IB_SIZE_BASE_IDX                                                                  0
485 #define mmSDMA0_RLC1_SKIP_CNTL                                                                         0x01b0
486 #define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX                                                                0
487 #define mmSDMA0_RLC1_CONTEXT_STATUS                                                                    0x01b1
488 #define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
489 #define mmSDMA0_RLC1_DOORBELL                                                                          0x01b2
490 #define mmSDMA0_RLC1_DOORBELL_BASE_IDX                                                                 0
491 #define mmSDMA0_RLC1_STATUS                                                                            0x01c8
492 #define mmSDMA0_RLC1_STATUS_BASE_IDX                                                                   0
493 #define mmSDMA0_RLC1_DOORBELL_LOG                                                                      0x01c9
494 #define mmSDMA0_RLC1_WATERMARK                                                                         0x01ca
495 #define mmSDMA0_RLC1_WATERMARK_BASE_IDX                                                                0
496 #define mmSDMA0_RLC1_DOORBELL_OFFSET                                                                   0x01cb
497 #define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
498 #define mmSDMA0_RLC1_CSA_ADDR_LO                                                                       0x01cc
499 #define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
500 #define mmSDMA0_RLC1_CSA_ADDR_HI                                                                       0x01cd
501 #define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
502 #define mmSDMA0_RLC1_IB_SUB_REMAIN                                                                     0x01cf
503 #define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
504 #define mmSDMA0_RLC1_PREEMPT                                                                           0x01d0
505 #define mmSDMA0_RLC1_PREEMPT_BASE_IDX                                                                  0
506 #define mmSDMA0_RLC1_DUMMY_REG                                                                         0x01d1
507 #define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX                                                                0
508 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x01d2
509 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
510 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x01d3
511 #define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
512 #define mmSDMA0_RLC1_RB_AQL_CNTL                                                                       0x01d4
513 #define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
514 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE                                                                  0x01d5
515 #define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
516 #define mmSDMA0_RLC1_MIDCMD_DATA0                                                                      0x01e0
517 #define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
518 #define mmSDMA0_RLC1_MIDCMD_DATA1                                                                      0x01e1
519 #define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
520 #define mmSDMA0_RLC1_MIDCMD_DATA2                                                                      0x01e2
521 #define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
522 #define mmSDMA0_RLC1_MIDCMD_DATA3                                                                      0x01e3
523 #define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
524 #define mmSDMA0_RLC1_MIDCMD_DATA4                                                                      0x01e4
525 #define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
526 #define mmSDMA0_RLC1_MIDCMD_DATA5                                                                      0x01e5
527 #define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
528 #define mmSDMA0_RLC1_MIDCMD_DATA6                                                                      0x01e6
529 #define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
530 #define mmSDMA0_RLC1_MIDCMD_DATA7                                                                      0x01e7
531 #define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
532 #define mmSDMA0_RLC1_MIDCMD_DATA8                                                                      0x01e8
533 #define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
534 #define mmSDMA0_RLC1_MIDCMD_CNTL                                                                       0x01e9
535 #define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
536 #define mmSDMA0_RLC2_RB_CNTL                                                                           0x0200
537 #define mmSDMA0_RLC2_RB_CNTL_BASE_IDX                                                                  0
538 #define mmSDMA0_RLC2_RB_BASE                                                                           0x0201
539 #define mmSDMA0_RLC2_RB_BASE_BASE_IDX                                                                  0
540 #define mmSDMA0_RLC2_RB_BASE_HI                                                                        0x0202
541 #define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX                                                               0
542 #define mmSDMA0_RLC2_RB_RPTR                                                                           0x0203
543 #define mmSDMA0_RLC2_RB_RPTR_BASE_IDX                                                                  0
544 #define mmSDMA0_RLC2_RB_RPTR_HI                                                                        0x0204
545 #define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
546 #define mmSDMA0_RLC2_RB_WPTR                                                                           0x0205
547 #define mmSDMA0_RLC2_RB_WPTR_BASE_IDX                                                                  0
548 #define mmSDMA0_RLC2_RB_WPTR_HI                                                                        0x0206
549 #define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
550 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL                                                                 0x0207
551 #define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
552 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI                                                                   0x0208
553 #define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
554 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO                                                                   0x0209
555 #define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
556 #define mmSDMA0_RLC2_IB_CNTL                                                                           0x020a
557 #define mmSDMA0_RLC2_IB_CNTL_BASE_IDX                                                                  0
558 #define mmSDMA0_RLC2_IB_RPTR                                                                           0x020b
559 #define mmSDMA0_RLC2_IB_RPTR_BASE_IDX                                                                  0
560 #define mmSDMA0_RLC2_IB_OFFSET                                                                         0x020c
561 #define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX                                                                0
562 #define mmSDMA0_RLC2_IB_BASE_LO                                                                        0x020d
563 #define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX                                                               0
564 #define mmSDMA0_RLC2_IB_BASE_HI                                                                        0x020e
565 #define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX                                                               0
566 #define mmSDMA0_RLC2_IB_SIZE                                                                           0x020f
567 #define mmSDMA0_RLC2_IB_SIZE_BASE_IDX                                                                  0
568 #define mmSDMA0_RLC2_SKIP_CNTL                                                                         0x0210
569 #define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX                                                                0
570 #define mmSDMA0_RLC2_CONTEXT_STATUS                                                                    0x0211
571 #define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
572 #define mmSDMA0_RLC2_DOORBELL                                                                          0x0212
573 #define mmSDMA0_RLC2_DOORBELL_BASE_IDX                                                                 0
574 #define mmSDMA0_RLC2_STATUS                                                                            0x0228
575 #define mmSDMA0_RLC2_STATUS_BASE_IDX                                                                   0
576 #define mmSDMA0_RLC2_DOORBELL_LOG                                                                      0x0229
577 #define mmSDMA0_RLC2_WATERMARK                                                                         0x022a
578 #define mmSDMA0_RLC2_WATERMARK_BASE_IDX                                                                0
579 #define mmSDMA0_RLC2_DOORBELL_OFFSET                                                                   0x022b
580 #define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
581 #define mmSDMA0_RLC2_CSA_ADDR_LO                                                                       0x022c
582 #define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
583 #define mmSDMA0_RLC2_CSA_ADDR_HI                                                                       0x022d
584 #define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
585 #define mmSDMA0_RLC2_IB_SUB_REMAIN                                                                     0x022f
586 #define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
587 #define mmSDMA0_RLC2_PREEMPT                                                                           0x0230
588 #define mmSDMA0_RLC2_PREEMPT_BASE_IDX                                                                  0
589 #define mmSDMA0_RLC2_DUMMY_REG                                                                         0x0231
590 #define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX                                                                0
591 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0232
592 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
593 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0233
594 #define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
595 #define mmSDMA0_RLC2_RB_AQL_CNTL                                                                       0x0234
596 #define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
597 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE                                                                  0x0235
598 #define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
599 #define mmSDMA0_RLC2_MIDCMD_DATA0                                                                      0x0240
600 #define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
601 #define mmSDMA0_RLC2_MIDCMD_DATA1                                                                      0x0241
602 #define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
603 #define mmSDMA0_RLC2_MIDCMD_DATA2                                                                      0x0242
604 #define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
605 #define mmSDMA0_RLC2_MIDCMD_DATA3                                                                      0x0243
606 #define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
607 #define mmSDMA0_RLC2_MIDCMD_DATA4                                                                      0x0244
608 #define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
609 #define mmSDMA0_RLC2_MIDCMD_DATA5                                                                      0x0245
610 #define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
611 #define mmSDMA0_RLC2_MIDCMD_DATA6                                                                      0x0246
612 #define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
613 #define mmSDMA0_RLC2_MIDCMD_DATA7                                                                      0x0247
614 #define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
615 #define mmSDMA0_RLC2_MIDCMD_DATA8                                                                      0x0248
616 #define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
617 #define mmSDMA0_RLC2_MIDCMD_CNTL                                                                       0x0249
618 #define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
619 #define mmSDMA0_RLC3_RB_CNTL                                                                           0x0260
620 #define mmSDMA0_RLC3_RB_CNTL_BASE_IDX                                                                  0
621 #define mmSDMA0_RLC3_RB_BASE                                                                           0x0261
622 #define mmSDMA0_RLC3_RB_BASE_BASE_IDX                                                                  0
623 #define mmSDMA0_RLC3_RB_BASE_HI                                                                        0x0262
624 #define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX                                                               0
625 #define mmSDMA0_RLC3_RB_RPTR                                                                           0x0263
626 #define mmSDMA0_RLC3_RB_RPTR_BASE_IDX                                                                  0
627 #define mmSDMA0_RLC3_RB_RPTR_HI                                                                        0x0264
628 #define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
629 #define mmSDMA0_RLC3_RB_WPTR                                                                           0x0265
630 #define mmSDMA0_RLC3_RB_WPTR_BASE_IDX                                                                  0
631 #define mmSDMA0_RLC3_RB_WPTR_HI                                                                        0x0266
632 #define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
633 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0267
634 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
635 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI                                                                   0x0268
636 #define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
637 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO                                                                   0x0269
638 #define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
639 #define mmSDMA0_RLC3_IB_CNTL                                                                           0x026a
640 #define mmSDMA0_RLC3_IB_CNTL_BASE_IDX                                                                  0
641 #define mmSDMA0_RLC3_IB_RPTR                                                                           0x026b
642 #define mmSDMA0_RLC3_IB_RPTR_BASE_IDX                                                                  0
643 #define mmSDMA0_RLC3_IB_OFFSET                                                                         0x026c
644 #define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX                                                                0
645 #define mmSDMA0_RLC3_IB_BASE_LO                                                                        0x026d
646 #define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX                                                               0
647 #define mmSDMA0_RLC3_IB_BASE_HI                                                                        0x026e
648 #define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX                                                               0
649 #define mmSDMA0_RLC3_IB_SIZE                                                                           0x026f
650 #define mmSDMA0_RLC3_IB_SIZE_BASE_IDX                                                                  0
651 #define mmSDMA0_RLC3_SKIP_CNTL                                                                         0x0270
652 #define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX                                                                0
653 #define mmSDMA0_RLC3_CONTEXT_STATUS                                                                    0x0271
654 #define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
655 #define mmSDMA0_RLC3_DOORBELL                                                                          0x0272
656 #define mmSDMA0_RLC3_DOORBELL_BASE_IDX                                                                 0
657 #define mmSDMA0_RLC3_STATUS                                                                            0x0288
658 #define mmSDMA0_RLC3_STATUS_BASE_IDX                                                                   0
659 #define mmSDMA0_RLC3_DOORBELL_LOG                                                                      0x0289
660 #define mmSDMA0_RLC3_WATERMARK                                                                         0x028a
661 #define mmSDMA0_RLC3_WATERMARK_BASE_IDX                                                                0
662 #define mmSDMA0_RLC3_DOORBELL_OFFSET                                                                   0x028b
663 #define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
664 #define mmSDMA0_RLC3_CSA_ADDR_LO                                                                       0x028c
665 #define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
666 #define mmSDMA0_RLC3_CSA_ADDR_HI                                                                       0x028d
667 #define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
668 #define mmSDMA0_RLC3_IB_SUB_REMAIN                                                                     0x028f
669 #define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
670 #define mmSDMA0_RLC3_PREEMPT                                                                           0x0290
671 #define mmSDMA0_RLC3_PREEMPT_BASE_IDX                                                                  0
672 #define mmSDMA0_RLC3_DUMMY_REG                                                                         0x0291
673 #define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX                                                                0
674 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0292
675 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
676 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x0293
677 #define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
678 #define mmSDMA0_RLC3_RB_AQL_CNTL                                                                       0x0294
679 #define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
680 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE                                                                  0x0295
681 #define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
682 #define mmSDMA0_RLC3_MIDCMD_DATA0                                                                      0x02a0
683 #define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
684 #define mmSDMA0_RLC3_MIDCMD_DATA1                                                                      0x02a1
685 #define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
686 #define mmSDMA0_RLC3_MIDCMD_DATA2                                                                      0x02a2
687 #define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
688 #define mmSDMA0_RLC3_MIDCMD_DATA3                                                                      0x02a3
689 #define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
690 #define mmSDMA0_RLC3_MIDCMD_DATA4                                                                      0x02a4
691 #define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
692 #define mmSDMA0_RLC3_MIDCMD_DATA5                                                                      0x02a5
693 #define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
694 #define mmSDMA0_RLC3_MIDCMD_DATA6                                                                      0x02a6
695 #define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
696 #define mmSDMA0_RLC3_MIDCMD_DATA7                                                                      0x02a7
697 #define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
698 #define mmSDMA0_RLC3_MIDCMD_DATA8                                                                      0x02a8
699 #define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
700 #define mmSDMA0_RLC3_MIDCMD_CNTL                                                                       0x02a9
701 #define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
702 #define mmSDMA0_RLC4_RB_CNTL                                                                           0x02c0
703 #define mmSDMA0_RLC4_RB_CNTL_BASE_IDX                                                                  0
704 #define mmSDMA0_RLC4_RB_BASE                                                                           0x02c1
705 #define mmSDMA0_RLC4_RB_BASE_BASE_IDX                                                                  0
706 #define mmSDMA0_RLC4_RB_BASE_HI                                                                        0x02c2
707 #define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX                                                               0
708 #define mmSDMA0_RLC4_RB_RPTR                                                                           0x02c3
709 #define mmSDMA0_RLC4_RB_RPTR_BASE_IDX                                                                  0
710 #define mmSDMA0_RLC4_RB_RPTR_HI                                                                        0x02c4
711 #define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
712 #define mmSDMA0_RLC4_RB_WPTR                                                                           0x02c5
713 #define mmSDMA0_RLC4_RB_WPTR_BASE_IDX                                                                  0
714 #define mmSDMA0_RLC4_RB_WPTR_HI                                                                        0x02c6
715 #define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
716 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL                                                                 0x02c7
717 #define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
718 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI                                                                   0x02c8
719 #define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
720 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO                                                                   0x02c9
721 #define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
722 #define mmSDMA0_RLC4_IB_CNTL                                                                           0x02ca
723 #define mmSDMA0_RLC4_IB_CNTL_BASE_IDX                                                                  0
724 #define mmSDMA0_RLC4_IB_RPTR                                                                           0x02cb
725 #define mmSDMA0_RLC4_IB_RPTR_BASE_IDX                                                                  0
726 #define mmSDMA0_RLC4_IB_OFFSET                                                                         0x02cc
727 #define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX                                                                0
728 #define mmSDMA0_RLC4_IB_BASE_LO                                                                        0x02cd
729 #define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX                                                               0
730 #define mmSDMA0_RLC4_IB_BASE_HI                                                                        0x02ce
731 #define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX                                                               0
732 #define mmSDMA0_RLC4_IB_SIZE                                                                           0x02cf
733 #define mmSDMA0_RLC4_IB_SIZE_BASE_IDX                                                                  0
734 #define mmSDMA0_RLC4_SKIP_CNTL                                                                         0x02d0
735 #define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX                                                                0
736 #define mmSDMA0_RLC4_CONTEXT_STATUS                                                                    0x02d1
737 #define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
738 #define mmSDMA0_RLC4_DOORBELL                                                                          0x02d2
739 #define mmSDMA0_RLC4_DOORBELL_BASE_IDX                                                                 0
740 #define mmSDMA0_RLC4_STATUS                                                                            0x02e8
741 #define mmSDMA0_RLC4_STATUS_BASE_IDX                                                                   0
742 #define mmSDMA0_RLC4_DOORBELL_LOG                                                                      0x02e9
743 #define mmSDMA0_RLC4_WATERMARK                                                                         0x02ea
744 #define mmSDMA0_RLC4_WATERMARK_BASE_IDX                                                                0
745 #define mmSDMA0_RLC4_DOORBELL_OFFSET                                                                   0x02eb
746 #define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
747 #define mmSDMA0_RLC4_CSA_ADDR_LO                                                                       0x02ec
748 #define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
749 #define mmSDMA0_RLC4_CSA_ADDR_HI                                                                       0x02ed
750 #define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
751 #define mmSDMA0_RLC4_IB_SUB_REMAIN                                                                     0x02ef
752 #define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
753 #define mmSDMA0_RLC4_PREEMPT                                                                           0x02f0
754 #define mmSDMA0_RLC4_PREEMPT_BASE_IDX                                                                  0
755 #define mmSDMA0_RLC4_DUMMY_REG                                                                         0x02f1
756 #define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX                                                                0
757 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x02f2
758 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
759 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x02f3
760 #define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
761 #define mmSDMA0_RLC4_RB_AQL_CNTL                                                                       0x02f4
762 #define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
763 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE                                                                  0x02f5
764 #define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
765 #define mmSDMA0_RLC4_MIDCMD_DATA0                                                                      0x0300
766 #define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
767 #define mmSDMA0_RLC4_MIDCMD_DATA1                                                                      0x0301
768 #define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
769 #define mmSDMA0_RLC4_MIDCMD_DATA2                                                                      0x0302
770 #define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
771 #define mmSDMA0_RLC4_MIDCMD_DATA3                                                                      0x0303
772 #define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
773 #define mmSDMA0_RLC4_MIDCMD_DATA4                                                                      0x0304
774 #define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
775 #define mmSDMA0_RLC4_MIDCMD_DATA5                                                                      0x0305
776 #define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
777 #define mmSDMA0_RLC4_MIDCMD_DATA6                                                                      0x0306
778 #define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
779 #define mmSDMA0_RLC4_MIDCMD_DATA7                                                                      0x0307
780 #define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
781 #define mmSDMA0_RLC4_MIDCMD_DATA8                                                                      0x0308
782 #define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
783 #define mmSDMA0_RLC4_MIDCMD_CNTL                                                                       0x0309
784 #define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
785 #define mmSDMA0_RLC5_RB_CNTL                                                                           0x0320
786 #define mmSDMA0_RLC5_RB_CNTL_BASE_IDX                                                                  0
787 #define mmSDMA0_RLC5_RB_BASE                                                                           0x0321
788 #define mmSDMA0_RLC5_RB_BASE_BASE_IDX                                                                  0
789 #define mmSDMA0_RLC5_RB_BASE_HI                                                                        0x0322
790 #define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX                                                               0
791 #define mmSDMA0_RLC5_RB_RPTR                                                                           0x0323
792 #define mmSDMA0_RLC5_RB_RPTR_BASE_IDX                                                                  0
793 #define mmSDMA0_RLC5_RB_RPTR_HI                                                                        0x0324
794 #define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
795 #define mmSDMA0_RLC5_RB_WPTR                                                                           0x0325
796 #define mmSDMA0_RLC5_RB_WPTR_BASE_IDX                                                                  0
797 #define mmSDMA0_RLC5_RB_WPTR_HI                                                                        0x0326
798 #define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
799 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL                                                                 0x0327
800 #define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
801 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI                                                                   0x0328
802 #define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
803 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO                                                                   0x0329
804 #define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
805 #define mmSDMA0_RLC5_IB_CNTL                                                                           0x032a
806 #define mmSDMA0_RLC5_IB_CNTL_BASE_IDX                                                                  0
807 #define mmSDMA0_RLC5_IB_RPTR                                                                           0x032b
808 #define mmSDMA0_RLC5_IB_RPTR_BASE_IDX                                                                  0
809 #define mmSDMA0_RLC5_IB_OFFSET                                                                         0x032c
810 #define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX                                                                0
811 #define mmSDMA0_RLC5_IB_BASE_LO                                                                        0x032d
812 #define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX                                                               0
813 #define mmSDMA0_RLC5_IB_BASE_HI                                                                        0x032e
814 #define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX                                                               0
815 #define mmSDMA0_RLC5_IB_SIZE                                                                           0x032f
816 #define mmSDMA0_RLC5_IB_SIZE_BASE_IDX                                                                  0
817 #define mmSDMA0_RLC5_SKIP_CNTL                                                                         0x0330
818 #define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX                                                                0
819 #define mmSDMA0_RLC5_CONTEXT_STATUS                                                                    0x0331
820 #define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
821 #define mmSDMA0_RLC5_DOORBELL                                                                          0x0332
822 #define mmSDMA0_RLC5_DOORBELL_BASE_IDX                                                                 0
823 #define mmSDMA0_RLC5_STATUS                                                                            0x0348
824 #define mmSDMA0_RLC5_STATUS_BASE_IDX                                                                   0
825 #define mmSDMA0_RLC5_DOORBELL_LOG                                                                      0x0349
826 #define mmSDMA0_RLC5_WATERMARK                                                                         0x034a
827 #define mmSDMA0_RLC5_WATERMARK_BASE_IDX                                                                0
828 #define mmSDMA0_RLC5_DOORBELL_OFFSET                                                                   0x034b
829 #define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
830 #define mmSDMA0_RLC5_CSA_ADDR_LO                                                                       0x034c
831 #define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
832 #define mmSDMA0_RLC5_CSA_ADDR_HI                                                                       0x034d
833 #define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
834 #define mmSDMA0_RLC5_IB_SUB_REMAIN                                                                     0x034f
835 #define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
836 #define mmSDMA0_RLC5_PREEMPT                                                                           0x0350
837 #define mmSDMA0_RLC5_PREEMPT_BASE_IDX                                                                  0
838 #define mmSDMA0_RLC5_DUMMY_REG                                                                         0x0351
839 #define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX                                                                0
840 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0352
841 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
842 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x0353
843 #define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
844 #define mmSDMA0_RLC5_RB_AQL_CNTL                                                                       0x0354
845 #define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
846 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE                                                                  0x0355
847 #define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
848 #define mmSDMA0_RLC5_MIDCMD_DATA0                                                                      0x0360
849 #define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
850 #define mmSDMA0_RLC5_MIDCMD_DATA1                                                                      0x0361
851 #define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
852 #define mmSDMA0_RLC5_MIDCMD_DATA2                                                                      0x0362
853 #define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
854 #define mmSDMA0_RLC5_MIDCMD_DATA3                                                                      0x0363
855 #define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
856 #define mmSDMA0_RLC5_MIDCMD_DATA4                                                                      0x0364
857 #define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
858 #define mmSDMA0_RLC5_MIDCMD_DATA5                                                                      0x0365
859 #define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
860 #define mmSDMA0_RLC5_MIDCMD_DATA6                                                                      0x0366
861 #define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
862 #define mmSDMA0_RLC5_MIDCMD_DATA7                                                                      0x0367
863 #define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
864 #define mmSDMA0_RLC5_MIDCMD_DATA8                                                                      0x0368
865 #define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
866 #define mmSDMA0_RLC5_MIDCMD_CNTL                                                                       0x0369
867 #define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
868 #define mmSDMA0_RLC6_RB_CNTL                                                                           0x0380
869 #define mmSDMA0_RLC6_RB_CNTL_BASE_IDX                                                                  0
870 #define mmSDMA0_RLC6_RB_BASE                                                                           0x0381
871 #define mmSDMA0_RLC6_RB_BASE_BASE_IDX                                                                  0
872 #define mmSDMA0_RLC6_RB_BASE_HI                                                                        0x0382
873 #define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX                                                               0
874 #define mmSDMA0_RLC6_RB_RPTR                                                                           0x0383
875 #define mmSDMA0_RLC6_RB_RPTR_BASE_IDX                                                                  0
876 #define mmSDMA0_RLC6_RB_RPTR_HI                                                                        0x0384
877 #define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
878 #define mmSDMA0_RLC6_RB_WPTR                                                                           0x0385
879 #define mmSDMA0_RLC6_RB_WPTR_BASE_IDX                                                                  0
880 #define mmSDMA0_RLC6_RB_WPTR_HI                                                                        0x0386
881 #define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
882 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0387
883 #define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
884 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI                                                                   0x0388
885 #define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
886 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO                                                                   0x0389
887 #define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
888 #define mmSDMA0_RLC6_IB_CNTL                                                                           0x038a
889 #define mmSDMA0_RLC6_IB_CNTL_BASE_IDX                                                                  0
890 #define mmSDMA0_RLC6_IB_RPTR                                                                           0x038b
891 #define mmSDMA0_RLC6_IB_RPTR_BASE_IDX                                                                  0
892 #define mmSDMA0_RLC6_IB_OFFSET                                                                         0x038c
893 #define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX                                                                0
894 #define mmSDMA0_RLC6_IB_BASE_LO                                                                        0x038d
895 #define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX                                                               0
896 #define mmSDMA0_RLC6_IB_BASE_HI                                                                        0x038e
897 #define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX                                                               0
898 #define mmSDMA0_RLC6_IB_SIZE                                                                           0x038f
899 #define mmSDMA0_RLC6_IB_SIZE_BASE_IDX                                                                  0
900 #define mmSDMA0_RLC6_SKIP_CNTL                                                                         0x0390
901 #define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX                                                                0
902 #define mmSDMA0_RLC6_CONTEXT_STATUS                                                                    0x0391
903 #define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
904 #define mmSDMA0_RLC6_DOORBELL                                                                          0x0392
905 #define mmSDMA0_RLC6_DOORBELL_BASE_IDX                                                                 0
906 #define mmSDMA0_RLC6_STATUS                                                                            0x03a8
907 #define mmSDMA0_RLC6_STATUS_BASE_IDX                                                                   0
908 #define mmSDMA0_RLC6_DOORBELL_LOG                                                                      0x03a9
909 #define mmSDMA0_RLC6_WATERMARK                                                                         0x03aa
910 #define mmSDMA0_RLC6_WATERMARK_BASE_IDX                                                                0
911 #define mmSDMA0_RLC6_DOORBELL_OFFSET                                                                   0x03ab
912 #define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
913 #define mmSDMA0_RLC6_CSA_ADDR_LO                                                                       0x03ac
914 #define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
915 #define mmSDMA0_RLC6_CSA_ADDR_HI                                                                       0x03ad
916 #define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
917 #define mmSDMA0_RLC6_IB_SUB_REMAIN                                                                     0x03af
918 #define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
919 #define mmSDMA0_RLC6_PREEMPT                                                                           0x03b0
920 #define mmSDMA0_RLC6_PREEMPT_BASE_IDX                                                                  0
921 #define mmSDMA0_RLC6_DUMMY_REG                                                                         0x03b1
922 #define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX                                                                0
923 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x03b2
924 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
925 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x03b3
926 #define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
927 #define mmSDMA0_RLC6_RB_AQL_CNTL                                                                       0x03b4
928 #define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
929 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE                                                                  0x03b5
930 #define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
931 #define mmSDMA0_RLC6_MIDCMD_DATA0                                                                      0x03c0
932 #define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
933 #define mmSDMA0_RLC6_MIDCMD_DATA1                                                                      0x03c1
934 #define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
935 #define mmSDMA0_RLC6_MIDCMD_DATA2                                                                      0x03c2
936 #define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
937 #define mmSDMA0_RLC6_MIDCMD_DATA3                                                                      0x03c3
938 #define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
939 #define mmSDMA0_RLC6_MIDCMD_DATA4                                                                      0x03c4
940 #define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
941 #define mmSDMA0_RLC6_MIDCMD_DATA5                                                                      0x03c5
942 #define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
943 #define mmSDMA0_RLC6_MIDCMD_DATA6                                                                      0x03c6
944 #define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
945 #define mmSDMA0_RLC6_MIDCMD_DATA7                                                                      0x03c7
946 #define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
947 #define mmSDMA0_RLC6_MIDCMD_DATA8                                                                      0x03c8
948 #define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
949 #define mmSDMA0_RLC6_MIDCMD_CNTL                                                                       0x03c9
950 #define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
951 #define mmSDMA0_RLC7_RB_CNTL                                                                           0x03e0
952 #define mmSDMA0_RLC7_RB_CNTL_BASE_IDX                                                                  0
953 #define mmSDMA0_RLC7_RB_BASE                                                                           0x03e1
954 #define mmSDMA0_RLC7_RB_BASE_BASE_IDX                                                                  0
955 #define mmSDMA0_RLC7_RB_BASE_HI                                                                        0x03e2
956 #define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX                                                               0
957 #define mmSDMA0_RLC7_RB_RPTR                                                                           0x03e3
958 #define mmSDMA0_RLC7_RB_RPTR_BASE_IDX                                                                  0
959 #define mmSDMA0_RLC7_RB_RPTR_HI                                                                        0x03e4
960 #define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
961 #define mmSDMA0_RLC7_RB_WPTR                                                                           0x03e5
962 #define mmSDMA0_RLC7_RB_WPTR_BASE_IDX                                                                  0
963 #define mmSDMA0_RLC7_RB_WPTR_HI                                                                        0x03e6
964 #define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
965 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL                                                                 0x03e7
966 #define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
967 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI                                                                   0x03e8
968 #define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
969 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO                                                                   0x03e9
970 #define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
971 #define mmSDMA0_RLC7_IB_CNTL                                                                           0x03ea
972 #define mmSDMA0_RLC7_IB_CNTL_BASE_IDX                                                                  0
973 #define mmSDMA0_RLC7_IB_RPTR                                                                           0x03eb
974 #define mmSDMA0_RLC7_IB_RPTR_BASE_IDX                                                                  0
975 #define mmSDMA0_RLC7_IB_OFFSET                                                                         0x03ec
976 #define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX                                                                0
977 #define mmSDMA0_RLC7_IB_BASE_LO                                                                        0x03ed
978 #define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX                                                               0
979 #define mmSDMA0_RLC7_IB_BASE_HI                                                                        0x03ee
980 #define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX                                                               0
981 #define mmSDMA0_RLC7_IB_SIZE                                                                           0x03ef
982 #define mmSDMA0_RLC7_IB_SIZE_BASE_IDX                                                                  0
983 #define mmSDMA0_RLC7_SKIP_CNTL                                                                         0x03f0
984 #define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX                                                                0
985 #define mmSDMA0_RLC7_CONTEXT_STATUS                                                                    0x03f1
986 #define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
987 #define mmSDMA0_RLC7_DOORBELL                                                                          0x03f2
988 #define mmSDMA0_RLC7_DOORBELL_BASE_IDX                                                                 0
989 #define mmSDMA0_RLC7_STATUS                                                                            0x0408
990 #define mmSDMA0_RLC7_STATUS_BASE_IDX                                                                   0
991 #define mmSDMA0_RLC7_DOORBELL_LOG                                                                      0x0409
992 #define mmSDMA0_RLC7_WATERMARK                                                                         0x040a
993 #define mmSDMA0_RLC7_WATERMARK_BASE_IDX                                                                0
994 #define mmSDMA0_RLC7_DOORBELL_OFFSET                                                                   0x040b
995 #define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
996 #define mmSDMA0_RLC7_CSA_ADDR_LO                                                                       0x040c
997 #define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
998 #define mmSDMA0_RLC7_CSA_ADDR_HI                                                                       0x040d
999 #define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
1000 #define mmSDMA0_RLC7_IB_SUB_REMAIN                                                                     0x040f
1001 #define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
1002 #define mmSDMA0_RLC7_PREEMPT                                                                           0x0410
1003 #define mmSDMA0_RLC7_PREEMPT_BASE_IDX                                                                  0
1004 #define mmSDMA0_RLC7_DUMMY_REG                                                                         0x0411
1005 #define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX                                                                0
1006 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x0412
1007 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1008 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x0413
1009 #define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1010 #define mmSDMA0_RLC7_RB_AQL_CNTL                                                                       0x0414
1011 #define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
1012 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE                                                                  0x0415
1013 #define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1014 #define mmSDMA0_RLC7_MIDCMD_DATA0                                                                      0x0420
1015 #define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
1016 #define mmSDMA0_RLC7_MIDCMD_DATA1                                                                      0x0421
1017 #define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
1018 #define mmSDMA0_RLC7_MIDCMD_DATA2                                                                      0x0422
1019 #define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
1020 #define mmSDMA0_RLC7_MIDCMD_DATA3                                                                      0x0423
1021 #define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
1022 #define mmSDMA0_RLC7_MIDCMD_DATA4                                                                      0x0424
1023 #define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
1024 #define mmSDMA0_RLC7_MIDCMD_DATA5                                                                      0x0425
1025 #define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
1026 #define mmSDMA0_RLC7_MIDCMD_DATA6                                                                      0x0426
1027 #define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
1028 #define mmSDMA0_RLC7_MIDCMD_DATA7                                                                      0x0427
1029 #define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
1030 #define mmSDMA0_RLC7_MIDCMD_DATA8                                                                      0x0428
1031 #define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
1032 #define mmSDMA0_RLC7_MIDCMD_CNTL                                                                       0x0429
1033 #define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
1034 
1035 
1036 // addressBlock: gc_sdma1_sdma1dec
1037 // base address: 0x6180
1038 #define mmSDMA1_DEC_START                                                                              0x0600
1039 #define mmSDMA1_DEC_START_BASE_IDX                                                                     0
1040 #define mmSDMA1_PG_CNTL                                                                                0x0616
1041 #define mmSDMA1_PG_CNTL_BASE_IDX                                                                       0
1042 #define mmSDMA1_PG_CTX_LO                                                                              0x0617
1043 #define mmSDMA1_PG_CTX_LO_BASE_IDX                                                                     0
1044 #define mmSDMA1_PG_CTX_HI                                                                              0x0618
1045 #define mmSDMA1_PG_CTX_HI_BASE_IDX                                                                     0
1046 #define mmSDMA1_PG_CTX_CNTL                                                                            0x0619
1047 #define mmSDMA1_PG_CTX_CNTL_BASE_IDX                                                                   0
1048 #define mmSDMA1_POWER_CNTL                                                                             0x061a
1049 #define mmSDMA1_POWER_CNTL_BASE_IDX                                                                    0
1050 #define mmSDMA1_CLK_CTRL                                                                               0x061b
1051 #define mmSDMA1_CLK_CTRL_BASE_IDX                                                                      0
1052 #define mmSDMA1_CNTL                                                                                   0x061c
1053 #define mmSDMA1_CNTL_BASE_IDX                                                                          0
1054 #define mmSDMA1_CHICKEN_BITS                                                                           0x061d
1055 #define mmSDMA1_CHICKEN_BITS_BASE_IDX                                                                  0
1056 #define mmSDMA1_GB_ADDR_CONFIG                                                                         0x061e
1057 #define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX                                                                0
1058 #define mmSDMA1_GB_ADDR_CONFIG_READ                                                                    0x061f
1059 #define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX                                                           0
1060 #define mmSDMA1_RB_RPTR_FETCH_HI                                                                       0x0620
1061 #define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX                                                              0
1062 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL                                                               0x0621
1063 #define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX                                                      0
1064 #define mmSDMA1_RB_RPTR_FETCH                                                                          0x0622
1065 #define mmSDMA1_RB_RPTR_FETCH_BASE_IDX                                                                 0
1066 #define mmSDMA1_IB_OFFSET_FETCH                                                                        0x0623
1067 #define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX                                                               0
1068 #define mmSDMA1_PROGRAM                                                                                0x0624
1069 #define mmSDMA1_PROGRAM_BASE_IDX                                                                       0
1070 #define mmSDMA1_STATUS_REG                                                                             0x0625
1071 #define mmSDMA1_STATUS_REG_BASE_IDX                                                                    0
1072 #define mmSDMA1_STATUS1_REG                                                                            0x0626
1073 #define mmSDMA1_STATUS1_REG_BASE_IDX                                                                   0
1074 #define mmSDMA1_RD_BURST_CNTL                                                                          0x0627
1075 #define mmSDMA1_RD_BURST_CNTL_BASE_IDX                                                                 0
1076 #define mmSDMA1_HBM_PAGE_CONFIG                                                                        0x0628
1077 #define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX                                                               0
1078 #define mmSDMA1_UCODE_CHECKSUM                                                                         0x0629
1079 #define mmSDMA1_UCODE_CHECKSUM_BASE_IDX                                                                0
1080 #define mmSDMA1_F32_CNTL                                                                               0x062a
1081 #define mmSDMA1_F32_CNTL_BASE_IDX                                                                      0
1082 #define mmSDMA1_FREEZE                                                                                 0x062b
1083 #define mmSDMA1_FREEZE_BASE_IDX                                                                        0
1084 #define mmSDMA1_PHASE0_QUANTUM                                                                         0x062c
1085 #define mmSDMA1_PHASE0_QUANTUM_BASE_IDX                                                                0
1086 #define mmSDMA1_PHASE1_QUANTUM                                                                         0x062d
1087 #define mmSDMA1_PHASE1_QUANTUM_BASE_IDX                                                                0
1088 #define mmSDMA1_EDC_CONFIG                                                                             0x0632
1089 #define mmSDMA1_EDC_CONFIG_BASE_IDX                                                                    0
1090 #define mmSDMA1_BA_THRESHOLD                                                                           0x0633
1091 #define mmSDMA1_BA_THRESHOLD_BASE_IDX                                                                  0
1092 #define mmSDMA1_ID                                                                                     0x0634
1093 #define mmSDMA1_ID_BASE_IDX                                                                            0
1094 #define mmSDMA1_VERSION                                                                                0x0635
1095 #define mmSDMA1_VERSION_BASE_IDX                                                                       0
1096 #define mmSDMA1_EDC_COUNTER                                                                            0x0636
1097 #define mmSDMA1_EDC_COUNTER_BASE_IDX                                                                   0
1098 #define mmSDMA1_EDC_COUNTER_CLEAR                                                                      0x0637
1099 #define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX                                                             0
1100 #define mmSDMA1_STATUS2_REG                                                                            0x0638
1101 #define mmSDMA1_STATUS2_REG_BASE_IDX                                                                   0
1102 #define mmSDMA1_ATOMIC_CNTL                                                                            0x0639
1103 #define mmSDMA1_ATOMIC_CNTL_BASE_IDX                                                                   0
1104 #define mmSDMA1_ATOMIC_PREOP_LO                                                                        0x063a
1105 #define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX                                                               0
1106 #define mmSDMA1_ATOMIC_PREOP_HI                                                                        0x063b
1107 #define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX                                                               0
1108 #define mmSDMA1_UTCL1_CNTL                                                                             0x063c
1109 #define mmSDMA1_UTCL1_CNTL_BASE_IDX                                                                    0
1110 #define mmSDMA1_UTCL1_WATERMK                                                                          0x063d
1111 #define mmSDMA1_UTCL1_WATERMK_BASE_IDX                                                                 0
1112 #define mmSDMA1_UTCL1_RD_STATUS                                                                        0x063e
1113 #define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX                                                               0
1114 #define mmSDMA1_UTCL1_WR_STATUS                                                                        0x063f
1115 #define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX                                                               0
1116 #define mmSDMA1_UTCL1_INV0                                                                             0x0640
1117 #define mmSDMA1_UTCL1_INV0_BASE_IDX                                                                    0
1118 #define mmSDMA1_UTCL1_INV1                                                                             0x0641
1119 #define mmSDMA1_UTCL1_INV1_BASE_IDX                                                                    0
1120 #define mmSDMA1_UTCL1_INV2                                                                             0x0642
1121 #define mmSDMA1_UTCL1_INV2_BASE_IDX                                                                    0
1122 #define mmSDMA1_UTCL1_RD_XNACK0                                                                        0x0643
1123 #define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX                                                               0
1124 #define mmSDMA1_UTCL1_RD_XNACK1                                                                        0x0644
1125 #define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX                                                               0
1126 #define mmSDMA1_UTCL1_WR_XNACK0                                                                        0x0645
1127 #define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX                                                               0
1128 #define mmSDMA1_UTCL1_WR_XNACK1                                                                        0x0646
1129 #define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX                                                               0
1130 #define mmSDMA1_UTCL1_TIMEOUT                                                                          0x0647
1131 #define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX                                                                 0
1132 #define mmSDMA1_UTCL1_PAGE                                                                             0x0648
1133 #define mmSDMA1_UTCL1_PAGE_BASE_IDX                                                                    0
1134 #define mmSDMA1_POWER_CNTL_IDLE                                                                        0x0649
1135 #define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX                                                               0
1136 #define mmSDMA1_RELAX_ORDERING_LUT                                                                     0x064a
1137 #define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX                                                            0
1138 #define mmSDMA1_CHICKEN_BITS_2                                                                         0x064b
1139 #define mmSDMA1_CHICKEN_BITS_2_BASE_IDX                                                                0
1140 #define mmSDMA1_STATUS3_REG                                                                            0x064c
1141 #define mmSDMA1_STATUS3_REG_BASE_IDX                                                                   0
1142 #define mmSDMA1_PHYSICAL_ADDR_LO                                                                       0x064d
1143 #define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX                                                              0
1144 #define mmSDMA1_PHYSICAL_ADDR_HI                                                                       0x064e
1145 #define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX                                                              0
1146 #define mmSDMA1_PHASE2_QUANTUM                                                                         0x064f
1147 #define mmSDMA1_PHASE2_QUANTUM_BASE_IDX                                                                0
1148 #define mmSDMA1_ERROR_LOG                                                                              0x0650
1149 #define mmSDMA1_ERROR_LOG_BASE_IDX                                                                     0
1150 #define mmSDMA1_PUB_DUMMY_REG0                                                                         0x0651
1151 #define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX                                                                0
1152 #define mmSDMA1_F32_COUNTER                                                                            0x0655
1153 #define mmSDMA1_F32_COUNTER_BASE_IDX                                                                   0
1154 #define mmSDMA1_PERFMON_CNTL                                                                           0x0657
1155 #define mmSDMA1_PERFMON_CNTL_BASE_IDX                                                                  0
1156 #define mmSDMA1_PERFCOUNTER0_RESULT                                                                    0x0658
1157 #define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX                                                           0
1158 #define mmSDMA1_PERFCOUNTER1_RESULT                                                                    0x0659
1159 #define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX                                                           0
1160 #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE                                                            0x065a
1161 #define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX                                                   0
1162 #define mmSDMA1_CRD_CNTL                                                                               0x065b
1163 #define mmSDMA1_CRD_CNTL_BASE_IDX                                                                      0
1164 #define mmSDMA1_GPU_IOV_VIOLATION_LOG                                                                  0x065d
1165 #define mmSDMA1_AQL_STATUS                                                                             0x065f
1166 #define mmSDMA1_AQL_STATUS_BASE_IDX                                                                    0
1167 #define mmSDMA1_EA_DBIT_ADDR_DATA                                                                      0x0660
1168 #define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX                                                             0
1169 #define mmSDMA1_EA_DBIT_ADDR_INDEX                                                                     0x0661
1170 #define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX                                                            0
1171 #define mmSDMA1_TLBI_GCR_CNTL                                                                          0x0662
1172 #define mmSDMA1_TLBI_GCR_CNTL_BASE_IDX                                                                 0
1173 #define mmSDMA1_TILING_CONFIG                                                                          0x0663
1174 #define mmSDMA1_TILING_CONFIG_BASE_IDX                                                                 0
1175 #define mmSDMA1_HASH                                                                                   0x0664
1176 #define mmSDMA1_HASH_BASE_IDX                                                                          0
1177 #define mmSDMA1_PERFCOUNTER0_SELECT                                                                    0x0668
1178 #define mmSDMA1_PERFCOUNTER0_SELECT_BASE_IDX                                                           0
1179 #define mmSDMA1_PERFCOUNTER0_SELECT1                                                                   0x0669
1180 #define mmSDMA1_PERFCOUNTER0_SELECT1_BASE_IDX                                                          0
1181 #define mmSDMA1_PERFCOUNTER0_LO                                                                        0x066a
1182 #define mmSDMA1_PERFCOUNTER0_LO_BASE_IDX                                                               0
1183 #define mmSDMA1_PERFCOUNTER0_HI                                                                        0x066b
1184 #define mmSDMA1_PERFCOUNTER0_HI_BASE_IDX                                                               0
1185 #define mmSDMA1_PERFCOUNTER1_SELECT                                                                    0x066c
1186 #define mmSDMA1_PERFCOUNTER1_SELECT_BASE_IDX                                                           0
1187 #define mmSDMA1_PERFCOUNTER1_SELECT1                                                                   0x066d
1188 #define mmSDMA1_PERFCOUNTER1_SELECT1_BASE_IDX                                                          0
1189 #define mmSDMA1_PERFCOUNTER1_LO                                                                        0x066e
1190 #define mmSDMA1_PERFCOUNTER1_LO_BASE_IDX                                                               0
1191 #define mmSDMA1_PERFCOUNTER1_HI                                                                        0x066f
1192 #define mmSDMA1_PERFCOUNTER1_HI_BASE_IDX                                                               0
1193 #define mmSDMA1_INT_STATUS                                                                             0x0670
1194 #define mmSDMA1_INT_STATUS_BASE_IDX                                                                    0
1195 #define mmSDMA1_GPU_IOV_VIOLATION_LOG2                                                                 0x0671
1196 #define mmSDMA1_GPU_IOV_VIOLATION_LOG2_BASE_IDX                                                        0
1197 #define mmSDMA1_HOLE_ADDR_LO                                                                           0x0672
1198 #define mmSDMA1_HOLE_ADDR_LO_BASE_IDX                                                                  0
1199 #define mmSDMA1_HOLE_ADDR_HI                                                                           0x0673
1200 #define mmSDMA1_HOLE_ADDR_HI_BASE_IDX                                                                  0
1201 #define mmSDMA1_GFX_RB_CNTL                                                                            0x0680
1202 #define mmSDMA1_GFX_RB_CNTL_BASE_IDX                                                                   0
1203 #define mmSDMA1_GFX_RB_BASE                                                                            0x0681
1204 #define mmSDMA1_GFX_RB_BASE_BASE_IDX                                                                   0
1205 #define mmSDMA1_GFX_RB_BASE_HI                                                                         0x0682
1206 #define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX                                                                0
1207 #define mmSDMA1_GFX_RB_RPTR                                                                            0x0683
1208 #define mmSDMA1_GFX_RB_RPTR_BASE_IDX                                                                   0
1209 #define mmSDMA1_GFX_RB_RPTR_HI                                                                         0x0684
1210 #define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX                                                                0
1211 #define mmSDMA1_GFX_RB_WPTR                                                                            0x0685
1212 #define mmSDMA1_GFX_RB_WPTR_BASE_IDX                                                                   0
1213 #define mmSDMA1_GFX_RB_WPTR_HI                                                                         0x0686
1214 #define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX                                                                0
1215 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL                                                                  0x0687
1216 #define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX                                                         0
1217 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI                                                                    0x0688
1218 #define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX                                                           0
1219 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO                                                                    0x0689
1220 #define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX                                                           0
1221 #define mmSDMA1_GFX_IB_CNTL                                                                            0x068a
1222 #define mmSDMA1_GFX_IB_CNTL_BASE_IDX                                                                   0
1223 #define mmSDMA1_GFX_IB_RPTR                                                                            0x068b
1224 #define mmSDMA1_GFX_IB_RPTR_BASE_IDX                                                                   0
1225 #define mmSDMA1_GFX_IB_OFFSET                                                                          0x068c
1226 #define mmSDMA1_GFX_IB_OFFSET_BASE_IDX                                                                 0
1227 #define mmSDMA1_GFX_IB_BASE_LO                                                                         0x068d
1228 #define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX                                                                0
1229 #define mmSDMA1_GFX_IB_BASE_HI                                                                         0x068e
1230 #define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX                                                                0
1231 #define mmSDMA1_GFX_IB_SIZE                                                                            0x068f
1232 #define mmSDMA1_GFX_IB_SIZE_BASE_IDX                                                                   0
1233 #define mmSDMA1_GFX_SKIP_CNTL                                                                          0x0690
1234 #define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX                                                                 0
1235 #define mmSDMA1_GFX_CONTEXT_STATUS                                                                     0x0691
1236 #define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX                                                            0
1237 #define mmSDMA1_GFX_DOORBELL                                                                           0x0692
1238 #define mmSDMA1_GFX_DOORBELL_BASE_IDX                                                                  0
1239 #define mmSDMA1_GFX_CONTEXT_CNTL                                                                       0x0693
1240 #define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX                                                              0
1241 #define mmSDMA1_GFX_STATUS                                                                             0x06a8
1242 #define mmSDMA1_GFX_STATUS_BASE_IDX                                                                    0
1243 #define mmSDMA1_GFX_DOORBELL_LOG                                                                       0x06a9
1244 #define mmSDMA1_GFX_WATERMARK                                                                          0x06aa
1245 #define mmSDMA1_GFX_WATERMARK_BASE_IDX                                                                 0
1246 #define mmSDMA1_GFX_DOORBELL_OFFSET                                                                    0x06ab
1247 #define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX                                                           0
1248 #define mmSDMA1_GFX_CSA_ADDR_LO                                                                        0x06ac
1249 #define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX                                                               0
1250 #define mmSDMA1_GFX_CSA_ADDR_HI                                                                        0x06ad
1251 #define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX                                                               0
1252 #define mmSDMA1_GFX_IB_SUB_REMAIN                                                                      0x06af
1253 #define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX                                                             0
1254 #define mmSDMA1_GFX_PREEMPT                                                                            0x06b0
1255 #define mmSDMA1_GFX_PREEMPT_BASE_IDX                                                                   0
1256 #define mmSDMA1_GFX_DUMMY_REG                                                                          0x06b1
1257 #define mmSDMA1_GFX_DUMMY_REG_BASE_IDX                                                                 0
1258 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI                                                               0x06b2
1259 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                      0
1260 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO                                                               0x06b3
1261 #define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                      0
1262 #define mmSDMA1_GFX_RB_AQL_CNTL                                                                        0x06b4
1263 #define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX                                                               0
1264 #define mmSDMA1_GFX_MINOR_PTR_UPDATE                                                                   0x06b5
1265 #define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX                                                          0
1266 #define mmSDMA1_GFX_MIDCMD_DATA0                                                                       0x06c0
1267 #define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX                                                              0
1268 #define mmSDMA1_GFX_MIDCMD_DATA1                                                                       0x06c1
1269 #define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX                                                              0
1270 #define mmSDMA1_GFX_MIDCMD_DATA2                                                                       0x06c2
1271 #define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX                                                              0
1272 #define mmSDMA1_GFX_MIDCMD_DATA3                                                                       0x06c3
1273 #define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX                                                              0
1274 #define mmSDMA1_GFX_MIDCMD_DATA4                                                                       0x06c4
1275 #define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX                                                              0
1276 #define mmSDMA1_GFX_MIDCMD_DATA5                                                                       0x06c5
1277 #define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX                                                              0
1278 #define mmSDMA1_GFX_MIDCMD_DATA6                                                                       0x06c6
1279 #define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX                                                              0
1280 #define mmSDMA1_GFX_MIDCMD_DATA7                                                                       0x06c7
1281 #define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX                                                              0
1282 #define mmSDMA1_GFX_MIDCMD_DATA8                                                                       0x06c8
1283 #define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX                                                              0
1284 #define mmSDMA1_GFX_MIDCMD_CNTL                                                                        0x06c9
1285 #define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX                                                               0
1286 #define mmSDMA1_PAGE_RB_CNTL                                                                           0x06e0
1287 #define mmSDMA1_PAGE_RB_CNTL_BASE_IDX                                                                  0
1288 #define mmSDMA1_PAGE_RB_BASE                                                                           0x06e1
1289 #define mmSDMA1_PAGE_RB_BASE_BASE_IDX                                                                  0
1290 #define mmSDMA1_PAGE_RB_BASE_HI                                                                        0x06e2
1291 #define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX                                                               0
1292 #define mmSDMA1_PAGE_RB_RPTR                                                                           0x06e3
1293 #define mmSDMA1_PAGE_RB_RPTR_BASE_IDX                                                                  0
1294 #define mmSDMA1_PAGE_RB_RPTR_HI                                                                        0x06e4
1295 #define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX                                                               0
1296 #define mmSDMA1_PAGE_RB_WPTR                                                                           0x06e5
1297 #define mmSDMA1_PAGE_RB_WPTR_BASE_IDX                                                                  0
1298 #define mmSDMA1_PAGE_RB_WPTR_HI                                                                        0x06e6
1299 #define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX                                                               0
1300 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL                                                                 0x06e7
1301 #define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1302 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI                                                                   0x06e8
1303 #define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1304 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO                                                                   0x06e9
1305 #define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1306 #define mmSDMA1_PAGE_IB_CNTL                                                                           0x06ea
1307 #define mmSDMA1_PAGE_IB_CNTL_BASE_IDX                                                                  0
1308 #define mmSDMA1_PAGE_IB_RPTR                                                                           0x06eb
1309 #define mmSDMA1_PAGE_IB_RPTR_BASE_IDX                                                                  0
1310 #define mmSDMA1_PAGE_IB_OFFSET                                                                         0x06ec
1311 #define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX                                                                0
1312 #define mmSDMA1_PAGE_IB_BASE_LO                                                                        0x06ed
1313 #define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX                                                               0
1314 #define mmSDMA1_PAGE_IB_BASE_HI                                                                        0x06ee
1315 #define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX                                                               0
1316 #define mmSDMA1_PAGE_IB_SIZE                                                                           0x06ef
1317 #define mmSDMA1_PAGE_IB_SIZE_BASE_IDX                                                                  0
1318 #define mmSDMA1_PAGE_SKIP_CNTL                                                                         0x06f0
1319 #define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX                                                                0
1320 #define mmSDMA1_PAGE_CONTEXT_STATUS                                                                    0x06f1
1321 #define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX                                                           0
1322 #define mmSDMA1_PAGE_DOORBELL                                                                          0x06f2
1323 #define mmSDMA1_PAGE_DOORBELL_BASE_IDX                                                                 0
1324 #define mmSDMA1_PAGE_STATUS                                                                            0x0708
1325 #define mmSDMA1_PAGE_STATUS_BASE_IDX                                                                   0
1326 #define mmSDMA1_PAGE_DOORBELL_LOG                                                                      0x0709
1327 #define mmSDMA1_PAGE_WATERMARK                                                                         0x070a
1328 #define mmSDMA1_PAGE_WATERMARK_BASE_IDX                                                                0
1329 #define mmSDMA1_PAGE_DOORBELL_OFFSET                                                                   0x070b
1330 #define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX                                                          0
1331 #define mmSDMA1_PAGE_CSA_ADDR_LO                                                                       0x070c
1332 #define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX                                                              0
1333 #define mmSDMA1_PAGE_CSA_ADDR_HI                                                                       0x070d
1334 #define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX                                                              0
1335 #define mmSDMA1_PAGE_IB_SUB_REMAIN                                                                     0x070f
1336 #define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX                                                            0
1337 #define mmSDMA1_PAGE_PREEMPT                                                                           0x0710
1338 #define mmSDMA1_PAGE_PREEMPT_BASE_IDX                                                                  0
1339 #define mmSDMA1_PAGE_DUMMY_REG                                                                         0x0711
1340 #define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX                                                                0
1341 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI                                                              0x0712
1342 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1343 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO                                                              0x0713
1344 #define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1345 #define mmSDMA1_PAGE_RB_AQL_CNTL                                                                       0x0714
1346 #define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX                                                              0
1347 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE                                                                  0x0715
1348 #define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1349 #define mmSDMA1_PAGE_MIDCMD_DATA0                                                                      0x0720
1350 #define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX                                                             0
1351 #define mmSDMA1_PAGE_MIDCMD_DATA1                                                                      0x0721
1352 #define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX                                                             0
1353 #define mmSDMA1_PAGE_MIDCMD_DATA2                                                                      0x0722
1354 #define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX                                                             0
1355 #define mmSDMA1_PAGE_MIDCMD_DATA3                                                                      0x0723
1356 #define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX                                                             0
1357 #define mmSDMA1_PAGE_MIDCMD_DATA4                                                                      0x0724
1358 #define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX                                                             0
1359 #define mmSDMA1_PAGE_MIDCMD_DATA5                                                                      0x0725
1360 #define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX                                                             0
1361 #define mmSDMA1_PAGE_MIDCMD_DATA6                                                                      0x0726
1362 #define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX                                                             0
1363 #define mmSDMA1_PAGE_MIDCMD_DATA7                                                                      0x0727
1364 #define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX                                                             0
1365 #define mmSDMA1_PAGE_MIDCMD_DATA8                                                                      0x0728
1366 #define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX                                                             0
1367 #define mmSDMA1_PAGE_MIDCMD_CNTL                                                                       0x0729
1368 #define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX                                                              0
1369 #define mmSDMA1_RLC0_RB_CNTL                                                                           0x0740
1370 #define mmSDMA1_RLC0_RB_CNTL_BASE_IDX                                                                  0
1371 #define mmSDMA1_RLC0_RB_BASE                                                                           0x0741
1372 #define mmSDMA1_RLC0_RB_BASE_BASE_IDX                                                                  0
1373 #define mmSDMA1_RLC0_RB_BASE_HI                                                                        0x0742
1374 #define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX                                                               0
1375 #define mmSDMA1_RLC0_RB_RPTR                                                                           0x0743
1376 #define mmSDMA1_RLC0_RB_RPTR_BASE_IDX                                                                  0
1377 #define mmSDMA1_RLC0_RB_RPTR_HI                                                                        0x0744
1378 #define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX                                                               0
1379 #define mmSDMA1_RLC0_RB_WPTR                                                                           0x0745
1380 #define mmSDMA1_RLC0_RB_WPTR_BASE_IDX                                                                  0
1381 #define mmSDMA1_RLC0_RB_WPTR_HI                                                                        0x0746
1382 #define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX                                                               0
1383 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL                                                                 0x0747
1384 #define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1385 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI                                                                   0x0748
1386 #define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1387 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO                                                                   0x0749
1388 #define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1389 #define mmSDMA1_RLC0_IB_CNTL                                                                           0x074a
1390 #define mmSDMA1_RLC0_IB_CNTL_BASE_IDX                                                                  0
1391 #define mmSDMA1_RLC0_IB_RPTR                                                                           0x074b
1392 #define mmSDMA1_RLC0_IB_RPTR_BASE_IDX                                                                  0
1393 #define mmSDMA1_RLC0_IB_OFFSET                                                                         0x074c
1394 #define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX                                                                0
1395 #define mmSDMA1_RLC0_IB_BASE_LO                                                                        0x074d
1396 #define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX                                                               0
1397 #define mmSDMA1_RLC0_IB_BASE_HI                                                                        0x074e
1398 #define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX                                                               0
1399 #define mmSDMA1_RLC0_IB_SIZE                                                                           0x074f
1400 #define mmSDMA1_RLC0_IB_SIZE_BASE_IDX                                                                  0
1401 #define mmSDMA1_RLC0_SKIP_CNTL                                                                         0x0750
1402 #define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX                                                                0
1403 #define mmSDMA1_RLC0_CONTEXT_STATUS                                                                    0x0751
1404 #define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX                                                           0
1405 #define mmSDMA1_RLC0_DOORBELL                                                                          0x0752
1406 #define mmSDMA1_RLC0_DOORBELL_BASE_IDX                                                                 0
1407 #define mmSDMA1_RLC0_STATUS                                                                            0x0768
1408 #define mmSDMA1_RLC0_STATUS_BASE_IDX                                                                   0
1409 #define mmSDMA1_RLC0_DOORBELL_LOG                                                                      0x0769
1410 #define mmSDMA1_RLC0_WATERMARK                                                                         0x076a
1411 #define mmSDMA1_RLC0_WATERMARK_BASE_IDX                                                                0
1412 #define mmSDMA1_RLC0_DOORBELL_OFFSET                                                                   0x076b
1413 #define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX                                                          0
1414 #define mmSDMA1_RLC0_CSA_ADDR_LO                                                                       0x076c
1415 #define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX                                                              0
1416 #define mmSDMA1_RLC0_CSA_ADDR_HI                                                                       0x076d
1417 #define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX                                                              0
1418 #define mmSDMA1_RLC0_IB_SUB_REMAIN                                                                     0x076f
1419 #define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX                                                            0
1420 #define mmSDMA1_RLC0_PREEMPT                                                                           0x0770
1421 #define mmSDMA1_RLC0_PREEMPT_BASE_IDX                                                                  0
1422 #define mmSDMA1_RLC0_DUMMY_REG                                                                         0x0771
1423 #define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX                                                                0
1424 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI                                                              0x0772
1425 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1426 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO                                                              0x0773
1427 #define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1428 #define mmSDMA1_RLC0_RB_AQL_CNTL                                                                       0x0774
1429 #define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX                                                              0
1430 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE                                                                  0x0775
1431 #define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1432 #define mmSDMA1_RLC0_MIDCMD_DATA0                                                                      0x0780
1433 #define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX                                                             0
1434 #define mmSDMA1_RLC0_MIDCMD_DATA1                                                                      0x0781
1435 #define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX                                                             0
1436 #define mmSDMA1_RLC0_MIDCMD_DATA2                                                                      0x0782
1437 #define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX                                                             0
1438 #define mmSDMA1_RLC0_MIDCMD_DATA3                                                                      0x0783
1439 #define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX                                                             0
1440 #define mmSDMA1_RLC0_MIDCMD_DATA4                                                                      0x0784
1441 #define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX                                                             0
1442 #define mmSDMA1_RLC0_MIDCMD_DATA5                                                                      0x0785
1443 #define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX                                                             0
1444 #define mmSDMA1_RLC0_MIDCMD_DATA6                                                                      0x0786
1445 #define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX                                                             0
1446 #define mmSDMA1_RLC0_MIDCMD_DATA7                                                                      0x0787
1447 #define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX                                                             0
1448 #define mmSDMA1_RLC0_MIDCMD_DATA8                                                                      0x0788
1449 #define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX                                                             0
1450 #define mmSDMA1_RLC0_MIDCMD_CNTL                                                                       0x0789
1451 #define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX                                                              0
1452 #define mmSDMA1_RLC1_RB_CNTL                                                                           0x07a0
1453 #define mmSDMA1_RLC1_RB_CNTL_BASE_IDX                                                                  0
1454 #define mmSDMA1_RLC1_RB_BASE                                                                           0x07a1
1455 #define mmSDMA1_RLC1_RB_BASE_BASE_IDX                                                                  0
1456 #define mmSDMA1_RLC1_RB_BASE_HI                                                                        0x07a2
1457 #define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX                                                               0
1458 #define mmSDMA1_RLC1_RB_RPTR                                                                           0x07a3
1459 #define mmSDMA1_RLC1_RB_RPTR_BASE_IDX                                                                  0
1460 #define mmSDMA1_RLC1_RB_RPTR_HI                                                                        0x07a4
1461 #define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX                                                               0
1462 #define mmSDMA1_RLC1_RB_WPTR                                                                           0x07a5
1463 #define mmSDMA1_RLC1_RB_WPTR_BASE_IDX                                                                  0
1464 #define mmSDMA1_RLC1_RB_WPTR_HI                                                                        0x07a6
1465 #define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX                                                               0
1466 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL                                                                 0x07a7
1467 #define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1468 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI                                                                   0x07a8
1469 #define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1470 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO                                                                   0x07a9
1471 #define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1472 #define mmSDMA1_RLC1_IB_CNTL                                                                           0x07aa
1473 #define mmSDMA1_RLC1_IB_CNTL_BASE_IDX                                                                  0
1474 #define mmSDMA1_RLC1_IB_RPTR                                                                           0x07ab
1475 #define mmSDMA1_RLC1_IB_RPTR_BASE_IDX                                                                  0
1476 #define mmSDMA1_RLC1_IB_OFFSET                                                                         0x07ac
1477 #define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX                                                                0
1478 #define mmSDMA1_RLC1_IB_BASE_LO                                                                        0x07ad
1479 #define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX                                                               0
1480 #define mmSDMA1_RLC1_IB_BASE_HI                                                                        0x07ae
1481 #define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX                                                               0
1482 #define mmSDMA1_RLC1_IB_SIZE                                                                           0x07af
1483 #define mmSDMA1_RLC1_IB_SIZE_BASE_IDX                                                                  0
1484 #define mmSDMA1_RLC1_SKIP_CNTL                                                                         0x07b0
1485 #define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX                                                                0
1486 #define mmSDMA1_RLC1_CONTEXT_STATUS                                                                    0x07b1
1487 #define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX                                                           0
1488 #define mmSDMA1_RLC1_DOORBELL                                                                          0x07b2
1489 #define mmSDMA1_RLC1_DOORBELL_BASE_IDX                                                                 0
1490 #define mmSDMA1_RLC1_STATUS                                                                            0x07c8
1491 #define mmSDMA1_RLC1_STATUS_BASE_IDX                                                                   0
1492 #define mmSDMA1_RLC1_DOORBELL_LOG                                                                      0x07c9
1493 #define mmSDMA1_RLC1_WATERMARK                                                                         0x07ca
1494 #define mmSDMA1_RLC1_WATERMARK_BASE_IDX                                                                0
1495 #define mmSDMA1_RLC1_DOORBELL_OFFSET                                                                   0x07cb
1496 #define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX                                                          0
1497 #define mmSDMA1_RLC1_CSA_ADDR_LO                                                                       0x07cc
1498 #define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX                                                              0
1499 #define mmSDMA1_RLC1_CSA_ADDR_HI                                                                       0x07cd
1500 #define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX                                                              0
1501 #define mmSDMA1_RLC1_IB_SUB_REMAIN                                                                     0x07cf
1502 #define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX                                                            0
1503 #define mmSDMA1_RLC1_PREEMPT                                                                           0x07d0
1504 #define mmSDMA1_RLC1_PREEMPT_BASE_IDX                                                                  0
1505 #define mmSDMA1_RLC1_DUMMY_REG                                                                         0x07d1
1506 #define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX                                                                0
1507 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI                                                              0x07d2
1508 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1509 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO                                                              0x07d3
1510 #define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1511 #define mmSDMA1_RLC1_RB_AQL_CNTL                                                                       0x07d4
1512 #define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX                                                              0
1513 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE                                                                  0x07d5
1514 #define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1515 #define mmSDMA1_RLC1_MIDCMD_DATA0                                                                      0x07e0
1516 #define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX                                                             0
1517 #define mmSDMA1_RLC1_MIDCMD_DATA1                                                                      0x07e1
1518 #define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX                                                             0
1519 #define mmSDMA1_RLC1_MIDCMD_DATA2                                                                      0x07e2
1520 #define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX                                                             0
1521 #define mmSDMA1_RLC1_MIDCMD_DATA3                                                                      0x07e3
1522 #define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX                                                             0
1523 #define mmSDMA1_RLC1_MIDCMD_DATA4                                                                      0x07e4
1524 #define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX                                                             0
1525 #define mmSDMA1_RLC1_MIDCMD_DATA5                                                                      0x07e5
1526 #define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX                                                             0
1527 #define mmSDMA1_RLC1_MIDCMD_DATA6                                                                      0x07e6
1528 #define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX                                                             0
1529 #define mmSDMA1_RLC1_MIDCMD_DATA7                                                                      0x07e7
1530 #define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX                                                             0
1531 #define mmSDMA1_RLC1_MIDCMD_DATA8                                                                      0x07e8
1532 #define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX                                                             0
1533 #define mmSDMA1_RLC1_MIDCMD_CNTL                                                                       0x07e9
1534 #define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX                                                              0
1535 #define mmSDMA1_RLC2_RB_CNTL                                                                           0x0800
1536 #define mmSDMA1_RLC2_RB_CNTL_BASE_IDX                                                                  0
1537 #define mmSDMA1_RLC2_RB_BASE                                                                           0x0801
1538 #define mmSDMA1_RLC2_RB_BASE_BASE_IDX                                                                  0
1539 #define mmSDMA1_RLC2_RB_BASE_HI                                                                        0x0802
1540 #define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX                                                               0
1541 #define mmSDMA1_RLC2_RB_RPTR                                                                           0x0803
1542 #define mmSDMA1_RLC2_RB_RPTR_BASE_IDX                                                                  0
1543 #define mmSDMA1_RLC2_RB_RPTR_HI                                                                        0x0804
1544 #define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX                                                               0
1545 #define mmSDMA1_RLC2_RB_WPTR                                                                           0x0805
1546 #define mmSDMA1_RLC2_RB_WPTR_BASE_IDX                                                                  0
1547 #define mmSDMA1_RLC2_RB_WPTR_HI                                                                        0x0806
1548 #define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX                                                               0
1549 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL                                                                 0x0807
1550 #define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1551 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI                                                                   0x0808
1552 #define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1553 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO                                                                   0x0809
1554 #define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1555 #define mmSDMA1_RLC2_IB_CNTL                                                                           0x080a
1556 #define mmSDMA1_RLC2_IB_CNTL_BASE_IDX                                                                  0
1557 #define mmSDMA1_RLC2_IB_RPTR                                                                           0x080b
1558 #define mmSDMA1_RLC2_IB_RPTR_BASE_IDX                                                                  0
1559 #define mmSDMA1_RLC2_IB_OFFSET                                                                         0x080c
1560 #define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX                                                                0
1561 #define mmSDMA1_RLC2_IB_BASE_LO                                                                        0x080d
1562 #define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX                                                               0
1563 #define mmSDMA1_RLC2_IB_BASE_HI                                                                        0x080e
1564 #define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX                                                               0
1565 #define mmSDMA1_RLC2_IB_SIZE                                                                           0x080f
1566 #define mmSDMA1_RLC2_IB_SIZE_BASE_IDX                                                                  0
1567 #define mmSDMA1_RLC2_SKIP_CNTL                                                                         0x0810
1568 #define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX                                                                0
1569 #define mmSDMA1_RLC2_CONTEXT_STATUS                                                                    0x0811
1570 #define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX                                                           0
1571 #define mmSDMA1_RLC2_DOORBELL                                                                          0x0812
1572 #define mmSDMA1_RLC2_DOORBELL_BASE_IDX                                                                 0
1573 #define mmSDMA1_RLC2_STATUS                                                                            0x0828
1574 #define mmSDMA1_RLC2_STATUS_BASE_IDX                                                                   0
1575 #define mmSDMA1_RLC2_DOORBELL_LOG                                                                      0x0829
1576 #define mmSDMA1_RLC2_WATERMARK                                                                         0x082a
1577 #define mmSDMA1_RLC2_WATERMARK_BASE_IDX                                                                0
1578 #define mmSDMA1_RLC2_DOORBELL_OFFSET                                                                   0x082b
1579 #define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX                                                          0
1580 #define mmSDMA1_RLC2_CSA_ADDR_LO                                                                       0x082c
1581 #define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX                                                              0
1582 #define mmSDMA1_RLC2_CSA_ADDR_HI                                                                       0x082d
1583 #define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX                                                              0
1584 #define mmSDMA1_RLC2_IB_SUB_REMAIN                                                                     0x082f
1585 #define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX                                                            0
1586 #define mmSDMA1_RLC2_PREEMPT                                                                           0x0830
1587 #define mmSDMA1_RLC2_PREEMPT_BASE_IDX                                                                  0
1588 #define mmSDMA1_RLC2_DUMMY_REG                                                                         0x0831
1589 #define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX                                                                0
1590 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI                                                              0x0832
1591 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1592 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO                                                              0x0833
1593 #define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1594 #define mmSDMA1_RLC2_RB_AQL_CNTL                                                                       0x0834
1595 #define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX                                                              0
1596 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE                                                                  0x0835
1597 #define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1598 #define mmSDMA1_RLC2_MIDCMD_DATA0                                                                      0x0840
1599 #define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX                                                             0
1600 #define mmSDMA1_RLC2_MIDCMD_DATA1                                                                      0x0841
1601 #define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX                                                             0
1602 #define mmSDMA1_RLC2_MIDCMD_DATA2                                                                      0x0842
1603 #define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX                                                             0
1604 #define mmSDMA1_RLC2_MIDCMD_DATA3                                                                      0x0843
1605 #define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX                                                             0
1606 #define mmSDMA1_RLC2_MIDCMD_DATA4                                                                      0x0844
1607 #define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX                                                             0
1608 #define mmSDMA1_RLC2_MIDCMD_DATA5                                                                      0x0845
1609 #define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX                                                             0
1610 #define mmSDMA1_RLC2_MIDCMD_DATA6                                                                      0x0846
1611 #define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX                                                             0
1612 #define mmSDMA1_RLC2_MIDCMD_DATA7                                                                      0x0847
1613 #define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX                                                             0
1614 #define mmSDMA1_RLC2_MIDCMD_DATA8                                                                      0x0848
1615 #define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX                                                             0
1616 #define mmSDMA1_RLC2_MIDCMD_CNTL                                                                       0x0849
1617 #define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX                                                              0
1618 #define mmSDMA1_RLC3_RB_CNTL                                                                           0x0860
1619 #define mmSDMA1_RLC3_RB_CNTL_BASE_IDX                                                                  0
1620 #define mmSDMA1_RLC3_RB_BASE                                                                           0x0861
1621 #define mmSDMA1_RLC3_RB_BASE_BASE_IDX                                                                  0
1622 #define mmSDMA1_RLC3_RB_BASE_HI                                                                        0x0862
1623 #define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX                                                               0
1624 #define mmSDMA1_RLC3_RB_RPTR                                                                           0x0863
1625 #define mmSDMA1_RLC3_RB_RPTR_BASE_IDX                                                                  0
1626 #define mmSDMA1_RLC3_RB_RPTR_HI                                                                        0x0864
1627 #define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX                                                               0
1628 #define mmSDMA1_RLC3_RB_WPTR                                                                           0x0865
1629 #define mmSDMA1_RLC3_RB_WPTR_BASE_IDX                                                                  0
1630 #define mmSDMA1_RLC3_RB_WPTR_HI                                                                        0x0866
1631 #define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX                                                               0
1632 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL                                                                 0x0867
1633 #define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1634 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI                                                                   0x0868
1635 #define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1636 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO                                                                   0x0869
1637 #define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1638 #define mmSDMA1_RLC3_IB_CNTL                                                                           0x086a
1639 #define mmSDMA1_RLC3_IB_CNTL_BASE_IDX                                                                  0
1640 #define mmSDMA1_RLC3_IB_RPTR                                                                           0x086b
1641 #define mmSDMA1_RLC3_IB_RPTR_BASE_IDX                                                                  0
1642 #define mmSDMA1_RLC3_IB_OFFSET                                                                         0x086c
1643 #define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX                                                                0
1644 #define mmSDMA1_RLC3_IB_BASE_LO                                                                        0x086d
1645 #define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX                                                               0
1646 #define mmSDMA1_RLC3_IB_BASE_HI                                                                        0x086e
1647 #define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX                                                               0
1648 #define mmSDMA1_RLC3_IB_SIZE                                                                           0x086f
1649 #define mmSDMA1_RLC3_IB_SIZE_BASE_IDX                                                                  0
1650 #define mmSDMA1_RLC3_SKIP_CNTL                                                                         0x0870
1651 #define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX                                                                0
1652 #define mmSDMA1_RLC3_CONTEXT_STATUS                                                                    0x0871
1653 #define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX                                                           0
1654 #define mmSDMA1_RLC3_DOORBELL                                                                          0x0872
1655 #define mmSDMA1_RLC3_DOORBELL_BASE_IDX                                                                 0
1656 #define mmSDMA1_RLC3_STATUS                                                                            0x0888
1657 #define mmSDMA1_RLC3_STATUS_BASE_IDX                                                                   0
1658 #define mmSDMA1_RLC3_DOORBELL_LOG                                                                      0x0889
1659 #define mmSDMA1_RLC3_WATERMARK                                                                         0x088a
1660 #define mmSDMA1_RLC3_WATERMARK_BASE_IDX                                                                0
1661 #define mmSDMA1_RLC3_DOORBELL_OFFSET                                                                   0x088b
1662 #define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX                                                          0
1663 #define mmSDMA1_RLC3_CSA_ADDR_LO                                                                       0x088c
1664 #define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX                                                              0
1665 #define mmSDMA1_RLC3_CSA_ADDR_HI                                                                       0x088d
1666 #define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX                                                              0
1667 #define mmSDMA1_RLC3_IB_SUB_REMAIN                                                                     0x088f
1668 #define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX                                                            0
1669 #define mmSDMA1_RLC3_PREEMPT                                                                           0x0890
1670 #define mmSDMA1_RLC3_PREEMPT_BASE_IDX                                                                  0
1671 #define mmSDMA1_RLC3_DUMMY_REG                                                                         0x0891
1672 #define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX                                                                0
1673 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI                                                              0x0892
1674 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1675 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO                                                              0x0893
1676 #define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1677 #define mmSDMA1_RLC3_RB_AQL_CNTL                                                                       0x0894
1678 #define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX                                                              0
1679 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE                                                                  0x0895
1680 #define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1681 #define mmSDMA1_RLC3_MIDCMD_DATA0                                                                      0x08a0
1682 #define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX                                                             0
1683 #define mmSDMA1_RLC3_MIDCMD_DATA1                                                                      0x08a1
1684 #define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX                                                             0
1685 #define mmSDMA1_RLC3_MIDCMD_DATA2                                                                      0x08a2
1686 #define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX                                                             0
1687 #define mmSDMA1_RLC3_MIDCMD_DATA3                                                                      0x08a3
1688 #define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX                                                             0
1689 #define mmSDMA1_RLC3_MIDCMD_DATA4                                                                      0x08a4
1690 #define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX                                                             0
1691 #define mmSDMA1_RLC3_MIDCMD_DATA5                                                                      0x08a5
1692 #define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX                                                             0
1693 #define mmSDMA1_RLC3_MIDCMD_DATA6                                                                      0x08a6
1694 #define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX                                                             0
1695 #define mmSDMA1_RLC3_MIDCMD_DATA7                                                                      0x08a7
1696 #define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX                                                             0
1697 #define mmSDMA1_RLC3_MIDCMD_DATA8                                                                      0x08a8
1698 #define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX                                                             0
1699 #define mmSDMA1_RLC3_MIDCMD_CNTL                                                                       0x08a9
1700 #define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX                                                              0
1701 #define mmSDMA1_RLC4_RB_CNTL                                                                           0x08c0
1702 #define mmSDMA1_RLC4_RB_CNTL_BASE_IDX                                                                  0
1703 #define mmSDMA1_RLC4_RB_BASE                                                                           0x08c1
1704 #define mmSDMA1_RLC4_RB_BASE_BASE_IDX                                                                  0
1705 #define mmSDMA1_RLC4_RB_BASE_HI                                                                        0x08c2
1706 #define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX                                                               0
1707 #define mmSDMA1_RLC4_RB_RPTR                                                                           0x08c3
1708 #define mmSDMA1_RLC4_RB_RPTR_BASE_IDX                                                                  0
1709 #define mmSDMA1_RLC4_RB_RPTR_HI                                                                        0x08c4
1710 #define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX                                                               0
1711 #define mmSDMA1_RLC4_RB_WPTR                                                                           0x08c5
1712 #define mmSDMA1_RLC4_RB_WPTR_BASE_IDX                                                                  0
1713 #define mmSDMA1_RLC4_RB_WPTR_HI                                                                        0x08c6
1714 #define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX                                                               0
1715 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL                                                                 0x08c7
1716 #define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1717 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI                                                                   0x08c8
1718 #define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1719 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO                                                                   0x08c9
1720 #define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1721 #define mmSDMA1_RLC4_IB_CNTL                                                                           0x08ca
1722 #define mmSDMA1_RLC4_IB_CNTL_BASE_IDX                                                                  0
1723 #define mmSDMA1_RLC4_IB_RPTR                                                                           0x08cb
1724 #define mmSDMA1_RLC4_IB_RPTR_BASE_IDX                                                                  0
1725 #define mmSDMA1_RLC4_IB_OFFSET                                                                         0x08cc
1726 #define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX                                                                0
1727 #define mmSDMA1_RLC4_IB_BASE_LO                                                                        0x08cd
1728 #define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX                                                               0
1729 #define mmSDMA1_RLC4_IB_BASE_HI                                                                        0x08ce
1730 #define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX                                                               0
1731 #define mmSDMA1_RLC4_IB_SIZE                                                                           0x08cf
1732 #define mmSDMA1_RLC4_IB_SIZE_BASE_IDX                                                                  0
1733 #define mmSDMA1_RLC4_SKIP_CNTL                                                                         0x08d0
1734 #define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX                                                                0
1735 #define mmSDMA1_RLC4_CONTEXT_STATUS                                                                    0x08d1
1736 #define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX                                                           0
1737 #define mmSDMA1_RLC4_DOORBELL                                                                          0x08d2
1738 #define mmSDMA1_RLC4_DOORBELL_BASE_IDX                                                                 0
1739 #define mmSDMA1_RLC4_STATUS                                                                            0x08e8
1740 #define mmSDMA1_RLC4_STATUS_BASE_IDX                                                                   0
1741 #define mmSDMA1_RLC4_DOORBELL_LOG                                                                      0x08e9
1742 #define mmSDMA1_RLC4_WATERMARK                                                                         0x08ea
1743 #define mmSDMA1_RLC4_WATERMARK_BASE_IDX                                                                0
1744 #define mmSDMA1_RLC4_DOORBELL_OFFSET                                                                   0x08eb
1745 #define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX                                                          0
1746 #define mmSDMA1_RLC4_CSA_ADDR_LO                                                                       0x08ec
1747 #define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX                                                              0
1748 #define mmSDMA1_RLC4_CSA_ADDR_HI                                                                       0x08ed
1749 #define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX                                                              0
1750 #define mmSDMA1_RLC4_IB_SUB_REMAIN                                                                     0x08ef
1751 #define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX                                                            0
1752 #define mmSDMA1_RLC4_PREEMPT                                                                           0x08f0
1753 #define mmSDMA1_RLC4_PREEMPT_BASE_IDX                                                                  0
1754 #define mmSDMA1_RLC4_DUMMY_REG                                                                         0x08f1
1755 #define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX                                                                0
1756 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI                                                              0x08f2
1757 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1758 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO                                                              0x08f3
1759 #define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1760 #define mmSDMA1_RLC4_RB_AQL_CNTL                                                                       0x08f4
1761 #define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX                                                              0
1762 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE                                                                  0x08f5
1763 #define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1764 #define mmSDMA1_RLC4_MIDCMD_DATA0                                                                      0x0900
1765 #define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX                                                             0
1766 #define mmSDMA1_RLC4_MIDCMD_DATA1                                                                      0x0901
1767 #define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX                                                             0
1768 #define mmSDMA1_RLC4_MIDCMD_DATA2                                                                      0x0902
1769 #define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX                                                             0
1770 #define mmSDMA1_RLC4_MIDCMD_DATA3                                                                      0x0903
1771 #define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX                                                             0
1772 #define mmSDMA1_RLC4_MIDCMD_DATA4                                                                      0x0904
1773 #define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX                                                             0
1774 #define mmSDMA1_RLC4_MIDCMD_DATA5                                                                      0x0905
1775 #define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX                                                             0
1776 #define mmSDMA1_RLC4_MIDCMD_DATA6                                                                      0x0906
1777 #define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX                                                             0
1778 #define mmSDMA1_RLC4_MIDCMD_DATA7                                                                      0x0907
1779 #define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX                                                             0
1780 #define mmSDMA1_RLC4_MIDCMD_DATA8                                                                      0x0908
1781 #define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX                                                             0
1782 #define mmSDMA1_RLC4_MIDCMD_CNTL                                                                       0x0909
1783 #define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX                                                              0
1784 #define mmSDMA1_RLC5_RB_CNTL                                                                           0x0920
1785 #define mmSDMA1_RLC5_RB_CNTL_BASE_IDX                                                                  0
1786 #define mmSDMA1_RLC5_RB_BASE                                                                           0x0921
1787 #define mmSDMA1_RLC5_RB_BASE_BASE_IDX                                                                  0
1788 #define mmSDMA1_RLC5_RB_BASE_HI                                                                        0x0922
1789 #define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX                                                               0
1790 #define mmSDMA1_RLC5_RB_RPTR                                                                           0x0923
1791 #define mmSDMA1_RLC5_RB_RPTR_BASE_IDX                                                                  0
1792 #define mmSDMA1_RLC5_RB_RPTR_HI                                                                        0x0924
1793 #define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX                                                               0
1794 #define mmSDMA1_RLC5_RB_WPTR                                                                           0x0925
1795 #define mmSDMA1_RLC5_RB_WPTR_BASE_IDX                                                                  0
1796 #define mmSDMA1_RLC5_RB_WPTR_HI                                                                        0x0926
1797 #define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX                                                               0
1798 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL                                                                 0x0927
1799 #define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1800 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI                                                                   0x0928
1801 #define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1802 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO                                                                   0x0929
1803 #define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1804 #define mmSDMA1_RLC5_IB_CNTL                                                                           0x092a
1805 #define mmSDMA1_RLC5_IB_CNTL_BASE_IDX                                                                  0
1806 #define mmSDMA1_RLC5_IB_RPTR                                                                           0x092b
1807 #define mmSDMA1_RLC5_IB_RPTR_BASE_IDX                                                                  0
1808 #define mmSDMA1_RLC5_IB_OFFSET                                                                         0x092c
1809 #define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX                                                                0
1810 #define mmSDMA1_RLC5_IB_BASE_LO                                                                        0x092d
1811 #define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX                                                               0
1812 #define mmSDMA1_RLC5_IB_BASE_HI                                                                        0x092e
1813 #define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX                                                               0
1814 #define mmSDMA1_RLC5_IB_SIZE                                                                           0x092f
1815 #define mmSDMA1_RLC5_IB_SIZE_BASE_IDX                                                                  0
1816 #define mmSDMA1_RLC5_SKIP_CNTL                                                                         0x0930
1817 #define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX                                                                0
1818 #define mmSDMA1_RLC5_CONTEXT_STATUS                                                                    0x0931
1819 #define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX                                                           0
1820 #define mmSDMA1_RLC5_DOORBELL                                                                          0x0932
1821 #define mmSDMA1_RLC5_DOORBELL_BASE_IDX                                                                 0
1822 #define mmSDMA1_RLC5_STATUS                                                                            0x0948
1823 #define mmSDMA1_RLC5_STATUS_BASE_IDX                                                                   0
1824 #define mmSDMA1_RLC5_DOORBELL_LOG                                                                      0x0949
1825 #define mmSDMA1_RLC5_WATERMARK                                                                         0x094a
1826 #define mmSDMA1_RLC5_WATERMARK_BASE_IDX                                                                0
1827 #define mmSDMA1_RLC5_DOORBELL_OFFSET                                                                   0x094b
1828 #define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX                                                          0
1829 #define mmSDMA1_RLC5_CSA_ADDR_LO                                                                       0x094c
1830 #define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX                                                              0
1831 #define mmSDMA1_RLC5_CSA_ADDR_HI                                                                       0x094d
1832 #define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX                                                              0
1833 #define mmSDMA1_RLC5_IB_SUB_REMAIN                                                                     0x094f
1834 #define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX                                                            0
1835 #define mmSDMA1_RLC5_PREEMPT                                                                           0x0950
1836 #define mmSDMA1_RLC5_PREEMPT_BASE_IDX                                                                  0
1837 #define mmSDMA1_RLC5_DUMMY_REG                                                                         0x0951
1838 #define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX                                                                0
1839 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI                                                              0x0952
1840 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1841 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO                                                              0x0953
1842 #define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1843 #define mmSDMA1_RLC5_RB_AQL_CNTL                                                                       0x0954
1844 #define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX                                                              0
1845 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE                                                                  0x0955
1846 #define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1847 #define mmSDMA1_RLC5_MIDCMD_DATA0                                                                      0x0960
1848 #define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX                                                             0
1849 #define mmSDMA1_RLC5_MIDCMD_DATA1                                                                      0x0961
1850 #define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX                                                             0
1851 #define mmSDMA1_RLC5_MIDCMD_DATA2                                                                      0x0962
1852 #define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX                                                             0
1853 #define mmSDMA1_RLC5_MIDCMD_DATA3                                                                      0x0963
1854 #define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX                                                             0
1855 #define mmSDMA1_RLC5_MIDCMD_DATA4                                                                      0x0964
1856 #define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX                                                             0
1857 #define mmSDMA1_RLC5_MIDCMD_DATA5                                                                      0x0965
1858 #define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX                                                             0
1859 #define mmSDMA1_RLC5_MIDCMD_DATA6                                                                      0x0966
1860 #define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX                                                             0
1861 #define mmSDMA1_RLC5_MIDCMD_DATA7                                                                      0x0967
1862 #define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX                                                             0
1863 #define mmSDMA1_RLC5_MIDCMD_DATA8                                                                      0x0968
1864 #define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX                                                             0
1865 #define mmSDMA1_RLC5_MIDCMD_CNTL                                                                       0x0969
1866 #define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX                                                              0
1867 #define mmSDMA1_RLC6_RB_CNTL                                                                           0x0980
1868 #define mmSDMA1_RLC6_RB_CNTL_BASE_IDX                                                                  0
1869 #define mmSDMA1_RLC6_RB_BASE                                                                           0x0981
1870 #define mmSDMA1_RLC6_RB_BASE_BASE_IDX                                                                  0
1871 #define mmSDMA1_RLC6_RB_BASE_HI                                                                        0x0982
1872 #define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX                                                               0
1873 #define mmSDMA1_RLC6_RB_RPTR                                                                           0x0983
1874 #define mmSDMA1_RLC6_RB_RPTR_BASE_IDX                                                                  0
1875 #define mmSDMA1_RLC6_RB_RPTR_HI                                                                        0x0984
1876 #define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX                                                               0
1877 #define mmSDMA1_RLC6_RB_WPTR                                                                           0x0985
1878 #define mmSDMA1_RLC6_RB_WPTR_BASE_IDX                                                                  0
1879 #define mmSDMA1_RLC6_RB_WPTR_HI                                                                        0x0986
1880 #define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX                                                               0
1881 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL                                                                 0x0987
1882 #define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1883 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI                                                                   0x0988
1884 #define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1885 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO                                                                   0x0989
1886 #define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1887 #define mmSDMA1_RLC6_IB_CNTL                                                                           0x098a
1888 #define mmSDMA1_RLC6_IB_CNTL_BASE_IDX                                                                  0
1889 #define mmSDMA1_RLC6_IB_RPTR                                                                           0x098b
1890 #define mmSDMA1_RLC6_IB_RPTR_BASE_IDX                                                                  0
1891 #define mmSDMA1_RLC6_IB_OFFSET                                                                         0x098c
1892 #define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX                                                                0
1893 #define mmSDMA1_RLC6_IB_BASE_LO                                                                        0x098d
1894 #define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX                                                               0
1895 #define mmSDMA1_RLC6_IB_BASE_HI                                                                        0x098e
1896 #define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX                                                               0
1897 #define mmSDMA1_RLC6_IB_SIZE                                                                           0x098f
1898 #define mmSDMA1_RLC6_IB_SIZE_BASE_IDX                                                                  0
1899 #define mmSDMA1_RLC6_SKIP_CNTL                                                                         0x0990
1900 #define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX                                                                0
1901 #define mmSDMA1_RLC6_CONTEXT_STATUS                                                                    0x0991
1902 #define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX                                                           0
1903 #define mmSDMA1_RLC6_DOORBELL                                                                          0x0992
1904 #define mmSDMA1_RLC6_DOORBELL_BASE_IDX                                                                 0
1905 #define mmSDMA1_RLC6_STATUS                                                                            0x09a8
1906 #define mmSDMA1_RLC6_STATUS_BASE_IDX                                                                   0
1907 #define mmSDMA1_RLC6_DOORBELL_LOG                                                                      0x09a9
1908 #define mmSDMA1_RLC6_WATERMARK                                                                         0x09aa
1909 #define mmSDMA1_RLC6_WATERMARK_BASE_IDX                                                                0
1910 #define mmSDMA1_RLC6_DOORBELL_OFFSET                                                                   0x09ab
1911 #define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX                                                          0
1912 #define mmSDMA1_RLC6_CSA_ADDR_LO                                                                       0x09ac
1913 #define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX                                                              0
1914 #define mmSDMA1_RLC6_CSA_ADDR_HI                                                                       0x09ad
1915 #define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX                                                              0
1916 #define mmSDMA1_RLC6_IB_SUB_REMAIN                                                                     0x09af
1917 #define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX                                                            0
1918 #define mmSDMA1_RLC6_PREEMPT                                                                           0x09b0
1919 #define mmSDMA1_RLC6_PREEMPT_BASE_IDX                                                                  0
1920 #define mmSDMA1_RLC6_DUMMY_REG                                                                         0x09b1
1921 #define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX                                                                0
1922 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI                                                              0x09b2
1923 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
1924 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO                                                              0x09b3
1925 #define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
1926 #define mmSDMA1_RLC6_RB_AQL_CNTL                                                                       0x09b4
1927 #define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX                                                              0
1928 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE                                                                  0x09b5
1929 #define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX                                                         0
1930 #define mmSDMA1_RLC6_MIDCMD_DATA0                                                                      0x09c0
1931 #define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX                                                             0
1932 #define mmSDMA1_RLC6_MIDCMD_DATA1                                                                      0x09c1
1933 #define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX                                                             0
1934 #define mmSDMA1_RLC6_MIDCMD_DATA2                                                                      0x09c2
1935 #define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX                                                             0
1936 #define mmSDMA1_RLC6_MIDCMD_DATA3                                                                      0x09c3
1937 #define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX                                                             0
1938 #define mmSDMA1_RLC6_MIDCMD_DATA4                                                                      0x09c4
1939 #define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX                                                             0
1940 #define mmSDMA1_RLC6_MIDCMD_DATA5                                                                      0x09c5
1941 #define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX                                                             0
1942 #define mmSDMA1_RLC6_MIDCMD_DATA6                                                                      0x09c6
1943 #define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX                                                             0
1944 #define mmSDMA1_RLC6_MIDCMD_DATA7                                                                      0x09c7
1945 #define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX                                                             0
1946 #define mmSDMA1_RLC6_MIDCMD_DATA8                                                                      0x09c8
1947 #define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX                                                             0
1948 #define mmSDMA1_RLC6_MIDCMD_CNTL                                                                       0x09c9
1949 #define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX                                                              0
1950 #define mmSDMA1_RLC7_RB_CNTL                                                                           0x09e0
1951 #define mmSDMA1_RLC7_RB_CNTL_BASE_IDX                                                                  0
1952 #define mmSDMA1_RLC7_RB_BASE                                                                           0x09e1
1953 #define mmSDMA1_RLC7_RB_BASE_BASE_IDX                                                                  0
1954 #define mmSDMA1_RLC7_RB_BASE_HI                                                                        0x09e2
1955 #define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX                                                               0
1956 #define mmSDMA1_RLC7_RB_RPTR                                                                           0x09e3
1957 #define mmSDMA1_RLC7_RB_RPTR_BASE_IDX                                                                  0
1958 #define mmSDMA1_RLC7_RB_RPTR_HI                                                                        0x09e4
1959 #define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX                                                               0
1960 #define mmSDMA1_RLC7_RB_WPTR                                                                           0x09e5
1961 #define mmSDMA1_RLC7_RB_WPTR_BASE_IDX                                                                  0
1962 #define mmSDMA1_RLC7_RB_WPTR_HI                                                                        0x09e6
1963 #define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX                                                               0
1964 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL                                                                 0x09e7
1965 #define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX                                                        0
1966 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI                                                                   0x09e8
1967 #define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX                                                          0
1968 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO                                                                   0x09e9
1969 #define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX                                                          0
1970 #define mmSDMA1_RLC7_IB_CNTL                                                                           0x09ea
1971 #define mmSDMA1_RLC7_IB_CNTL_BASE_IDX                                                                  0
1972 #define mmSDMA1_RLC7_IB_RPTR                                                                           0x09eb
1973 #define mmSDMA1_RLC7_IB_RPTR_BASE_IDX                                                                  0
1974 #define mmSDMA1_RLC7_IB_OFFSET                                                                         0x09ec
1975 #define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX                                                                0
1976 #define mmSDMA1_RLC7_IB_BASE_LO                                                                        0x09ed
1977 #define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX                                                               0
1978 #define mmSDMA1_RLC7_IB_BASE_HI                                                                        0x09ee
1979 #define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX                                                               0
1980 #define mmSDMA1_RLC7_IB_SIZE                                                                           0x09ef
1981 #define mmSDMA1_RLC7_IB_SIZE_BASE_IDX                                                                  0
1982 #define mmSDMA1_RLC7_SKIP_CNTL                                                                         0x09f0
1983 #define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX                                                                0
1984 #define mmSDMA1_RLC7_CONTEXT_STATUS                                                                    0x09f1
1985 #define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX                                                           0
1986 #define mmSDMA1_RLC7_DOORBELL                                                                          0x09f2
1987 #define mmSDMA1_RLC7_DOORBELL_BASE_IDX                                                                 0
1988 #define mmSDMA1_RLC7_STATUS                                                                            0x0a08
1989 #define mmSDMA1_RLC7_STATUS_BASE_IDX                                                                   0
1990 #define mmSDMA1_RLC7_DOORBELL_LOG                                                                      0x0a09
1991 #define mmSDMA1_RLC7_WATERMARK                                                                         0x0a0a
1992 #define mmSDMA1_RLC7_WATERMARK_BASE_IDX                                                                0
1993 #define mmSDMA1_RLC7_DOORBELL_OFFSET                                                                   0x0a0b
1994 #define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX                                                          0
1995 #define mmSDMA1_RLC7_CSA_ADDR_LO                                                                       0x0a0c
1996 #define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX                                                              0
1997 #define mmSDMA1_RLC7_CSA_ADDR_HI                                                                       0x0a0d
1998 #define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX                                                              0
1999 #define mmSDMA1_RLC7_IB_SUB_REMAIN                                                                     0x0a0f
2000 #define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX                                                            0
2001 #define mmSDMA1_RLC7_PREEMPT                                                                           0x0a10
2002 #define mmSDMA1_RLC7_PREEMPT_BASE_IDX                                                                  0
2003 #define mmSDMA1_RLC7_DUMMY_REG                                                                         0x0a11
2004 #define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX                                                                0
2005 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI                                                              0x0a12
2006 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
2007 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO                                                              0x0a13
2008 #define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
2009 #define mmSDMA1_RLC7_RB_AQL_CNTL                                                                       0x0a14
2010 #define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX                                                              0
2011 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE                                                                  0x0a15
2012 #define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX                                                         0
2013 #define mmSDMA1_RLC7_MIDCMD_DATA0                                                                      0x0a20
2014 #define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX                                                             0
2015 #define mmSDMA1_RLC7_MIDCMD_DATA1                                                                      0x0a21
2016 #define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX                                                             0
2017 #define mmSDMA1_RLC7_MIDCMD_DATA2                                                                      0x0a22
2018 #define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX                                                             0
2019 #define mmSDMA1_RLC7_MIDCMD_DATA3                                                                      0x0a23
2020 #define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX                                                             0
2021 #define mmSDMA1_RLC7_MIDCMD_DATA4                                                                      0x0a24
2022 #define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX                                                             0
2023 #define mmSDMA1_RLC7_MIDCMD_DATA5                                                                      0x0a25
2024 #define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX                                                             0
2025 #define mmSDMA1_RLC7_MIDCMD_DATA6                                                                      0x0a26
2026 #define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX                                                             0
2027 #define mmSDMA1_RLC7_MIDCMD_DATA7                                                                      0x0a27
2028 #define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX                                                             0
2029 #define mmSDMA1_RLC7_MIDCMD_DATA8                                                                      0x0a28
2030 #define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX                                                             0
2031 #define mmSDMA1_RLC7_MIDCMD_CNTL                                                                       0x0a29
2032 #define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX                                                              0
2033 
2034 
2035 // addressBlock: gc_grbmdec
2036 // base address: 0x8000
2037 #define mmGRBM_CNTL                                                                                    0x0da0
2038 #define mmGRBM_CNTL_BASE_IDX                                                                           0
2039 #define mmGRBM_SKEW_CNTL                                                                               0x0da1
2040 #define mmGRBM_SKEW_CNTL_BASE_IDX                                                                      0
2041 #define mmGRBM_STATUS2                                                                                 0x0da2
2042 #define mmGRBM_STATUS2_BASE_IDX                                                                        0
2043 #define mmGRBM_PWR_CNTL                                                                                0x0da3
2044 #define mmGRBM_PWR_CNTL_BASE_IDX                                                                       0
2045 #define mmGRBM_STATUS                                                                                  0x0da4
2046 #define mmGRBM_STATUS_BASE_IDX                                                                         0
2047 #define mmGRBM_STATUS_SE0                                                                              0x0da5
2048 #define mmGRBM_STATUS_SE0_BASE_IDX                                                                     0
2049 #define mmGRBM_STATUS_SE1                                                                              0x0da6
2050 #define mmGRBM_STATUS_SE1_BASE_IDX                                                                     0
2051 #define mmGRBM_STATUS3                                                                                 0x0da7
2052 #define mmGRBM_STATUS3_BASE_IDX                                                                        0
2053 #define mmGRBM_SOFT_RESET                                                                              0x0da8
2054 #define mmGRBM_SOFT_RESET_BASE_IDX                                                                     0
2055 #define mmGRBM_GFX_CLKEN_CNTL                                                                          0x0dac
2056 #define mmGRBM_GFX_CLKEN_CNTL_BASE_IDX                                                                 0
2057 #define mmGRBM_WAIT_IDLE_CLOCKS                                                                        0x0dad
2058 #define mmGRBM_WAIT_IDLE_CLOCKS_BASE_IDX                                                               0
2059 #define mmGRBM_STATUS_SE2                                                                              0x0dae
2060 #define mmGRBM_STATUS_SE2_BASE_IDX                                                                     0
2061 #define mmGRBM_STATUS_SE3                                                                              0x0daf
2062 #define mmGRBM_STATUS_SE3_BASE_IDX                                                                     0
2063 #define mmGRBM_PM_CNTL                                                                                 0x0db0
2064 #define mmGRBM_PM_CNTL_BASE_IDX                                                                        0
2065 #define mmGRBM_READ_ERROR                                                                              0x0db6
2066 #define mmGRBM_READ_ERROR_BASE_IDX                                                                     0
2067 #define mmGRBM_READ_ERROR2                                                                             0x0db7
2068 #define mmGRBM_READ_ERROR2_BASE_IDX                                                                    0
2069 #define mmGRBM_INT_CNTL                                                                                0x0db8
2070 #define mmGRBM_INT_CNTL_BASE_IDX                                                                       0
2071 #define mmGRBM_TRAP_OP                                                                                 0x0db9
2072 #define mmGRBM_TRAP_OP_BASE_IDX                                                                        0
2073 #define mmGRBM_TRAP_ADDR                                                                               0x0dba
2074 #define mmGRBM_TRAP_ADDR_BASE_IDX                                                                      0
2075 #define mmGRBM_TRAP_ADDR_MSK                                                                           0x0dbb
2076 #define mmGRBM_TRAP_ADDR_MSK_BASE_IDX                                                                  0
2077 #define mmGRBM_TRAP_WD                                                                                 0x0dbc
2078 #define mmGRBM_TRAP_WD_BASE_IDX                                                                        0
2079 #define mmGRBM_TRAP_WD_MSK                                                                             0x0dbd
2080 #define mmGRBM_TRAP_WD_MSK_BASE_IDX                                                                    0
2081 #define mmGRBM_DSM_BYPASS                                                                              0x0dbe
2082 #define mmGRBM_DSM_BYPASS_BASE_IDX                                                                     0
2083 #define mmGRBM_WRITE_ERROR                                                                             0x0dbf
2084 #define mmGRBM_WRITE_ERROR_BASE_IDX                                                                    0
2085 #define mmGRBM_IOV_ERROR                                                                               0x0dc0
2086 #define mmGRBM_IOV_ERROR_BASE_IDX                                                                      0
2087 #define mmGRBM_CHIP_REVISION                                                                           0x0dc1
2088 #define mmGRBM_CHIP_REVISION_BASE_IDX                                                                  0
2089 #define mmGRBM_GFX_CNTL                                                                                0x0dc2
2090 #define mmGRBM_GFX_CNTL_BASE_IDX                                                                       0
2091 #define mmGRBM_IH_CREDIT                                                                               0x0dc4
2092 #define mmGRBM_IH_CREDIT_BASE_IDX                                                                      0
2093 #define mmGRBM_PWR_CNTL2                                                                               0x0dc5
2094 #define mmGRBM_PWR_CNTL2_BASE_IDX                                                                      0
2095 #define mmGRBM_UTCL2_INVAL_RANGE_START                                                                 0x0dc6
2096 #define mmGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX                                                        0
2097 #define mmGRBM_UTCL2_INVAL_RANGE_END                                                                   0x0dc7
2098 #define mmGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX                                                          0
2099 #define mmGRBM_IOV_READ_ERROR                                                                          0x0dc9
2100 #define mmGRBM_IOV_READ_ERROR_BASE_IDX                                                                 0
2101 #define mmGRBM_FENCE_RANGE0                                                                            0x0dca
2102 #define mmGRBM_FENCE_RANGE0_BASE_IDX                                                                   0
2103 #define mmGRBM_FENCE_RANGE1                                                                            0x0dcb
2104 #define mmGRBM_FENCE_RANGE1_BASE_IDX                                                                   0
2105 #define mmGRBM_NOWHERE                                                                                 0x0ddf
2106 #define mmGRBM_NOWHERE_BASE_IDX                                                                        0
2107 #define mmGRBM_SCRATCH_REG0                                                                            0x0de0
2108 #define mmGRBM_SCRATCH_REG0_BASE_IDX                                                                   0
2109 #define mmGRBM_SCRATCH_REG1                                                                            0x0de1
2110 #define mmGRBM_SCRATCH_REG1_BASE_IDX                                                                   0
2111 #define mmGRBM_SCRATCH_REG2                                                                            0x0de2
2112 #define mmGRBM_SCRATCH_REG2_BASE_IDX                                                                   0
2113 #define mmGRBM_SCRATCH_REG3                                                                            0x0de3
2114 #define mmGRBM_SCRATCH_REG3_BASE_IDX                                                                   0
2115 #define mmGRBM_SCRATCH_REG4                                                                            0x0de4
2116 #define mmGRBM_SCRATCH_REG4_BASE_IDX                                                                   0
2117 #define mmGRBM_SCRATCH_REG5                                                                            0x0de5
2118 #define mmGRBM_SCRATCH_REG5_BASE_IDX                                                                   0
2119 #define mmGRBM_SCRATCH_REG6                                                                            0x0de6
2120 #define mmGRBM_SCRATCH_REG6_BASE_IDX                                                                   0
2121 #define mmGRBM_SCRATCH_REG7                                                                            0x0de7
2122 #define mmGRBM_SCRATCH_REG7_BASE_IDX                                                                   0
2123 
2124 
2125 // addressBlock: gc_cpdec
2126 // base address: 0x8200
2127 #define mmCP_CPC_STATUS                                                                                0x0e24
2128 #define mmCP_CPC_STATUS_BASE_IDX                                                                       0
2129 #define mmCP_CPC_BUSY_STAT                                                                             0x0e25
2130 #define mmCP_CPC_BUSY_STAT_BASE_IDX                                                                    0
2131 #define mmCP_CPC_STALLED_STAT1                                                                         0x0e26
2132 #define mmCP_CPC_STALLED_STAT1_BASE_IDX                                                                0
2133 #define mmCP_CPF_STATUS                                                                                0x0e27
2134 #define mmCP_CPF_STATUS_BASE_IDX                                                                       0
2135 #define mmCP_CPF_BUSY_STAT                                                                             0x0e28
2136 #define mmCP_CPF_BUSY_STAT_BASE_IDX                                                                    0
2137 #define mmCP_CPF_STALLED_STAT1                                                                         0x0e29
2138 #define mmCP_CPF_STALLED_STAT1_BASE_IDX                                                                0
2139 #define mmCP_CPC_BUSY_STAT2                                                                            0x0e2a
2140 #define mmCP_CPC_BUSY_STAT2_BASE_IDX                                                                   0
2141 #define mmCP_CPC_GRBM_FREE_COUNT                                                                       0x0e2b
2142 #define mmCP_CPC_GRBM_FREE_COUNT_BASE_IDX                                                              0
2143 #define mmCP_MEC_CNTL                                                                                  0x0e2d
2144 #define mmCP_MEC_CNTL_BASE_IDX                                                                         0
2145 #define mmCP_MEC_ME1_HEADER_DUMP                                                                       0x0e2e
2146 #define mmCP_MEC_ME1_HEADER_DUMP_BASE_IDX                                                              0
2147 #define mmCP_MEC_ME2_HEADER_DUMP                                                                       0x0e2f
2148 #define mmCP_MEC_ME2_HEADER_DUMP_BASE_IDX                                                              0
2149 #define mmCP_CPC_SCRATCH_INDEX                                                                         0x0e30
2150 #define mmCP_CPC_SCRATCH_INDEX_BASE_IDX                                                                0
2151 #define mmCP_CPC_SCRATCH_DATA                                                                          0x0e31
2152 #define mmCP_CPC_SCRATCH_DATA_BASE_IDX                                                                 0
2153 #define mmCP_CPF_GRBM_FREE_COUNT                                                                       0x0e32
2154 #define mmCP_CPF_GRBM_FREE_COUNT_BASE_IDX                                                              0
2155 #define mmCP_CPF_BUSY_STAT2                                                                            0x0e33
2156 #define mmCP_CPF_BUSY_STAT2_BASE_IDX                                                                   0
2157 #define mmCP_CPC_HALT_HYST_COUNT                                                                       0x0e47
2158 #define mmCP_CPC_HALT_HYST_COUNT_BASE_IDX                                                              0
2159 #define mmCP_CE_COMPARE_COUNT                                                                          0x0e60
2160 #define mmCP_CE_COMPARE_COUNT_BASE_IDX                                                                 0
2161 #define mmCP_CE_DE_COUNT                                                                               0x0e61
2162 #define mmCP_CE_DE_COUNT_BASE_IDX                                                                      0
2163 #define mmCP_DE_CE_COUNT                                                                               0x0e62
2164 #define mmCP_DE_CE_COUNT_BASE_IDX                                                                      0
2165 #define mmCP_DE_LAST_INVAL_COUNT                                                                       0x0e63
2166 #define mmCP_DE_LAST_INVAL_COUNT_BASE_IDX                                                              0
2167 #define mmCP_DE_DE_COUNT                                                                               0x0e64
2168 #define mmCP_DE_DE_COUNT_BASE_IDX                                                                      0
2169 #define mmCP_STALLED_STAT3                                                                             0x0f3c
2170 #define mmCP_STALLED_STAT3_BASE_IDX                                                                    0
2171 #define mmCP_STALLED_STAT1                                                                             0x0f3d
2172 #define mmCP_STALLED_STAT1_BASE_IDX                                                                    0
2173 #define mmCP_STALLED_STAT2                                                                             0x0f3e
2174 #define mmCP_STALLED_STAT2_BASE_IDX                                                                    0
2175 #define mmCP_BUSY_STAT                                                                                 0x0f3f
2176 #define mmCP_BUSY_STAT_BASE_IDX                                                                        0
2177 #define mmCP_STAT                                                                                      0x0f40
2178 #define mmCP_STAT_BASE_IDX                                                                             0
2179 #define mmCP_ME_HEADER_DUMP                                                                            0x0f41
2180 #define mmCP_ME_HEADER_DUMP_BASE_IDX                                                                   0
2181 #define mmCP_PFP_HEADER_DUMP                                                                           0x0f42
2182 #define mmCP_PFP_HEADER_DUMP_BASE_IDX                                                                  0
2183 #define mmCP_GRBM_FREE_COUNT                                                                           0x0f43
2184 #define mmCP_GRBM_FREE_COUNT_BASE_IDX                                                                  0
2185 #define mmCP_CE_HEADER_DUMP                                                                            0x0f44
2186 #define mmCP_CE_HEADER_DUMP_BASE_IDX                                                                   0
2187 #define mmCP_PFP_INSTR_PNTR                                                                            0x0f45
2188 #define mmCP_PFP_INSTR_PNTR_BASE_IDX                                                                   0
2189 #define mmCP_ME_INSTR_PNTR                                                                             0x0f46
2190 #define mmCP_ME_INSTR_PNTR_BASE_IDX                                                                    0
2191 #define mmCP_CE_INSTR_PNTR                                                                             0x0f47
2192 #define mmCP_CE_INSTR_PNTR_BASE_IDX                                                                    0
2193 #define mmCP_MEC1_INSTR_PNTR                                                                           0x0f48
2194 #define mmCP_MEC1_INSTR_PNTR_BASE_IDX                                                                  0
2195 #define mmCP_MEC2_INSTR_PNTR                                                                           0x0f49
2196 #define mmCP_MEC2_INSTR_PNTR_BASE_IDX                                                                  0
2197 #define mmCP_CSF_STAT                                                                                  0x0f54
2198 #define mmCP_CSF_STAT_BASE_IDX                                                                         0
2199 #define mmCP_ME_CNTL                                                                                   0x0f56
2200 #define mmCP_ME_CNTL_BASE_IDX                                                                          0
2201 #define mmCP_CNTX_STAT                                                                                 0x0f58
2202 #define mmCP_CNTX_STAT_BASE_IDX                                                                        0
2203 #define mmCP_ME_PREEMPTION                                                                             0x0f59
2204 #define mmCP_ME_PREEMPTION_BASE_IDX                                                                    0
2205 #define mmCP_ROQ_THRESHOLDS                                                                            0x0f5c
2206 #define mmCP_ROQ_THRESHOLDS_BASE_IDX                                                                   0
2207 #define mmCP_MEQ_STQ_THRESHOLD                                                                         0x0f5d
2208 #define mmCP_MEQ_STQ_THRESHOLD_BASE_IDX                                                                0
2209 #define mmCP_RB2_RPTR                                                                                  0x0f5e
2210 #define mmCP_RB2_RPTR_BASE_IDX                                                                         0
2211 #define mmCP_RB1_RPTR                                                                                  0x0f5f
2212 #define mmCP_RB1_RPTR_BASE_IDX                                                                         0
2213 #define mmCP_RB0_RPTR                                                                                  0x0f60
2214 #define mmCP_RB0_RPTR_BASE_IDX                                                                         0
2215 #define mmCP_RB_RPTR                                                                                   0x0f60
2216 #define mmCP_RB_RPTR_BASE_IDX                                                                          0
2217 #define mmCP_RB_WPTR_DELAY                                                                             0x0f61
2218 #define mmCP_RB_WPTR_DELAY_BASE_IDX                                                                    0
2219 #define mmCP_RB_WPTR_POLL_CNTL                                                                         0x0f62
2220 #define mmCP_RB_WPTR_POLL_CNTL_BASE_IDX                                                                0
2221 #define mmCP_ROQ1_THRESHOLDS                                                                           0x0f75
2222 #define mmCP_ROQ1_THRESHOLDS_BASE_IDX                                                                  0
2223 #define mmCP_ROQ2_THRESHOLDS                                                                           0x0f76
2224 #define mmCP_ROQ2_THRESHOLDS_BASE_IDX                                                                  0
2225 #define mmCP_STQ_THRESHOLDS                                                                            0x0f77
2226 #define mmCP_STQ_THRESHOLDS_BASE_IDX                                                                   0
2227 #define mmCP_QUEUE_THRESHOLDS                                                                          0x0f78
2228 #define mmCP_QUEUE_THRESHOLDS_BASE_IDX                                                                 0
2229 #define mmCP_MEQ_THRESHOLDS                                                                            0x0f79
2230 #define mmCP_MEQ_THRESHOLDS_BASE_IDX                                                                   0
2231 #define mmCP_ROQ_AVAIL                                                                                 0x0f7a
2232 #define mmCP_ROQ_AVAIL_BASE_IDX                                                                        0
2233 #define mmCP_STQ_AVAIL                                                                                 0x0f7b
2234 #define mmCP_STQ_AVAIL_BASE_IDX                                                                        0
2235 #define mmCP_ROQ2_AVAIL                                                                                0x0f7c
2236 #define mmCP_ROQ2_AVAIL_BASE_IDX                                                                       0
2237 #define mmCP_MEQ_AVAIL                                                                                 0x0f7d
2238 #define mmCP_MEQ_AVAIL_BASE_IDX                                                                        0
2239 #define mmCP_CMD_INDEX                                                                                 0x0f7e
2240 #define mmCP_CMD_INDEX_BASE_IDX                                                                        0
2241 #define mmCP_CMD_DATA                                                                                  0x0f7f
2242 #define mmCP_CMD_DATA_BASE_IDX                                                                         0
2243 #define mmCP_ROQ_RB_STAT                                                                               0x0f80
2244 #define mmCP_ROQ_RB_STAT_BASE_IDX                                                                      0
2245 #define mmCP_ROQ_IB1_STAT                                                                              0x0f81
2246 #define mmCP_ROQ_IB1_STAT_BASE_IDX                                                                     0
2247 #define mmCP_ROQ_IB2_STAT                                                                              0x0f82
2248 #define mmCP_ROQ_IB2_STAT_BASE_IDX                                                                     0
2249 #define mmCP_STQ_STAT                                                                                  0x0f83
2250 #define mmCP_STQ_STAT_BASE_IDX                                                                         0
2251 #define mmCP_STQ_WR_STAT                                                                               0x0f84
2252 #define mmCP_STQ_WR_STAT_BASE_IDX                                                                      0
2253 #define mmCP_MEQ_STAT                                                                                  0x0f85
2254 #define mmCP_MEQ_STAT_BASE_IDX                                                                         0
2255 #define mmCP_CEQ1_AVAIL                                                                                0x0f86
2256 #define mmCP_CEQ1_AVAIL_BASE_IDX                                                                       0
2257 #define mmCP_CEQ2_AVAIL                                                                                0x0f87
2258 #define mmCP_CEQ2_AVAIL_BASE_IDX                                                                       0
2259 #define mmCP_CE_ROQ_RB_STAT                                                                            0x0f88
2260 #define mmCP_CE_ROQ_RB_STAT_BASE_IDX                                                                   0
2261 #define mmCP_CE_ROQ_IB1_STAT                                                                           0x0f89
2262 #define mmCP_CE_ROQ_IB1_STAT_BASE_IDX                                                                  0
2263 #define mmCP_CE_ROQ_IB2_STAT                                                                           0x0f8a
2264 #define mmCP_CE_ROQ_IB2_STAT_BASE_IDX                                                                  0
2265 #define mmCP_CE_ROQ_DB_STAT                                                                            0x0f8b
2266 #define mmCP_CE_ROQ_DB_STAT_BASE_IDX                                                                   0
2267 #define mmCP_ROQ3_THRESHOLDS                                                                           0x0f8c
2268 #define mmCP_ROQ3_THRESHOLDS_BASE_IDX                                                                  0
2269 #define mmCP_ROQ_DB_STAT                                                                               0x0f8d
2270 #define mmCP_ROQ_DB_STAT_BASE_IDX                                                                      0
2271 
2272 
2273 // addressBlock: gc_padec
2274 // base address: 0x8800
2275 #define mmVGT_VTX_VECT_EJECT_REG                                                                       0x0fcc
2276 #define mmVGT_VTX_VECT_EJECT_REG_BASE_IDX                                                              0
2277 #define mmVGT_DMA_DATA_FIFO_DEPTH                                                                      0x0fcd
2278 #define mmVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX                                                             0
2279 #define mmVGT_DMA_REQ_FIFO_DEPTH                                                                       0x0fce
2280 #define mmVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX                                                              0
2281 #define mmVGT_DRAW_INIT_FIFO_DEPTH                                                                     0x0fcf
2282 #define mmVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX                                                            0
2283 #define mmVGT_LAST_COPY_STATE                                                                          0x0fd0
2284 #define mmVGT_LAST_COPY_STATE_BASE_IDX                                                                 0
2285 #define mmVGT_CACHE_INVALIDATION                                                                       0x0fd1
2286 #define mmVGT_CACHE_INVALIDATION_BASE_IDX                                                              0
2287 #define mmVGT_ESGS_RING_SIZE                                                                           0x0fd2
2288 #define mmVGT_ESGS_RING_SIZE_BASE_IDX                                                                  0
2289 #define mmVGT_GSVS_RING_SIZE                                                                           0x0fd3
2290 #define mmVGT_GSVS_RING_SIZE_BASE_IDX                                                                  0
2291 #define mmVGT_FIFO_DEPTHS                                                                              0x0fd4
2292 #define mmVGT_FIFO_DEPTHS_BASE_IDX                                                                     0
2293 #define mmVGT_GS_VERTEX_REUSE                                                                          0x0fd5
2294 #define mmVGT_GS_VERTEX_REUSE_BASE_IDX                                                                 0
2295 #define mmVGT_MC_LAT_CNTL                                                                              0x0fd6
2296 #define mmVGT_MC_LAT_CNTL_BASE_IDX                                                                     0
2297 #define mmIA_UTCL1_STATUS_2                                                                            0x0fd7
2298 #define mmIA_UTCL1_STATUS_2_BASE_IDX                                                                   0
2299 #define mmVGT_CNTL_STATUS                                                                              0x0fdc
2300 #define mmVGT_CNTL_STATUS_BASE_IDX                                                                     0
2301 #define mmWD_CNTL_STATUS                                                                               0x0fdf
2302 #define mmWD_CNTL_STATUS_BASE_IDX                                                                      0
2303 #define mmCC_GC_PRIM_CONFIG                                                                            0x0fe0
2304 #define mmCC_GC_PRIM_CONFIG_BASE_IDX                                                                   0
2305 #define mmGC_USER_PRIM_CONFIG                                                                          0x0fe1
2306 #define mmGC_USER_PRIM_CONFIG_BASE_IDX                                                                 0
2307 #define mmWD_QOS                                                                                       0x0fe2
2308 #define mmWD_QOS_BASE_IDX                                                                              0
2309 #define mmWD_UTCL1_CNTL                                                                                0x0fe3
2310 #define mmWD_UTCL1_CNTL_BASE_IDX                                                                       0
2311 #define mmWD_UTCL1_STATUS                                                                              0x0fe4
2312 #define mmWD_UTCL1_STATUS_BASE_IDX                                                                     0
2313 #define mmGE_PC_CNTL                                                                                   0x0fe5
2314 #define mmGE_PC_CNTL_BASE_IDX                                                                          0
2315 #define mmIA_UTCL1_CNTL                                                                                0x0fe6
2316 #define mmIA_UTCL1_CNTL_BASE_IDX                                                                       0
2317 #define mmIA_UTCL1_STATUS                                                                              0x0fe7
2318 #define mmIA_UTCL1_STATUS_BASE_IDX                                                                     0
2319 #define mmGE_FAST_CLKS                                                                                 0x0fe8
2320 #define mmGE_FAST_CLKS_BASE_IDX                                                                        0
2321 #define mmVGT_TF_RING_SIZE                                                                             0x1002
2322 #define mmVGT_TF_RING_SIZE_BASE_IDX                                                                    0
2323 #define mmVGT_SYS_CONFIG                                                                               0x1003
2324 #define mmVGT_SYS_CONFIG_BASE_IDX                                                                      0
2325 #define mmGE_PRIV_CONTROL                                                                              0x1004
2326 #define mmGE_PRIV_CONTROL_BASE_IDX                                                                     0
2327 #define mmGE_STATUS                                                                                    0x1005
2328 #define mmGE_STATUS_BASE_IDX                                                                           0
2329 #define mmVGT_VS_MAX_WAVE_ID                                                                           0x1008
2330 #define mmVGT_VS_MAX_WAVE_ID_BASE_IDX                                                                  0
2331 #define mmVGT_GS_MAX_WAVE_ID                                                                           0x1009
2332 #define mmVGT_GS_MAX_WAVE_ID_BASE_IDX                                                                  0
2333 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0                                                               0x100b
2334 #define mmCC_GC_SHADER_ARRAY_CONFIG_GEN0_BASE_IDX                                                      0
2335 #define mmVGT_HS_OFFCHIP_PARAM                                                                         0x100c
2336 #define mmVGT_HS_OFFCHIP_PARAM_BASE_IDX                                                                0
2337 #define mmGFX_PIPE_CONTROL                                                                             0x100d
2338 #define mmGFX_PIPE_CONTROL_BASE_IDX                                                                    0
2339 #define mmVGT_TF_MEMORY_BASE                                                                           0x100e
2340 #define mmVGT_TF_MEMORY_BASE_BASE_IDX                                                                  0
2341 #define mmCC_GC_SHADER_ARRAY_CONFIG                                                                    0x100f
2342 #define mmCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX                                                           0
2343 #define mmGC_USER_SHADER_ARRAY_CONFIG                                                                  0x1010
2344 #define mmGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX                                                         0
2345 #define mmVGT_DMA_PRIMITIVE_TYPE                                                                       0x1011
2346 #define mmVGT_DMA_PRIMITIVE_TYPE_BASE_IDX                                                              0
2347 #define mmVGT_DMA_CONTROL                                                                              0x1012
2348 #define mmVGT_DMA_CONTROL_BASE_IDX                                                                     0
2349 #define mmVGT_DMA_LS_HS_CONFIG                                                                         0x1013
2350 #define mmVGT_DMA_LS_HS_CONFIG_BASE_IDX                                                                0
2351 #define mmVGT_STRMOUT_DELAY                                                                            0x1015
2352 #define mmVGT_STRMOUT_DELAY_BASE_IDX                                                                   0
2353 #define mmWD_BUF_RESOURCE_1                                                                            0x1016
2354 #define mmWD_BUF_RESOURCE_1_BASE_IDX                                                                   0
2355 #define mmWD_BUF_RESOURCE_2                                                                            0x1017
2356 #define mmWD_BUF_RESOURCE_2_BASE_IDX                                                                   0
2357 #define mmVGT_TF_MEMORY_BASE_HI                                                                        0x1018
2358 #define mmVGT_TF_MEMORY_BASE_HI_BASE_IDX                                                               0
2359 #define mmPA_CL_CNTL_STATUS                                                                            0x1024
2360 #define mmPA_CL_CNTL_STATUS_BASE_IDX                                                                   0
2361 #define mmPA_CL_ENHANCE                                                                                0x1025
2362 #define mmPA_CL_ENHANCE_BASE_IDX                                                                       0
2363 #define mmPA_SU_CNTL_STATUS                                                                            0x1034
2364 #define mmPA_SU_CNTL_STATUS_BASE_IDX                                                                   0
2365 #define mmPA_SC_FIFO_DEPTH_CNTL                                                                        0x1035
2366 #define mmPA_SC_FIFO_DEPTH_CNTL_BASE_IDX                                                               0
2367 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK                                                                0x1060
2368 #define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                       0
2369 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK                                                               0x1061
2370 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                      0
2371 #define mmPA_SC_TRAP_SCREEN_HV_LOCK                                                                    0x1062
2372 #define mmPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX                                                           0
2373 #define mmPA_SC_FORCE_EOV_MAX_CNTS                                                                     0x1069
2374 #define mmPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX                                                            0
2375 #define mmPA_SC_BINNER_EVENT_CNTL_0                                                                    0x106c
2376 #define mmPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX                                                           0
2377 #define mmPA_SC_BINNER_EVENT_CNTL_1                                                                    0x106d
2378 #define mmPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX                                                           0
2379 #define mmPA_SC_BINNER_EVENT_CNTL_2                                                                    0x106e
2380 #define mmPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX                                                           0
2381 #define mmPA_SC_BINNER_EVENT_CNTL_3                                                                    0x106f
2382 #define mmPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX                                                           0
2383 #define mmPA_SC_BINNER_TIMEOUT_COUNTER                                                                 0x1070
2384 #define mmPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX                                                        0
2385 #define mmPA_SC_BINNER_PERF_CNTL_0                                                                     0x1071
2386 #define mmPA_SC_BINNER_PERF_CNTL_0_BASE_IDX                                                            0
2387 #define mmPA_SC_BINNER_PERF_CNTL_1                                                                     0x1072
2388 #define mmPA_SC_BINNER_PERF_CNTL_1_BASE_IDX                                                            0
2389 #define mmPA_SC_BINNER_PERF_CNTL_2                                                                     0x1073
2390 #define mmPA_SC_BINNER_PERF_CNTL_2_BASE_IDX                                                            0
2391 #define mmPA_SC_BINNER_PERF_CNTL_3                                                                     0x1074
2392 #define mmPA_SC_BINNER_PERF_CNTL_3_BASE_IDX                                                            0
2393 #define mmPA_SC_ENHANCE_2                                                                              0x107c
2394 #define mmPA_SC_ENHANCE_2_BASE_IDX                                                                     0
2395 #define mmPA_SC_ENHANCE_INTERNAL                                                                       0x107d
2396 #define mmPA_SC_ENHANCE_INTERNAL_BASE_IDX                                                              0
2397 #define mmPA_SC_BINNER_CNTL_OVERRIDE                                                                   0x107e
2398 #define mmPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX                                                          0
2399 #define mmPA_SC_PBB_OVERRIDE_FLAG                                                                      0x107f
2400 #define mmPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX                                                             0
2401 #define mmPA_PH_INTERFACE_FIFO_SIZE                                                                    0x1080
2402 #define mmPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX                                                           0
2403 #define mmPA_PH_ENHANCE                                                                                0x1081
2404 #define mmPA_PH_ENHANCE_BASE_IDX                                                                       0
2405 #define mmPA_SC_BC_WAVE_BREAK                                                                          0x1084
2406 #define mmPA_SC_BC_WAVE_BREAK_BASE_IDX                                                                 0
2407 #define mmPA_SC_FIFO_SIZE                                                                              0x1093
2408 #define mmPA_SC_FIFO_SIZE_BASE_IDX                                                                     0
2409 #define mmPA_SC_IF_FIFO_SIZE                                                                           0x1095
2410 #define mmPA_SC_IF_FIFO_SIZE_BASE_IDX                                                                  0
2411 #define mmPA_SC_PKR_WAVE_TABLE_CNTL                                                                    0x1098
2412 #define mmPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX                                                           0
2413 #define mmPA_SIDEBAND_REQUEST_DELAYS                                                                   0x109b
2414 #define mmPA_SIDEBAND_REQUEST_DELAYS_BASE_IDX                                                          0
2415 #define mmPA_SC_ENHANCE                                                                                0x109c
2416 #define mmPA_SC_ENHANCE_BASE_IDX                                                                       0
2417 #define mmPA_SC_ENHANCE_1                                                                              0x109d
2418 #define mmPA_SC_ENHANCE_1_BASE_IDX                                                                     0
2419 #define mmPA_SC_DSM_CNTL                                                                               0x109e
2420 #define mmPA_SC_DSM_CNTL_BASE_IDX                                                                      0
2421 #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE                                                           0x109f
2422 #define mmPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX                                                  0
2423 
2424 
2425 // addressBlock: gc_sqdec
2426 // base address: 0x8c00
2427 #define mmSQ_CONFIG                                                                                    0x10a0
2428 #define mmSQ_CONFIG_BASE_IDX                                                                           0
2429 #define mmSQC_CONFIG                                                                                   0x10a1
2430 #define mmSQC_CONFIG_BASE_IDX                                                                          0
2431 #define mmLDS_CONFIG                                                                                   0x10a2
2432 #define mmLDS_CONFIG_BASE_IDX                                                                          0
2433 #define mmSQ_RANDOM_WAVE_PRI                                                                           0x10a3
2434 #define mmSQ_RANDOM_WAVE_PRI_BASE_IDX                                                                  0
2435 #define mmSQG_STATUS                                                                                   0x10a4
2436 #define mmSQG_STATUS_BASE_IDX                                                                          0
2437 #define mmSQ_FIFO_SIZES                                                                                0x10a5
2438 #define mmSQ_FIFO_SIZES_BASE_IDX                                                                       0
2439 #define mmSQ_DSM_CNTL                                                                                  0x10a6
2440 #define mmSQ_DSM_CNTL_BASE_IDX                                                                         0
2441 #define mmSQ_DSM_CNTL2                                                                                 0x10a7
2442 #define mmSQ_DSM_CNTL2_BASE_IDX                                                                        0
2443 #define mmSQ_RUNTIME_CONFIG                                                                            0x10a8
2444 #define mmSQ_RUNTIME_CONFIG_BASE_IDX                                                                   0
2445 #define mmSH_MEM_BASES                                                                                 0x10aa
2446 #define mmSH_MEM_BASES_BASE_IDX                                                                        0
2447 #define mmSP_CONFIG                                                                                    0x10ab
2448 #define mmSP_CONFIG_BASE_IDX                                                                           0
2449 #define mmSQ_ARB_CONFIG                                                                                0x10ac
2450 #define mmSQ_ARB_CONFIG_BASE_IDX                                                                       0
2451 #define mmSH_MEM_CONFIG                                                                                0x10ad
2452 #define mmSH_MEM_CONFIG_BASE_IDX                                                                       0
2453 #define mmCC_GC_SHADER_RATE_CONFIG                                                                     0x10b2
2454 #define mmCC_GC_SHADER_RATE_CONFIG_BASE_IDX                                                            0
2455 #define mmGC_USER_SHADER_RATE_CONFIG                                                                   0x10b3
2456 #define mmGC_USER_SHADER_RATE_CONFIG_BASE_IDX                                                          0
2457 #define mmSQ_INTERRUPT_AUTO_MASK                                                                       0x10b4
2458 #define mmSQ_INTERRUPT_AUTO_MASK_BASE_IDX                                                              0
2459 #define mmSQ_INTERRUPT_MSG_CTRL                                                                        0x10b5
2460 #define mmSQ_INTERRUPT_MSG_CTRL_BASE_IDX                                                               0
2461 #define mmSQG_UTCL0_CNTL1                                                                              0x10b7
2462 #define mmSQG_UTCL0_CNTL1_BASE_IDX                                                                     0
2463 #define mmSQG_UTCL0_CNTL2                                                                              0x10b8
2464 #define mmSQG_UTCL0_CNTL2_BASE_IDX                                                                     0
2465 #define mmSQG_UTCL0_STATUS                                                                             0x10b9
2466 #define mmSQG_UTCL0_STATUS_BASE_IDX                                                                    0
2467 #define mmSQG_CONFIG                                                                                   0x10ba
2468 #define mmSQG_CONFIG_BASE_IDX                                                                          0
2469 #define mmSQ_SHADER_TBA_LO                                                                             0x10bc
2470 #define mmSQ_SHADER_TBA_LO_BASE_IDX                                                                    0
2471 #define mmSQ_SHADER_TBA_HI                                                                             0x10bd
2472 #define mmSQ_SHADER_TBA_HI_BASE_IDX                                                                    0
2473 #define mmSQ_SHADER_TMA_LO                                                                             0x10be
2474 #define mmSQ_SHADER_TMA_LO_BASE_IDX                                                                    0
2475 #define mmSQ_SHADER_TMA_HI                                                                             0x10bf
2476 #define mmSQ_SHADER_TMA_HI_BASE_IDX                                                                    0
2477 #define mmSQ_WATCH0_ADDR_H                                                                             0x10d0
2478 #define mmSQ_WATCH0_ADDR_H_BASE_IDX                                                                    0
2479 #define mmSQ_WATCH0_ADDR_L                                                                             0x10d1
2480 #define mmSQ_WATCH0_ADDR_L_BASE_IDX                                                                    0
2481 #define mmSQ_WATCH0_CNTL                                                                               0x10d2
2482 #define mmSQ_WATCH0_CNTL_BASE_IDX                                                                      0
2483 #define mmSQ_WATCH1_ADDR_H                                                                             0x10d3
2484 #define mmSQ_WATCH1_ADDR_H_BASE_IDX                                                                    0
2485 #define mmSQ_WATCH1_ADDR_L                                                                             0x10d4
2486 #define mmSQ_WATCH1_ADDR_L_BASE_IDX                                                                    0
2487 #define mmSQ_WATCH1_CNTL                                                                               0x10d5
2488 #define mmSQ_WATCH1_CNTL_BASE_IDX                                                                      0
2489 #define mmSQ_WATCH2_ADDR_H                                                                             0x10d6
2490 #define mmSQ_WATCH2_ADDR_H_BASE_IDX                                                                    0
2491 #define mmSQ_WATCH2_ADDR_L                                                                             0x10d7
2492 #define mmSQ_WATCH2_ADDR_L_BASE_IDX                                                                    0
2493 #define mmSQ_WATCH2_CNTL                                                                               0x10d8
2494 #define mmSQ_WATCH2_CNTL_BASE_IDX                                                                      0
2495 #define mmSQ_WATCH3_ADDR_H                                                                             0x10d9
2496 #define mmSQ_WATCH3_ADDR_H_BASE_IDX                                                                    0
2497 #define mmSQ_WATCH3_ADDR_L                                                                             0x10da
2498 #define mmSQ_WATCH3_ADDR_L_BASE_IDX                                                                    0
2499 #define mmSQ_WATCH3_CNTL                                                                               0x10db
2500 #define mmSQ_WATCH3_CNTL_BASE_IDX                                                                      0
2501 #define mmSQ_THREAD_TRACE_BUF0_BASE                                                                    0x10e0
2502 #define mmSQ_THREAD_TRACE_BUF0_BASE_BASE_IDX                                                           0
2503 #define mmSQ_THREAD_TRACE_BUF0_SIZE                                                                    0x10e1
2504 #define mmSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX                                                           0
2505 #define mmSQ_THREAD_TRACE_BUF1_BASE                                                                    0x10e2
2506 #define mmSQ_THREAD_TRACE_BUF1_BASE_BASE_IDX                                                           0
2507 #define mmSQ_THREAD_TRACE_BUF1_SIZE                                                                    0x10e3
2508 #define mmSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX                                                           0
2509 #define mmSQ_THREAD_TRACE_WPTR                                                                         0x10e4
2510 #define mmSQ_THREAD_TRACE_WPTR_BASE_IDX                                                                0
2511 #define mmSQ_THREAD_TRACE_MASK                                                                         0x10e5
2512 #define mmSQ_THREAD_TRACE_MASK_BASE_IDX                                                                0
2513 #define mmSQ_THREAD_TRACE_TOKEN_MASK                                                                   0x10e6
2514 #define mmSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX                                                          0
2515 #define mmSQ_THREAD_TRACE_CTRL                                                                         0x10e7
2516 #define mmSQ_THREAD_TRACE_CTRL_BASE_IDX                                                                0
2517 #define mmSQ_THREAD_TRACE_STATUS                                                                       0x10e8
2518 #define mmSQ_THREAD_TRACE_STATUS_BASE_IDX                                                              0
2519 #define mmSQ_THREAD_TRACE_DROPPED_CNTR                                                                 0x10e9
2520 #define mmSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX                                                        0
2521 #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR                                                                0x10eb
2522 #define mmSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX                                                       0
2523 #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR                                                              0x10ec
2524 #define mmSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX                                                     0
2525 #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR                                                               0x10ed
2526 #define mmSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX                                                      0
2527 #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR                                                             0x10ee
2528 #define mmSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX                                                    0
2529 #define mmSQ_IND_INDEX                                                                                 0x1118
2530 #define mmSQ_IND_INDEX_BASE_IDX                                                                        0
2531 #define mmSQ_IND_DATA                                                                                  0x1119
2532 #define mmSQ_IND_DATA_BASE_IDX                                                                         0
2533 #define mmSQ_CMD                                                                                       0x111b
2534 #define mmSQ_CMD_BASE_IDX                                                                              0
2535 #define mmSQ_TIME_HI                                                                                   0x111c
2536 #define mmSQ_TIME_HI_BASE_IDX                                                                          0
2537 #define mmSQ_TIME_LO                                                                                   0x111d
2538 #define mmSQ_TIME_LO_BASE_IDX                                                                          0
2539 #define mmSQ_LB_CTR_CTRL                                                                               0x1138
2540 #define mmSQ_LB_CTR_CTRL_BASE_IDX                                                                      0
2541 #define mmSQ_LB_DATA0                                                                                  0x1139
2542 #define mmSQ_LB_DATA0_BASE_IDX                                                                         0
2543 #define mmSQ_LB_DATA1                                                                                  0x113a
2544 #define mmSQ_LB_DATA1_BASE_IDX                                                                         0
2545 #define mmSQ_LB_DATA2                                                                                  0x113b
2546 #define mmSQ_LB_DATA2_BASE_IDX                                                                         0
2547 #define mmSQ_LB_DATA3                                                                                  0x113c
2548 #define mmSQ_LB_DATA3_BASE_IDX                                                                         0
2549 #define mmSQ_LB_CTR_SEL0                                                                               0x113d
2550 #define mmSQ_LB_CTR_SEL0_BASE_IDX                                                                      0
2551 #define mmSQ_LB_CTR_SEL1                                                                               0x113e
2552 #define mmSQ_LB_CTR_SEL1_BASE_IDX                                                                      0
2553 #define mmSQ_EDC_CNT                                                                                   0x1146
2554 #define mmSQ_EDC_CNT_BASE_IDX                                                                          0
2555 #define mmSQ_EDC_FUE_CNTL                                                                              0x1147
2556 #define mmSQ_EDC_FUE_CNTL_BASE_IDX                                                                     0
2557 #define mmSQ_WREXEC_EXEC_HI                                                                            0x1151
2558 #define mmSQ_WREXEC_EXEC_HI_BASE_IDX                                                                   0
2559 #define mmSQ_WREXEC_EXEC_LO                                                                            0x1151
2560 #define mmSQ_WREXEC_EXEC_LO_BASE_IDX                                                                   0
2561 #define mmSQC_ICACHE_UTCL0_CNTL1                                                                       0x1173
2562 #define mmSQC_ICACHE_UTCL0_CNTL1_BASE_IDX                                                              0
2563 #define mmSQC_ICACHE_UTCL0_CNTL2                                                                       0x1174
2564 #define mmSQC_ICACHE_UTCL0_CNTL2_BASE_IDX                                                              0
2565 #define mmSQC_DCACHE_UTCL0_CNTL1                                                                       0x1175
2566 #define mmSQC_DCACHE_UTCL0_CNTL1_BASE_IDX                                                              0
2567 #define mmSQC_DCACHE_UTCL0_CNTL2                                                                       0x1176
2568 #define mmSQC_DCACHE_UTCL0_CNTL2_BASE_IDX                                                              0
2569 #define mmSQC_ICACHE_UTCL0_STATUS                                                                      0x1177
2570 #define mmSQC_ICACHE_UTCL0_STATUS_BASE_IDX                                                             0
2571 #define mmSQC_DCACHE_UTCL0_STATUS                                                                      0x1178
2572 #define mmSQC_DCACHE_UTCL0_STATUS_BASE_IDX                                                             0
2573 #define mmSQC_MISC_CONFIG                                                                              0x1179
2574 #define mmSQC_MISC_CONFIG_BASE_IDX                                                                     0
2575 
2576 
2577 // addressBlock: gc_shsdec
2578 // base address: 0x9000
2579 #define mmSX_DEBUG_1                                                                                   0x11b8
2580 #define mmSX_DEBUG_1_BASE_IDX                                                                          0
2581 #define mmSPI_PS_MAX_WAVE_ID                                                                           0x11da
2582 #define mmSPI_PS_MAX_WAVE_ID_BASE_IDX                                                                  0
2583 #define mmSPI_START_PHASE                                                                              0x11db
2584 #define mmSPI_START_PHASE_BASE_IDX                                                                     0
2585 #define mmSPI_GFX_CNTL                                                                                 0x11dc
2586 #define mmSPI_GFX_CNTL_BASE_IDX                                                                        0
2587 #define mmSPI_USER_ACCUM_VMID_CNTL                                                                     0x11df
2588 #define mmSPI_USER_ACCUM_VMID_CNTL_BASE_IDX                                                            0
2589 #define mmSPI_CONFIG_CNTL                                                                              0x11e0
2590 #define mmSPI_CONFIG_CNTL_BASE_IDX                                                                     0
2591 #define mmSPI_DSM_CNTL                                                                                 0x11e3
2592 #define mmSPI_DSM_CNTL_BASE_IDX                                                                        0
2593 #define mmSPI_DSM_CNTL2                                                                                0x11e4
2594 #define mmSPI_DSM_CNTL2_BASE_IDX                                                                       0
2595 #define mmSPI_EDC_CNT                                                                                  0x11e5
2596 #define mmSPI_EDC_CNT_BASE_IDX                                                                         0
2597 #define mmSPI_WAVE_LIMIT_CNTL                                                                          0x11ed
2598 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX                                                                 0
2599 #define mmSPI_CONFIG_CNTL_2                                                                            0x11ee
2600 #define mmSPI_CONFIG_CNTL_2_BASE_IDX                                                                   0
2601 #define mmSPI_CONFIG_CNTL_1                                                                            0x11ef
2602 #define mmSPI_CONFIG_CNTL_1_BASE_IDX                                                                   0
2603 #define mmSPI_WF_LIFETIME_CNTL                                                                         0x124a
2604 #define mmSPI_WF_LIFETIME_CNTL_BASE_IDX                                                                0
2605 #define mmSPI_WF_LIFETIME_LIMIT_0                                                                      0x124b
2606 #define mmSPI_WF_LIFETIME_LIMIT_0_BASE_IDX                                                             0
2607 #define mmSPI_WF_LIFETIME_LIMIT_1                                                                      0x124c
2608 #define mmSPI_WF_LIFETIME_LIMIT_1_BASE_IDX                                                             0
2609 #define mmSPI_WF_LIFETIME_LIMIT_2                                                                      0x124d
2610 #define mmSPI_WF_LIFETIME_LIMIT_2_BASE_IDX                                                             0
2611 #define mmSPI_WF_LIFETIME_LIMIT_3                                                                      0x124e
2612 #define mmSPI_WF_LIFETIME_LIMIT_3_BASE_IDX                                                             0
2613 #define mmSPI_WF_LIFETIME_LIMIT_4                                                                      0x124f
2614 #define mmSPI_WF_LIFETIME_LIMIT_4_BASE_IDX                                                             0
2615 #define mmSPI_WF_LIFETIME_LIMIT_5                                                                      0x1250
2616 #define mmSPI_WF_LIFETIME_LIMIT_5_BASE_IDX                                                             0
2617 #define mmSPI_WF_LIFETIME_LIMIT_6                                                                      0x1251
2618 #define mmSPI_WF_LIFETIME_LIMIT_6_BASE_IDX                                                             0
2619 #define mmSPI_WF_LIFETIME_LIMIT_7                                                                      0x1252
2620 #define mmSPI_WF_LIFETIME_LIMIT_7_BASE_IDX                                                             0
2621 #define mmSPI_WF_LIFETIME_LIMIT_8                                                                      0x1253
2622 #define mmSPI_WF_LIFETIME_LIMIT_8_BASE_IDX                                                             0
2623 #define mmSPI_WF_LIFETIME_LIMIT_9                                                                      0x1254
2624 #define mmSPI_WF_LIFETIME_LIMIT_9_BASE_IDX                                                             0
2625 #define mmSPI_WF_LIFETIME_STATUS_0                                                                     0x1255
2626 #define mmSPI_WF_LIFETIME_STATUS_0_BASE_IDX                                                            0
2627 #define mmSPI_WF_LIFETIME_STATUS_1                                                                     0x1256
2628 #define mmSPI_WF_LIFETIME_STATUS_1_BASE_IDX                                                            0
2629 #define mmSPI_WF_LIFETIME_STATUS_2                                                                     0x1257
2630 #define mmSPI_WF_LIFETIME_STATUS_2_BASE_IDX                                                            0
2631 #define mmSPI_WF_LIFETIME_STATUS_3                                                                     0x1258
2632 #define mmSPI_WF_LIFETIME_STATUS_3_BASE_IDX                                                            0
2633 #define mmSPI_WF_LIFETIME_STATUS_4                                                                     0x1259
2634 #define mmSPI_WF_LIFETIME_STATUS_4_BASE_IDX                                                            0
2635 #define mmSPI_WF_LIFETIME_STATUS_5                                                                     0x125a
2636 #define mmSPI_WF_LIFETIME_STATUS_5_BASE_IDX                                                            0
2637 #define mmSPI_WF_LIFETIME_STATUS_6                                                                     0x125b
2638 #define mmSPI_WF_LIFETIME_STATUS_6_BASE_IDX                                                            0
2639 #define mmSPI_WF_LIFETIME_STATUS_7                                                                     0x125c
2640 #define mmSPI_WF_LIFETIME_STATUS_7_BASE_IDX                                                            0
2641 #define mmSPI_WF_LIFETIME_STATUS_8                                                                     0x125d
2642 #define mmSPI_WF_LIFETIME_STATUS_8_BASE_IDX                                                            0
2643 #define mmSPI_WF_LIFETIME_STATUS_9                                                                     0x125e
2644 #define mmSPI_WF_LIFETIME_STATUS_9_BASE_IDX                                                            0
2645 #define mmSPI_WF_LIFETIME_STATUS_10                                                                    0x125f
2646 #define mmSPI_WF_LIFETIME_STATUS_10_BASE_IDX                                                           0
2647 #define mmSPI_WF_LIFETIME_STATUS_11                                                                    0x1260
2648 #define mmSPI_WF_LIFETIME_STATUS_11_BASE_IDX                                                           0
2649 #define mmSPI_WF_LIFETIME_STATUS_12                                                                    0x1261
2650 #define mmSPI_WF_LIFETIME_STATUS_12_BASE_IDX                                                           0
2651 #define mmSPI_WF_LIFETIME_STATUS_13                                                                    0x1262
2652 #define mmSPI_WF_LIFETIME_STATUS_13_BASE_IDX                                                           0
2653 #define mmSPI_WF_LIFETIME_STATUS_14                                                                    0x1263
2654 #define mmSPI_WF_LIFETIME_STATUS_14_BASE_IDX                                                           0
2655 #define mmSPI_WF_LIFETIME_STATUS_15                                                                    0x1264
2656 #define mmSPI_WF_LIFETIME_STATUS_15_BASE_IDX                                                           0
2657 #define mmSPI_WF_LIFETIME_STATUS_16                                                                    0x1265
2658 #define mmSPI_WF_LIFETIME_STATUS_16_BASE_IDX                                                           0
2659 #define mmSPI_WF_LIFETIME_STATUS_17                                                                    0x1266
2660 #define mmSPI_WF_LIFETIME_STATUS_17_BASE_IDX                                                           0
2661 #define mmSPI_WF_LIFETIME_STATUS_18                                                                    0x1267
2662 #define mmSPI_WF_LIFETIME_STATUS_18_BASE_IDX                                                           0
2663 #define mmSPI_WF_LIFETIME_STATUS_19                                                                    0x1268
2664 #define mmSPI_WF_LIFETIME_STATUS_19_BASE_IDX                                                           0
2665 #define mmSPI_WF_LIFETIME_STATUS_20                                                                    0x1269
2666 #define mmSPI_WF_LIFETIME_STATUS_20_BASE_IDX                                                           0
2667 #define mmSPI_LB_CTR_CTRL                                                                              0x1274
2668 #define mmSPI_LB_CTR_CTRL_BASE_IDX                                                                     0
2669 #define mmSPI_LB_WGP_MASK                                                                              0x1275
2670 #define mmSPI_LB_WGP_MASK_BASE_IDX                                                                     0
2671 #define mmSPI_LB_DATA_REG                                                                              0x1276
2672 #define mmSPI_LB_DATA_REG_BASE_IDX                                                                     0
2673 #define mmSPI_PG_ENABLE_STATIC_WGP_MASK                                                                0x1277
2674 #define mmSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX                                                       0
2675 #define mmSPI_GDS_CREDITS                                                                              0x1278
2676 #define mmSPI_GDS_CREDITS_BASE_IDX                                                                     0
2677 #define mmSPI_SX_EXPORT_BUFFER_SIZES                                                                   0x1279
2678 #define mmSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX                                                          0
2679 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES                                                               0x127a
2680 #define mmSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX                                                      0
2681 #define mmSPI_CSQ_WF_ACTIVE_STATUS                                                                     0x127b
2682 #define mmSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX                                                            0
2683 #define mmSPI_CSQ_WF_ACTIVE_COUNT_0                                                                    0x127c
2684 #define mmSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX                                                           0
2685 #define mmSPI_CSQ_WF_ACTIVE_COUNT_1                                                                    0x127d
2686 #define mmSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX                                                           0
2687 #define mmSPI_CSQ_WF_ACTIVE_COUNT_2                                                                    0x127e
2688 #define mmSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX                                                           0
2689 #define mmSPI_CSQ_WF_ACTIVE_COUNT_3                                                                    0x127f
2690 #define mmSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX                                                           0
2691 #define mmSPI_CSQ_WF_ACTIVE_COUNT_4                                                                    0x1280
2692 #define mmSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX                                                           0
2693 #define mmSPI_CSQ_WF_ACTIVE_COUNT_5                                                                    0x1281
2694 #define mmSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX                                                           0
2695 #define mmSPI_CSQ_WF_ACTIVE_COUNT_6                                                                    0x1282
2696 #define mmSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX                                                           0
2697 #define mmSPI_CSQ_WF_ACTIVE_COUNT_7                                                                    0x1283
2698 #define mmSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX                                                           0
2699 #define mmSPI_LB_DATA_WAVES                                                                            0x1284
2700 #define mmSPI_LB_DATA_WAVES_BASE_IDX                                                                   0
2701 #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS                                                                 0x1285
2702 #define mmSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX                                                        0
2703 #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS                                                                 0x1286
2704 #define mmSPI_LB_DATA_PERWGP_WAVE_VSPS_BASE_IDX                                                        0
2705 #define mmSPI_LB_DATA_PERWGP_WAVE_CS                                                                   0x1287
2706 #define mmSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX                                                          0
2707 #define mmSPI_P0_TRAP_SCREEN_PSBA_LO                                                                   0x128c
2708 #define mmSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2709 #define mmSPI_P0_TRAP_SCREEN_PSBA_HI                                                                   0x128d
2710 #define mmSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2711 #define mmSPI_P0_TRAP_SCREEN_PSMA_LO                                                                   0x128e
2712 #define mmSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2713 #define mmSPI_P0_TRAP_SCREEN_PSMA_HI                                                                   0x128f
2714 #define mmSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2715 #define mmSPI_P0_TRAP_SCREEN_GPR_MIN                                                                   0x1290
2716 #define mmSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2717 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO                                                                   0x1291
2718 #define mmSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX                                                          0
2719 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI                                                                   0x1292
2720 #define mmSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX                                                          0
2721 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO                                                                   0x1293
2722 #define mmSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX                                                          0
2723 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI                                                                   0x1294
2724 #define mmSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX                                                          0
2725 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN                                                                   0x1295
2726 #define mmSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX                                                          0
2727 
2728 
2729 // addressBlock: gc_tpdec
2730 // base address: 0x9400
2731 #define mmTD_CNTL                                                                                      0x12c5
2732 #define mmTD_CNTL_BASE_IDX                                                                             0
2733 #define mmTD_STATUS                                                                                    0x12c6
2734 #define mmTD_STATUS_BASE_IDX                                                                           0
2735 #define mmTD_POWER_CNTL                                                                                0x12ca
2736 #define mmTD_POWER_CNTL_BASE_IDX                                                                       0
2737 #define mmTD_DSM_CNTL                                                                                  0x12cf
2738 #define mmTD_DSM_CNTL_BASE_IDX                                                                         0
2739 #define mmTD_DSM_CNTL2                                                                                 0x12d0
2740 #define mmTD_DSM_CNTL2_BASE_IDX                                                                        0
2741 #define mmTD_SCRATCH                                                                                   0x12d3
2742 #define mmTD_SCRATCH_BASE_IDX                                                                          0
2743 #define mmTA_POWER_CNTL                                                                                0x12e0
2744 #define mmTA_POWER_CNTL_BASE_IDX                                                                       0
2745 #define mmTA_CNTL                                                                                      0x12e1
2746 #define mmTA_CNTL_BASE_IDX                                                                             0
2747 #define mmTA_CNTL_AUX                                                                                  0x12e2
2748 #define mmTA_CNTL_AUX_BASE_IDX                                                                         0
2749 #define mmTA_RESERVED_010C                                                                             0x12e3
2750 #define mmTA_RESERVED_010C_BASE_IDX                                                                    0
2751 #define mmTA_STATUS                                                                                    0x12e8
2752 #define mmTA_STATUS_BASE_IDX                                                                           0
2753 #define mmTA_SCRATCH                                                                                   0x1304
2754 #define mmTA_SCRATCH_BASE_IDX                                                                          0
2755 
2756 
2757 // addressBlock: gc_gdsdec
2758 // base address: 0x9700
2759 #define mmGDS_CONFIG                                                                                   0x1360
2760 #define mmGDS_CONFIG_BASE_IDX                                                                          0
2761 #define mmGDS_CNTL_STATUS                                                                              0x1361
2762 #define mmGDS_CNTL_STATUS_BASE_IDX                                                                     0
2763 #define mmGDS_ENHANCE                                                                                  0x1362
2764 #define mmGDS_ENHANCE_BASE_IDX                                                                         0
2765 #define mmGDS_PROTECTION_FAULT                                                                         0x1363
2766 #define mmGDS_PROTECTION_FAULT_BASE_IDX                                                                0
2767 #define mmGDS_VM_PROTECTION_FAULT                                                                      0x1364
2768 #define mmGDS_VM_PROTECTION_FAULT_BASE_IDX                                                             0
2769 #define mmGDS_EDC_CNT                                                                                  0x1365
2770 #define mmGDS_EDC_CNT_BASE_IDX                                                                         0
2771 #define mmGDS_EDC_GRBM_CNT                                                                             0x1366
2772 #define mmGDS_EDC_GRBM_CNT_BASE_IDX                                                                    0
2773 #define mmGDS_EDC_OA_DED                                                                               0x1367
2774 #define mmGDS_EDC_OA_DED_BASE_IDX                                                                      0
2775 #define mmGDS_DSM_CNTL                                                                                 0x136a
2776 #define mmGDS_DSM_CNTL_BASE_IDX                                                                        0
2777 #define mmGDS_EDC_OA_PHY_CNT                                                                           0x136b
2778 #define mmGDS_EDC_OA_PHY_CNT_BASE_IDX                                                                  0
2779 #define mmGDS_EDC_OA_PIPE_CNT                                                                          0x136c
2780 #define mmGDS_EDC_OA_PIPE_CNT_BASE_IDX                                                                 0
2781 #define mmGDS_DSM_CNTL2                                                                                0x136d
2782 #define mmGDS_DSM_CNTL2_BASE_IDX                                                                       0
2783 #define mmGDS_WD_GDS_CSB                                                                               0x136e
2784 #define mmGDS_WD_GDS_CSB_BASE_IDX                                                                      0
2785 
2786 
2787 // addressBlock: gc_rbdec
2788 // base address: 0x9800
2789 #define mmDB_DEBUG                                                                                     0x13ac
2790 #define mmDB_DEBUG_BASE_IDX                                                                            0
2791 #define mmDB_DEBUG2                                                                                    0x13ad
2792 #define mmDB_DEBUG2_BASE_IDX                                                                           0
2793 #define mmDB_DEBUG3                                                                                    0x13ae
2794 #define mmDB_DEBUG3_BASE_IDX                                                                           0
2795 #define mmDB_DEBUG4                                                                                    0x13af
2796 #define mmDB_DEBUG4_BASE_IDX                                                                           0
2797 #define mmDB_ETILE_STUTTER_CONTROL                                                                     0x13b0
2798 #define mmDB_ETILE_STUTTER_CONTROL_BASE_IDX                                                            0
2799 #define mmDB_LTILE_STUTTER_CONTROL                                                                     0x13b1
2800 #define mmDB_LTILE_STUTTER_CONTROL_BASE_IDX                                                            0
2801 #define mmDB_EQUAD_STUTTER_CONTROL                                                                     0x13b2
2802 #define mmDB_EQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2803 #define mmDB_LQUAD_STUTTER_CONTROL                                                                     0x13b3
2804 #define mmDB_LQUAD_STUTTER_CONTROL_BASE_IDX                                                            0
2805 #define mmDB_CREDIT_LIMIT                                                                              0x13b4
2806 #define mmDB_CREDIT_LIMIT_BASE_IDX                                                                     0
2807 #define mmDB_WATERMARKS                                                                                0x13b5
2808 #define mmDB_WATERMARKS_BASE_IDX                                                                       0
2809 #define mmDB_SUBTILE_CONTROL                                                                           0x13b6
2810 #define mmDB_SUBTILE_CONTROL_BASE_IDX                                                                  0
2811 #define mmDB_FREE_CACHELINES                                                                           0x13b7
2812 #define mmDB_FREE_CACHELINES_BASE_IDX                                                                  0
2813 #define mmDB_FIFO_DEPTH1                                                                               0x13b8
2814 #define mmDB_FIFO_DEPTH1_BASE_IDX                                                                      0
2815 #define mmDB_FIFO_DEPTH2                                                                               0x13b9
2816 #define mmDB_FIFO_DEPTH2_BASE_IDX                                                                      0
2817 #define mmDB_LAST_OF_BURST_CONFIG                                                                      0x13ba
2818 #define mmDB_LAST_OF_BURST_CONFIG_BASE_IDX                                                             0
2819 #define mmDB_RING_CONTROL                                                                              0x13bb
2820 #define mmDB_RING_CONTROL_BASE_IDX                                                                     0
2821 #define mmDB_MEM_ARB_WATERMARKS                                                                        0x13bc
2822 #define mmDB_MEM_ARB_WATERMARKS_BASE_IDX                                                               0
2823 #define mmDB_FIFO_DEPTH3                                                                               0x13bd
2824 #define mmDB_FIFO_DEPTH3_BASE_IDX                                                                      0
2825 #define mmDB_RMI_BC_GL2_CACHE_CONTROL                                                                  0x13be
2826 #define mmDB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX                                                         0
2827 #define mmDB_EXCEPTION_CONTROL                                                                         0x13bf
2828 #define mmDB_EXCEPTION_CONTROL_BASE_IDX                                                                0
2829 #define mmDB_DFSM_CONFIG                                                                               0x13d0
2830 #define mmDB_DFSM_CONFIG_BASE_IDX                                                                      0
2831 #define mmDB_DFSM_TILES_IN_FLIGHT                                                                      0x13d2
2832 #define mmDB_DFSM_TILES_IN_FLIGHT_BASE_IDX                                                             0
2833 #define mmDB_DFSM_PRIMS_IN_FLIGHT                                                                      0x13d3
2834 #define mmDB_DFSM_PRIMS_IN_FLIGHT_BASE_IDX                                                             0
2835 #define mmDB_DFSM_WATCHDOG                                                                             0x13d4
2836 #define mmDB_DFSM_WATCHDOG_BASE_IDX                                                                    0
2837 #define mmDB_DFSM_FLUSH_ENABLE                                                                         0x13d5
2838 #define mmDB_DFSM_FLUSH_ENABLE_BASE_IDX                                                                0
2839 #define mmDB_DFSM_FLUSH_AUX_EVENT                                                                      0x13d6
2840 #define mmDB_DFSM_FLUSH_AUX_EVENT_BASE_IDX                                                             0
2841 #define mmDB_FGCG_SRAMS_CLK_CTRL                                                                       0x13d7
2842 #define mmDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX                                                              0
2843 #define mmDB_FGCG_INTERFACES_CLK_CTRL                                                                  0x13d8
2844 #define mmDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX                                                         0
2845 #define mmCC_RB_REDUNDANCY                                                                             0x13dc
2846 #define mmCC_RB_REDUNDANCY_BASE_IDX                                                                    0
2847 #define mmCC_RB_BACKEND_DISABLE                                                                        0x13dd
2848 #define mmCC_RB_BACKEND_DISABLE_BASE_IDX                                                               0
2849 #define mmGB_ADDR_CONFIG                                                                               0x13de
2850 #define mmGB_ADDR_CONFIG_BASE_IDX                                                                      0
2851 #define mmGB_BACKEND_MAP                                                                               0x13df
2852 #define mmGB_BACKEND_MAP_BASE_IDX                                                                      0
2853 #define mmGB_GPU_ID                                                                                    0x13e0
2854 #define mmGB_GPU_ID_BASE_IDX                                                                           0
2855 #define mmCC_RB_DAISY_CHAIN                                                                            0x13e1
2856 #define mmCC_RB_DAISY_CHAIN_BASE_IDX                                                                   0
2857 #define mmGB_ADDR_CONFIG_READ                                                                          0x13e2
2858 #define mmGB_ADDR_CONFIG_READ_BASE_IDX                                                                 0
2859 #define mmGB_TILE_MODE0                                                                                0x13e4
2860 #define mmGB_TILE_MODE0_BASE_IDX                                                                       0
2861 #define mmGB_TILE_MODE1                                                                                0x13e5
2862 #define mmGB_TILE_MODE1_BASE_IDX                                                                       0
2863 #define mmGB_TILE_MODE2                                                                                0x13e6
2864 #define mmGB_TILE_MODE2_BASE_IDX                                                                       0
2865 #define mmGB_TILE_MODE3                                                                                0x13e7
2866 #define mmGB_TILE_MODE3_BASE_IDX                                                                       0
2867 #define mmGB_TILE_MODE4                                                                                0x13e8
2868 #define mmGB_TILE_MODE4_BASE_IDX                                                                       0
2869 #define mmGB_TILE_MODE5                                                                                0x13e9
2870 #define mmGB_TILE_MODE5_BASE_IDX                                                                       0
2871 #define mmGB_TILE_MODE6                                                                                0x13ea
2872 #define mmGB_TILE_MODE6_BASE_IDX                                                                       0
2873 #define mmGB_TILE_MODE7                                                                                0x13eb
2874 #define mmGB_TILE_MODE7_BASE_IDX                                                                       0
2875 #define mmGB_TILE_MODE8                                                                                0x13ec
2876 #define mmGB_TILE_MODE8_BASE_IDX                                                                       0
2877 #define mmGB_TILE_MODE9                                                                                0x13ed
2878 #define mmGB_TILE_MODE9_BASE_IDX                                                                       0
2879 #define mmGB_TILE_MODE10                                                                               0x13ee
2880 #define mmGB_TILE_MODE10_BASE_IDX                                                                      0
2881 #define mmGB_TILE_MODE11                                                                               0x13ef
2882 #define mmGB_TILE_MODE11_BASE_IDX                                                                      0
2883 #define mmGB_TILE_MODE12                                                                               0x13f0
2884 #define mmGB_TILE_MODE12_BASE_IDX                                                                      0
2885 #define mmGB_TILE_MODE13                                                                               0x13f1
2886 #define mmGB_TILE_MODE13_BASE_IDX                                                                      0
2887 #define mmGB_TILE_MODE14                                                                               0x13f2
2888 #define mmGB_TILE_MODE14_BASE_IDX                                                                      0
2889 #define mmGB_TILE_MODE15                                                                               0x13f3
2890 #define mmGB_TILE_MODE15_BASE_IDX                                                                      0
2891 #define mmGB_TILE_MODE16                                                                               0x13f4
2892 #define mmGB_TILE_MODE16_BASE_IDX                                                                      0
2893 #define mmGB_TILE_MODE17                                                                               0x13f5
2894 #define mmGB_TILE_MODE17_BASE_IDX                                                                      0
2895 #define mmGB_TILE_MODE18                                                                               0x13f6
2896 #define mmGB_TILE_MODE18_BASE_IDX                                                                      0
2897 #define mmGB_TILE_MODE19                                                                               0x13f7
2898 #define mmGB_TILE_MODE19_BASE_IDX                                                                      0
2899 #define mmGB_TILE_MODE20                                                                               0x13f8
2900 #define mmGB_TILE_MODE20_BASE_IDX                                                                      0
2901 #define mmGB_TILE_MODE21                                                                               0x13f9
2902 #define mmGB_TILE_MODE21_BASE_IDX                                                                      0
2903 #define mmGB_TILE_MODE22                                                                               0x13fa
2904 #define mmGB_TILE_MODE22_BASE_IDX                                                                      0
2905 #define mmGB_TILE_MODE23                                                                               0x13fb
2906 #define mmGB_TILE_MODE23_BASE_IDX                                                                      0
2907 #define mmGB_TILE_MODE24                                                                               0x13fc
2908 #define mmGB_TILE_MODE24_BASE_IDX                                                                      0
2909 #define mmGB_TILE_MODE25                                                                               0x13fd
2910 #define mmGB_TILE_MODE25_BASE_IDX                                                                      0
2911 #define mmGB_TILE_MODE26                                                                               0x13fe
2912 #define mmGB_TILE_MODE26_BASE_IDX                                                                      0
2913 #define mmGB_TILE_MODE27                                                                               0x13ff
2914 #define mmGB_TILE_MODE27_BASE_IDX                                                                      0
2915 #define mmGB_TILE_MODE28                                                                               0x1400
2916 #define mmGB_TILE_MODE28_BASE_IDX                                                                      0
2917 #define mmGB_TILE_MODE29                                                                               0x1401
2918 #define mmGB_TILE_MODE29_BASE_IDX                                                                      0
2919 #define mmGB_TILE_MODE30                                                                               0x1402
2920 #define mmGB_TILE_MODE30_BASE_IDX                                                                      0
2921 #define mmGB_TILE_MODE31                                                                               0x1403
2922 #define mmGB_TILE_MODE31_BASE_IDX                                                                      0
2923 #define mmGB_MACROTILE_MODE0                                                                           0x1404
2924 #define mmGB_MACROTILE_MODE0_BASE_IDX                                                                  0
2925 #define mmGB_MACROTILE_MODE1                                                                           0x1405
2926 #define mmGB_MACROTILE_MODE1_BASE_IDX                                                                  0
2927 #define mmGB_MACROTILE_MODE2                                                                           0x1406
2928 #define mmGB_MACROTILE_MODE2_BASE_IDX                                                                  0
2929 #define mmGB_MACROTILE_MODE3                                                                           0x1407
2930 #define mmGB_MACROTILE_MODE3_BASE_IDX                                                                  0
2931 #define mmGB_MACROTILE_MODE4                                                                           0x1408
2932 #define mmGB_MACROTILE_MODE4_BASE_IDX                                                                  0
2933 #define mmGB_MACROTILE_MODE5                                                                           0x1409
2934 #define mmGB_MACROTILE_MODE5_BASE_IDX                                                                  0
2935 #define mmGB_MACROTILE_MODE6                                                                           0x140a
2936 #define mmGB_MACROTILE_MODE6_BASE_IDX                                                                  0
2937 #define mmGB_MACROTILE_MODE7                                                                           0x140b
2938 #define mmGB_MACROTILE_MODE7_BASE_IDX                                                                  0
2939 #define mmGB_MACROTILE_MODE8                                                                           0x140c
2940 #define mmGB_MACROTILE_MODE8_BASE_IDX                                                                  0
2941 #define mmGB_MACROTILE_MODE9                                                                           0x140d
2942 #define mmGB_MACROTILE_MODE9_BASE_IDX                                                                  0
2943 #define mmGB_MACROTILE_MODE10                                                                          0x140e
2944 #define mmGB_MACROTILE_MODE10_BASE_IDX                                                                 0
2945 #define mmGB_MACROTILE_MODE11                                                                          0x140f
2946 #define mmGB_MACROTILE_MODE11_BASE_IDX                                                                 0
2947 #define mmGB_MACROTILE_MODE12                                                                          0x1410
2948 #define mmGB_MACROTILE_MODE12_BASE_IDX                                                                 0
2949 #define mmGB_MACROTILE_MODE13                                                                          0x1411
2950 #define mmGB_MACROTILE_MODE13_BASE_IDX                                                                 0
2951 #define mmGB_MACROTILE_MODE14                                                                          0x1412
2952 #define mmGB_MACROTILE_MODE14_BASE_IDX                                                                 0
2953 #define mmGB_MACROTILE_MODE15                                                                          0x1413
2954 #define mmGB_MACROTILE_MODE15_BASE_IDX                                                                 0
2955 #define mmCB_HW_CONTROL_4                                                                              0x1422
2956 #define mmCB_HW_CONTROL_4_BASE_IDX                                                                     0
2957 #define mmCB_HW_CONTROL_3                                                                              0x1423
2958 #define mmCB_HW_CONTROL_3_BASE_IDX                                                                     0
2959 #define mmCB_HW_CONTROL                                                                                0x1424
2960 #define mmCB_HW_CONTROL_BASE_IDX                                                                       0
2961 #define mmCB_HW_CONTROL_1                                                                              0x1425
2962 #define mmCB_HW_CONTROL_1_BASE_IDX                                                                     0
2963 #define mmCB_HW_CONTROL_2                                                                              0x1426
2964 #define mmCB_HW_CONTROL_2_BASE_IDX                                                                     0
2965 #define mmCB_DCC_CONFIG                                                                                0x1427
2966 #define mmCB_DCC_CONFIG_BASE_IDX                                                                       0
2967 #define mmCB_HW_MEM_ARBITER_RD                                                                         0x1428
2968 #define mmCB_HW_MEM_ARBITER_RD_BASE_IDX                                                                0
2969 #define mmCB_HW_MEM_ARBITER_WR                                                                         0x1429
2970 #define mmCB_HW_MEM_ARBITER_WR_BASE_IDX                                                                0
2971 #define mmCB_RMI_BC_GL2_CACHE_CONTROL                                                                  0x142a
2972 #define mmCB_RMI_BC_GL2_CACHE_CONTROL_BASE_IDX                                                         0
2973 #define mmCB_STUTTER_CONTROL_CMASK_RDLAT                                                               0x142b
2974 #define mmCB_STUTTER_CONTROL_CMASK_RDLAT_BASE_IDX                                                      0
2975 #define mmCB_STUTTER_CONTROL_FMASK_RDLAT                                                               0x142c
2976 #define mmCB_STUTTER_CONTROL_FMASK_RDLAT_BASE_IDX                                                      0
2977 #define mmCB_STUTTER_CONTROL_COLOR_RDLAT                                                               0x142d
2978 #define mmCB_STUTTER_CONTROL_COLOR_RDLAT_BASE_IDX                                                      0
2979 #define mmCB_CACHE_EVICT_POINTS                                                                        0x142e
2980 #define mmCB_CACHE_EVICT_POINTS_BASE_IDX                                                               0
2981 #define mmGC_USER_RB_REDUNDANCY                                                                        0x147e
2982 #define mmGC_USER_RB_REDUNDANCY_BASE_IDX                                                               0
2983 #define mmGC_USER_RB_BACKEND_DISABLE                                                                   0x147f
2984 #define mmGC_USER_RB_BACKEND_DISABLE_BASE_IDX                                                          0
2985 
2986 
2987 // addressBlock: gc_gceadec2
2988 // base address: 0x9c00
2989 #define mmGCEA_SDP_VCD_RESERVE1                                                                        0x14a0
2990 #define mmGCEA_SDP_VCD_RESERVE1_BASE_IDX                                                               0
2991 #define mmGCEA_SDP_REQ_CNTL                                                                            0x14a1
2992 #define mmGCEA_SDP_REQ_CNTL_BASE_IDX                                                                   0
2993 #define mmGCEA_MISC                                                                                    0x14a2
2994 #define mmGCEA_MISC_BASE_IDX                                                                           0
2995 #define mmGCEA_LATENCY_SAMPLING                                                                        0x14a3
2996 #define mmGCEA_LATENCY_SAMPLING_BASE_IDX                                                               0
2997 #define mmGCEA_PERFCOUNTER_LO                                                                          0x14a4
2998 #define mmGCEA_PERFCOUNTER_LO_BASE_IDX                                                                 0
2999 #define mmGCEA_PERFCOUNTER_HI                                                                          0x14a5
3000 #define mmGCEA_PERFCOUNTER_HI_BASE_IDX                                                                 0
3001 #define mmGCEA_PERFCOUNTER0_CFG                                                                        0x14a6
3002 #define mmGCEA_PERFCOUNTER0_CFG_BASE_IDX                                                               0
3003 #define mmGCEA_PERFCOUNTER1_CFG                                                                        0x14a7
3004 #define mmGCEA_PERFCOUNTER1_CFG_BASE_IDX                                                               0
3005 #define mmGCEA_PERFCOUNTER_RSLT_CNTL                                                                   0x14a8
3006 #define mmGCEA_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                          0
3007 #define mmGCEA_EDC_CNT                                                                                 0x14b2
3008 #define mmGCEA_EDC_CNT_BASE_IDX                                                                        0
3009 #define mmGCEA_EDC_CNT2                                                                                0x14b3
3010 #define mmGCEA_EDC_CNT2_BASE_IDX                                                                       0
3011 #define mmGCEA_DSM_CNTL                                                                                0x14b4
3012 #define mmGCEA_DSM_CNTL_BASE_IDX                                                                       0
3013 #define mmGCEA_DSM_CNTLA                                                                               0x14b5
3014 #define mmGCEA_DSM_CNTLA_BASE_IDX                                                                      0
3015 #define mmGCEA_DSM_CNTLB                                                                               0x14b6
3016 #define mmGCEA_DSM_CNTLB_BASE_IDX                                                                      0
3017 #define mmGCEA_DSM_CNTL2                                                                               0x14b7
3018 #define mmGCEA_DSM_CNTL2_BASE_IDX                                                                      0
3019 #define mmGCEA_DSM_CNTL2A                                                                              0x14b8
3020 #define mmGCEA_DSM_CNTL2A_BASE_IDX                                                                     0
3021 #define mmGCEA_DSM_CNTL2B                                                                              0x14b9
3022 #define mmGCEA_DSM_CNTL2B_BASE_IDX                                                                     0
3023 #define mmGCEA_GL2C_XBR_CREDITS                                                                        0x14ba
3024 #define mmGCEA_GL2C_XBR_CREDITS_BASE_IDX                                                               0
3025 #define mmGCEA_GL2C_XBR_MAXBURST                                                                       0x14bb
3026 #define mmGCEA_GL2C_XBR_MAXBURST_BASE_IDX                                                              0
3027 #define mmGCEA_PROBE_CNTL                                                                              0x14bc
3028 #define mmGCEA_PROBE_CNTL_BASE_IDX                                                                     0
3029 #define mmGCEA_PROBE_MAP                                                                               0x14bd
3030 #define mmGCEA_PROBE_MAP_BASE_IDX                                                                      0
3031 #define mmGCEA_ERR_STATUS                                                                              0x14be
3032 #define mmGCEA_ERR_STATUS_BASE_IDX                                                                     0
3033 #define mmGCEA_MISC2                                                                                   0x14bf
3034 #define mmGCEA_MISC2_BASE_IDX                                                                          0
3035 
3036 
3037 // addressBlock: gc_spipdec2
3038 // base address: 0x9c80
3039 #define mmSPI_PQEV_CTRL                                                                                0x14c0
3040 #define mmSPI_PQEV_CTRL_BASE_IDX                                                                       0
3041 #define mmSPI_SYS_COMPUTE                                                                              0x14c1
3042 #define mmSPI_SYS_COMPUTE_BASE_IDX                                                                     0
3043 #define mmSPI_SYS_WIF_CNTL                                                                             0x14c2
3044 #define mmSPI_SYS_WIF_CNTL_BASE_IDX                                                                    0
3045 
3046 
3047 // addressBlock: gc_gceadec3
3048 // base address: 0x9dc0
3049 #define mmGCEA_DRAM_BANK_ARB                                                                           0x1510
3050 #define mmGCEA_DRAM_BANK_ARB_BASE_IDX                                                                  0
3051 #define mmGCEA_DRAM_BANK_ARB_RFSH                                                                      0x1511
3052 #define mmGCEA_DRAM_BANK_ARB_RFSH_BASE_IDX                                                             0
3053 #define mmGCEA_SDP_BACKDOOR_CMDCREDITS0                                                                0x1512
3054 #define mmGCEA_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX                                                       0
3055 #define mmGCEA_SDP_BACKDOOR_CMDCREDITS1                                                                0x1513
3056 #define mmGCEA_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX                                                       0
3057 #define mmGCEA_SDP_BACKDOOR_DATACREDITS0                                                               0x1514
3058 #define mmGCEA_SDP_BACKDOOR_DATACREDITS0_BASE_IDX                                                      0
3059 #define mmGCEA_SDP_BACKDOOR_DATACREDITS1                                                               0x1515
3060 #define mmGCEA_SDP_BACKDOOR_DATACREDITS1_BASE_IDX                                                      0
3061 #define mmGCEA_SDP_BACKDOOR_MISCCREDITS                                                                0x1516
3062 #define mmGCEA_SDP_BACKDOOR_MISCCREDITS_BASE_IDX                                                       0
3063 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH                                                              0x1517
3064 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PACH_BASE_IDX                                                     0
3065 #define mmGCEA_RRET_MEM_RESERVE                                                                        0x1518
3066 #define mmGCEA_RRET_MEM_RESERVE_BASE_IDX                                                               0
3067 #define mmGCEA_ADDRDEC_SELECT                                                                          0x1519
3068 #define mmGCEA_ADDRDEC_SELECT_BASE_IDX                                                                 0
3069 #define mmGCEA_SDP_ENABLE                                                                              0x151a
3070 #define mmGCEA_SDP_ENABLE_BASE_IDX                                                                     0
3071 
3072 
3073 // addressBlock: gc_rmi_rmidec
3074 // base address: 0x9e00
3075 #define mmRMI_GENERAL_CNTL                                                                             0x1520
3076 #define mmRMI_GENERAL_CNTL_BASE_IDX                                                                    0
3077 #define mmRMI_GENERAL_CNTL1                                                                            0x1521
3078 #define mmRMI_GENERAL_CNTL1_BASE_IDX                                                                   0
3079 #define mmRMI_GENERAL_STATUS                                                                           0x1522
3080 #define mmRMI_GENERAL_STATUS_BASE_IDX                                                                  0
3081 #define mmRMI_SUBBLOCK_STATUS0                                                                         0x1523
3082 #define mmRMI_SUBBLOCK_STATUS0_BASE_IDX                                                                0
3083 #define mmRMI_SUBBLOCK_STATUS1                                                                         0x1524
3084 #define mmRMI_SUBBLOCK_STATUS1_BASE_IDX                                                                0
3085 #define mmRMI_SUBBLOCK_STATUS2                                                                         0x1525
3086 #define mmRMI_SUBBLOCK_STATUS2_BASE_IDX                                                                0
3087 #define mmRMI_SUBBLOCK_STATUS3                                                                         0x1526
3088 #define mmRMI_SUBBLOCK_STATUS3_BASE_IDX                                                                0
3089 #define mmRMI_XBAR_CONFIG                                                                              0x1527
3090 #define mmRMI_XBAR_CONFIG_BASE_IDX                                                                     0
3091 #define mmRMI_PROBE_POP_LOGIC_CNTL                                                                     0x1528
3092 #define mmRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX                                                            0
3093 #define mmRMI_UTC_XNACK_N_MISC_CNTL                                                                    0x1529
3094 #define mmRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX                                                           0
3095 #define mmRMI_DEMUX_CNTL                                                                               0x152a
3096 #define mmRMI_DEMUX_CNTL_BASE_IDX                                                                      0
3097 #define mmRMI_UTCL1_CNTL1                                                                              0x152b
3098 #define mmRMI_UTCL1_CNTL1_BASE_IDX                                                                     0
3099 #define mmRMI_UTCL1_CNTL2                                                                              0x152c
3100 #define mmRMI_UTCL1_CNTL2_BASE_IDX                                                                     0
3101 #define mmRMI_UTC_UNIT_CONFIG                                                                          0x152d
3102 #define mmRMI_UTC_UNIT_CONFIG_BASE_IDX                                                                 0
3103 #define mmRMI_TCIW_FORMATTER0_CNTL                                                                     0x152e
3104 #define mmRMI_TCIW_FORMATTER0_CNTL_BASE_IDX                                                            0
3105 #define mmRMI_TCIW_FORMATTER1_CNTL                                                                     0x152f
3106 #define mmRMI_TCIW_FORMATTER1_CNTL_BASE_IDX                                                            0
3107 #define mmRMI_SCOREBOARD_CNTL                                                                          0x1530
3108 #define mmRMI_SCOREBOARD_CNTL_BASE_IDX                                                                 0
3109 #define mmRMI_SCOREBOARD_STATUS0                                                                       0x1531
3110 #define mmRMI_SCOREBOARD_STATUS0_BASE_IDX                                                              0
3111 #define mmRMI_SCOREBOARD_STATUS1                                                                       0x1532
3112 #define mmRMI_SCOREBOARD_STATUS1_BASE_IDX                                                              0
3113 #define mmRMI_SCOREBOARD_STATUS2                                                                       0x1533
3114 #define mmRMI_SCOREBOARD_STATUS2_BASE_IDX                                                              0
3115 #define mmRMI_XBAR_ARBITER_CONFIG                                                                      0x1534
3116 #define mmRMI_XBAR_ARBITER_CONFIG_BASE_IDX                                                             0
3117 #define mmRMI_XBAR_ARBITER_CONFIG_1                                                                    0x1535
3118 #define mmRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX                                                           0
3119 #define mmRMI_CLOCK_CNTRL                                                                              0x1536
3120 #define mmRMI_CLOCK_CNTRL_BASE_IDX                                                                     0
3121 #define mmRMI_UTCL1_STATUS                                                                             0x1537
3122 #define mmRMI_UTCL1_STATUS_BASE_IDX                                                                    0
3123 #define mmRMI_RB_GLX_CID_MAP                                                                           0x1538
3124 #define mmRMI_RB_GLX_CID_MAP_BASE_IDX                                                                  0
3125 #define mmRMI_SPARE                                                                                    0x153f
3126 #define mmRMI_SPARE_BASE_IDX                                                                           0
3127 #define mmRMI_SPARE_1                                                                                  0x1540
3128 #define mmRMI_SPARE_1_BASE_IDX                                                                         0
3129 #define mmRMI_SPARE_2                                                                                  0x1541
3130 #define mmRMI_SPARE_2_BASE_IDX                                                                         0
3131 #define mmCC_RMI_REDUNDANCY                                                                            0x1542
3132 #define mmCC_RMI_REDUNDANCY_BASE_IDX                                                                   0
3133 #define mmGC_USER_RMI_REDUNDANCY                                                                       0x1543
3134 #define mmGC_USER_RMI_REDUNDANCY_BASE_IDX                                                              0
3135 
3136 
3137 // addressBlock: gc_pmmdec
3138 // base address: 0x9f80
3139 #define mmPMM_GENERAL_CNTL                                                                             0x1580
3140 #define mmPMM_GENERAL_CNTL_BASE_IDX                                                                    0
3141 #define mmGCR_PIO_CNTL                                                                                 0x1581
3142 #define mmGCR_PIO_CNTL_BASE_IDX                                                                        0
3143 #define mmGCR_PIO_DATA                                                                                 0x1582
3144 #define mmGCR_PIO_DATA_BASE_IDX                                                                        0
3145 #define mmGCR_GENERAL_CNTL                                                                             0x1583
3146 #define mmGCR_GENERAL_CNTL_BASE_IDX                                                                    0
3147 #define mmGCR_TARGET_DISABLE                                                                           0x1584
3148 #define mmGCR_TARGET_DISABLE_BASE_IDX                                                                  0
3149 #define mmGCR_CMD_STATUS                                                                               0x1585
3150 #define mmGCR_CMD_STATUS_BASE_IDX                                                                      0
3151 #define mmGCR_SPARE                                                                                    0x1586
3152 #define mmGCR_SPARE_BASE_IDX                                                                           0
3153 
3154 
3155 // addressBlock: gc_utcl1dec
3156 // base address: 0x9fa0
3157 #define mmUTCL1_CTRL                                                                                   0x1588
3158 #define mmUTCL1_CTRL_BASE_IDX                                                                          0
3159 #define mmUTCL1_ALOG                                                                                   0x1589
3160 #define mmUTCL1_ALOG_BASE_IDX                                                                          0
3161 #define mmUTCL1_UTCL0_INVREQ_DISABLE                                                                   0x158a
3162 #define mmUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX                                                          0
3163 #define mmGCRD_SA_TARGETS_DISABLE                                                                      0x158b
3164 #define mmGCRD_SA_TARGETS_DISABLE_BASE_IDX                                                             0
3165 
3166 
3167 // addressBlock: gc_gcatcl2dec
3168 // base address: 0xa000
3169 #define mmGC_ATC_L2_CNTL                                                                               0x15a0
3170 #define mmGC_ATC_L2_CNTL_BASE_IDX                                                                      0
3171 #define mmGC_ATC_L2_CNTL2                                                                              0x15a1
3172 #define mmGC_ATC_L2_CNTL2_BASE_IDX                                                                     0
3173 #define mmGC_ATC_L2_CACHE_DATA0                                                                        0x15a4
3174 #define mmGC_ATC_L2_CACHE_DATA0_BASE_IDX                                                               0
3175 #define mmGC_ATC_L2_CACHE_DATA1                                                                        0x15a5
3176 #define mmGC_ATC_L2_CACHE_DATA1_BASE_IDX                                                               0
3177 #define mmGC_ATC_L2_CACHE_DATA2                                                                        0x15a6
3178 #define mmGC_ATC_L2_CACHE_DATA2_BASE_IDX                                                               0
3179 #define mmGC_ATC_L2_CNTL3                                                                              0x15a7
3180 #define mmGC_ATC_L2_CNTL3_BASE_IDX                                                                     0
3181 #define mmGC_ATC_L2_STATUS                                                                             0x15a8
3182 #define mmGC_ATC_L2_STATUS_BASE_IDX                                                                    0
3183 #define mmGC_ATC_L2_STATUS2                                                                            0x15a9
3184 #define mmGC_ATC_L2_STATUS2_BASE_IDX                                                                   0
3185 #define mmGC_ATC_L2_MISC_CG                                                                            0x15aa
3186 #define mmGC_ATC_L2_MISC_CG_BASE_IDX                                                                   0
3187 #define mmGC_ATC_L2_MEM_POWER_LS                                                                       0x15ab
3188 #define mmGC_ATC_L2_MEM_POWER_LS_BASE_IDX                                                              0
3189 #define mmGC_ATC_L2_CGTT_CLK_CTRL                                                                      0x15ac
3190 #define mmGC_ATC_L2_CGTT_CLK_CTRL_BASE_IDX                                                             0
3191 #define mmGC_ATC_L2_SDPPORT_CTRL                                                                       0x15ad
3192 #define mmGC_ATC_L2_SDPPORT_CTRL_BASE_IDX                                                              0
3193 
3194 
3195 // addressBlock: gc_gcvml2pfdec
3196 // base address: 0xa100
3197 #define mmGCVM_L2_CNTL                                                                                 0x15e0
3198 #define mmGCVM_L2_CNTL_BASE_IDX                                                                        0
3199 #define mmGCVM_L2_CNTL2                                                                                0x15e1
3200 #define mmGCVM_L2_CNTL2_BASE_IDX                                                                       0
3201 #define mmGCVM_L2_CNTL3                                                                                0x15e2
3202 #define mmGCVM_L2_CNTL3_BASE_IDX                                                                       0
3203 #define mmGCVM_L2_STATUS                                                                               0x15e3
3204 #define mmGCVM_L2_STATUS_BASE_IDX                                                                      0
3205 #define mmGCVM_DUMMY_PAGE_FAULT_CNTL                                                                   0x15e4
3206 #define mmGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX                                                          0
3207 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32                                                              0x15e5
3208 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX                                                     0
3209 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32                                                              0x15e6
3210 #define mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX                                                     0
3211 #define mmGCVM_INVALIDATE_CNTL                                                                         0x15e7
3212 #define mmGCVM_INVALIDATE_CNTL_BASE_IDX                                                                0
3213 #define mmGCVM_L2_PROTECTION_FAULT_CNTL                                                                0x15e8
3214 #define mmGCVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX                                                       0
3215 #define mmGCVM_L2_PROTECTION_FAULT_CNTL2                                                               0x15e9
3216 #define mmGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX                                                      0
3217 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3                                                            0x15ea
3218 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX                                                   0
3219 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4                                                            0x15eb
3220 #define mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX                                                   0
3221 #define mmGCVM_L2_PROTECTION_FAULT_STATUS                                                              0x15ec
3222 #define mmGCVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX                                                     0
3223 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32                                                           0x15ed
3224 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX                                                  0
3225 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32                                                           0x15ee
3226 #define mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX                                                  0
3227 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32                                                   0x15ef
3228 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX                                          0
3229 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32                                                   0x15f0
3230 #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX                                          0
3231 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32                                             0x15f2
3232 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX                                    0
3233 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32                                             0x15f3
3234 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX                                    0
3235 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32                                            0x15f4
3236 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX                                   0
3237 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32                                            0x15f5
3238 #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX                                   0
3239 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32                                                0x15f6
3240 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX                                       0
3241 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32                                                0x15f7
3242 #define mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX                                       0
3243 #define mmGCVM_L2_CNTL4                                                                                0x15f8
3244 #define mmGCVM_L2_CNTL4_BASE_IDX                                                                       0
3245 #define mmGCVM_L2_MM_GROUP_RT_CLASSES                                                                  0x15f9
3246 #define mmGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX                                                         0
3247 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID                                                             0x15fa
3248 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX                                                    0
3249 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2                                                            0x15fb
3250 #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX                                                   0
3251 #define mmGCVM_L2_CACHE_PARITY_CNTL                                                                    0x15fc
3252 #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX                                                           0
3253 #define mmGCVM_L2_CGTT_CLK_CTRL                                                                        0x15ff
3254 #define mmGCVM_L2_CGTT_CLK_CTRL_BASE_IDX                                                               0
3255 #define mmGCVM_L2_CNTL5                                                                                0x1601
3256 #define mmGCVM_L2_CNTL5_BASE_IDX                                                                       0
3257 #define mmGCVM_L2_GCR_CNTL                                                                             0x1602
3258 #define mmGCVM_L2_GCR_CNTL_BASE_IDX                                                                    0
3259 #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME                                                            0x1603
3260 #define mmGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX                                                   0
3261 #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT                                                     0x1604
3262 #define mmGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
3263 #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME                                                            0x1605
3264 #define mmGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX                                                   0
3265 #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT                                                     0x1606
3266 #define mmGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX                                            0
3267 
3268 
3269 // addressBlock: gc_gcvml2vcdec
3270 // base address: 0xa200
3271 #define mmGCVM_CONTEXT0_CNTL                                                                           0x1620
3272 #define mmGCVM_CONTEXT0_CNTL_BASE_IDX                                                                  0
3273 #define mmGCVM_CONTEXT1_CNTL                                                                           0x1621
3274 #define mmGCVM_CONTEXT1_CNTL_BASE_IDX                                                                  0
3275 #define mmGCVM_CONTEXT2_CNTL                                                                           0x1622
3276 #define mmGCVM_CONTEXT2_CNTL_BASE_IDX                                                                  0
3277 #define mmGCVM_CONTEXT3_CNTL                                                                           0x1623
3278 #define mmGCVM_CONTEXT3_CNTL_BASE_IDX                                                                  0
3279 #define mmGCVM_CONTEXT4_CNTL                                                                           0x1624
3280 #define mmGCVM_CONTEXT4_CNTL_BASE_IDX                                                                  0
3281 #define mmGCVM_CONTEXT5_CNTL                                                                           0x1625
3282 #define mmGCVM_CONTEXT5_CNTL_BASE_IDX                                                                  0
3283 #define mmGCVM_CONTEXT6_CNTL                                                                           0x1626
3284 #define mmGCVM_CONTEXT6_CNTL_BASE_IDX                                                                  0
3285 #define mmGCVM_CONTEXT7_CNTL                                                                           0x1627
3286 #define mmGCVM_CONTEXT7_CNTL_BASE_IDX                                                                  0
3287 #define mmGCVM_CONTEXT8_CNTL                                                                           0x1628
3288 #define mmGCVM_CONTEXT8_CNTL_BASE_IDX                                                                  0
3289 #define mmGCVM_CONTEXT9_CNTL                                                                           0x1629
3290 #define mmGCVM_CONTEXT9_CNTL_BASE_IDX                                                                  0
3291 #define mmGCVM_CONTEXT10_CNTL                                                                          0x162a
3292 #define mmGCVM_CONTEXT10_CNTL_BASE_IDX                                                                 0
3293 #define mmGCVM_CONTEXT11_CNTL                                                                          0x162b
3294 #define mmGCVM_CONTEXT11_CNTL_BASE_IDX                                                                 0
3295 #define mmGCVM_CONTEXT12_CNTL                                                                          0x162c
3296 #define mmGCVM_CONTEXT12_CNTL_BASE_IDX                                                                 0
3297 #define mmGCVM_CONTEXT13_CNTL                                                                          0x162d
3298 #define mmGCVM_CONTEXT13_CNTL_BASE_IDX                                                                 0
3299 #define mmGCVM_CONTEXT14_CNTL                                                                          0x162e
3300 #define mmGCVM_CONTEXT14_CNTL_BASE_IDX                                                                 0
3301 #define mmGCVM_CONTEXT15_CNTL                                                                          0x162f
3302 #define mmGCVM_CONTEXT15_CNTL_BASE_IDX                                                                 0
3303 #define mmGCVM_CONTEXTS_DISABLE                                                                        0x1630
3304 #define mmGCVM_CONTEXTS_DISABLE_BASE_IDX                                                               0
3305 #define mmGCVM_INVALIDATE_ENG0_SEM                                                                     0x1631
3306 #define mmGCVM_INVALIDATE_ENG0_SEM_BASE_IDX                                                            0
3307 #define mmGCVM_INVALIDATE_ENG1_SEM                                                                     0x1632
3308 #define mmGCVM_INVALIDATE_ENG1_SEM_BASE_IDX                                                            0
3309 #define mmGCVM_INVALIDATE_ENG2_SEM                                                                     0x1633
3310 #define mmGCVM_INVALIDATE_ENG2_SEM_BASE_IDX                                                            0
3311 #define mmGCVM_INVALIDATE_ENG3_SEM                                                                     0x1634
3312 #define mmGCVM_INVALIDATE_ENG3_SEM_BASE_IDX                                                            0
3313 #define mmGCVM_INVALIDATE_ENG4_SEM                                                                     0x1635
3314 #define mmGCVM_INVALIDATE_ENG4_SEM_BASE_IDX                                                            0
3315 #define mmGCVM_INVALIDATE_ENG5_SEM                                                                     0x1636
3316 #define mmGCVM_INVALIDATE_ENG5_SEM_BASE_IDX                                                            0
3317 #define mmGCVM_INVALIDATE_ENG6_SEM                                                                     0x1637
3318 #define mmGCVM_INVALIDATE_ENG6_SEM_BASE_IDX                                                            0
3319 #define mmGCVM_INVALIDATE_ENG7_SEM                                                                     0x1638
3320 #define mmGCVM_INVALIDATE_ENG7_SEM_BASE_IDX                                                            0
3321 #define mmGCVM_INVALIDATE_ENG8_SEM                                                                     0x1639
3322 #define mmGCVM_INVALIDATE_ENG8_SEM_BASE_IDX                                                            0
3323 #define mmGCVM_INVALIDATE_ENG9_SEM                                                                     0x163a
3324 #define mmGCVM_INVALIDATE_ENG9_SEM_BASE_IDX                                                            0
3325 #define mmGCVM_INVALIDATE_ENG10_SEM                                                                    0x163b
3326 #define mmGCVM_INVALIDATE_ENG10_SEM_BASE_IDX                                                           0
3327 #define mmGCVM_INVALIDATE_ENG11_SEM                                                                    0x163c
3328 #define mmGCVM_INVALIDATE_ENG11_SEM_BASE_IDX                                                           0
3329 #define mmGCVM_INVALIDATE_ENG12_SEM                                                                    0x163d
3330 #define mmGCVM_INVALIDATE_ENG12_SEM_BASE_IDX                                                           0
3331 #define mmGCVM_INVALIDATE_ENG13_SEM                                                                    0x163e
3332 #define mmGCVM_INVALIDATE_ENG13_SEM_BASE_IDX                                                           0
3333 #define mmGCVM_INVALIDATE_ENG14_SEM                                                                    0x163f
3334 #define mmGCVM_INVALIDATE_ENG14_SEM_BASE_IDX                                                           0
3335 #define mmGCVM_INVALIDATE_ENG15_SEM                                                                    0x1640
3336 #define mmGCVM_INVALIDATE_ENG15_SEM_BASE_IDX                                                           0
3337 #define mmGCVM_INVALIDATE_ENG16_SEM                                                                    0x1641
3338 #define mmGCVM_INVALIDATE_ENG16_SEM_BASE_IDX                                                           0
3339 #define mmGCVM_INVALIDATE_ENG17_SEM                                                                    0x1642
3340 #define mmGCVM_INVALIDATE_ENG17_SEM_BASE_IDX                                                           0
3341 #define mmGCVM_INVALIDATE_ENG0_REQ                                                                     0x1643
3342 #define mmGCVM_INVALIDATE_ENG0_REQ_BASE_IDX                                                            0
3343 #define mmGCVM_INVALIDATE_ENG1_REQ                                                                     0x1644
3344 #define mmGCVM_INVALIDATE_ENG1_REQ_BASE_IDX                                                            0
3345 #define mmGCVM_INVALIDATE_ENG2_REQ                                                                     0x1645
3346 #define mmGCVM_INVALIDATE_ENG2_REQ_BASE_IDX                                                            0
3347 #define mmGCVM_INVALIDATE_ENG3_REQ                                                                     0x1646
3348 #define mmGCVM_INVALIDATE_ENG3_REQ_BASE_IDX                                                            0
3349 #define mmGCVM_INVALIDATE_ENG4_REQ                                                                     0x1647
3350 #define mmGCVM_INVALIDATE_ENG4_REQ_BASE_IDX                                                            0
3351 #define mmGCVM_INVALIDATE_ENG5_REQ                                                                     0x1648
3352 #define mmGCVM_INVALIDATE_ENG5_REQ_BASE_IDX                                                            0
3353 #define mmGCVM_INVALIDATE_ENG6_REQ                                                                     0x1649
3354 #define mmGCVM_INVALIDATE_ENG6_REQ_BASE_IDX                                                            0
3355 #define mmGCVM_INVALIDATE_ENG7_REQ                                                                     0x164a
3356 #define mmGCVM_INVALIDATE_ENG7_REQ_BASE_IDX                                                            0
3357 #define mmGCVM_INVALIDATE_ENG8_REQ                                                                     0x164b
3358 #define mmGCVM_INVALIDATE_ENG8_REQ_BASE_IDX                                                            0
3359 #define mmGCVM_INVALIDATE_ENG9_REQ                                                                     0x164c
3360 #define mmGCVM_INVALIDATE_ENG9_REQ_BASE_IDX                                                            0
3361 #define mmGCVM_INVALIDATE_ENG10_REQ                                                                    0x164d
3362 #define mmGCVM_INVALIDATE_ENG10_REQ_BASE_IDX                                                           0
3363 #define mmGCVM_INVALIDATE_ENG11_REQ                                                                    0x164e
3364 #define mmGCVM_INVALIDATE_ENG11_REQ_BASE_IDX                                                           0
3365 #define mmGCVM_INVALIDATE_ENG12_REQ                                                                    0x164f
3366 #define mmGCVM_INVALIDATE_ENG12_REQ_BASE_IDX                                                           0
3367 #define mmGCVM_INVALIDATE_ENG13_REQ                                                                    0x1650
3368 #define mmGCVM_INVALIDATE_ENG13_REQ_BASE_IDX                                                           0
3369 #define mmGCVM_INVALIDATE_ENG14_REQ                                                                    0x1651
3370 #define mmGCVM_INVALIDATE_ENG14_REQ_BASE_IDX                                                           0
3371 #define mmGCVM_INVALIDATE_ENG15_REQ                                                                    0x1652
3372 #define mmGCVM_INVALIDATE_ENG15_REQ_BASE_IDX                                                           0
3373 #define mmGCVM_INVALIDATE_ENG16_REQ                                                                    0x1653
3374 #define mmGCVM_INVALIDATE_ENG16_REQ_BASE_IDX                                                           0
3375 #define mmGCVM_INVALIDATE_ENG17_REQ                                                                    0x1654
3376 #define mmGCVM_INVALIDATE_ENG17_REQ_BASE_IDX                                                           0
3377 #define mmGCVM_INVALIDATE_ENG0_ACK                                                                     0x1655
3378 #define mmGCVM_INVALIDATE_ENG0_ACK_BASE_IDX                                                            0
3379 #define mmGCVM_INVALIDATE_ENG1_ACK                                                                     0x1656
3380 #define mmGCVM_INVALIDATE_ENG1_ACK_BASE_IDX                                                            0
3381 #define mmGCVM_INVALIDATE_ENG2_ACK                                                                     0x1657
3382 #define mmGCVM_INVALIDATE_ENG2_ACK_BASE_IDX                                                            0
3383 #define mmGCVM_INVALIDATE_ENG3_ACK                                                                     0x1658
3384 #define mmGCVM_INVALIDATE_ENG3_ACK_BASE_IDX                                                            0
3385 #define mmGCVM_INVALIDATE_ENG4_ACK                                                                     0x1659
3386 #define mmGCVM_INVALIDATE_ENG4_ACK_BASE_IDX                                                            0
3387 #define mmGCVM_INVALIDATE_ENG5_ACK                                                                     0x165a
3388 #define mmGCVM_INVALIDATE_ENG5_ACK_BASE_IDX                                                            0
3389 #define mmGCVM_INVALIDATE_ENG6_ACK                                                                     0x165b
3390 #define mmGCVM_INVALIDATE_ENG6_ACK_BASE_IDX                                                            0
3391 #define mmGCVM_INVALIDATE_ENG7_ACK                                                                     0x165c
3392 #define mmGCVM_INVALIDATE_ENG7_ACK_BASE_IDX                                                            0
3393 #define mmGCVM_INVALIDATE_ENG8_ACK                                                                     0x165d
3394 #define mmGCVM_INVALIDATE_ENG8_ACK_BASE_IDX                                                            0
3395 #define mmGCVM_INVALIDATE_ENG9_ACK                                                                     0x165e
3396 #define mmGCVM_INVALIDATE_ENG9_ACK_BASE_IDX                                                            0
3397 #define mmGCVM_INVALIDATE_ENG10_ACK                                                                    0x165f
3398 #define mmGCVM_INVALIDATE_ENG10_ACK_BASE_IDX                                                           0
3399 #define mmGCVM_INVALIDATE_ENG11_ACK                                                                    0x1660
3400 #define mmGCVM_INVALIDATE_ENG11_ACK_BASE_IDX                                                           0
3401 #define mmGCVM_INVALIDATE_ENG12_ACK                                                                    0x1661
3402 #define mmGCVM_INVALIDATE_ENG12_ACK_BASE_IDX                                                           0
3403 #define mmGCVM_INVALIDATE_ENG13_ACK                                                                    0x1662
3404 #define mmGCVM_INVALIDATE_ENG13_ACK_BASE_IDX                                                           0
3405 #define mmGCVM_INVALIDATE_ENG14_ACK                                                                    0x1663
3406 #define mmGCVM_INVALIDATE_ENG14_ACK_BASE_IDX                                                           0
3407 #define mmGCVM_INVALIDATE_ENG15_ACK                                                                    0x1664
3408 #define mmGCVM_INVALIDATE_ENG15_ACK_BASE_IDX                                                           0
3409 #define mmGCVM_INVALIDATE_ENG16_ACK                                                                    0x1665
3410 #define mmGCVM_INVALIDATE_ENG16_ACK_BASE_IDX                                                           0
3411 #define mmGCVM_INVALIDATE_ENG17_ACK                                                                    0x1666
3412 #define mmGCVM_INVALIDATE_ENG17_ACK_BASE_IDX                                                           0
3413 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32                                                         0x1667
3414 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX                                                0
3415 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32                                                         0x1668
3416 #define mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX                                                0
3417 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32                                                         0x1669
3418 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX                                                0
3419 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32                                                         0x166a
3420 #define mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX                                                0
3421 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32                                                         0x166b
3422 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX                                                0
3423 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32                                                         0x166c
3424 #define mmGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX                                                0
3425 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32                                                         0x166d
3426 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX                                                0
3427 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32                                                         0x166e
3428 #define mmGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX                                                0
3429 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32                                                         0x166f
3430 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX                                                0
3431 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32                                                         0x1670
3432 #define mmGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX                                                0
3433 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32                                                         0x1671
3434 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX                                                0
3435 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32                                                         0x1672
3436 #define mmGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX                                                0
3437 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32                                                         0x1673
3438 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX                                                0
3439 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32                                                         0x1674
3440 #define mmGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX                                                0
3441 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32                                                         0x1675
3442 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX                                                0
3443 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32                                                         0x1676
3444 #define mmGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX                                                0
3445 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32                                                         0x1677
3446 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX                                                0
3447 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32                                                         0x1678
3448 #define mmGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX                                                0
3449 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32                                                         0x1679
3450 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX                                                0
3451 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32                                                         0x167a
3452 #define mmGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX                                                0
3453 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32                                                        0x167b
3454 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX                                               0
3455 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32                                                        0x167c
3456 #define mmGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX                                               0
3457 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32                                                        0x167d
3458 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX                                               0
3459 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32                                                        0x167e
3460 #define mmGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX                                               0
3461 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32                                                        0x167f
3462 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX                                               0
3463 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32                                                        0x1680
3464 #define mmGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX                                               0
3465 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32                                                        0x1681
3466 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX                                               0
3467 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32                                                        0x1682
3468 #define mmGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX                                               0
3469 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32                                                        0x1683
3470 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX                                               0
3471 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32                                                        0x1684
3472 #define mmGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX                                               0
3473 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32                                                        0x1685
3474 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX                                               0
3475 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32                                                        0x1686
3476 #define mmGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX                                               0
3477 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32                                                        0x1687
3478 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX                                               0
3479 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32                                                        0x1688
3480 #define mmGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX                                               0
3481 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32                                                        0x1689
3482 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX                                               0
3483 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32                                                        0x168a
3484 #define mmGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX                                               0
3485 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32                                                      0x168b
3486 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3487 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32                                                      0x168c
3488 #define mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3489 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32                                                      0x168d
3490 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3491 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32                                                      0x168e
3492 #define mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3493 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32                                                      0x168f
3494 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3495 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1690
3496 #define mmGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3497 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1691
3498 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3499 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1692
3500 #define mmGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3501 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1693
3502 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3503 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1694
3504 #define mmGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3505 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1695
3506 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3507 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1696
3508 #define mmGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3509 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1697
3510 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3511 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32                                                      0x1698
3512 #define mmGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3513 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32                                                      0x1699
3514 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3515 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32                                                      0x169a
3516 #define mmGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3517 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32                                                      0x169b
3518 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3519 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32                                                      0x169c
3520 #define mmGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3521 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32                                                      0x169d
3522 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                             0
3523 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32                                                      0x169e
3524 #define mmGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                             0
3525 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32                                                     0x169f
3526 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3527 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16a0
3528 #define mmGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3529 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32                                                     0x16a1
3530 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3531 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16a2
3532 #define mmGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3533 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32                                                     0x16a3
3534 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3535 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16a4
3536 #define mmGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3537 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32                                                     0x16a5
3538 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3539 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16a6
3540 #define mmGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3541 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32                                                     0x16a7
3542 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3543 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16a8
3544 #define mmGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3545 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32                                                     0x16a9
3546 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX                                            0
3547 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32                                                     0x16aa
3548 #define mmGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX                                            0
3549 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32                                                     0x16ab
3550 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3551 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32                                                     0x16ac
3552 #define mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3553 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32                                                     0x16ad
3554 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3555 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32                                                     0x16ae
3556 #define mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3557 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32                                                     0x16af
3558 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3559 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32                                                     0x16b0
3560 #define mmGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3561 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32                                                     0x16b1
3562 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3563 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32                                                     0x16b2
3564 #define mmGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3565 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32                                                     0x16b3
3566 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3567 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32                                                     0x16b4
3568 #define mmGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3569 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32                                                     0x16b5
3570 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3571 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32                                                     0x16b6
3572 #define mmGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3573 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32                                                     0x16b7
3574 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3575 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32                                                     0x16b8
3576 #define mmGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3577 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32                                                     0x16b9
3578 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3579 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32                                                     0x16ba
3580 #define mmGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3581 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32                                                     0x16bb
3582 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3583 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32                                                     0x16bc
3584 #define mmGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3585 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32                                                     0x16bd
3586 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                            0
3587 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32                                                     0x16be
3588 #define mmGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                            0
3589 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32                                                    0x16bf
3590 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3591 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32                                                    0x16c0
3592 #define mmGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3593 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32                                                    0x16c1
3594 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3595 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32                                                    0x16c2
3596 #define mmGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3597 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32                                                    0x16c3
3598 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3599 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32                                                    0x16c4
3600 #define mmGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3601 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32                                                    0x16c5
3602 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3603 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32                                                    0x16c6
3604 #define mmGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3605 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32                                                    0x16c7
3606 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3607 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32                                                    0x16c8
3608 #define mmGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3609 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32                                                    0x16c9
3610 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX                                           0
3611 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32                                                    0x16ca
3612 #define mmGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX                                           0
3613 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32                                                       0x16cb
3614 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3615 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32                                                       0x16cc
3616 #define mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3617 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32                                                       0x16cd
3618 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3619 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32                                                       0x16ce
3620 #define mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3621 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32                                                       0x16cf
3622 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3623 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32                                                       0x16d0
3624 #define mmGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3625 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32                                                       0x16d1
3626 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3627 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32                                                       0x16d2
3628 #define mmGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3629 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32                                                       0x16d3
3630 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3631 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32                                                       0x16d4
3632 #define mmGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3633 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32                                                       0x16d5
3634 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3635 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32                                                       0x16d6
3636 #define mmGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3637 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32                                                       0x16d7
3638 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3639 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32                                                       0x16d8
3640 #define mmGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3641 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32                                                       0x16d9
3642 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3643 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32                                                       0x16da
3644 #define mmGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3645 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32                                                       0x16db
3646 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3647 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32                                                       0x16dc
3648 #define mmGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3649 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32                                                       0x16dd
3650 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                              0
3651 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32                                                       0x16de
3652 #define mmGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                              0
3653 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32                                                      0x16df
3654 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3655 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32                                                      0x16e0
3656 #define mmGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3657 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32                                                      0x16e1
3658 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3659 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32                                                      0x16e2
3660 #define mmGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3661 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32                                                      0x16e3
3662 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3663 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32                                                      0x16e4
3664 #define mmGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3665 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32                                                      0x16e5
3666 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3667 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32                                                      0x16e6
3668 #define mmGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3669 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32                                                      0x16e7
3670 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3671 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32                                                      0x16e8
3672 #define mmGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3673 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32                                                      0x16e9
3674 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX                                             0
3675 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32                                                      0x16ea
3676 #define mmGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX                                             0
3677 
3678 
3679 // addressBlock: gc_gcvmsharedpfdec
3680 // base address: 0xa590
3681 #define mmGCMC_VM_NB_MMIOBASE                                                                          0x1704
3682 #define mmGCMC_VM_NB_MMIOBASE_BASE_IDX                                                                 0
3683 #define mmGCMC_VM_NB_MMIOLIMIT                                                                         0x1705
3684 #define mmGCMC_VM_NB_MMIOLIMIT_BASE_IDX                                                                0
3685 #define mmGCMC_VM_NB_PCI_CTRL                                                                          0x1706
3686 #define mmGCMC_VM_NB_PCI_CTRL_BASE_IDX                                                                 0
3687 #define mmGCMC_VM_NB_PCI_ARB                                                                           0x1707
3688 #define mmGCMC_VM_NB_PCI_ARB_BASE_IDX                                                                  0
3689 #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1                                                                 0x1708
3690 #define mmGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX                                                        0
3691 #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2                                                                0x1709
3692 #define mmGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX                                                       0
3693 #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2                                                                0x170a
3694 #define mmGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX                                                       0
3695 #define mmGCMC_VM_FB_OFFSET                                                                            0x170b
3696 #define mmGCMC_VM_FB_OFFSET_BASE_IDX                                                                   0
3697 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB                                                     0x170c
3698 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX                                            0
3699 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB                                                     0x170d
3700 #define mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX                                            0
3701 #define mmGCMC_VM_STEERING                                                                             0x170e
3702 #define mmGCMC_VM_STEERING_BASE_IDX                                                                    0
3703 #define mmGCMC_SHARED_VIRT_RESET_REQ                                                                   0x170f
3704 #define mmGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX                                                          0
3705 #define mmGCMC_MEM_POWER_LS                                                                            0x1710
3706 #define mmGCMC_MEM_POWER_LS_BASE_IDX                                                                   0
3707 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START                                                         0x1711
3708 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX                                                0
3709 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END                                                           0x1712
3710 #define mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX                                                  0
3711 #define mmGCMC_VM_APT_CNTL                                                                             0x1713
3712 #define mmGCMC_VM_APT_CNTL_BASE_IDX                                                                    0
3713 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL                                                          0x1714
3714 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX                                                 0
3715 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START                                                              0x1715
3716 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX                                                     0
3717 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END                                                                0x1716
3718 #define mmGCMC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX                                                       0
3719 #define mmGCMC_SHARED_VIRT_RESET_REQ2                                                                  0x1717
3720 #define mmGCMC_SHARED_VIRT_RESET_REQ2_BASE_IDX                                                         0
3721 
3722 
3723 // addressBlock: gc_gcvmsharedvcdec
3724 // base address: 0xa600
3725 #define mmGCMC_VM_FB_LOCATION_BASE                                                                     0x1720
3726 #define mmGCMC_VM_FB_LOCATION_BASE_BASE_IDX                                                            0
3727 #define mmGCMC_VM_FB_LOCATION_TOP                                                                      0x1721
3728 #define mmGCMC_VM_FB_LOCATION_TOP_BASE_IDX                                                             0
3729 #define mmGCMC_VM_AGP_TOP                                                                              0x1722
3730 #define mmGCMC_VM_AGP_TOP_BASE_IDX                                                                     0
3731 #define mmGCMC_VM_AGP_BOT                                                                              0x1723
3732 #define mmGCMC_VM_AGP_BOT_BASE_IDX                                                                     0
3733 #define mmGCMC_VM_AGP_BASE                                                                             0x1724
3734 #define mmGCMC_VM_AGP_BASE_BASE_IDX                                                                    0
3735 #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR                                                             0x1725
3736 #define mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX                                                    0
3737 #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR                                                            0x1726
3738 #define mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX                                                   0
3739 #define mmGCMC_VM_MX_L1_TLB_CNTL                                                                       0x1727
3740 #define mmGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX                                                              0
3741 
3742 
3743 // addressBlock: gc_gceadec
3744 // base address: 0xa800
3745 #define mmGCEA_DRAM_RD_CLI2GRP_MAP0                                                                    0x17a0
3746 #define mmGCEA_DRAM_RD_CLI2GRP_MAP0_BASE_IDX                                                           0
3747 #define mmGCEA_DRAM_RD_CLI2GRP_MAP1                                                                    0x17a1
3748 #define mmGCEA_DRAM_RD_CLI2GRP_MAP1_BASE_IDX                                                           0
3749 #define mmGCEA_DRAM_WR_CLI2GRP_MAP0                                                                    0x17a2
3750 #define mmGCEA_DRAM_WR_CLI2GRP_MAP0_BASE_IDX                                                           0
3751 #define mmGCEA_DRAM_WR_CLI2GRP_MAP1                                                                    0x17a3
3752 #define mmGCEA_DRAM_WR_CLI2GRP_MAP1_BASE_IDX                                                           0
3753 #define mmGCEA_DRAM_RD_GRP2VC_MAP                                                                      0x17a4
3754 #define mmGCEA_DRAM_RD_GRP2VC_MAP_BASE_IDX                                                             0
3755 #define mmGCEA_DRAM_WR_GRP2VC_MAP                                                                      0x17a5
3756 #define mmGCEA_DRAM_WR_GRP2VC_MAP_BASE_IDX                                                             0
3757 #define mmGCEA_DRAM_RD_LAZY                                                                            0x17a6
3758 #define mmGCEA_DRAM_RD_LAZY_BASE_IDX                                                                   0
3759 #define mmGCEA_DRAM_WR_LAZY                                                                            0x17a7
3760 #define mmGCEA_DRAM_WR_LAZY_BASE_IDX                                                                   0
3761 #define mmGCEA_DRAM_RD_CAM_CNTL                                                                        0x17a8
3762 #define mmGCEA_DRAM_RD_CAM_CNTL_BASE_IDX                                                               0
3763 #define mmGCEA_DRAM_WR_CAM_CNTL                                                                        0x17a9
3764 #define mmGCEA_DRAM_WR_CAM_CNTL_BASE_IDX                                                               0
3765 #define mmGCEA_DRAM_PAGE_BURST                                                                         0x17aa
3766 #define mmGCEA_DRAM_PAGE_BURST_BASE_IDX                                                                0
3767 #define mmGCEA_DRAM_RD_PRI_AGE                                                                         0x17ab
3768 #define mmGCEA_DRAM_RD_PRI_AGE_BASE_IDX                                                                0
3769 #define mmGCEA_DRAM_WR_PRI_AGE                                                                         0x17ac
3770 #define mmGCEA_DRAM_WR_PRI_AGE_BASE_IDX                                                                0
3771 #define mmGCEA_DRAM_RD_PRI_QUEUING                                                                     0x17ad
3772 #define mmGCEA_DRAM_RD_PRI_QUEUING_BASE_IDX                                                            0
3773 #define mmGCEA_DRAM_WR_PRI_QUEUING                                                                     0x17ae
3774 #define mmGCEA_DRAM_WR_PRI_QUEUING_BASE_IDX                                                            0
3775 #define mmGCEA_DRAM_RD_PRI_FIXED                                                                       0x17af
3776 #define mmGCEA_DRAM_RD_PRI_FIXED_BASE_IDX                                                              0
3777 #define mmGCEA_DRAM_WR_PRI_FIXED                                                                       0x17b0
3778 #define mmGCEA_DRAM_WR_PRI_FIXED_BASE_IDX                                                              0
3779 #define mmGCEA_DRAM_RD_PRI_URGENCY                                                                     0x17b1
3780 #define mmGCEA_DRAM_RD_PRI_URGENCY_BASE_IDX                                                            0
3781 #define mmGCEA_DRAM_WR_PRI_URGENCY                                                                     0x17b2
3782 #define mmGCEA_DRAM_WR_PRI_URGENCY_BASE_IDX                                                            0
3783 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1                                                                  0x17b3
3784 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX                                                         0
3785 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2                                                                  0x17b4
3786 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX                                                         0
3787 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3                                                                  0x17b5
3788 #define mmGCEA_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX                                                         0
3789 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1                                                                  0x17b6
3790 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX                                                         0
3791 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2                                                                  0x17b7
3792 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX                                                         0
3793 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3                                                                  0x17b8
3794 #define mmGCEA_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX                                                         0
3795 #define mmGCEA_ADDRNORM_BASE_ADDR0                                                                     0x17d4
3796 #define mmGCEA_ADDRNORM_BASE_ADDR0_BASE_IDX                                                            0
3797 #define mmGCEA_ADDRNORM_LIMIT_ADDR0                                                                    0x17d5
3798 #define mmGCEA_ADDRNORM_LIMIT_ADDR0_BASE_IDX                                                           0
3799 #define mmGCEA_ADDRNORM_BASE_ADDR1                                                                     0x17d6
3800 #define mmGCEA_ADDRNORM_BASE_ADDR1_BASE_IDX                                                            0
3801 #define mmGCEA_ADDRNORM_LIMIT_ADDR1                                                                    0x17d7
3802 #define mmGCEA_ADDRNORM_LIMIT_ADDR1_BASE_IDX                                                           0
3803 #define mmGCEA_ADDRNORM_OFFSET_ADDR1                                                                   0x17d8
3804 #define mmGCEA_ADDRNORM_OFFSET_ADDR1_BASE_IDX                                                          0
3805 #define mmGCEA_ADDRNORMDRAM_HOLE_CNTL                                                                  0x17e3
3806 #define mmGCEA_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX                                                         0
3807 #define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG                                                            0x17e5
3808 #define mmGCEA_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX                                                   0
3809 #define mmGCEA_ADDRDEC_BANK_CFG                                                                        0x17e7
3810 #define mmGCEA_ADDRDEC_BANK_CFG_BASE_IDX                                                               0
3811 #define mmGCEA_ADDRDEC_MISC_CFG                                                                        0x17e8
3812 #define mmGCEA_ADDRDEC_MISC_CFG_BASE_IDX                                                               0
3813 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0                                                             0x17e9
3814 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX                                                    0
3815 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1                                                             0x17ea
3816 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX                                                    0
3817 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2                                                             0x17eb
3818 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX                                                    0
3819 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3                                                             0x17ec
3820 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX                                                    0
3821 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4                                                             0x17ed
3822 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX                                                    0
3823 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC                                                                0x17ee
3824 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX                                                       0
3825 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2                                                               0x17ef
3826 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX                                                      0
3827 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0                                                               0x17f0
3828 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX                                                      0
3829 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1                                                               0x17f1
3830 #define mmGCEA_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX                                                      0
3831 #define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE                                                              0x17f2
3832 #define mmGCEA_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX                                                     0
3833 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0                                                          0x17f3
3834 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START0_BASE_IDX                                                 0
3835 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0                                                            0x17f4
3836 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END0_BASE_IDX                                                   0
3837 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1                                                          0x17f5
3838 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_START1_BASE_IDX                                                 0
3839 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1                                                            0x17f6
3840 #define mmGCEA_ADDRDECDRAM_HARVNA_ADDR_END1_BASE_IDX                                                   0
3841 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS0                                                                  0x1805
3842 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX                                                         0
3843 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS1                                                                  0x1806
3844 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX                                                         0
3845 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS2                                                                  0x1807
3846 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX                                                         0
3847 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS3                                                                  0x1808
3848 #define mmGCEA_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX                                                         0
3849 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0                                                               0x1809
3850 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX                                                      0
3851 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1                                                               0x180a
3852 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX                                                      0
3853 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2                                                               0x180b
3854 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX                                                      0
3855 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3                                                               0x180c
3856 #define mmGCEA_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX                                                      0
3857 #define mmGCEA_ADDRDEC0_ADDR_MASK_CS01                                                                 0x180d
3858 #define mmGCEA_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX                                                        0
3859 #define mmGCEA_ADDRDEC0_ADDR_MASK_CS23                                                                 0x180e
3860 #define mmGCEA_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX                                                        0
3861 #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01                                                              0x180f
3862 #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX                                                     0
3863 #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23                                                              0x1810
3864 #define mmGCEA_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX                                                     0
3865 #define mmGCEA_ADDRDEC0_ADDR_CFG_CS01                                                                  0x1811
3866 #define mmGCEA_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX                                                         0
3867 #define mmGCEA_ADDRDEC0_ADDR_CFG_CS23                                                                  0x1812
3868 #define mmGCEA_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX                                                         0
3869 #define mmGCEA_ADDRDEC0_ADDR_SEL_CS01                                                                  0x1813
3870 #define mmGCEA_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX                                                         0
3871 #define mmGCEA_ADDRDEC0_ADDR_SEL_CS23                                                                  0x1814
3872 #define mmGCEA_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX                                                         0
3873 #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01                                                                0x1815
3874 #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX                                                       0
3875 #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23                                                                0x1816
3876 #define mmGCEA_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX                                                       0
3877 #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01                                                                0x1817
3878 #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX                                                       0
3879 #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23                                                                0x1818
3880 #define mmGCEA_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX                                                       0
3881 #define mmGCEA_ADDRDEC0_RM_SEL_CS01                                                                    0x1819
3882 #define mmGCEA_ADDRDEC0_RM_SEL_CS01_BASE_IDX                                                           0
3883 #define mmGCEA_ADDRDEC0_RM_SEL_CS23                                                                    0x181a
3884 #define mmGCEA_ADDRDEC0_RM_SEL_CS23_BASE_IDX                                                           0
3885 #define mmGCEA_ADDRDEC0_RM_SEL_SECCS01                                                                 0x181b
3886 #define mmGCEA_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX                                                        0
3887 #define mmGCEA_ADDRDEC0_RM_SEL_SECCS23                                                                 0x181c
3888 #define mmGCEA_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX                                                        0
3889 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS0                                                                  0x181d
3890 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX                                                         0
3891 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS1                                                                  0x181e
3892 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX                                                         0
3893 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS2                                                                  0x181f
3894 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX                                                         0
3895 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS3                                                                  0x1820
3896 #define mmGCEA_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX                                                         0
3897 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0                                                               0x1821
3898 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX                                                      0
3899 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1                                                               0x1822
3900 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX                                                      0
3901 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2                                                               0x1823
3902 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX                                                      0
3903 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3                                                               0x1824
3904 #define mmGCEA_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX                                                      0
3905 #define mmGCEA_ADDRDEC1_ADDR_MASK_CS01                                                                 0x1825
3906 #define mmGCEA_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX                                                        0
3907 #define mmGCEA_ADDRDEC1_ADDR_MASK_CS23                                                                 0x1826
3908 #define mmGCEA_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX                                                        0
3909 #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01                                                              0x1827
3910 #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX                                                     0
3911 #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23                                                              0x1828
3912 #define mmGCEA_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX                                                     0
3913 #define mmGCEA_ADDRDEC1_ADDR_CFG_CS01                                                                  0x1829
3914 #define mmGCEA_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX                                                         0
3915 #define mmGCEA_ADDRDEC1_ADDR_CFG_CS23                                                                  0x182a
3916 #define mmGCEA_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX                                                         0
3917 #define mmGCEA_ADDRDEC1_ADDR_SEL_CS01                                                                  0x182b
3918 #define mmGCEA_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX                                                         0
3919 #define mmGCEA_ADDRDEC1_ADDR_SEL_CS23                                                                  0x182c
3920 #define mmGCEA_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX                                                         0
3921 #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01                                                                0x182d
3922 #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX                                                       0
3923 #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23                                                                0x182e
3924 #define mmGCEA_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX                                                       0
3925 #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01                                                                0x182f
3926 #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX                                                       0
3927 #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23                                                                0x1830
3928 #define mmGCEA_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX                                                       0
3929 #define mmGCEA_ADDRDEC1_RM_SEL_CS01                                                                    0x1831
3930 #define mmGCEA_ADDRDEC1_RM_SEL_CS01_BASE_IDX                                                           0
3931 #define mmGCEA_ADDRDEC1_RM_SEL_CS23                                                                    0x1832
3932 #define mmGCEA_ADDRDEC1_RM_SEL_CS23_BASE_IDX                                                           0
3933 #define mmGCEA_ADDRDEC1_RM_SEL_SECCS01                                                                 0x1833
3934 #define mmGCEA_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX                                                        0
3935 #define mmGCEA_ADDRDEC1_RM_SEL_SECCS23                                                                 0x1834
3936 #define mmGCEA_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX                                                        0
3937 #define mmGCEA_IO_RD_CLI2GRP_MAP0                                                                      0x187d
3938 #define mmGCEA_IO_RD_CLI2GRP_MAP0_BASE_IDX                                                             0
3939 #define mmGCEA_IO_RD_CLI2GRP_MAP1                                                                      0x187e
3940 #define mmGCEA_IO_RD_CLI2GRP_MAP1_BASE_IDX                                                             0
3941 #define mmGCEA_IO_WR_CLI2GRP_MAP0                                                                      0x187f
3942 #define mmGCEA_IO_WR_CLI2GRP_MAP0_BASE_IDX                                                             0
3943 #define mmGCEA_IO_WR_CLI2GRP_MAP1                                                                      0x1880
3944 #define mmGCEA_IO_WR_CLI2GRP_MAP1_BASE_IDX                                                             0
3945 #define mmGCEA_IO_RD_COMBINE_FLUSH                                                                     0x1881
3946 #define mmGCEA_IO_RD_COMBINE_FLUSH_BASE_IDX                                                            0
3947 #define mmGCEA_IO_WR_COMBINE_FLUSH                                                                     0x1882
3948 #define mmGCEA_IO_WR_COMBINE_FLUSH_BASE_IDX                                                            0
3949 #define mmGCEA_IO_GROUP_BURST                                                                          0x1883
3950 #define mmGCEA_IO_GROUP_BURST_BASE_IDX                                                                 0
3951 #define mmGCEA_IO_RD_PRI_AGE                                                                           0x1884
3952 #define mmGCEA_IO_RD_PRI_AGE_BASE_IDX                                                                  0
3953 #define mmGCEA_IO_WR_PRI_AGE                                                                           0x1885
3954 #define mmGCEA_IO_WR_PRI_AGE_BASE_IDX                                                                  0
3955 #define mmGCEA_IO_RD_PRI_QUEUING                                                                       0x1886
3956 #define mmGCEA_IO_RD_PRI_QUEUING_BASE_IDX                                                              0
3957 #define mmGCEA_IO_WR_PRI_QUEUING                                                                       0x1887
3958 #define mmGCEA_IO_WR_PRI_QUEUING_BASE_IDX                                                              0
3959 #define mmGCEA_IO_RD_PRI_FIXED                                                                         0x1888
3960 #define mmGCEA_IO_RD_PRI_FIXED_BASE_IDX                                                                0
3961 #define mmGCEA_IO_WR_PRI_FIXED                                                                         0x1889
3962 #define mmGCEA_IO_WR_PRI_FIXED_BASE_IDX                                                                0
3963 #define mmGCEA_IO_RD_PRI_URGENCY                                                                       0x188a
3964 #define mmGCEA_IO_RD_PRI_URGENCY_BASE_IDX                                                              0
3965 #define mmGCEA_IO_WR_PRI_URGENCY                                                                       0x188b
3966 #define mmGCEA_IO_WR_PRI_URGENCY_BASE_IDX                                                              0
3967 #define mmGCEA_IO_RD_PRI_URGENCY_MASKING                                                               0x188c
3968 #define mmGCEA_IO_RD_PRI_URGENCY_MASKING_BASE_IDX                                                      0
3969 #define mmGCEA_IO_WR_PRI_URGENCY_MASKING                                                               0x188d
3970 #define mmGCEA_IO_WR_PRI_URGENCY_MASKING_BASE_IDX                                                      0
3971 #define mmGCEA_IO_RD_PRI_QUANT_PRI1                                                                    0x188e
3972 #define mmGCEA_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                           0
3973 #define mmGCEA_IO_RD_PRI_QUANT_PRI2                                                                    0x188f
3974 #define mmGCEA_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                           0
3975 #define mmGCEA_IO_RD_PRI_QUANT_PRI3                                                                    0x1890
3976 #define mmGCEA_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                           0
3977 #define mmGCEA_IO_WR_PRI_QUANT_PRI1                                                                    0x1891
3978 #define mmGCEA_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                           0
3979 #define mmGCEA_IO_WR_PRI_QUANT_PRI2                                                                    0x1892
3980 #define mmGCEA_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                           0
3981 #define mmGCEA_IO_WR_PRI_QUANT_PRI3                                                                    0x1893
3982 #define mmGCEA_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                           0
3983 #define mmGCEA_SDP_ARB_DRAM                                                                            0x1894
3984 #define mmGCEA_SDP_ARB_DRAM_BASE_IDX                                                                   0
3985 #define mmGCEA_SDP_ARB_FINAL                                                                           0x1896
3986 #define mmGCEA_SDP_ARB_FINAL_BASE_IDX                                                                  0
3987 #define mmGCEA_SDP_DRAM_PRIORITY                                                                       0x1897
3988 #define mmGCEA_SDP_DRAM_PRIORITY_BASE_IDX                                                              0
3989 #define mmGCEA_SDP_IO_PRIORITY                                                                         0x1899
3990 #define mmGCEA_SDP_IO_PRIORITY_BASE_IDX                                                                0
3991 #define mmGCEA_SDP_CREDITS                                                                             0x189a
3992 #define mmGCEA_SDP_CREDITS_BASE_IDX                                                                    0
3993 #define mmGCEA_SDP_TAG_RESERVE0                                                                        0x189b
3994 #define mmGCEA_SDP_TAG_RESERVE0_BASE_IDX                                                               0
3995 #define mmGCEA_SDP_TAG_RESERVE1                                                                        0x189c
3996 #define mmGCEA_SDP_TAG_RESERVE1_BASE_IDX                                                               0
3997 #define mmGCEA_SDP_VCC_RESERVE0                                                                        0x189d
3998 #define mmGCEA_SDP_VCC_RESERVE0_BASE_IDX                                                               0
3999 #define mmGCEA_SDP_VCC_RESERVE1                                                                        0x189e
4000 #define mmGCEA_SDP_VCC_RESERVE1_BASE_IDX                                                               0
4001 #define mmGCEA_SDP_VCD_RESERVE0                                                                        0x189f
4002 #define mmGCEA_SDP_VCD_RESERVE0_BASE_IDX                                                               0
4003 
4004 
4005 // addressBlock: gc_tcdec
4006 // base address: 0xac00
4007 #define mmTCP_INVALIDATE                                                                               0x18a0
4008 #define mmTCP_INVALIDATE_BASE_IDX                                                                      0
4009 #define mmTCP_STATUS                                                                                   0x18a1
4010 #define mmTCP_STATUS_BASE_IDX                                                                          0
4011 #define mmTCP_CNTL                                                                                     0x18a2
4012 #define mmTCP_CNTL_BASE_IDX                                                                            0
4013 #define mmTCP_CREDIT                                                                                   0x18a6
4014 #define mmTCP_CREDIT_BASE_IDX                                                                          0
4015 #define mmTCP_BUFFER_ADDR_HASH_CNTL                                                                    0x18b6
4016 #define mmTCP_BUFFER_ADDR_HASH_CNTL_BASE_IDX                                                           0
4017 #define mmTCP_EDC_CNT                                                                                  0x18b7
4018 #define mmTCP_EDC_CNT_BASE_IDX                                                                         0
4019 #define mmTCI_STATUS                                                                                   0x1901
4020 #define mmTCI_STATUS_BASE_IDX                                                                          0
4021 #define mmTCI_CNTL_1                                                                                   0x1902
4022 #define mmTCI_CNTL_1_BASE_IDX                                                                          0
4023 #define mmTCI_CNTL_2                                                                                   0x1903
4024 #define mmTCI_CNTL_2_BASE_IDX                                                                          0
4025 
4026 
4027 // addressBlock: gc_shdec
4028 // base address: 0xb000
4029 #define mmSPI_SHADER_PGM_RSRC4_PS                                                                      0x19a1
4030 #define mmSPI_SHADER_PGM_RSRC4_PS_BASE_IDX                                                             0
4031 #define mmSPI_SHADER_PGM_CHKSUM_PS                                                                     0x19a6
4032 #define mmSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX                                                            0
4033 #define mmSPI_SHADER_PGM_RSRC3_PS                                                                      0x19a7
4034 #define mmSPI_SHADER_PGM_RSRC3_PS_BASE_IDX                                                             0
4035 #define mmSPI_SHADER_PGM_LO_PS                                                                         0x19a8
4036 #define mmSPI_SHADER_PGM_LO_PS_BASE_IDX                                                                0
4037 #define mmSPI_SHADER_PGM_HI_PS                                                                         0x19a9
4038 #define mmSPI_SHADER_PGM_HI_PS_BASE_IDX                                                                0
4039 #define mmSPI_SHADER_PGM_RSRC1_PS                                                                      0x19aa
4040 #define mmSPI_SHADER_PGM_RSRC1_PS_BASE_IDX                                                             0
4041 #define mmSPI_SHADER_PGM_RSRC2_PS                                                                      0x19ab
4042 #define mmSPI_SHADER_PGM_RSRC2_PS_BASE_IDX                                                             0
4043 #define mmSPI_SHADER_USER_DATA_PS_0                                                                    0x19ac
4044 #define mmSPI_SHADER_USER_DATA_PS_0_BASE_IDX                                                           0
4045 #define mmSPI_SHADER_USER_DATA_PS_1                                                                    0x19ad
4046 #define mmSPI_SHADER_USER_DATA_PS_1_BASE_IDX                                                           0
4047 #define mmSPI_SHADER_USER_DATA_PS_2                                                                    0x19ae
4048 #define mmSPI_SHADER_USER_DATA_PS_2_BASE_IDX                                                           0
4049 #define mmSPI_SHADER_USER_DATA_PS_3                                                                    0x19af
4050 #define mmSPI_SHADER_USER_DATA_PS_3_BASE_IDX                                                           0
4051 #define mmSPI_SHADER_USER_DATA_PS_4                                                                    0x19b0
4052 #define mmSPI_SHADER_USER_DATA_PS_4_BASE_IDX                                                           0
4053 #define mmSPI_SHADER_USER_DATA_PS_5                                                                    0x19b1
4054 #define mmSPI_SHADER_USER_DATA_PS_5_BASE_IDX                                                           0
4055 #define mmSPI_SHADER_USER_DATA_PS_6                                                                    0x19b2
4056 #define mmSPI_SHADER_USER_DATA_PS_6_BASE_IDX                                                           0
4057 #define mmSPI_SHADER_USER_DATA_PS_7                                                                    0x19b3
4058 #define mmSPI_SHADER_USER_DATA_PS_7_BASE_IDX                                                           0
4059 #define mmSPI_SHADER_USER_DATA_PS_8                                                                    0x19b4
4060 #define mmSPI_SHADER_USER_DATA_PS_8_BASE_IDX                                                           0
4061 #define mmSPI_SHADER_USER_DATA_PS_9                                                                    0x19b5
4062 #define mmSPI_SHADER_USER_DATA_PS_9_BASE_IDX                                                           0
4063 #define mmSPI_SHADER_USER_DATA_PS_10                                                                   0x19b6
4064 #define mmSPI_SHADER_USER_DATA_PS_10_BASE_IDX                                                          0
4065 #define mmSPI_SHADER_USER_DATA_PS_11                                                                   0x19b7
4066 #define mmSPI_SHADER_USER_DATA_PS_11_BASE_IDX                                                          0
4067 #define mmSPI_SHADER_USER_DATA_PS_12                                                                   0x19b8
4068 #define mmSPI_SHADER_USER_DATA_PS_12_BASE_IDX                                                          0
4069 #define mmSPI_SHADER_USER_DATA_PS_13                                                                   0x19b9
4070 #define mmSPI_SHADER_USER_DATA_PS_13_BASE_IDX                                                          0
4071 #define mmSPI_SHADER_USER_DATA_PS_14                                                                   0x19ba
4072 #define mmSPI_SHADER_USER_DATA_PS_14_BASE_IDX                                                          0
4073 #define mmSPI_SHADER_USER_DATA_PS_15                                                                   0x19bb
4074 #define mmSPI_SHADER_USER_DATA_PS_15_BASE_IDX                                                          0
4075 #define mmSPI_SHADER_USER_DATA_PS_16                                                                   0x19bc
4076 #define mmSPI_SHADER_USER_DATA_PS_16_BASE_IDX                                                          0
4077 #define mmSPI_SHADER_USER_DATA_PS_17                                                                   0x19bd
4078 #define mmSPI_SHADER_USER_DATA_PS_17_BASE_IDX                                                          0
4079 #define mmSPI_SHADER_USER_DATA_PS_18                                                                   0x19be
4080 #define mmSPI_SHADER_USER_DATA_PS_18_BASE_IDX                                                          0
4081 #define mmSPI_SHADER_USER_DATA_PS_19                                                                   0x19bf
4082 #define mmSPI_SHADER_USER_DATA_PS_19_BASE_IDX                                                          0
4083 #define mmSPI_SHADER_USER_DATA_PS_20                                                                   0x19c0
4084 #define mmSPI_SHADER_USER_DATA_PS_20_BASE_IDX                                                          0
4085 #define mmSPI_SHADER_USER_DATA_PS_21                                                                   0x19c1
4086 #define mmSPI_SHADER_USER_DATA_PS_21_BASE_IDX                                                          0
4087 #define mmSPI_SHADER_USER_DATA_PS_22                                                                   0x19c2
4088 #define mmSPI_SHADER_USER_DATA_PS_22_BASE_IDX                                                          0
4089 #define mmSPI_SHADER_USER_DATA_PS_23                                                                   0x19c3
4090 #define mmSPI_SHADER_USER_DATA_PS_23_BASE_IDX                                                          0
4091 #define mmSPI_SHADER_USER_DATA_PS_24                                                                   0x19c4
4092 #define mmSPI_SHADER_USER_DATA_PS_24_BASE_IDX                                                          0
4093 #define mmSPI_SHADER_USER_DATA_PS_25                                                                   0x19c5
4094 #define mmSPI_SHADER_USER_DATA_PS_25_BASE_IDX                                                          0
4095 #define mmSPI_SHADER_USER_DATA_PS_26                                                                   0x19c6
4096 #define mmSPI_SHADER_USER_DATA_PS_26_BASE_IDX                                                          0
4097 #define mmSPI_SHADER_USER_DATA_PS_27                                                                   0x19c7
4098 #define mmSPI_SHADER_USER_DATA_PS_27_BASE_IDX                                                          0
4099 #define mmSPI_SHADER_USER_DATA_PS_28                                                                   0x19c8
4100 #define mmSPI_SHADER_USER_DATA_PS_28_BASE_IDX                                                          0
4101 #define mmSPI_SHADER_USER_DATA_PS_29                                                                   0x19c9
4102 #define mmSPI_SHADER_USER_DATA_PS_29_BASE_IDX                                                          0
4103 #define mmSPI_SHADER_USER_DATA_PS_30                                                                   0x19ca
4104 #define mmSPI_SHADER_USER_DATA_PS_30_BASE_IDX                                                          0
4105 #define mmSPI_SHADER_USER_DATA_PS_31                                                                   0x19cb
4106 #define mmSPI_SHADER_USER_DATA_PS_31_BASE_IDX                                                          0
4107 #define mmSPI_SHADER_REQ_CTRL_PS                                                                       0x19d0
4108 #define mmSPI_SHADER_REQ_CTRL_PS_BASE_IDX                                                              0
4109 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS                                                             0x19d1
4110 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_PS_BASE_IDX                                                    0
4111 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0                                                               0x19d2
4112 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_0_BASE_IDX                                                      0
4113 #define mmSPI_SHADER_USER_ACCUM_PS_0                                                                   0x19d2
4114 #define mmSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX                                                          0
4115 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1                                                               0x19d3
4116 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_1_BASE_IDX                                                      0
4117 #define mmSPI_SHADER_USER_ACCUM_PS_1                                                                   0x19d3
4118 #define mmSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX                                                          0
4119 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2                                                               0x19d4
4120 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_2_BASE_IDX                                                      0
4121 #define mmSPI_SHADER_USER_ACCUM_PS_2                                                                   0x19d4
4122 #define mmSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX                                                          0
4123 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3                                                               0x19d5
4124 #define mmSPI_SHADER_PREF_PRI_ACCUM_PS_3_BASE_IDX                                                      0
4125 #define mmSPI_SHADER_USER_ACCUM_PS_3                                                                   0x19d5
4126 #define mmSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX                                                          0
4127 #define mmSPI_SHADER_PGM_RSRC4_VS                                                                      0x19e1
4128 #define mmSPI_SHADER_PGM_RSRC4_VS_BASE_IDX                                                             0
4129 #define mmSPI_SHADER_PGM_CHKSUM_VS                                                                     0x19e5
4130 #define mmSPI_SHADER_PGM_CHKSUM_VS_BASE_IDX                                                            0
4131 #define mmSPI_SHADER_PGM_RSRC3_VS                                                                      0x19e6
4132 #define mmSPI_SHADER_PGM_RSRC3_VS_BASE_IDX                                                             0
4133 #define mmSPI_SHADER_LATE_ALLOC_VS                                                                     0x19e7
4134 #define mmSPI_SHADER_LATE_ALLOC_VS_BASE_IDX                                                            0
4135 #define mmSPI_SHADER_PGM_LO_VS                                                                         0x19e8
4136 #define mmSPI_SHADER_PGM_LO_VS_BASE_IDX                                                                0
4137 #define mmSPI_SHADER_PGM_HI_VS                                                                         0x19e9
4138 #define mmSPI_SHADER_PGM_HI_VS_BASE_IDX                                                                0
4139 #define mmSPI_SHADER_PGM_RSRC1_VS                                                                      0x19ea
4140 #define mmSPI_SHADER_PGM_RSRC1_VS_BASE_IDX                                                             0
4141 #define mmSPI_SHADER_PGM_RSRC2_VS                                                                      0x19eb
4142 #define mmSPI_SHADER_PGM_RSRC2_VS_BASE_IDX                                                             0
4143 #define mmSPI_SHADER_USER_DATA_VS_0                                                                    0x19ec
4144 #define mmSPI_SHADER_USER_DATA_VS_0_BASE_IDX                                                           0
4145 #define mmSPI_SHADER_USER_DATA_VS_1                                                                    0x19ed
4146 #define mmSPI_SHADER_USER_DATA_VS_1_BASE_IDX                                                           0
4147 #define mmSPI_SHADER_USER_DATA_VS_2                                                                    0x19ee
4148 #define mmSPI_SHADER_USER_DATA_VS_2_BASE_IDX                                                           0
4149 #define mmSPI_SHADER_USER_DATA_VS_3                                                                    0x19ef
4150 #define mmSPI_SHADER_USER_DATA_VS_3_BASE_IDX                                                           0
4151 #define mmSPI_SHADER_USER_DATA_VS_4                                                                    0x19f0
4152 #define mmSPI_SHADER_USER_DATA_VS_4_BASE_IDX                                                           0
4153 #define mmSPI_SHADER_USER_DATA_VS_5                                                                    0x19f1
4154 #define mmSPI_SHADER_USER_DATA_VS_5_BASE_IDX                                                           0
4155 #define mmSPI_SHADER_USER_DATA_VS_6                                                                    0x19f2
4156 #define mmSPI_SHADER_USER_DATA_VS_6_BASE_IDX                                                           0
4157 #define mmSPI_SHADER_USER_DATA_VS_7                                                                    0x19f3
4158 #define mmSPI_SHADER_USER_DATA_VS_7_BASE_IDX                                                           0
4159 #define mmSPI_SHADER_USER_DATA_VS_8                                                                    0x19f4
4160 #define mmSPI_SHADER_USER_DATA_VS_8_BASE_IDX                                                           0
4161 #define mmSPI_SHADER_USER_DATA_VS_9                                                                    0x19f5
4162 #define mmSPI_SHADER_USER_DATA_VS_9_BASE_IDX                                                           0
4163 #define mmSPI_SHADER_USER_DATA_VS_10                                                                   0x19f6
4164 #define mmSPI_SHADER_USER_DATA_VS_10_BASE_IDX                                                          0
4165 #define mmSPI_SHADER_USER_DATA_VS_11                                                                   0x19f7
4166 #define mmSPI_SHADER_USER_DATA_VS_11_BASE_IDX                                                          0
4167 #define mmSPI_SHADER_USER_DATA_VS_12                                                                   0x19f8
4168 #define mmSPI_SHADER_USER_DATA_VS_12_BASE_IDX                                                          0
4169 #define mmSPI_SHADER_USER_DATA_VS_13                                                                   0x19f9
4170 #define mmSPI_SHADER_USER_DATA_VS_13_BASE_IDX                                                          0
4171 #define mmSPI_SHADER_USER_DATA_VS_14                                                                   0x19fa
4172 #define mmSPI_SHADER_USER_DATA_VS_14_BASE_IDX                                                          0
4173 #define mmSPI_SHADER_USER_DATA_VS_15                                                                   0x19fb
4174 #define mmSPI_SHADER_USER_DATA_VS_15_BASE_IDX                                                          0
4175 #define mmSPI_SHADER_USER_DATA_VS_16                                                                   0x19fc
4176 #define mmSPI_SHADER_USER_DATA_VS_16_BASE_IDX                                                          0
4177 #define mmSPI_SHADER_USER_DATA_VS_17                                                                   0x19fd
4178 #define mmSPI_SHADER_USER_DATA_VS_17_BASE_IDX                                                          0
4179 #define mmSPI_SHADER_USER_DATA_VS_18                                                                   0x19fe
4180 #define mmSPI_SHADER_USER_DATA_VS_18_BASE_IDX                                                          0
4181 #define mmSPI_SHADER_USER_DATA_VS_19                                                                   0x19ff
4182 #define mmSPI_SHADER_USER_DATA_VS_19_BASE_IDX                                                          0
4183 #define mmSPI_SHADER_USER_DATA_VS_20                                                                   0x1a00
4184 #define mmSPI_SHADER_USER_DATA_VS_20_BASE_IDX                                                          0
4185 #define mmSPI_SHADER_USER_DATA_VS_21                                                                   0x1a01
4186 #define mmSPI_SHADER_USER_DATA_VS_21_BASE_IDX                                                          0
4187 #define mmSPI_SHADER_USER_DATA_VS_22                                                                   0x1a02
4188 #define mmSPI_SHADER_USER_DATA_VS_22_BASE_IDX                                                          0
4189 #define mmSPI_SHADER_USER_DATA_VS_23                                                                   0x1a03
4190 #define mmSPI_SHADER_USER_DATA_VS_23_BASE_IDX                                                          0
4191 #define mmSPI_SHADER_USER_DATA_VS_24                                                                   0x1a04
4192 #define mmSPI_SHADER_USER_DATA_VS_24_BASE_IDX                                                          0
4193 #define mmSPI_SHADER_USER_DATA_VS_25                                                                   0x1a05
4194 #define mmSPI_SHADER_USER_DATA_VS_25_BASE_IDX                                                          0
4195 #define mmSPI_SHADER_USER_DATA_VS_26                                                                   0x1a06
4196 #define mmSPI_SHADER_USER_DATA_VS_26_BASE_IDX                                                          0
4197 #define mmSPI_SHADER_USER_DATA_VS_27                                                                   0x1a07
4198 #define mmSPI_SHADER_USER_DATA_VS_27_BASE_IDX                                                          0
4199 #define mmSPI_SHADER_USER_DATA_VS_28                                                                   0x1a08
4200 #define mmSPI_SHADER_USER_DATA_VS_28_BASE_IDX                                                          0
4201 #define mmSPI_SHADER_USER_DATA_VS_29                                                                   0x1a09
4202 #define mmSPI_SHADER_USER_DATA_VS_29_BASE_IDX                                                          0
4203 #define mmSPI_SHADER_USER_DATA_VS_30                                                                   0x1a0a
4204 #define mmSPI_SHADER_USER_DATA_VS_30_BASE_IDX                                                          0
4205 #define mmSPI_SHADER_USER_DATA_VS_31                                                                   0x1a0b
4206 #define mmSPI_SHADER_USER_DATA_VS_31_BASE_IDX                                                          0
4207 #define mmSPI_SHADER_REQ_CTRL_VS                                                                       0x1a10
4208 #define mmSPI_SHADER_REQ_CTRL_VS_BASE_IDX                                                              0
4209 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS                                                             0x1a11
4210 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_VS_BASE_IDX                                                    0
4211 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0                                                               0x1a12
4212 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_0_BASE_IDX                                                      0
4213 #define mmSPI_SHADER_USER_ACCUM_VS_0                                                                   0x1a12
4214 #define mmSPI_SHADER_USER_ACCUM_VS_0_BASE_IDX                                                          0
4215 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1                                                               0x1a13
4216 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_1_BASE_IDX                                                      0
4217 #define mmSPI_SHADER_USER_ACCUM_VS_1                                                                   0x1a13
4218 #define mmSPI_SHADER_USER_ACCUM_VS_1_BASE_IDX                                                          0
4219 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2                                                               0x1a14
4220 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_2_BASE_IDX                                                      0
4221 #define mmSPI_SHADER_USER_ACCUM_VS_2                                                                   0x1a14
4222 #define mmSPI_SHADER_USER_ACCUM_VS_2_BASE_IDX                                                          0
4223 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3                                                               0x1a15
4224 #define mmSPI_SHADER_PREF_PRI_ACCUM_VS_3_BASE_IDX                                                      0
4225 #define mmSPI_SHADER_USER_ACCUM_VS_3                                                                   0x1a15
4226 #define mmSPI_SHADER_USER_ACCUM_VS_3_BASE_IDX                                                          0
4227 #define mmSPI_SHADER_PGM_RSRC2_GS_VS                                                                   0x1a1b
4228 #define mmSPI_SHADER_PGM_RSRC2_GS_VS_BASE_IDX                                                          0
4229 #define mmSPI_SHADER_PGM_RSRC2_ES_VS                                                                   0x1a1c
4230 #define mmSPI_SHADER_PGM_RSRC2_ES_VS_BASE_IDX                                                          0
4231 #define mmSPI_SHADER_PGM_RSRC2_LS_VS                                                                   0x1a1d
4232 #define mmSPI_SHADER_PGM_RSRC2_LS_VS_BASE_IDX                                                          0
4233 #define mmSPI_SHADER_PGM_CHKSUM_GS                                                                     0x1a20
4234 #define mmSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX                                                            0
4235 #define mmSPI_SHADER_PGM_RSRC4_GS                                                                      0x1a21
4236 #define mmSPI_SHADER_PGM_RSRC4_GS_BASE_IDX                                                             0
4237 #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS                                                              0x1a22
4238 #define mmSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX                                                     0
4239 #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS                                                              0x1a23
4240 #define mmSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX                                                     0
4241 #define mmSPI_SHADER_PGM_LO_ES_GS                                                                      0x1a24
4242 #define mmSPI_SHADER_PGM_LO_ES_GS_BASE_IDX                                                             0
4243 #define mmSPI_SHADER_PGM_HI_ES_GS                                                                      0x1a25
4244 #define mmSPI_SHADER_PGM_HI_ES_GS_BASE_IDX                                                             0
4245 #define mmSPI_SHADER_PGM_RSRC3_GS                                                                      0x1a27
4246 #define mmSPI_SHADER_PGM_RSRC3_GS_BASE_IDX                                                             0
4247 #define mmSPI_SHADER_PGM_LO_GS                                                                         0x1a28
4248 #define mmSPI_SHADER_PGM_LO_GS_BASE_IDX                                                                0
4249 #define mmSPI_SHADER_PGM_HI_GS                                                                         0x1a29
4250 #define mmSPI_SHADER_PGM_HI_GS_BASE_IDX                                                                0
4251 #define mmSPI_SHADER_PGM_RSRC1_GS                                                                      0x1a2a
4252 #define mmSPI_SHADER_PGM_RSRC1_GS_BASE_IDX                                                             0
4253 #define mmSPI_SHADER_PGM_RSRC2_GS                                                                      0x1a2b
4254 #define mmSPI_SHADER_PGM_RSRC2_GS_BASE_IDX                                                             0
4255 #define mmSPI_SHADER_USER_DATA_GS_0                                                                    0x1a2c
4256 #define mmSPI_SHADER_USER_DATA_GS_0_BASE_IDX                                                           0
4257 #define mmSPI_SHADER_USER_DATA_GS_1                                                                    0x1a2d
4258 #define mmSPI_SHADER_USER_DATA_GS_1_BASE_IDX                                                           0
4259 #define mmSPI_SHADER_USER_DATA_GS_2                                                                    0x1a2e
4260 #define mmSPI_SHADER_USER_DATA_GS_2_BASE_IDX                                                           0
4261 #define mmSPI_SHADER_USER_DATA_GS_3                                                                    0x1a2f
4262 #define mmSPI_SHADER_USER_DATA_GS_3_BASE_IDX                                                           0
4263 #define mmSPI_SHADER_USER_DATA_GS_4                                                                    0x1a30
4264 #define mmSPI_SHADER_USER_DATA_GS_4_BASE_IDX                                                           0
4265 #define mmSPI_SHADER_USER_DATA_GS_5                                                                    0x1a31
4266 #define mmSPI_SHADER_USER_DATA_GS_5_BASE_IDX                                                           0
4267 #define mmSPI_SHADER_USER_DATA_GS_6                                                                    0x1a32
4268 #define mmSPI_SHADER_USER_DATA_GS_6_BASE_IDX                                                           0
4269 #define mmSPI_SHADER_USER_DATA_GS_7                                                                    0x1a33
4270 #define mmSPI_SHADER_USER_DATA_GS_7_BASE_IDX                                                           0
4271 #define mmSPI_SHADER_USER_DATA_GS_8                                                                    0x1a34
4272 #define mmSPI_SHADER_USER_DATA_GS_8_BASE_IDX                                                           0
4273 #define mmSPI_SHADER_USER_DATA_GS_9                                                                    0x1a35
4274 #define mmSPI_SHADER_USER_DATA_GS_9_BASE_IDX                                                           0
4275 #define mmSPI_SHADER_USER_DATA_GS_10                                                                   0x1a36
4276 #define mmSPI_SHADER_USER_DATA_GS_10_BASE_IDX                                                          0
4277 #define mmSPI_SHADER_USER_DATA_GS_11                                                                   0x1a37
4278 #define mmSPI_SHADER_USER_DATA_GS_11_BASE_IDX                                                          0
4279 #define mmSPI_SHADER_USER_DATA_GS_12                                                                   0x1a38
4280 #define mmSPI_SHADER_USER_DATA_GS_12_BASE_IDX                                                          0
4281 #define mmSPI_SHADER_USER_DATA_GS_13                                                                   0x1a39
4282 #define mmSPI_SHADER_USER_DATA_GS_13_BASE_IDX                                                          0
4283 #define mmSPI_SHADER_USER_DATA_GS_14                                                                   0x1a3a
4284 #define mmSPI_SHADER_USER_DATA_GS_14_BASE_IDX                                                          0
4285 #define mmSPI_SHADER_USER_DATA_GS_15                                                                   0x1a3b
4286 #define mmSPI_SHADER_USER_DATA_GS_15_BASE_IDX                                                          0
4287 #define mmSPI_SHADER_USER_DATA_GS_16                                                                   0x1a3c
4288 #define mmSPI_SHADER_USER_DATA_GS_16_BASE_IDX                                                          0
4289 #define mmSPI_SHADER_USER_DATA_GS_17                                                                   0x1a3d
4290 #define mmSPI_SHADER_USER_DATA_GS_17_BASE_IDX                                                          0
4291 #define mmSPI_SHADER_USER_DATA_GS_18                                                                   0x1a3e
4292 #define mmSPI_SHADER_USER_DATA_GS_18_BASE_IDX                                                          0
4293 #define mmSPI_SHADER_USER_DATA_GS_19                                                                   0x1a3f
4294 #define mmSPI_SHADER_USER_DATA_GS_19_BASE_IDX                                                          0
4295 #define mmSPI_SHADER_USER_DATA_GS_20                                                                   0x1a40
4296 #define mmSPI_SHADER_USER_DATA_GS_20_BASE_IDX                                                          0
4297 #define mmSPI_SHADER_USER_DATA_GS_21                                                                   0x1a41
4298 #define mmSPI_SHADER_USER_DATA_GS_21_BASE_IDX                                                          0
4299 #define mmSPI_SHADER_USER_DATA_GS_22                                                                   0x1a42
4300 #define mmSPI_SHADER_USER_DATA_GS_22_BASE_IDX                                                          0
4301 #define mmSPI_SHADER_USER_DATA_GS_23                                                                   0x1a43
4302 #define mmSPI_SHADER_USER_DATA_GS_23_BASE_IDX                                                          0
4303 #define mmSPI_SHADER_USER_DATA_GS_24                                                                   0x1a44
4304 #define mmSPI_SHADER_USER_DATA_GS_24_BASE_IDX                                                          0
4305 #define mmSPI_SHADER_USER_DATA_GS_25                                                                   0x1a45
4306 #define mmSPI_SHADER_USER_DATA_GS_25_BASE_IDX                                                          0
4307 #define mmSPI_SHADER_USER_DATA_GS_26                                                                   0x1a46
4308 #define mmSPI_SHADER_USER_DATA_GS_26_BASE_IDX                                                          0
4309 #define mmSPI_SHADER_USER_DATA_GS_27                                                                   0x1a47
4310 #define mmSPI_SHADER_USER_DATA_GS_27_BASE_IDX                                                          0
4311 #define mmSPI_SHADER_USER_DATA_GS_28                                                                   0x1a48
4312 #define mmSPI_SHADER_USER_DATA_GS_28_BASE_IDX                                                          0
4313 #define mmSPI_SHADER_USER_DATA_GS_29                                                                   0x1a49
4314 #define mmSPI_SHADER_USER_DATA_GS_29_BASE_IDX                                                          0
4315 #define mmSPI_SHADER_USER_DATA_GS_30                                                                   0x1a4a
4316 #define mmSPI_SHADER_USER_DATA_GS_30_BASE_IDX                                                          0
4317 #define mmSPI_SHADER_USER_DATA_GS_31                                                                   0x1a4b
4318 #define mmSPI_SHADER_USER_DATA_GS_31_BASE_IDX                                                          0
4319 #define mmSPI_SHADER_REQ_CTRL_ESGS                                                                     0x1a50
4320 #define mmSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX                                                            0
4321 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS                                                           0x1a51
4322 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_ESGS_BASE_IDX                                                  0
4323 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0                                                             0x1a52
4324 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_0_BASE_IDX                                                    0
4325 #define mmSPI_SHADER_USER_ACCUM_ESGS_0                                                                 0x1a52
4326 #define mmSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX                                                        0
4327 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1                                                             0x1a53
4328 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_1_BASE_IDX                                                    0
4329 #define mmSPI_SHADER_USER_ACCUM_ESGS_1                                                                 0x1a53
4330 #define mmSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX                                                        0
4331 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2                                                             0x1a54
4332 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_2_BASE_IDX                                                    0
4333 #define mmSPI_SHADER_USER_ACCUM_ESGS_2                                                                 0x1a54
4334 #define mmSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX                                                        0
4335 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3                                                             0x1a55
4336 #define mmSPI_SHADER_PREF_PRI_ACCUM_ESGS_3_BASE_IDX                                                    0
4337 #define mmSPI_SHADER_USER_ACCUM_ESGS_3                                                                 0x1a55
4338 #define mmSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX                                                        0
4339 #define mmSPI_SHADER_PGM_RSRC2_ES_GS                                                                   0x1a5c
4340 #define mmSPI_SHADER_PGM_RSRC2_ES_GS_BASE_IDX                                                          0
4341 #define mmSPI_SHADER_PGM_RSRC3_ES                                                                      0x1a67
4342 #define mmSPI_SHADER_PGM_RSRC3_ES_BASE_IDX                                                             0
4343 #define mmSPI_SHADER_PGM_LO_ES                                                                         0x1a68
4344 #define mmSPI_SHADER_PGM_LO_ES_BASE_IDX                                                                0
4345 #define mmSPI_SHADER_PGM_HI_ES                                                                         0x1a69
4346 #define mmSPI_SHADER_PGM_HI_ES_BASE_IDX                                                                0
4347 #define mmSPI_SHADER_PGM_RSRC1_ES                                                                      0x1a6a
4348 #define mmSPI_SHADER_PGM_RSRC1_ES_BASE_IDX                                                             0
4349 #define mmSPI_SHADER_PGM_RSRC2_ES                                                                      0x1a6b
4350 #define mmSPI_SHADER_PGM_RSRC2_ES_BASE_IDX                                                             0
4351 #define mmSPI_SHADER_USER_DATA_ES_0                                                                    0x1a6c
4352 #define mmSPI_SHADER_USER_DATA_ES_0_BASE_IDX                                                           0
4353 #define mmSPI_SHADER_USER_DATA_ES_1                                                                    0x1a6d
4354 #define mmSPI_SHADER_USER_DATA_ES_1_BASE_IDX                                                           0
4355 #define mmSPI_SHADER_USER_DATA_ES_2                                                                    0x1a6e
4356 #define mmSPI_SHADER_USER_DATA_ES_2_BASE_IDX                                                           0
4357 #define mmSPI_SHADER_USER_DATA_ES_3                                                                    0x1a6f
4358 #define mmSPI_SHADER_USER_DATA_ES_3_BASE_IDX                                                           0
4359 #define mmSPI_SHADER_USER_DATA_ES_4                                                                    0x1a70
4360 #define mmSPI_SHADER_USER_DATA_ES_4_BASE_IDX                                                           0
4361 #define mmSPI_SHADER_USER_DATA_ES_5                                                                    0x1a71
4362 #define mmSPI_SHADER_USER_DATA_ES_5_BASE_IDX                                                           0
4363 #define mmSPI_SHADER_USER_DATA_ES_6                                                                    0x1a72
4364 #define mmSPI_SHADER_USER_DATA_ES_6_BASE_IDX                                                           0
4365 #define mmSPI_SHADER_USER_DATA_ES_7                                                                    0x1a73
4366 #define mmSPI_SHADER_USER_DATA_ES_7_BASE_IDX                                                           0
4367 #define mmSPI_SHADER_USER_DATA_ES_8                                                                    0x1a74
4368 #define mmSPI_SHADER_USER_DATA_ES_8_BASE_IDX                                                           0
4369 #define mmSPI_SHADER_USER_DATA_ES_9                                                                    0x1a75
4370 #define mmSPI_SHADER_USER_DATA_ES_9_BASE_IDX                                                           0
4371 #define mmSPI_SHADER_USER_DATA_ES_10                                                                   0x1a76
4372 #define mmSPI_SHADER_USER_DATA_ES_10_BASE_IDX                                                          0
4373 #define mmSPI_SHADER_USER_DATA_ES_11                                                                   0x1a77
4374 #define mmSPI_SHADER_USER_DATA_ES_11_BASE_IDX                                                          0
4375 #define mmSPI_SHADER_USER_DATA_ES_12                                                                   0x1a78
4376 #define mmSPI_SHADER_USER_DATA_ES_12_BASE_IDX                                                          0
4377 #define mmSPI_SHADER_USER_DATA_ES_13                                                                   0x1a79
4378 #define mmSPI_SHADER_USER_DATA_ES_13_BASE_IDX                                                          0
4379 #define mmSPI_SHADER_USER_DATA_ES_14                                                                   0x1a7a
4380 #define mmSPI_SHADER_USER_DATA_ES_14_BASE_IDX                                                          0
4381 #define mmSPI_SHADER_USER_DATA_ES_15                                                                   0x1a7b
4382 #define mmSPI_SHADER_USER_DATA_ES_15_BASE_IDX                                                          0
4383 #define mmSPI_SHADER_PGM_RSRC2_LS_ES                                                                   0x1a9d
4384 #define mmSPI_SHADER_PGM_RSRC2_LS_ES_BASE_IDX                                                          0
4385 #define mmSPI_SHADER_PGM_CHKSUM_HS                                                                     0x1aa0
4386 #define mmSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX                                                            0
4387 #define mmSPI_SHADER_PGM_RSRC4_HS                                                                      0x1aa1
4388 #define mmSPI_SHADER_PGM_RSRC4_HS_BASE_IDX                                                             0
4389 #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS                                                              0x1aa2
4390 #define mmSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX                                                     0
4391 #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS                                                              0x1aa3
4392 #define mmSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX                                                     0
4393 #define mmSPI_SHADER_PGM_LO_LS_HS                                                                      0x1aa4
4394 #define mmSPI_SHADER_PGM_LO_LS_HS_BASE_IDX                                                             0
4395 #define mmSPI_SHADER_PGM_HI_LS_HS                                                                      0x1aa5
4396 #define mmSPI_SHADER_PGM_HI_LS_HS_BASE_IDX                                                             0
4397 #define mmSPI_SHADER_PGM_RSRC3_HS                                                                      0x1aa7
4398 #define mmSPI_SHADER_PGM_RSRC3_HS_BASE_IDX                                                             0
4399 #define mmSPI_SHADER_PGM_LO_HS                                                                         0x1aa8
4400 #define mmSPI_SHADER_PGM_LO_HS_BASE_IDX                                                                0
4401 #define mmSPI_SHADER_PGM_HI_HS                                                                         0x1aa9
4402 #define mmSPI_SHADER_PGM_HI_HS_BASE_IDX                                                                0
4403 #define mmSPI_SHADER_PGM_RSRC1_HS                                                                      0x1aaa
4404 #define mmSPI_SHADER_PGM_RSRC1_HS_BASE_IDX                                                             0
4405 #define mmSPI_SHADER_PGM_RSRC2_HS                                                                      0x1aab
4406 #define mmSPI_SHADER_PGM_RSRC2_HS_BASE_IDX                                                             0
4407 #define mmSPI_SHADER_USER_DATA_HS_0                                                                    0x1aac
4408 #define mmSPI_SHADER_USER_DATA_HS_0_BASE_IDX                                                           0
4409 #define mmSPI_SHADER_USER_DATA_HS_1                                                                    0x1aad
4410 #define mmSPI_SHADER_USER_DATA_HS_1_BASE_IDX                                                           0
4411 #define mmSPI_SHADER_USER_DATA_HS_2                                                                    0x1aae
4412 #define mmSPI_SHADER_USER_DATA_HS_2_BASE_IDX                                                           0
4413 #define mmSPI_SHADER_USER_DATA_HS_3                                                                    0x1aaf
4414 #define mmSPI_SHADER_USER_DATA_HS_3_BASE_IDX                                                           0
4415 #define mmSPI_SHADER_USER_DATA_HS_4                                                                    0x1ab0
4416 #define mmSPI_SHADER_USER_DATA_HS_4_BASE_IDX                                                           0
4417 #define mmSPI_SHADER_USER_DATA_HS_5                                                                    0x1ab1
4418 #define mmSPI_SHADER_USER_DATA_HS_5_BASE_IDX                                                           0
4419 #define mmSPI_SHADER_USER_DATA_HS_6                                                                    0x1ab2
4420 #define mmSPI_SHADER_USER_DATA_HS_6_BASE_IDX                                                           0
4421 #define mmSPI_SHADER_USER_DATA_HS_7                                                                    0x1ab3
4422 #define mmSPI_SHADER_USER_DATA_HS_7_BASE_IDX                                                           0
4423 #define mmSPI_SHADER_USER_DATA_HS_8                                                                    0x1ab4
4424 #define mmSPI_SHADER_USER_DATA_HS_8_BASE_IDX                                                           0
4425 #define mmSPI_SHADER_USER_DATA_HS_9                                                                    0x1ab5
4426 #define mmSPI_SHADER_USER_DATA_HS_9_BASE_IDX                                                           0
4427 #define mmSPI_SHADER_USER_DATA_HS_10                                                                   0x1ab6
4428 #define mmSPI_SHADER_USER_DATA_HS_10_BASE_IDX                                                          0
4429 #define mmSPI_SHADER_USER_DATA_HS_11                                                                   0x1ab7
4430 #define mmSPI_SHADER_USER_DATA_HS_11_BASE_IDX                                                          0
4431 #define mmSPI_SHADER_USER_DATA_HS_12                                                                   0x1ab8
4432 #define mmSPI_SHADER_USER_DATA_HS_12_BASE_IDX                                                          0
4433 #define mmSPI_SHADER_USER_DATA_HS_13                                                                   0x1ab9
4434 #define mmSPI_SHADER_USER_DATA_HS_13_BASE_IDX                                                          0
4435 #define mmSPI_SHADER_USER_DATA_HS_14                                                                   0x1aba
4436 #define mmSPI_SHADER_USER_DATA_HS_14_BASE_IDX                                                          0
4437 #define mmSPI_SHADER_USER_DATA_HS_15                                                                   0x1abb
4438 #define mmSPI_SHADER_USER_DATA_HS_15_BASE_IDX                                                          0
4439 #define mmSPI_SHADER_USER_DATA_HS_16                                                                   0x1abc
4440 #define mmSPI_SHADER_USER_DATA_HS_16_BASE_IDX                                                          0
4441 #define mmSPI_SHADER_USER_DATA_HS_17                                                                   0x1abd
4442 #define mmSPI_SHADER_USER_DATA_HS_17_BASE_IDX                                                          0
4443 #define mmSPI_SHADER_USER_DATA_HS_18                                                                   0x1abe
4444 #define mmSPI_SHADER_USER_DATA_HS_18_BASE_IDX                                                          0
4445 #define mmSPI_SHADER_USER_DATA_HS_19                                                                   0x1abf
4446 #define mmSPI_SHADER_USER_DATA_HS_19_BASE_IDX                                                          0
4447 #define mmSPI_SHADER_USER_DATA_HS_20                                                                   0x1ac0
4448 #define mmSPI_SHADER_USER_DATA_HS_20_BASE_IDX                                                          0
4449 #define mmSPI_SHADER_USER_DATA_HS_21                                                                   0x1ac1
4450 #define mmSPI_SHADER_USER_DATA_HS_21_BASE_IDX                                                          0
4451 #define mmSPI_SHADER_USER_DATA_HS_22                                                                   0x1ac2
4452 #define mmSPI_SHADER_USER_DATA_HS_22_BASE_IDX                                                          0
4453 #define mmSPI_SHADER_USER_DATA_HS_23                                                                   0x1ac3
4454 #define mmSPI_SHADER_USER_DATA_HS_23_BASE_IDX                                                          0
4455 #define mmSPI_SHADER_USER_DATA_HS_24                                                                   0x1ac4
4456 #define mmSPI_SHADER_USER_DATA_HS_24_BASE_IDX                                                          0
4457 #define mmSPI_SHADER_USER_DATA_HS_25                                                                   0x1ac5
4458 #define mmSPI_SHADER_USER_DATA_HS_25_BASE_IDX                                                          0
4459 #define mmSPI_SHADER_USER_DATA_HS_26                                                                   0x1ac6
4460 #define mmSPI_SHADER_USER_DATA_HS_26_BASE_IDX                                                          0
4461 #define mmSPI_SHADER_USER_DATA_HS_27                                                                   0x1ac7
4462 #define mmSPI_SHADER_USER_DATA_HS_27_BASE_IDX                                                          0
4463 #define mmSPI_SHADER_USER_DATA_HS_28                                                                   0x1ac8
4464 #define mmSPI_SHADER_USER_DATA_HS_28_BASE_IDX                                                          0
4465 #define mmSPI_SHADER_USER_DATA_HS_29                                                                   0x1ac9
4466 #define mmSPI_SHADER_USER_DATA_HS_29_BASE_IDX                                                          0
4467 #define mmSPI_SHADER_USER_DATA_HS_30                                                                   0x1aca
4468 #define mmSPI_SHADER_USER_DATA_HS_30_BASE_IDX                                                          0
4469 #define mmSPI_SHADER_USER_DATA_HS_31                                                                   0x1acb
4470 #define mmSPI_SHADER_USER_DATA_HS_31_BASE_IDX                                                          0
4471 #define mmSPI_SHADER_REQ_CTRL_LSHS                                                                     0x1ad0
4472 #define mmSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX                                                            0
4473 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS                                                           0x1ad1
4474 #define mmSPI_SHADER_PREF_PRI_CNTR_CTRL_LSHS_BASE_IDX                                                  0
4475 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0                                                             0x1ad2
4476 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_0_BASE_IDX                                                    0
4477 #define mmSPI_SHADER_USER_ACCUM_LSHS_0                                                                 0x1ad2
4478 #define mmSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX                                                        0
4479 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1                                                             0x1ad3
4480 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_1_BASE_IDX                                                    0
4481 #define mmSPI_SHADER_USER_ACCUM_LSHS_1                                                                 0x1ad3
4482 #define mmSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX                                                        0
4483 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2                                                             0x1ad4
4484 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_2_BASE_IDX                                                    0
4485 #define mmSPI_SHADER_USER_ACCUM_LSHS_2                                                                 0x1ad4
4486 #define mmSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX                                                        0
4487 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3                                                             0x1ad5
4488 #define mmSPI_SHADER_PREF_PRI_ACCUM_LSHS_3_BASE_IDX                                                    0
4489 #define mmSPI_SHADER_USER_ACCUM_LSHS_3                                                                 0x1ad5
4490 #define mmSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX                                                        0
4491 #define mmSPI_SHADER_PGM_RSRC2_LS_HS                                                                   0x1add
4492 #define mmSPI_SHADER_PGM_RSRC2_LS_HS_BASE_IDX                                                          0
4493 #define mmSPI_SHADER_PGM_RSRC3_LS                                                                      0x1ae7
4494 #define mmSPI_SHADER_PGM_RSRC3_LS_BASE_IDX                                                             0
4495 #define mmSPI_SHADER_PGM_LO_LS                                                                         0x1ae8
4496 #define mmSPI_SHADER_PGM_LO_LS_BASE_IDX                                                                0
4497 #define mmSPI_SHADER_PGM_HI_LS                                                                         0x1ae9
4498 #define mmSPI_SHADER_PGM_HI_LS_BASE_IDX                                                                0
4499 #define mmSPI_SHADER_PGM_RSRC1_LS                                                                      0x1aea
4500 #define mmSPI_SHADER_PGM_RSRC1_LS_BASE_IDX                                                             0
4501 #define mmSPI_SHADER_PGM_RSRC2_LS                                                                      0x1aeb
4502 #define mmSPI_SHADER_PGM_RSRC2_LS_BASE_IDX                                                             0
4503 #define mmSPI_SHADER_USER_DATA_LS_0                                                                    0x1aec
4504 #define mmSPI_SHADER_USER_DATA_LS_0_BASE_IDX                                                           0
4505 #define mmSPI_SHADER_USER_DATA_LS_1                                                                    0x1aed
4506 #define mmSPI_SHADER_USER_DATA_LS_1_BASE_IDX                                                           0
4507 #define mmSPI_SHADER_USER_DATA_LS_2                                                                    0x1aee
4508 #define mmSPI_SHADER_USER_DATA_LS_2_BASE_IDX                                                           0
4509 #define mmSPI_SHADER_USER_DATA_LS_3                                                                    0x1aef
4510 #define mmSPI_SHADER_USER_DATA_LS_3_BASE_IDX                                                           0
4511 #define mmSPI_SHADER_USER_DATA_LS_4                                                                    0x1af0
4512 #define mmSPI_SHADER_USER_DATA_LS_4_BASE_IDX                                                           0
4513 #define mmSPI_SHADER_USER_DATA_LS_5                                                                    0x1af1
4514 #define mmSPI_SHADER_USER_DATA_LS_5_BASE_IDX                                                           0
4515 #define mmSPI_SHADER_USER_DATA_LS_6                                                                    0x1af2
4516 #define mmSPI_SHADER_USER_DATA_LS_6_BASE_IDX                                                           0
4517 #define mmSPI_SHADER_USER_DATA_LS_7                                                                    0x1af3
4518 #define mmSPI_SHADER_USER_DATA_LS_7_BASE_IDX                                                           0
4519 #define mmSPI_SHADER_USER_DATA_LS_8                                                                    0x1af4
4520 #define mmSPI_SHADER_USER_DATA_LS_8_BASE_IDX                                                           0
4521 #define mmSPI_SHADER_USER_DATA_LS_9                                                                    0x1af5
4522 #define mmSPI_SHADER_USER_DATA_LS_9_BASE_IDX                                                           0
4523 #define mmSPI_SHADER_USER_DATA_LS_10                                                                   0x1af6
4524 #define mmSPI_SHADER_USER_DATA_LS_10_BASE_IDX                                                          0
4525 #define mmSPI_SHADER_USER_DATA_LS_11                                                                   0x1af7
4526 #define mmSPI_SHADER_USER_DATA_LS_11_BASE_IDX                                                          0
4527 #define mmSPI_SHADER_USER_DATA_LS_12                                                                   0x1af8
4528 #define mmSPI_SHADER_USER_DATA_LS_12_BASE_IDX                                                          0
4529 #define mmSPI_SHADER_USER_DATA_LS_13                                                                   0x1af9
4530 #define mmSPI_SHADER_USER_DATA_LS_13_BASE_IDX                                                          0
4531 #define mmSPI_SHADER_USER_DATA_LS_14                                                                   0x1afa
4532 #define mmSPI_SHADER_USER_DATA_LS_14_BASE_IDX                                                          0
4533 #define mmSPI_SHADER_USER_DATA_LS_15                                                                   0x1afb
4534 #define mmSPI_SHADER_USER_DATA_LS_15_BASE_IDX                                                          0
4535 #define mmCOMPUTE_DISPATCH_INITIATOR                                                                   0x1ba0
4536 #define mmCOMPUTE_DISPATCH_INITIATOR_BASE_IDX                                                          0
4537 #define mmCOMPUTE_DIM_X                                                                                0x1ba1
4538 #define mmCOMPUTE_DIM_X_BASE_IDX                                                                       0
4539 #define mmCOMPUTE_DIM_Y                                                                                0x1ba2
4540 #define mmCOMPUTE_DIM_Y_BASE_IDX                                                                       0
4541 #define mmCOMPUTE_DIM_Z                                                                                0x1ba3
4542 #define mmCOMPUTE_DIM_Z_BASE_IDX                                                                       0
4543 #define mmCOMPUTE_START_X                                                                              0x1ba4
4544 #define mmCOMPUTE_START_X_BASE_IDX                                                                     0
4545 #define mmCOMPUTE_START_Y                                                                              0x1ba5
4546 #define mmCOMPUTE_START_Y_BASE_IDX                                                                     0
4547 #define mmCOMPUTE_START_Z                                                                              0x1ba6
4548 #define mmCOMPUTE_START_Z_BASE_IDX                                                                     0
4549 #define mmCOMPUTE_NUM_THREAD_X                                                                         0x1ba7
4550 #define mmCOMPUTE_NUM_THREAD_X_BASE_IDX                                                                0
4551 #define mmCOMPUTE_NUM_THREAD_Y                                                                         0x1ba8
4552 #define mmCOMPUTE_NUM_THREAD_Y_BASE_IDX                                                                0
4553 #define mmCOMPUTE_NUM_THREAD_Z                                                                         0x1ba9
4554 #define mmCOMPUTE_NUM_THREAD_Z_BASE_IDX                                                                0
4555 #define mmCOMPUTE_PIPELINESTAT_ENABLE                                                                  0x1baa
4556 #define mmCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX                                                         0
4557 #define mmCOMPUTE_PERFCOUNT_ENABLE                                                                     0x1bab
4558 #define mmCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX                                                            0
4559 #define mmCOMPUTE_PGM_LO                                                                               0x1bac
4560 #define mmCOMPUTE_PGM_LO_BASE_IDX                                                                      0
4561 #define mmCOMPUTE_PGM_HI                                                                               0x1bad
4562 #define mmCOMPUTE_PGM_HI_BASE_IDX                                                                      0
4563 #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO                                                                 0x1bae
4564 #define mmCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX                                                        0
4565 #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI                                                                 0x1baf
4566 #define mmCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX                                                        0
4567 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO                                                             0x1bb0
4568 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX                                                    0
4569 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI                                                             0x1bb1
4570 #define mmCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX                                                    0
4571 #define mmCOMPUTE_PGM_RSRC1                                                                            0x1bb2
4572 #define mmCOMPUTE_PGM_RSRC1_BASE_IDX                                                                   0
4573 #define mmCOMPUTE_PGM_RSRC2                                                                            0x1bb3
4574 #define mmCOMPUTE_PGM_RSRC2_BASE_IDX                                                                   0
4575 #define mmCOMPUTE_VMID                                                                                 0x1bb4
4576 #define mmCOMPUTE_VMID_BASE_IDX                                                                        0
4577 #define mmCOMPUTE_RESOURCE_LIMITS                                                                      0x1bb5
4578 #define mmCOMPUTE_RESOURCE_LIMITS_BASE_IDX                                                             0
4579 #define mmCOMPUTE_DESTINATION_EN_SE0                                                                   0x1bb6
4580 #define mmCOMPUTE_DESTINATION_EN_SE0_BASE_IDX                                                          0
4581 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0                                                               0x1bb6
4582 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX                                                      0
4583 #define mmCOMPUTE_DESTINATION_EN_SE1                                                                   0x1bb7
4584 #define mmCOMPUTE_DESTINATION_EN_SE1_BASE_IDX                                                          0
4585 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1                                                               0x1bb7
4586 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX                                                      0
4587 #define mmCOMPUTE_TMPRING_SIZE                                                                         0x1bb8
4588 #define mmCOMPUTE_TMPRING_SIZE_BASE_IDX                                                                0
4589 #define mmCOMPUTE_DESTINATION_EN_SE2                                                                   0x1bb9
4590 #define mmCOMPUTE_DESTINATION_EN_SE2_BASE_IDX                                                          0
4591 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2                                                               0x1bb9
4592 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX                                                      0
4593 #define mmCOMPUTE_DESTINATION_EN_SE3                                                                   0x1bba
4594 #define mmCOMPUTE_DESTINATION_EN_SE3_BASE_IDX                                                          0
4595 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3                                                               0x1bba
4596 #define mmCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX                                                      0
4597 #define mmCOMPUTE_RESTART_X                                                                            0x1bbb
4598 #define mmCOMPUTE_RESTART_X_BASE_IDX                                                                   0
4599 #define mmCOMPUTE_RESTART_Y                                                                            0x1bbc
4600 #define mmCOMPUTE_RESTART_Y_BASE_IDX                                                                   0
4601 #define mmCOMPUTE_RESTART_Z                                                                            0x1bbd
4602 #define mmCOMPUTE_RESTART_Z_BASE_IDX                                                                   0
4603 #define mmCOMPUTE_THREAD_TRACE_ENABLE                                                                  0x1bbe
4604 #define mmCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX                                                         0
4605 #define mmCOMPUTE_MISC_RESERVED                                                                        0x1bbf
4606 #define mmCOMPUTE_MISC_RESERVED_BASE_IDX                                                               0
4607 #define mmCOMPUTE_DISPATCH_ID                                                                          0x1bc0
4608 #define mmCOMPUTE_DISPATCH_ID_BASE_IDX                                                                 0
4609 #define mmCOMPUTE_THREADGROUP_ID                                                                       0x1bc1
4610 #define mmCOMPUTE_THREADGROUP_ID_BASE_IDX                                                              0
4611 #define mmCOMPUTE_REQ_CTRL                                                                             0x1bc2
4612 #define mmCOMPUTE_REQ_CTRL_BASE_IDX                                                                    0
4613 #define mmCOMPUTE_PREF_PRI_ACCUM_0                                                                     0x1bc4
4614 #define mmCOMPUTE_PREF_PRI_ACCUM_0_BASE_IDX                                                            0
4615 #define mmCOMPUTE_USER_ACCUM_0                                                                         0x1bc4
4616 #define mmCOMPUTE_USER_ACCUM_0_BASE_IDX                                                                0
4617 #define mmCOMPUTE_PREF_PRI_ACCUM_1                                                                     0x1bc5
4618 #define mmCOMPUTE_PREF_PRI_ACCUM_1_BASE_IDX                                                            0
4619 #define mmCOMPUTE_USER_ACCUM_1                                                                         0x1bc5
4620 #define mmCOMPUTE_USER_ACCUM_1_BASE_IDX                                                                0
4621 #define mmCOMPUTE_PREF_PRI_ACCUM_2                                                                     0x1bc6
4622 #define mmCOMPUTE_PREF_PRI_ACCUM_2_BASE_IDX                                                            0
4623 #define mmCOMPUTE_USER_ACCUM_2                                                                         0x1bc6
4624 #define mmCOMPUTE_USER_ACCUM_2_BASE_IDX                                                                0
4625 #define mmCOMPUTE_PREF_PRI_ACCUM_3                                                                     0x1bc7
4626 #define mmCOMPUTE_PREF_PRI_ACCUM_3_BASE_IDX                                                            0
4627 #define mmCOMPUTE_USER_ACCUM_3                                                                         0x1bc7
4628 #define mmCOMPUTE_USER_ACCUM_3_BASE_IDX                                                                0
4629 #define mmCOMPUTE_PGM_RSRC3                                                                            0x1bc8
4630 #define mmCOMPUTE_PGM_RSRC3_BASE_IDX                                                                   0
4631 #define mmCOMPUTE_DDID_INDEX                                                                           0x1bc9
4632 #define mmCOMPUTE_DDID_INDEX_BASE_IDX                                                                  0
4633 #define mmCOMPUTE_SHADER_CHKSUM                                                                        0x1bca
4634 #define mmCOMPUTE_SHADER_CHKSUM_BASE_IDX                                                               0
4635 #define mmCOMPUTE_RELAUNCH                                                                             0x1bcb
4636 #define mmCOMPUTE_RELAUNCH_BASE_IDX                                                                    0
4637 #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO                                                                 0x1bcc
4638 #define mmCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX                                                        0
4639 #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI                                                                 0x1bcd
4640 #define mmCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX                                                        0
4641 #define mmCOMPUTE_RELAUNCH2                                                                            0x1bce
4642 #define mmCOMPUTE_RELAUNCH2_BASE_IDX                                                                   0
4643 #define mmCOMPUTE_USER_DATA_0                                                                          0x1be0
4644 #define mmCOMPUTE_USER_DATA_0_BASE_IDX                                                                 0
4645 #define mmCOMPUTE_USER_DATA_1                                                                          0x1be1
4646 #define mmCOMPUTE_USER_DATA_1_BASE_IDX                                                                 0
4647 #define mmCOMPUTE_USER_DATA_2                                                                          0x1be2
4648 #define mmCOMPUTE_USER_DATA_2_BASE_IDX                                                                 0
4649 #define mmCOMPUTE_USER_DATA_3                                                                          0x1be3
4650 #define mmCOMPUTE_USER_DATA_3_BASE_IDX                                                                 0
4651 #define mmCOMPUTE_USER_DATA_4                                                                          0x1be4
4652 #define mmCOMPUTE_USER_DATA_4_BASE_IDX                                                                 0
4653 #define mmCOMPUTE_USER_DATA_5                                                                          0x1be5
4654 #define mmCOMPUTE_USER_DATA_5_BASE_IDX                                                                 0
4655 #define mmCOMPUTE_USER_DATA_6                                                                          0x1be6
4656 #define mmCOMPUTE_USER_DATA_6_BASE_IDX                                                                 0
4657 #define mmCOMPUTE_USER_DATA_7                                                                          0x1be7
4658 #define mmCOMPUTE_USER_DATA_7_BASE_IDX                                                                 0
4659 #define mmCOMPUTE_USER_DATA_8                                                                          0x1be8
4660 #define mmCOMPUTE_USER_DATA_8_BASE_IDX                                                                 0
4661 #define mmCOMPUTE_USER_DATA_9                                                                          0x1be9
4662 #define mmCOMPUTE_USER_DATA_9_BASE_IDX                                                                 0
4663 #define mmCOMPUTE_USER_DATA_10                                                                         0x1bea
4664 #define mmCOMPUTE_USER_DATA_10_BASE_IDX                                                                0
4665 #define mmCOMPUTE_USER_DATA_11                                                                         0x1beb
4666 #define mmCOMPUTE_USER_DATA_11_BASE_IDX                                                                0
4667 #define mmCOMPUTE_USER_DATA_12                                                                         0x1bec
4668 #define mmCOMPUTE_USER_DATA_12_BASE_IDX                                                                0
4669 #define mmCOMPUTE_USER_DATA_13                                                                         0x1bed
4670 #define mmCOMPUTE_USER_DATA_13_BASE_IDX                                                                0
4671 #define mmCOMPUTE_USER_DATA_14                                                                         0x1bee
4672 #define mmCOMPUTE_USER_DATA_14_BASE_IDX                                                                0
4673 #define mmCOMPUTE_USER_DATA_15                                                                         0x1bef
4674 #define mmCOMPUTE_USER_DATA_15_BASE_IDX                                                                0
4675 #define mmCOMPUTE_DISPATCH_TUNNEL                                                                      0x1c1d
4676 #define mmCOMPUTE_DISPATCH_TUNNEL_BASE_IDX                                                             0
4677 #define mmCOMPUTE_DISPATCH_END                                                                         0x1c1e
4678 #define mmCOMPUTE_DISPATCH_END_BASE_IDX                                                                0
4679 #define mmCOMPUTE_NOWHERE                                                                              0x1c1f
4680 #define mmCOMPUTE_NOWHERE_BASE_IDX                                                                     0
4681 
4682 
4683 // addressBlock: gc_cppdec
4684 // base address: 0xc080
4685 #define mmCP_EOPQ_WAIT_TIME                                                                            0x1dd5
4686 #define mmCP_EOPQ_WAIT_TIME_BASE_IDX                                                                   0
4687 #define mmCP_CPC_MGCG_SYNC_CNTL                                                                        0x1dd6
4688 #define mmCP_CPC_MGCG_SYNC_CNTL_BASE_IDX                                                               0
4689 #define mmCPC_INT_INFO                                                                                 0x1dd7
4690 #define mmCPC_INT_INFO_BASE_IDX                                                                        0
4691 #define mmCP_VIRT_STATUS                                                                               0x1dd8
4692 #define mmCP_VIRT_STATUS_BASE_IDX                                                                      0
4693 #define mmCPC_INT_ADDR                                                                                 0x1dd9
4694 #define mmCPC_INT_ADDR_BASE_IDX                                                                        0
4695 #define mmCPC_INT_PASID                                                                                0x1dda
4696 #define mmCPC_INT_PASID_BASE_IDX                                                                       0
4697 #define mmCP_GFX_ERROR                                                                                 0x1ddb
4698 #define mmCP_GFX_ERROR_BASE_IDX                                                                        0
4699 #define mmCPG_UTCL1_CNTL                                                                               0x1ddc
4700 #define mmCPG_UTCL1_CNTL_BASE_IDX                                                                      0
4701 #define mmCPC_UTCL1_CNTL                                                                               0x1ddd
4702 #define mmCPC_UTCL1_CNTL_BASE_IDX                                                                      0
4703 #define mmCPF_UTCL1_CNTL                                                                               0x1dde
4704 #define mmCPF_UTCL1_CNTL_BASE_IDX                                                                      0
4705 #define mmCP_AQL_SMM_STATUS                                                                            0x1ddf
4706 #define mmCP_AQL_SMM_STATUS_BASE_IDX                                                                   0
4707 #define mmCP_RB0_BASE                                                                                  0x1de0
4708 #define mmCP_RB0_BASE_BASE_IDX                                                                         0
4709 #define mmCP_RB_BASE                                                                                   0x1de0
4710 #define mmCP_RB_BASE_BASE_IDX                                                                          0
4711 #define mmCP_RB0_CNTL                                                                                  0x1de1
4712 #define mmCP_RB0_CNTL_BASE_IDX                                                                         0
4713 #define mmCP_RB_CNTL                                                                                   0x1de1
4714 #define mmCP_RB_CNTL_BASE_IDX                                                                          0
4715 #define mmCP_RB_RPTR_WR                                                                                0x1de2
4716 #define mmCP_RB_RPTR_WR_BASE_IDX                                                                       0
4717 #define mmCP_RB0_RPTR_ADDR                                                                             0x1de3
4718 #define mmCP_RB0_RPTR_ADDR_BASE_IDX                                                                    0
4719 #define mmCP_RB_RPTR_ADDR                                                                              0x1de3
4720 #define mmCP_RB_RPTR_ADDR_BASE_IDX                                                                     0
4721 #define mmCP_RB0_RPTR_ADDR_HI                                                                          0x1de4
4722 #define mmCP_RB0_RPTR_ADDR_HI_BASE_IDX                                                                 0
4723 #define mmCP_RB_RPTR_ADDR_HI                                                                           0x1de4
4724 #define mmCP_RB_RPTR_ADDR_HI_BASE_IDX                                                                  0
4725 #define mmCP_RB0_BUFSZ_MASK                                                                            0x1de5
4726 #define mmCP_RB0_BUFSZ_MASK_BASE_IDX                                                                   0
4727 #define mmCP_RB_BUFSZ_MASK                                                                             0x1de5
4728 #define mmCP_RB_BUFSZ_MASK_BASE_IDX                                                                    0
4729 #define mmGC_PRIV_MODE                                                                                 0x1de8
4730 #define mmGC_PRIV_MODE_BASE_IDX                                                                        0
4731 #define mmCP_INT_CNTL                                                                                  0x1de9
4732 #define mmCP_INT_CNTL_BASE_IDX                                                                         0
4733 #define mmCP_INT_STATUS                                                                                0x1dea
4734 #define mmCP_INT_STATUS_BASE_IDX                                                                       0
4735 #define mmCP_DEVICE_ID                                                                                 0x1deb
4736 #define mmCP_DEVICE_ID_BASE_IDX                                                                        0
4737 #define mmCP_ME0_PIPE_PRIORITY_CNTS                                                                    0x1dec
4738 #define mmCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4739 #define mmCP_RING_PRIORITY_CNTS                                                                        0x1dec
4740 #define mmCP_RING_PRIORITY_CNTS_BASE_IDX                                                               0
4741 #define mmCP_ME0_PIPE0_PRIORITY                                                                        0x1ded
4742 #define mmCP_ME0_PIPE0_PRIORITY_BASE_IDX                                                               0
4743 #define mmCP_RING0_PRIORITY                                                                            0x1ded
4744 #define mmCP_RING0_PRIORITY_BASE_IDX                                                                   0
4745 #define mmCP_ME0_PIPE1_PRIORITY                                                                        0x1dee
4746 #define mmCP_ME0_PIPE1_PRIORITY_BASE_IDX                                                               0
4747 #define mmCP_RING1_PRIORITY                                                                            0x1dee
4748 #define mmCP_RING1_PRIORITY_BASE_IDX                                                                   0
4749 #define mmCP_ME0_PIPE2_PRIORITY                                                                        0x1def
4750 #define mmCP_ME0_PIPE2_PRIORITY_BASE_IDX                                                               0
4751 #define mmCP_RING2_PRIORITY                                                                            0x1def
4752 #define mmCP_RING2_PRIORITY_BASE_IDX                                                                   0
4753 #define mmCP_FATAL_ERROR                                                                               0x1df0
4754 #define mmCP_FATAL_ERROR_BASE_IDX                                                                      0
4755 #define mmCP_RB_VMID                                                                                   0x1df1
4756 #define mmCP_RB_VMID_BASE_IDX                                                                          0
4757 #define mmCP_ME0_PIPE0_VMID                                                                            0x1df2
4758 #define mmCP_ME0_PIPE0_VMID_BASE_IDX                                                                   0
4759 #define mmCP_ME0_PIPE1_VMID                                                                            0x1df3
4760 #define mmCP_ME0_PIPE1_VMID_BASE_IDX                                                                   0
4761 #define mmCP_RB0_WPTR                                                                                  0x1df4
4762 #define mmCP_RB0_WPTR_BASE_IDX                                                                         0
4763 #define mmCP_RB_WPTR                                                                                   0x1df4
4764 #define mmCP_RB_WPTR_BASE_IDX                                                                          0
4765 #define mmCP_RB0_WPTR_HI                                                                               0x1df5
4766 #define mmCP_RB0_WPTR_HI_BASE_IDX                                                                      0
4767 #define mmCP_RB_WPTR_HI                                                                                0x1df5
4768 #define mmCP_RB_WPTR_HI_BASE_IDX                                                                       0
4769 #define mmCP_RB1_WPTR                                                                                  0x1df6
4770 #define mmCP_RB1_WPTR_BASE_IDX                                                                         0
4771 #define mmCP_RB1_WPTR_HI                                                                               0x1df7
4772 #define mmCP_RB1_WPTR_HI_BASE_IDX                                                                      0
4773 #define mmCP_RB2_WPTR                                                                                  0x1df8
4774 #define mmCP_RB2_WPTR_BASE_IDX                                                                         0
4775 #define mmCP_PROCESS_QUANTUM                                                                           0x1df9
4776 #define mmCP_PROCESS_QUANTUM_BASE_IDX                                                                  0
4777 #define mmCP_RB_DOORBELL_RANGE_LOWER                                                                   0x1dfa
4778 #define mmCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX                                                          0
4779 #define mmCP_RB_DOORBELL_RANGE_UPPER                                                                   0x1dfb
4780 #define mmCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX                                                          0
4781 #define mmCP_MEC_DOORBELL_RANGE_LOWER                                                                  0x1dfc
4782 #define mmCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX                                                         0
4783 #define mmCP_MEC_DOORBELL_RANGE_UPPER                                                                  0x1dfd
4784 #define mmCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX                                                         0
4785 #define mmCPG_UTCL1_ERROR                                                                              0x1dfe
4786 #define mmCPG_UTCL1_ERROR_BASE_IDX                                                                     0
4787 #define mmCPC_UTCL1_ERROR                                                                              0x1dff
4788 #define mmCPC_UTCL1_ERROR_BASE_IDX                                                                     0
4789 #define mmCP_RB1_BASE                                                                                  0x1e00
4790 #define mmCP_RB1_BASE_BASE_IDX                                                                         0
4791 #define mmCP_RB1_CNTL                                                                                  0x1e01
4792 #define mmCP_RB1_CNTL_BASE_IDX                                                                         0
4793 #define mmCP_RB1_RPTR_ADDR                                                                             0x1e02
4794 #define mmCP_RB1_RPTR_ADDR_BASE_IDX                                                                    0
4795 #define mmCP_RB1_RPTR_ADDR_HI                                                                          0x1e03
4796 #define mmCP_RB1_RPTR_ADDR_HI_BASE_IDX                                                                 0
4797 #define mmCP_RB1_BUFSZ_MASK                                                                            0x1e04
4798 #define mmCP_RB1_BUFSZ_MASK_BASE_IDX                                                                   0
4799 #define mmCP_RB2_BASE                                                                                  0x1e05
4800 #define mmCP_RB2_BASE_BASE_IDX                                                                         0
4801 #define mmCP_RB2_CNTL                                                                                  0x1e06
4802 #define mmCP_RB2_CNTL_BASE_IDX                                                                         0
4803 #define mmCP_RB2_RPTR_ADDR                                                                             0x1e07
4804 #define mmCP_RB2_RPTR_ADDR_BASE_IDX                                                                    0
4805 #define mmCP_RB2_RPTR_ADDR_HI                                                                          0x1e08
4806 #define mmCP_RB2_RPTR_ADDR_HI_BASE_IDX                                                                 0
4807 #define mmCP_INT_CNTL_RING0                                                                            0x1e0a
4808 #define mmCP_INT_CNTL_RING0_BASE_IDX                                                                   0
4809 #define mmCP_INT_CNTL_RING1                                                                            0x1e0b
4810 #define mmCP_INT_CNTL_RING1_BASE_IDX                                                                   0
4811 #define mmCP_INT_CNTL_RING2                                                                            0x1e0c
4812 #define mmCP_INT_CNTL_RING2_BASE_IDX                                                                   0
4813 #define mmCP_INT_STATUS_RING0                                                                          0x1e0d
4814 #define mmCP_INT_STATUS_RING0_BASE_IDX                                                                 0
4815 #define mmCP_INT_STATUS_RING1                                                                          0x1e0e
4816 #define mmCP_INT_STATUS_RING1_BASE_IDX                                                                 0
4817 #define mmCP_INT_STATUS_RING2                                                                          0x1e0f
4818 #define mmCP_INT_STATUS_RING2_BASE_IDX                                                                 0
4819 #define mmCP_PWR_CNTL                                                                                  0x1e18
4820 #define mmCP_PWR_CNTL_BASE_IDX                                                                         0
4821 #define mmCP_MEM_SLP_CNTL                                                                              0x1e19
4822 #define mmCP_MEM_SLP_CNTL_BASE_IDX                                                                     0
4823 #define mmCP_ECC_FIRSTOCCURRENCE                                                                       0x1e1a
4824 #define mmCP_ECC_FIRSTOCCURRENCE_BASE_IDX                                                              0
4825 #define mmCP_ECC_FIRSTOCCURRENCE_RING0                                                                 0x1e1b
4826 #define mmCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX                                                        0
4827 #define mmCP_ECC_FIRSTOCCURRENCE_RING1                                                                 0x1e1c
4828 #define mmCP_ECC_FIRSTOCCURRENCE_RING1_BASE_IDX                                                        0
4829 #define mmCP_ECC_FIRSTOCCURRENCE_RING2                                                                 0x1e1d
4830 #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX                                                        0
4831 #define mmGB_EDC_MODE                                                                                  0x1e1e
4832 #define mmGB_EDC_MODE_BASE_IDX                                                                         0
4833 #define mmCP_DEBUG                                                                                     0x1e1f
4834 #define mmCP_DEBUG_BASE_IDX                                                                            0
4835 #define mmCP_FETCHER_SOURCE                                                                            0x1e22
4836 #define mmCP_FETCHER_SOURCE_BASE_IDX                                                                   0
4837 #define mmCP_PQ_WPTR_POLL_CNTL                                                                         0x1e23
4838 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX                                                                0
4839 #define mmCP_PQ_WPTR_POLL_CNTL1                                                                        0x1e24
4840 #define mmCP_PQ_WPTR_POLL_CNTL1_BASE_IDX                                                               0
4841 #define mmCP_ME1_PIPE0_INT_CNTL                                                                        0x1e25
4842 #define mmCP_ME1_PIPE0_INT_CNTL_BASE_IDX                                                               0
4843 #define mmCP_ME1_PIPE1_INT_CNTL                                                                        0x1e26
4844 #define mmCP_ME1_PIPE1_INT_CNTL_BASE_IDX                                                               0
4845 #define mmCP_ME1_PIPE2_INT_CNTL                                                                        0x1e27
4846 #define mmCP_ME1_PIPE2_INT_CNTL_BASE_IDX                                                               0
4847 #define mmCP_ME1_PIPE3_INT_CNTL                                                                        0x1e28
4848 #define mmCP_ME1_PIPE3_INT_CNTL_BASE_IDX                                                               0
4849 #define mmCP_ME2_PIPE0_INT_CNTL                                                                        0x1e29
4850 #define mmCP_ME2_PIPE0_INT_CNTL_BASE_IDX                                                               0
4851 #define mmCP_ME2_PIPE1_INT_CNTL                                                                        0x1e2a
4852 #define mmCP_ME2_PIPE1_INT_CNTL_BASE_IDX                                                               0
4853 #define mmCP_ME2_PIPE2_INT_CNTL                                                                        0x1e2b
4854 #define mmCP_ME2_PIPE2_INT_CNTL_BASE_IDX                                                               0
4855 #define mmCP_ME2_PIPE3_INT_CNTL                                                                        0x1e2c
4856 #define mmCP_ME2_PIPE3_INT_CNTL_BASE_IDX                                                               0
4857 #define mmCP_ME1_PIPE0_INT_STATUS                                                                      0x1e2d
4858 #define mmCP_ME1_PIPE0_INT_STATUS_BASE_IDX                                                             0
4859 #define mmCP_ME1_PIPE1_INT_STATUS                                                                      0x1e2e
4860 #define mmCP_ME1_PIPE1_INT_STATUS_BASE_IDX                                                             0
4861 #define mmCP_ME1_PIPE2_INT_STATUS                                                                      0x1e2f
4862 #define mmCP_ME1_PIPE2_INT_STATUS_BASE_IDX                                                             0
4863 #define mmCP_ME1_PIPE3_INT_STATUS                                                                      0x1e30
4864 #define mmCP_ME1_PIPE3_INT_STATUS_BASE_IDX                                                             0
4865 #define mmCP_ME2_PIPE0_INT_STATUS                                                                      0x1e31
4866 #define mmCP_ME2_PIPE0_INT_STATUS_BASE_IDX                                                             0
4867 #define mmCP_ME2_PIPE1_INT_STATUS                                                                      0x1e32
4868 #define mmCP_ME2_PIPE1_INT_STATUS_BASE_IDX                                                             0
4869 #define mmCP_ME2_PIPE2_INT_STATUS                                                                      0x1e33
4870 #define mmCP_ME2_PIPE2_INT_STATUS_BASE_IDX                                                             0
4871 #define mmCP_ME2_PIPE3_INT_STATUS                                                                      0x1e34
4872 #define mmCP_ME2_PIPE3_INT_STATUS_BASE_IDX                                                             0
4873 #define mmCP_ME1_INT_STAT_DEBUG                                                                        0x1e35
4874 #define mmCP_ME1_INT_STAT_DEBUG_BASE_IDX                                                               0
4875 #define mmCP_ME2_INT_STAT_DEBUG                                                                        0x1e36
4876 #define mmCP_ME2_INT_STAT_DEBUG_BASE_IDX                                                               0
4877 #define mmCP_GFX_QUEUE_INDEX                                                                           0x1e37
4878 #define mmCP_GFX_QUEUE_INDEX_BASE_IDX                                                                  0
4879 #define mmCC_GC_EDC_CONFIG                                                                             0x1e38
4880 #define mmCC_GC_EDC_CONFIG_BASE_IDX                                                                    0
4881 #define mmCP_ME1_PIPE_PRIORITY_CNTS                                                                    0x1e39
4882 #define mmCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4883 #define mmCP_ME1_PIPE0_PRIORITY                                                                        0x1e3a
4884 #define mmCP_ME1_PIPE0_PRIORITY_BASE_IDX                                                               0
4885 #define mmCP_ME1_PIPE1_PRIORITY                                                                        0x1e3b
4886 #define mmCP_ME1_PIPE1_PRIORITY_BASE_IDX                                                               0
4887 #define mmCP_ME1_PIPE2_PRIORITY                                                                        0x1e3c
4888 #define mmCP_ME1_PIPE2_PRIORITY_BASE_IDX                                                               0
4889 #define mmCP_ME1_PIPE3_PRIORITY                                                                        0x1e3d
4890 #define mmCP_ME1_PIPE3_PRIORITY_BASE_IDX                                                               0
4891 #define mmCP_ME2_PIPE_PRIORITY_CNTS                                                                    0x1e3e
4892 #define mmCP_ME2_PIPE_PRIORITY_CNTS_BASE_IDX                                                           0
4893 #define mmCP_ME2_PIPE0_PRIORITY                                                                        0x1e3f
4894 #define mmCP_ME2_PIPE0_PRIORITY_BASE_IDX                                                               0
4895 #define mmCP_ME2_PIPE1_PRIORITY                                                                        0x1e40
4896 #define mmCP_ME2_PIPE1_PRIORITY_BASE_IDX                                                               0
4897 #define mmCP_ME2_PIPE2_PRIORITY                                                                        0x1e41
4898 #define mmCP_ME2_PIPE2_PRIORITY_BASE_IDX                                                               0
4899 #define mmCP_ME2_PIPE3_PRIORITY                                                                        0x1e42
4900 #define mmCP_ME2_PIPE3_PRIORITY_BASE_IDX                                                               0
4901 #define mmCP_CE_PRGRM_CNTR_START                                                                       0x1e43
4902 #define mmCP_CE_PRGRM_CNTR_START_BASE_IDX                                                              0
4903 #define mmCP_PFP_PRGRM_CNTR_START                                                                      0x1e44
4904 #define mmCP_PFP_PRGRM_CNTR_START_BASE_IDX                                                             0
4905 #define mmCP_ME_PRGRM_CNTR_START                                                                       0x1e45
4906 #define mmCP_ME_PRGRM_CNTR_START_BASE_IDX                                                              0
4907 #define mmCP_MEC1_PRGRM_CNTR_START                                                                     0x1e46
4908 #define mmCP_MEC1_PRGRM_CNTR_START_BASE_IDX                                                            0
4909 #define mmCP_MEC2_PRGRM_CNTR_START                                                                     0x1e47
4910 #define mmCP_MEC2_PRGRM_CNTR_START_BASE_IDX                                                            0
4911 #define mmCP_CE_INTR_ROUTINE_START                                                                     0x1e48
4912 #define mmCP_CE_INTR_ROUTINE_START_BASE_IDX                                                            0
4913 #define mmCP_PFP_INTR_ROUTINE_START                                                                    0x1e49
4914 #define mmCP_PFP_INTR_ROUTINE_START_BASE_IDX                                                           0
4915 #define mmCP_ME_INTR_ROUTINE_START                                                                     0x1e4a
4916 #define mmCP_ME_INTR_ROUTINE_START_BASE_IDX                                                            0
4917 #define mmCP_MEC1_INTR_ROUTINE_START                                                                   0x1e4b
4918 #define mmCP_MEC1_INTR_ROUTINE_START_BASE_IDX                                                          0
4919 #define mmCP_MEC2_INTR_ROUTINE_START                                                                   0x1e4c
4920 #define mmCP_MEC2_INTR_ROUTINE_START_BASE_IDX                                                          0
4921 #define mmCP_CONTEXT_CNTL                                                                              0x1e4d
4922 #define mmCP_CONTEXT_CNTL_BASE_IDX                                                                     0
4923 #define mmCP_MAX_CONTEXT                                                                               0x1e4e
4924 #define mmCP_MAX_CONTEXT_BASE_IDX                                                                      0
4925 #define mmCP_IQ_WAIT_TIME1                                                                             0x1e4f
4926 #define mmCP_IQ_WAIT_TIME1_BASE_IDX                                                                    0
4927 #define mmCP_IQ_WAIT_TIME2                                                                             0x1e50
4928 #define mmCP_IQ_WAIT_TIME2_BASE_IDX                                                                    0
4929 #define mmCP_RB0_BASE_HI                                                                               0x1e51
4930 #define mmCP_RB0_BASE_HI_BASE_IDX                                                                      0
4931 #define mmCP_RB1_BASE_HI                                                                               0x1e52
4932 #define mmCP_RB1_BASE_HI_BASE_IDX                                                                      0
4933 #define mmCP_VMID_RESET                                                                                0x1e53
4934 #define mmCP_VMID_RESET_BASE_IDX                                                                       0
4935 #define mmCPC_INT_CNTL                                                                                 0x1e54
4936 #define mmCPC_INT_CNTL_BASE_IDX                                                                        0
4937 #define mmCPC_INT_STATUS                                                                               0x1e55
4938 #define mmCPC_INT_STATUS_BASE_IDX                                                                      0
4939 #define mmCP_VMID_PREEMPT                                                                              0x1e56
4940 #define mmCP_VMID_PREEMPT_BASE_IDX                                                                     0
4941 #define mmCPC_INT_CNTX_ID                                                                              0x1e57
4942 #define mmCPC_INT_CNTX_ID_BASE_IDX                                                                     0
4943 #define mmCP_PQ_STATUS                                                                                 0x1e58
4944 #define mmCP_PQ_STATUS_BASE_IDX                                                                        0
4945 #define mmCP_CE_CS_PARTITION_INDEX                                                                     0x1e59
4946 #define mmCP_CE_CS_PARTITION_INDEX_BASE_IDX                                                            0
4947 #define mmCP_MEC1_F32_INT_DIS                                                                          0x1e5d
4948 #define mmCP_MEC1_F32_INT_DIS_BASE_IDX                                                                 0
4949 #define mmCP_MEC2_F32_INT_DIS                                                                          0x1e5e
4950 #define mmCP_MEC2_F32_INT_DIS_BASE_IDX                                                                 0
4951 #define mmCP_VMID_STATUS                                                                               0x1e5f
4952 #define mmCP_VMID_STATUS_BASE_IDX                                                                      0
4953 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO                                                            0x1e60
4954 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                   0
4955 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI                                                            0x1e61
4956 #define mmCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                   0
4957 #define mmCPC_SUSPEND_CTX_SAVE_CONTROL                                                                 0x1e62
4958 #define mmCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX                                                        0
4959 #define mmCPC_SUSPEND_CNTL_STACK_OFFSET                                                                0x1e63
4960 #define mmCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                       0
4961 #define mmCPC_SUSPEND_CNTL_STACK_SIZE                                                                  0x1e64
4962 #define mmCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX                                                         0
4963 #define mmCPC_SUSPEND_WG_STATE_OFFSET                                                                  0x1e65
4964 #define mmCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                         0
4965 #define mmCPC_SUSPEND_CTX_SAVE_SIZE                                                                    0x1e66
4966 #define mmCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX                                                           0
4967 #define mmCPC_OS_PIPES                                                                                 0x1e67
4968 #define mmCPC_OS_PIPES_BASE_IDX                                                                        0
4969 #define mmCP_SUSPEND_RESUME_REQ                                                                        0x1e68
4970 #define mmCP_SUSPEND_RESUME_REQ_BASE_IDX                                                               0
4971 #define mmCP_SUSPEND_CNTL                                                                              0x1e69
4972 #define mmCP_SUSPEND_CNTL_BASE_IDX                                                                     0
4973 #define mmCP_IQ_WAIT_TIME3                                                                             0x1e6a
4974 #define mmCP_IQ_WAIT_TIME3_BASE_IDX                                                                    0
4975 #define mmCPC_DDID_BASE_ADDR_LO                                                                        0x1e6b
4976 #define mmCPC_DDID_BASE_ADDR_LO_BASE_IDX                                                               0
4977 #define mmCP_DDID_BASE_ADDR_LO                                                                         0x1e6b
4978 #define mmCP_DDID_BASE_ADDR_LO_BASE_IDX                                                                0
4979 #define mmCPC_DDID_BASE_ADDR_HI                                                                        0x1e6c
4980 #define mmCPC_DDID_BASE_ADDR_HI_BASE_IDX                                                               0
4981 #define mmCP_DDID_BASE_ADDR_HI                                                                         0x1e6c
4982 #define mmCP_DDID_BASE_ADDR_HI_BASE_IDX                                                                0
4983 #define mmCPC_DDID_CNTL                                                                                0x1e6d
4984 #define mmCPC_DDID_CNTL_BASE_IDX                                                                       0
4985 #define mmCP_DDID_CNTL                                                                                 0x1e6d
4986 #define mmCP_DDID_CNTL_BASE_IDX                                                                        0
4987 #define mmCP_GFX_DDID_INFLIGHT_COUNT                                                                   0x1e6e
4988 #define mmCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
4989 #define mmCP_GFX_DDID_WPTR                                                                             0x1e6f
4990 #define mmCP_GFX_DDID_WPTR_BASE_IDX                                                                    0
4991 #define mmCP_GFX_DDID_RPTR                                                                             0x1e70
4992 #define mmCP_GFX_DDID_RPTR_BASE_IDX                                                                    0
4993 #define mmCP_GFX_DDID_DELTA_RPT_COUNT                                                                  0x1e71
4994 #define mmCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
4995 #define mmCP_GFX_HPD_STATUS0                                                                           0x1e72
4996 #define mmCP_GFX_HPD_STATUS0_BASE_IDX                                                                  0
4997 #define mmCP_GFX_HPD_CONTROL0                                                                          0x1e73
4998 #define mmCP_GFX_HPD_CONTROL0_BASE_IDX                                                                 0
4999 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO                                                               0x1e74
5000 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX                                                      0
5001 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI                                                               0x1e75
5002 #define mmCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX                                                      0
5003 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO                                                               0x1e76
5004 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX                                                      0
5005 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI                                                               0x1e77
5006 #define mmCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX                                                      0
5007 #define mmCP_GFX_INDEX_MUTEX                                                                           0x1e78
5008 #define mmCP_GFX_INDEX_MUTEX_BASE_IDX                                                                  0
5009 #define mmCP_GFX_MQD_BASE_ADDR                                                                         0x1e7e
5010 #define mmCP_GFX_MQD_BASE_ADDR_BASE_IDX                                                                0
5011 #define mmCP_GFX_MQD_BASE_ADDR_HI                                                                      0x1e7f
5012 #define mmCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX                                                             0
5013 #define mmCP_GFX_HQD_ACTIVE                                                                            0x1e80
5014 #define mmCP_GFX_HQD_ACTIVE_BASE_IDX                                                                   0
5015 #define mmCP_GFX_HQD_VMID                                                                              0x1e81
5016 #define mmCP_GFX_HQD_VMID_BASE_IDX                                                                     0
5017 #define mmCP_GFX_HQD_QUEUE_PRIORITY                                                                    0x1e84
5018 #define mmCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX                                                           0
5019 #define mmCP_GFX_HQD_QUANTUM                                                                           0x1e85
5020 #define mmCP_GFX_HQD_QUANTUM_BASE_IDX                                                                  0
5021 #define mmCP_GFX_HQD_BASE                                                                              0x1e86
5022 #define mmCP_GFX_HQD_BASE_BASE_IDX                                                                     0
5023 #define mmCP_GFX_HQD_BASE_HI                                                                           0x1e87
5024 #define mmCP_GFX_HQD_BASE_HI_BASE_IDX                                                                  0
5025 #define mmCP_GFX_HQD_RPTR                                                                              0x1e88
5026 #define mmCP_GFX_HQD_RPTR_BASE_IDX                                                                     0
5027 #define mmCP_GFX_HQD_RPTR_ADDR                                                                         0x1e89
5028 #define mmCP_GFX_HQD_RPTR_ADDR_BASE_IDX                                                                0
5029 #define mmCP_GFX_HQD_RPTR_ADDR_HI                                                                      0x1e8a
5030 #define mmCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX                                                             0
5031 #define mmCP_RB_WPTR_POLL_ADDR_LO                                                                      0x1e8b
5032 #define mmCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX                                                             0
5033 #define mmCP_RB_WPTR_POLL_ADDR_HI                                                                      0x1e8c
5034 #define mmCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX                                                             0
5035 #define mmCP_RB_DOORBELL_CONTROL                                                                       0x1e8d
5036 #define mmCP_RB_DOORBELL_CONTROL_BASE_IDX                                                              0
5037 #define mmCP_GFX_HQD_OFFSET                                                                            0x1e8e
5038 #define mmCP_GFX_HQD_OFFSET_BASE_IDX                                                                   0
5039 #define mmCP_GFX_HQD_CNTL                                                                              0x1e8f
5040 #define mmCP_GFX_HQD_CNTL_BASE_IDX                                                                     0
5041 #define mmCP_GFX_HQD_CSMD_RPTR                                                                         0x1e90
5042 #define mmCP_GFX_HQD_CSMD_RPTR_BASE_IDX                                                                0
5043 #define mmCP_GFX_HQD_WPTR                                                                              0x1e91
5044 #define mmCP_GFX_HQD_WPTR_BASE_IDX                                                                     0
5045 #define mmCP_GFX_HQD_WPTR_HI                                                                           0x1e92
5046 #define mmCP_GFX_HQD_WPTR_HI_BASE_IDX                                                                  0
5047 #define mmCP_GFX_HQD_DEQUEUE_REQUEST                                                                   0x1e93
5048 #define mmCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX                                                          0
5049 #define mmCP_GFX_HQD_MAPPED                                                                            0x1e94
5050 #define mmCP_GFX_HQD_MAPPED_BASE_IDX                                                                   0
5051 #define mmCP_GFX_HQD_QUE_MGR_CONTROL                                                                   0x1e95
5052 #define mmCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX                                                          0
5053 #define mmCP_GFX_HQD_HQ_STATUS0                                                                        0x1e98
5054 #define mmCP_GFX_HQD_HQ_STATUS0_BASE_IDX                                                               0
5055 #define mmCP_GFX_HQD_HQ_CONTROL0                                                                       0x1e99
5056 #define mmCP_GFX_HQD_HQ_CONTROL0_BASE_IDX                                                              0
5057 #define mmCP_GFX_MQD_CONTROL                                                                           0x1e9a
5058 #define mmCP_GFX_MQD_CONTROL_BASE_IDX                                                                  0
5059 #define mmCP_HQD_GFX_CONTROL                                                                           0x1e9f
5060 #define mmCP_HQD_GFX_CONTROL_BASE_IDX                                                                  0
5061 #define mmCP_HQD_GFX_STATUS                                                                            0x1ea0
5062 #define mmCP_HQD_GFX_STATUS_BASE_IDX                                                                   0
5063 #define mmCP_GFX_HQD_CE_RPTR_WR                                                                        0x1ea1
5064 #define mmCP_GFX_HQD_CE_RPTR_WR_BASE_IDX                                                               0
5065 #define mmCP_GFX_HQD_CE_BASE                                                                           0x1ea2
5066 #define mmCP_GFX_HQD_CE_BASE_BASE_IDX                                                                  0
5067 #define mmCP_GFX_HQD_CE_BASE_HI                                                                        0x1ea3
5068 #define mmCP_GFX_HQD_CE_BASE_HI_BASE_IDX                                                               0
5069 #define mmCP_GFX_HQD_CE_RPTR                                                                           0x1ea4
5070 #define mmCP_GFX_HQD_CE_RPTR_BASE_IDX                                                                  0
5071 #define mmCP_GFX_HQD_CE_RPTR_ADDR                                                                      0x1ea5
5072 #define mmCP_GFX_HQD_CE_RPTR_ADDR_BASE_IDX                                                             0
5073 #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI                                                                   0x1ea6
5074 #define mmCP_GFX_HQD_CE_RPTR_ADDR_HI_BASE_IDX                                                          0
5075 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO                                                              0x1ea7
5076 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_LO_BASE_IDX                                                     0
5077 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI                                                              0x1ea8
5078 #define mmCP_GFX_HQD_CE_WPTR_POLL_ADDR_HI_BASE_IDX                                                     0
5079 #define mmCP_GFX_HQD_CE_OFFSET                                                                         0x1ea9
5080 #define mmCP_GFX_HQD_CE_OFFSET_BASE_IDX                                                                0
5081 #define mmCP_GFX_HQD_CE_CNTL                                                                           0x1eaa
5082 #define mmCP_GFX_HQD_CE_CNTL_BASE_IDX                                                                  0
5083 #define mmCP_GFX_HQD_CE_CSMD_RPTR                                                                      0x1eab
5084 #define mmCP_GFX_HQD_CE_CSMD_RPTR_BASE_IDX                                                             0
5085 #define mmCP_GFX_HQD_CE_WPTR                                                                           0x1eac
5086 #define mmCP_GFX_HQD_CE_WPTR_BASE_IDX                                                                  0
5087 #define mmCP_GFX_HQD_CE_WPTR_HI                                                                        0x1ead
5088 #define mmCP_GFX_HQD_CE_WPTR_HI_BASE_IDX                                                               0
5089 #define mmCP_CE_DOORBELL_CONTROL                                                                       0x1eae
5090 #define mmCP_CE_DOORBELL_CONTROL_BASE_IDX                                                              0
5091 #define mmCP_DMA_WATCH0_ADDR_LO                                                                        0x1ec0
5092 #define mmCP_DMA_WATCH0_ADDR_LO_BASE_IDX                                                               0
5093 #define mmCP_DMA_WATCH0_ADDR_HI                                                                        0x1ec1
5094 #define mmCP_DMA_WATCH0_ADDR_HI_BASE_IDX                                                               0
5095 #define mmCP_DMA_WATCH0_MASK                                                                           0x1ec2
5096 #define mmCP_DMA_WATCH0_MASK_BASE_IDX                                                                  0
5097 #define mmCP_DMA_WATCH0_CNTL                                                                           0x1ec3
5098 #define mmCP_DMA_WATCH0_CNTL_BASE_IDX                                                                  0
5099 #define mmCP_DMA_WATCH1_ADDR_LO                                                                        0x1ec4
5100 #define mmCP_DMA_WATCH1_ADDR_LO_BASE_IDX                                                               0
5101 #define mmCP_DMA_WATCH1_ADDR_HI                                                                        0x1ec5
5102 #define mmCP_DMA_WATCH1_ADDR_HI_BASE_IDX                                                               0
5103 #define mmCP_DMA_WATCH1_MASK                                                                           0x1ec6
5104 #define mmCP_DMA_WATCH1_MASK_BASE_IDX                                                                  0
5105 #define mmCP_DMA_WATCH1_CNTL                                                                           0x1ec7
5106 #define mmCP_DMA_WATCH1_CNTL_BASE_IDX                                                                  0
5107 #define mmCP_DMA_WATCH2_ADDR_LO                                                                        0x1ec8
5108 #define mmCP_DMA_WATCH2_ADDR_LO_BASE_IDX                                                               0
5109 #define mmCP_DMA_WATCH2_ADDR_HI                                                                        0x1ec9
5110 #define mmCP_DMA_WATCH2_ADDR_HI_BASE_IDX                                                               0
5111 #define mmCP_DMA_WATCH2_MASK                                                                           0x1eca
5112 #define mmCP_DMA_WATCH2_MASK_BASE_IDX                                                                  0
5113 #define mmCP_DMA_WATCH2_CNTL                                                                           0x1ecb
5114 #define mmCP_DMA_WATCH2_CNTL_BASE_IDX                                                                  0
5115 #define mmCP_DMA_WATCH3_ADDR_LO                                                                        0x1ecc
5116 #define mmCP_DMA_WATCH3_ADDR_LO_BASE_IDX                                                               0
5117 #define mmCP_DMA_WATCH3_ADDR_HI                                                                        0x1ecd
5118 #define mmCP_DMA_WATCH3_ADDR_HI_BASE_IDX                                                               0
5119 #define mmCP_DMA_WATCH3_MASK                                                                           0x1ece
5120 #define mmCP_DMA_WATCH3_MASK_BASE_IDX                                                                  0
5121 #define mmCP_DMA_WATCH3_CNTL                                                                           0x1ecf
5122 #define mmCP_DMA_WATCH3_CNTL_BASE_IDX                                                                  0
5123 #define mmCP_DMA_WATCH_STAT_ADDR_LO                                                                    0x1ed0
5124 #define mmCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX                                                           0
5125 #define mmCP_DMA_WATCH_STAT_ADDR_HI                                                                    0x1ed1
5126 #define mmCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX                                                           0
5127 #define mmCP_DMA_WATCH_STAT                                                                            0x1ed2
5128 #define mmCP_DMA_WATCH_STAT_BASE_IDX                                                                   0
5129 #define mmCP_PFP_JT_STAT                                                                               0x1ed3
5130 #define mmCP_PFP_JT_STAT_BASE_IDX                                                                      0
5131 #define mmCP_CE_JT_STAT                                                                                0x1ed4
5132 #define mmCP_CE_JT_STAT_BASE_IDX                                                                       0
5133 #define mmCP_MEC_JT_STAT                                                                               0x1ed5
5134 #define mmCP_MEC_JT_STAT_BASE_IDX                                                                      0
5135 #define mmCP_RB_DOORBELL_CLEAR                                                                         0x1f28
5136 #define mmCP_RB_DOORBELL_CLEAR_BASE_IDX                                                                0
5137 #define mmCP_RB0_ACTIVE                                                                                0x1f40
5138 #define mmCP_RB0_ACTIVE_BASE_IDX                                                                       0
5139 #define mmCP_RB_ACTIVE                                                                                 0x1f40
5140 #define mmCP_RB_ACTIVE_BASE_IDX                                                                        0
5141 #define mmCP_RB1_ACTIVE                                                                                0x1f41
5142 #define mmCP_RB1_ACTIVE_BASE_IDX                                                                       0
5143 #define mmCP_RB_STATUS                                                                                 0x1f43
5144 #define mmCP_RB_STATUS_BASE_IDX                                                                        0
5145 #define mmCPG_RCIU_CAM_INDEX                                                                           0x1f44
5146 #define mmCPG_RCIU_CAM_INDEX_BASE_IDX                                                                  0
5147 #define mmCPG_RCIU_CAM_DATA                                                                            0x1f45
5148 #define mmCPG_RCIU_CAM_DATA_BASE_IDX                                                                   0
5149 #define mmCPG_RCIU_CAM_DATA_PHASE0                                                                     0x1f45
5150 #define mmCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX                                                            0
5151 #define mmCPG_RCIU_CAM_DATA_PHASE1                                                                     0x1f45
5152 #define mmCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX                                                            0
5153 #define mmCPG_RCIU_CAM_DATA_PHASE2                                                                     0x1f45
5154 #define mmCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX                                                            0
5155 #define mmCPF_GCR_CNTL                                                                                 0x1f53
5156 #define mmCPF_GCR_CNTL_BASE_IDX                                                                        0
5157 #define mmCPG_UTCL1_STATUS                                                                             0x1f54
5158 #define mmCPG_UTCL1_STATUS_BASE_IDX                                                                    0
5159 #define mmCPC_UTCL1_STATUS                                                                             0x1f55
5160 #define mmCPC_UTCL1_STATUS_BASE_IDX                                                                    0
5161 #define mmCPF_UTCL1_STATUS                                                                             0x1f56
5162 #define mmCPF_UTCL1_STATUS_BASE_IDX                                                                    0
5163 #define mmCP_SD_CNTL                                                                                   0x1f57
5164 #define mmCP_SD_CNTL_BASE_IDX                                                                          0
5165 #define mmCP_SOFT_RESET_CNTL                                                                           0x1f59
5166 #define mmCP_SOFT_RESET_CNTL_BASE_IDX                                                                  0
5167 #define mmCP_CPC_GFX_CNTL                                                                              0x1f5a
5168 #define mmCP_CPC_GFX_CNTL_BASE_IDX                                                                     0
5169 
5170 
5171 // addressBlock: gc_spipdec
5172 // base address: 0xc700
5173 #define mmSPI_ARB_PRIORITY                                                                             0x1f60
5174 #define mmSPI_ARB_PRIORITY_BASE_IDX                                                                    0
5175 #define mmSPI_ARB_CYCLES_0                                                                             0x1f61
5176 #define mmSPI_ARB_CYCLES_0_BASE_IDX                                                                    0
5177 #define mmSPI_ARB_CYCLES_1                                                                             0x1f62
5178 #define mmSPI_ARB_CYCLES_1_BASE_IDX                                                                    0
5179 #define mmSPI_WCL_PIPE_PERCENT_GFX                                                                     0x1f67
5180 #define mmSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX                                                            0
5181 #define mmSPI_WCL_PIPE_PERCENT_HP3D                                                                    0x1f68
5182 #define mmSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX                                                           0
5183 #define mmSPI_WCL_PIPE_PERCENT_CS0                                                                     0x1f69
5184 #define mmSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX                                                            0
5185 #define mmSPI_WCL_PIPE_PERCENT_CS1                                                                     0x1f6a
5186 #define mmSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX                                                            0
5187 #define mmSPI_WCL_PIPE_PERCENT_CS2                                                                     0x1f6b
5188 #define mmSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX                                                            0
5189 #define mmSPI_WCL_PIPE_PERCENT_CS3                                                                     0x1f6c
5190 #define mmSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX                                                            0
5191 #define mmSPI_WCL_PIPE_PERCENT_CS4                                                                     0x1f6d
5192 #define mmSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX                                                            0
5193 #define mmSPI_WCL_PIPE_PERCENT_CS5                                                                     0x1f6e
5194 #define mmSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX                                                            0
5195 #define mmSPI_WCL_PIPE_PERCENT_CS6                                                                     0x1f6f
5196 #define mmSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX                                                            0
5197 #define mmSPI_WCL_PIPE_PERCENT_CS7                                                                     0x1f70
5198 #define mmSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX                                                            0
5199 #define mmSPI_GDBG_WAVE_CNTL                                                                           0x1f71
5200 #define mmSPI_GDBG_WAVE_CNTL_BASE_IDX                                                                  0
5201 #define mmSPI_GDBG_TRAP_CONFIG                                                                         0x1f72
5202 #define mmSPI_GDBG_TRAP_CONFIG_BASE_IDX                                                                0
5203 #define mmSPI_GDBG_TRAP_MASK                                                                           0x1f73
5204 #define mmSPI_GDBG_TRAP_MASK_BASE_IDX                                                                  0
5205 #define mmSPI_GDBG_WAVE_CNTL2                                                                          0x1f74
5206 #define mmSPI_GDBG_WAVE_CNTL2_BASE_IDX                                                                 0
5207 #define mmSPI_GDBG_WAVE_CNTL3                                                                          0x1f75
5208 #define mmSPI_GDBG_WAVE_CNTL3_BASE_IDX                                                                 0
5209 #define mmSPI_GDBG_TRAP_DATA0                                                                          0x1f78
5210 #define mmSPI_GDBG_TRAP_DATA0_BASE_IDX                                                                 0
5211 #define mmSPI_GDBG_TRAP_DATA1                                                                          0x1f79
5212 #define mmSPI_GDBG_TRAP_DATA1_BASE_IDX                                                                 0
5213 #define mmSPI_COMPUTE_QUEUE_RESET                                                                      0x1f7b
5214 #define mmSPI_COMPUTE_QUEUE_RESET_BASE_IDX                                                             0
5215 #define mmSPI_RESOURCE_RESERVE_CU_0                                                                    0x1f7c
5216 #define mmSPI_RESOURCE_RESERVE_CU_0_BASE_IDX                                                           0
5217 #define mmSPI_RESOURCE_RESERVE_CU_1                                                                    0x1f7d
5218 #define mmSPI_RESOURCE_RESERVE_CU_1_BASE_IDX                                                           0
5219 #define mmSPI_RESOURCE_RESERVE_CU_2                                                                    0x1f7e
5220 #define mmSPI_RESOURCE_RESERVE_CU_2_BASE_IDX                                                           0
5221 #define mmSPI_RESOURCE_RESERVE_CU_3                                                                    0x1f7f
5222 #define mmSPI_RESOURCE_RESERVE_CU_3_BASE_IDX                                                           0
5223 #define mmSPI_RESOURCE_RESERVE_CU_4                                                                    0x1f80
5224 #define mmSPI_RESOURCE_RESERVE_CU_4_BASE_IDX                                                           0
5225 #define mmSPI_RESOURCE_RESERVE_CU_5                                                                    0x1f81
5226 #define mmSPI_RESOURCE_RESERVE_CU_5_BASE_IDX                                                           0
5227 #define mmSPI_RESOURCE_RESERVE_CU_6                                                                    0x1f82
5228 #define mmSPI_RESOURCE_RESERVE_CU_6_BASE_IDX                                                           0
5229 #define mmSPI_RESOURCE_RESERVE_CU_7                                                                    0x1f83
5230 #define mmSPI_RESOURCE_RESERVE_CU_7_BASE_IDX                                                           0
5231 #define mmSPI_RESOURCE_RESERVE_CU_8                                                                    0x1f84
5232 #define mmSPI_RESOURCE_RESERVE_CU_8_BASE_IDX                                                           0
5233 #define mmSPI_RESOURCE_RESERVE_CU_9                                                                    0x1f85
5234 #define mmSPI_RESOURCE_RESERVE_CU_9_BASE_IDX                                                           0
5235 #define mmSPI_RESOURCE_RESERVE_EN_CU_0                                                                 0x1f86
5236 #define mmSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX                                                        0
5237 #define mmSPI_RESOURCE_RESERVE_EN_CU_1                                                                 0x1f87
5238 #define mmSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX                                                        0
5239 #define mmSPI_RESOURCE_RESERVE_EN_CU_2                                                                 0x1f88
5240 #define mmSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX                                                        0
5241 #define mmSPI_RESOURCE_RESERVE_EN_CU_3                                                                 0x1f89
5242 #define mmSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX                                                        0
5243 #define mmSPI_RESOURCE_RESERVE_EN_CU_4                                                                 0x1f8a
5244 #define mmSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX                                                        0
5245 #define mmSPI_RESOURCE_RESERVE_EN_CU_5                                                                 0x1f8b
5246 #define mmSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX                                                        0
5247 #define mmSPI_RESOURCE_RESERVE_EN_CU_6                                                                 0x1f8c
5248 #define mmSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX                                                        0
5249 #define mmSPI_RESOURCE_RESERVE_EN_CU_7                                                                 0x1f8d
5250 #define mmSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX                                                        0
5251 #define mmSPI_RESOURCE_RESERVE_EN_CU_8                                                                 0x1f8e
5252 #define mmSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX                                                        0
5253 #define mmSPI_RESOURCE_RESERVE_EN_CU_9                                                                 0x1f8f
5254 #define mmSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX                                                        0
5255 #define mmSPI_RESOURCE_RESERVE_CU_10                                                                   0x1f90
5256 #define mmSPI_RESOURCE_RESERVE_CU_10_BASE_IDX                                                          0
5257 #define mmSPI_RESOURCE_RESERVE_CU_11                                                                   0x1f91
5258 #define mmSPI_RESOURCE_RESERVE_CU_11_BASE_IDX                                                          0
5259 #define mmSPI_RESOURCE_RESERVE_EN_CU_10                                                                0x1f92
5260 #define mmSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX                                                       0
5261 #define mmSPI_RESOURCE_RESERVE_EN_CU_11                                                                0x1f93
5262 #define mmSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX                                                       0
5263 #define mmSPI_RESOURCE_RESERVE_CU_12                                                                   0x1f94
5264 #define mmSPI_RESOURCE_RESERVE_CU_12_BASE_IDX                                                          0
5265 #define mmSPI_RESOURCE_RESERVE_CU_13                                                                   0x1f95
5266 #define mmSPI_RESOURCE_RESERVE_CU_13_BASE_IDX                                                          0
5267 #define mmSPI_RESOURCE_RESERVE_CU_14                                                                   0x1f96
5268 #define mmSPI_RESOURCE_RESERVE_CU_14_BASE_IDX                                                          0
5269 #define mmSPI_RESOURCE_RESERVE_CU_15                                                                   0x1f97
5270 #define mmSPI_RESOURCE_RESERVE_CU_15_BASE_IDX                                                          0
5271 #define mmSPI_RESOURCE_RESERVE_EN_CU_12                                                                0x1f98
5272 #define mmSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX                                                       0
5273 #define mmSPI_RESOURCE_RESERVE_EN_CU_13                                                                0x1f99
5274 #define mmSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX                                                       0
5275 #define mmSPI_RESOURCE_RESERVE_EN_CU_14                                                                0x1f9a
5276 #define mmSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX                                                       0
5277 #define mmSPI_RESOURCE_RESERVE_EN_CU_15                                                                0x1f9b
5278 #define mmSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX                                                       0
5279 #define mmSPI_COMPUTE_WF_CTX_SAVE                                                                      0x1f9c
5280 #define mmSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX                                                             0
5281 #define mmSPI_ARB_CNTL_0                                                                               0x1f9d
5282 #define mmSPI_ARB_CNTL_0_BASE_IDX                                                                      0
5283 #define mmSPI_FEATURE_CTRL                                                                             0x1f9e
5284 #define mmSPI_FEATURE_CTRL_BASE_IDX                                                                    0
5285 #define mmSPI_SHADER_RSRC_LIMIT_CTRL                                                                   0x1f9f
5286 #define mmSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX                                                          0
5287 
5288 
5289 // addressBlock: gc_cpphqddec
5290 // base address: 0xc800
5291 #define mmCP_HPD_MES_ROQ_OFFSETS                                                                       0x1fa4
5292 #define mmCP_HPD_MES_ROQ_OFFSETS_BASE_IDX                                                              0
5293 #define mmCP_HPD_ROQ_OFFSETS                                                                           0x1fa4
5294 #define mmCP_HPD_ROQ_OFFSETS_BASE_IDX                                                                  0
5295 #define mmCP_HPD_STATUS0                                                                               0x1fa5
5296 #define mmCP_HPD_STATUS0_BASE_IDX                                                                      0
5297 #define mmCP_HPD_UTCL1_CNTL                                                                            0x1fa6
5298 #define mmCP_HPD_UTCL1_CNTL_BASE_IDX                                                                   0
5299 #define mmCP_HPD_UTCL1_ERROR                                                                           0x1fa7
5300 #define mmCP_HPD_UTCL1_ERROR_BASE_IDX                                                                  0
5301 #define mmCP_HPD_UTCL1_ERROR_ADDR                                                                      0x1fa8
5302 #define mmCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX                                                             0
5303 #define mmCP_MQD_BASE_ADDR                                                                             0x1fa9
5304 #define mmCP_MQD_BASE_ADDR_BASE_IDX                                                                    0
5305 #define mmCP_MQD_BASE_ADDR_HI                                                                          0x1faa
5306 #define mmCP_MQD_BASE_ADDR_HI_BASE_IDX                                                                 0
5307 #define mmCP_HQD_ACTIVE                                                                                0x1fab
5308 #define mmCP_HQD_ACTIVE_BASE_IDX                                                                       0
5309 #define mmCP_HQD_VMID                                                                                  0x1fac
5310 #define mmCP_HQD_VMID_BASE_IDX                                                                         0
5311 #define mmCP_HQD_PERSISTENT_STATE                                                                      0x1fad
5312 #define mmCP_HQD_PERSISTENT_STATE_BASE_IDX                                                             0
5313 #define mmCP_HQD_PIPE_PRIORITY                                                                         0x1fae
5314 #define mmCP_HQD_PIPE_PRIORITY_BASE_IDX                                                                0
5315 #define mmCP_HQD_QUEUE_PRIORITY                                                                        0x1faf
5316 #define mmCP_HQD_QUEUE_PRIORITY_BASE_IDX                                                               0
5317 #define mmCP_HQD_QUANTUM                                                                               0x1fb0
5318 #define mmCP_HQD_QUANTUM_BASE_IDX                                                                      0
5319 #define mmCP_HQD_PQ_BASE                                                                               0x1fb1
5320 #define mmCP_HQD_PQ_BASE_BASE_IDX                                                                      0
5321 #define mmCP_HQD_PQ_BASE_HI                                                                            0x1fb2
5322 #define mmCP_HQD_PQ_BASE_HI_BASE_IDX                                                                   0
5323 #define mmCP_HQD_PQ_RPTR                                                                               0x1fb3
5324 #define mmCP_HQD_PQ_RPTR_BASE_IDX                                                                      0
5325 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR                                                                   0x1fb4
5326 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX                                                          0
5327 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI                                                                0x1fb5
5328 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX                                                       0
5329 #define mmCP_HQD_PQ_WPTR_POLL_ADDR                                                                     0x1fb6
5330 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX                                                            0
5331 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI                                                                  0x1fb7
5332 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX                                                         0
5333 #define mmCP_HQD_PQ_DOORBELL_CONTROL                                                                   0x1fb8
5334 #define mmCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX                                                          0
5335 #define mmCP_HQD_PQ_CONTROL                                                                            0x1fba
5336 #define mmCP_HQD_PQ_CONTROL_BASE_IDX                                                                   0
5337 #define mmCP_HQD_IB_BASE_ADDR                                                                          0x1fbb
5338 #define mmCP_HQD_IB_BASE_ADDR_BASE_IDX                                                                 0
5339 #define mmCP_HQD_IB_BASE_ADDR_HI                                                                       0x1fbc
5340 #define mmCP_HQD_IB_BASE_ADDR_HI_BASE_IDX                                                              0
5341 #define mmCP_HQD_IB_RPTR                                                                               0x1fbd
5342 #define mmCP_HQD_IB_RPTR_BASE_IDX                                                                      0
5343 #define mmCP_HQD_IB_CONTROL                                                                            0x1fbe
5344 #define mmCP_HQD_IB_CONTROL_BASE_IDX                                                                   0
5345 #define mmCP_HQD_IQ_TIMER                                                                              0x1fbf
5346 #define mmCP_HQD_IQ_TIMER_BASE_IDX                                                                     0
5347 #define mmCP_HQD_IQ_RPTR                                                                               0x1fc0
5348 #define mmCP_HQD_IQ_RPTR_BASE_IDX                                                                      0
5349 #define mmCP_HQD_DEQUEUE_REQUEST                                                                       0x1fc1
5350 #define mmCP_HQD_DEQUEUE_REQUEST_BASE_IDX                                                              0
5351 #define mmCP_HQD_DMA_OFFLOAD                                                                           0x1fc2
5352 #define mmCP_HQD_DMA_OFFLOAD_BASE_IDX                                                                  0
5353 #define mmCP_HQD_OFFLOAD                                                                               0x1fc2
5354 #define mmCP_HQD_OFFLOAD_BASE_IDX                                                                      0
5355 #define mmCP_HQD_SEMA_CMD                                                                              0x1fc3
5356 #define mmCP_HQD_SEMA_CMD_BASE_IDX                                                                     0
5357 #define mmCP_HQD_MSG_TYPE                                                                              0x1fc4
5358 #define mmCP_HQD_MSG_TYPE_BASE_IDX                                                                     0
5359 #define mmCP_HQD_ATOMIC0_PREOP_LO                                                                      0x1fc5
5360 #define mmCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX                                                             0
5361 #define mmCP_HQD_ATOMIC0_PREOP_HI                                                                      0x1fc6
5362 #define mmCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX                                                             0
5363 #define mmCP_HQD_ATOMIC1_PREOP_LO                                                                      0x1fc7
5364 #define mmCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX                                                             0
5365 #define mmCP_HQD_ATOMIC1_PREOP_HI                                                                      0x1fc8
5366 #define mmCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX                                                             0
5367 #define mmCP_HQD_HQ_SCHEDULER0                                                                         0x1fc9
5368 #define mmCP_HQD_HQ_SCHEDULER0_BASE_IDX                                                                0
5369 #define mmCP_HQD_HQ_STATUS0                                                                            0x1fc9
5370 #define mmCP_HQD_HQ_STATUS0_BASE_IDX                                                                   0
5371 #define mmCP_HQD_HQ_CONTROL0                                                                           0x1fca
5372 #define mmCP_HQD_HQ_CONTROL0_BASE_IDX                                                                  0
5373 #define mmCP_HQD_HQ_SCHEDULER1                                                                         0x1fca
5374 #define mmCP_HQD_HQ_SCHEDULER1_BASE_IDX                                                                0
5375 #define mmCP_MQD_CONTROL                                                                               0x1fcb
5376 #define mmCP_MQD_CONTROL_BASE_IDX                                                                      0
5377 #define mmCP_HQD_HQ_STATUS1                                                                            0x1fcc
5378 #define mmCP_HQD_HQ_STATUS1_BASE_IDX                                                                   0
5379 #define mmCP_HQD_HQ_CONTROL1                                                                           0x1fcd
5380 #define mmCP_HQD_HQ_CONTROL1_BASE_IDX                                                                  0
5381 #define mmCP_HQD_EOP_BASE_ADDR                                                                         0x1fce
5382 #define mmCP_HQD_EOP_BASE_ADDR_BASE_IDX                                                                0
5383 #define mmCP_HQD_EOP_BASE_ADDR_HI                                                                      0x1fcf
5384 #define mmCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX                                                             0
5385 #define mmCP_HQD_EOP_CONTROL                                                                           0x1fd0
5386 #define mmCP_HQD_EOP_CONTROL_BASE_IDX                                                                  0
5387 #define mmCP_HQD_EOP_RPTR                                                                              0x1fd1
5388 #define mmCP_HQD_EOP_RPTR_BASE_IDX                                                                     0
5389 #define mmCP_HQD_EOP_WPTR                                                                              0x1fd2
5390 #define mmCP_HQD_EOP_WPTR_BASE_IDX                                                                     0
5391 #define mmCP_HQD_EOP_EVENTS                                                                            0x1fd3
5392 #define mmCP_HQD_EOP_EVENTS_BASE_IDX                                                                   0
5393 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO                                                                 0x1fd4
5394 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX                                                        0
5395 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI                                                                 0x1fd5
5396 #define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX                                                        0
5397 #define mmCP_HQD_CTX_SAVE_CONTROL                                                                      0x1fd6
5398 #define mmCP_HQD_CTX_SAVE_CONTROL_BASE_IDX                                                             0
5399 #define mmCP_HQD_CNTL_STACK_OFFSET                                                                     0x1fd7
5400 #define mmCP_HQD_CNTL_STACK_OFFSET_BASE_IDX                                                            0
5401 #define mmCP_HQD_CNTL_STACK_SIZE                                                                       0x1fd8
5402 #define mmCP_HQD_CNTL_STACK_SIZE_BASE_IDX                                                              0
5403 #define mmCP_HQD_WG_STATE_OFFSET                                                                       0x1fd9
5404 #define mmCP_HQD_WG_STATE_OFFSET_BASE_IDX                                                              0
5405 #define mmCP_HQD_CTX_SAVE_SIZE                                                                         0x1fda
5406 #define mmCP_HQD_CTX_SAVE_SIZE_BASE_IDX                                                                0
5407 #define mmCP_HQD_GDS_RESOURCE_STATE                                                                    0x1fdb
5408 #define mmCP_HQD_GDS_RESOURCE_STATE_BASE_IDX                                                           0
5409 #define mmCP_HQD_ERROR                                                                                 0x1fdc
5410 #define mmCP_HQD_ERROR_BASE_IDX                                                                        0
5411 #define mmCP_HQD_EOP_WPTR_MEM                                                                          0x1fdd
5412 #define mmCP_HQD_EOP_WPTR_MEM_BASE_IDX                                                                 0
5413 #define mmCP_HQD_AQL_CONTROL                                                                           0x1fde
5414 #define mmCP_HQD_AQL_CONTROL_BASE_IDX                                                                  0
5415 #define mmCP_HQD_PQ_WPTR_LO                                                                            0x1fdf
5416 #define mmCP_HQD_PQ_WPTR_LO_BASE_IDX                                                                   0
5417 #define mmCP_HQD_PQ_WPTR_HI                                                                            0x1fe0
5418 #define mmCP_HQD_PQ_WPTR_HI_BASE_IDX                                                                   0
5419 #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET                                                             0x1fe1
5420 #define mmCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX                                                    0
5421 #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT                                                             0x1fe2
5422 #define mmCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX                                                    0
5423 #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET                                                               0x1fe3
5424 #define mmCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX                                                      0
5425 #define mmCP_HQD_DDID_RPTR                                                                             0x1fe4
5426 #define mmCP_HQD_DDID_RPTR_BASE_IDX                                                                    0
5427 #define mmCP_HQD_DDID_WPTR                                                                             0x1fe5
5428 #define mmCP_HQD_DDID_WPTR_BASE_IDX                                                                    0
5429 #define mmCP_HQD_DDID_INFLIGHT_COUNT                                                                   0x1fe6
5430 #define mmCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX                                                          0
5431 #define mmCP_HQD_DDID_DELTA_RPT_COUNT                                                                  0x1fe7
5432 #define mmCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX                                                         0
5433 #define mmCP_HQD_DEQUEUE_STATUS                                                                        0x1fe8
5434 #define mmCP_HQD_DEQUEUE_STATUS_BASE_IDX                                                               0
5435 
5436 
5437 // addressBlock: gc_didtdec
5438 // base address: 0xca00
5439 #define mmDIDT_IND_INDEX                                                                               0x2020
5440 #define mmDIDT_IND_INDEX_BASE_IDX                                                                      0
5441 #define mmDIDT_IND_DATA                                                                                0x2021
5442 #define mmDIDT_IND_DATA_BASE_IDX                                                                       0
5443 #define mmDIDT_INDEX_AUTO_INCR_EN                                                                      0x2022
5444 #define mmDIDT_INDEX_AUTO_INCR_EN_BASE_IDX                                                             0
5445 
5446 
5447 // addressBlock: gc_gccacdec
5448 // base address: 0xca10
5449 #define mmGC_CAC_CTRL_1                                                                                0x2024
5450 #define mmGC_CAC_CTRL_1_BASE_IDX                                                                       0
5451 #define mmGC_CAC_CTRL_2                                                                                0x2025
5452 #define mmGC_CAC_CTRL_2_BASE_IDX                                                                       0
5453 #define mmGC_CAC_AGGR_LOWER                                                                            0x2026
5454 #define mmGC_CAC_AGGR_LOWER_BASE_IDX                                                                   0
5455 #define mmGC_CAC_AGGR_UPPER                                                                            0x2027
5456 #define mmGC_CAC_AGGR_UPPER_BASE_IDX                                                                   0
5457 #define mmGC_CAC_SOFT_CTRL                                                                             0x2028
5458 #define mmGC_CAC_SOFT_CTRL_BASE_IDX                                                                    0
5459 #define mmGC_DIDT_CTRL0                                                                                0x2029
5460 #define mmGC_DIDT_CTRL0_BASE_IDX                                                                       0
5461 #define mmGC_DIDT_CTRL1                                                                                0x202a
5462 #define mmGC_DIDT_CTRL1_BASE_IDX                                                                       0
5463 #define mmGC_DIDT_CTRL2                                                                                0x202b
5464 #define mmGC_DIDT_CTRL2_BASE_IDX                                                                       0
5465 #define mmGC_DIDT_WEIGHT                                                                               0x202c
5466 #define mmGC_DIDT_WEIGHT_BASE_IDX                                                                      0
5467 #define mmGC_THROTTLE_CTRL                                                                             0x202d
5468 #define mmGC_THROTTLE_CTRL_BASE_IDX                                                                    0
5469 #define mmGC_EDC_CTRL                                                                                  0x202e
5470 #define mmGC_EDC_CTRL_BASE_IDX                                                                         0
5471 #define mmGC_EDC_THRESHOLD                                                                             0x202f
5472 #define mmGC_EDC_THRESHOLD_BASE_IDX                                                                    0
5473 #define mmGC_EDC_STATUS                                                                                0x2030
5474 #define mmGC_EDC_STATUS_BASE_IDX                                                                       0
5475 #define mmGC_EDC_OVERFLOW                                                                              0x2031
5476 #define mmGC_EDC_OVERFLOW_BASE_IDX                                                                     0
5477 #define mmGC_EDC_ROLLING_POWER_DELTA                                                                   0x2032
5478 #define mmGC_EDC_ROLLING_POWER_DELTA_BASE_IDX                                                          0
5479 #define mmGC_THROTTLE_CTRL1                                                                            0x2033
5480 #define mmGC_THROTTLE_CTRL1_BASE_IDX                                                                   0
5481 #define mmGC_THROTTLE_STATUS                                                                           0x2036
5482 #define mmGC_THROTTLE_STATUS_BASE_IDX                                                                  0
5483 #define mmEDC_PERF_COUNTER                                                                             0x2037
5484 #define mmEDC_PERF_COUNTER_BASE_IDX                                                                    0
5485 #define mmPCC_PERF_COUNTER                                                                             0x2038
5486 #define mmPCC_PERF_COUNTER_BASE_IDX                                                                    0
5487 #define mmPWRBRK_PERF_COUNTER                                                                          0x2039
5488 #define mmPWRBRK_PERF_COUNTER_BASE_IDX                                                                 0
5489 #define mmGC_CAC_IND_INDEX                                                                             0x203c
5490 #define mmGC_CAC_IND_INDEX_BASE_IDX                                                                    0
5491 #define mmGC_CAC_IND_DATA                                                                              0x203d
5492 #define mmGC_CAC_IND_DATA_BASE_IDX                                                                     0
5493 #define mmSE_CAC_IND_INDEX                                                                             0x203e
5494 #define mmSE_CAC_IND_INDEX_BASE_IDX                                                                    0
5495 #define mmSE_CAC_IND_DATA                                                                              0x203f
5496 #define mmSE_CAC_IND_DATA_BASE_IDX                                                                     0
5497 
5498 
5499 // addressBlock: gc_tcpdec
5500 // base address: 0xca80
5501 #define mmTCP_WATCH0_ADDR_H                                                                            0x2040
5502 #define mmTCP_WATCH0_ADDR_H_BASE_IDX                                                                   0
5503 #define mmTCP_WATCH0_ADDR_L                                                                            0x2041
5504 #define mmTCP_WATCH0_ADDR_L_BASE_IDX                                                                   0
5505 #define mmTCP_WATCH0_CNTL                                                                              0x2042
5506 #define mmTCP_WATCH0_CNTL_BASE_IDX                                                                     0
5507 #define mmTCP_WATCH1_ADDR_H                                                                            0x2043
5508 #define mmTCP_WATCH1_ADDR_H_BASE_IDX                                                                   0
5509 #define mmTCP_WATCH1_ADDR_L                                                                            0x2044
5510 #define mmTCP_WATCH1_ADDR_L_BASE_IDX                                                                   0
5511 #define mmTCP_WATCH1_CNTL                                                                              0x2045
5512 #define mmTCP_WATCH1_CNTL_BASE_IDX                                                                     0
5513 #define mmTCP_WATCH2_ADDR_H                                                                            0x2046
5514 #define mmTCP_WATCH2_ADDR_H_BASE_IDX                                                                   0
5515 #define mmTCP_WATCH2_ADDR_L                                                                            0x2047
5516 #define mmTCP_WATCH2_ADDR_L_BASE_IDX                                                                   0
5517 #define mmTCP_WATCH2_CNTL                                                                              0x2048
5518 #define mmTCP_WATCH2_CNTL_BASE_IDX                                                                     0
5519 #define mmTCP_WATCH3_ADDR_H                                                                            0x2049
5520 #define mmTCP_WATCH3_ADDR_H_BASE_IDX                                                                   0
5521 #define mmTCP_WATCH3_ADDR_L                                                                            0x204a
5522 #define mmTCP_WATCH3_ADDR_L_BASE_IDX                                                                   0
5523 #define mmTCP_WATCH3_CNTL                                                                              0x204b
5524 #define mmTCP_WATCH3_CNTL_BASE_IDX                                                                     0
5525 #define mmTCP_CNTL2                                                                                    0x2054
5526 #define mmTCP_CNTL2_BASE_IDX                                                                           0
5527 #define mmTCP_UTCL0_CNTL1                                                                              0x2055
5528 #define mmTCP_UTCL0_CNTL1_BASE_IDX                                                                     0
5529 #define mmTCP_UTCL0_CNTL2                                                                              0x2056
5530 #define mmTCP_UTCL0_CNTL2_BASE_IDX                                                                     0
5531 #define mmTCP_UTCL0_STATUS                                                                             0x2057
5532 #define mmTCP_UTCL0_STATUS_BASE_IDX                                                                    0
5533 #define mmTCP_PERFCOUNTER_FILTER                                                                       0x2059
5534 #define mmTCP_PERFCOUNTER_FILTER_BASE_IDX                                                              0
5535 #define mmTCP_PERFCOUNTER_FILTER_EN                                                                    0x205a
5536 #define mmTCP_PERFCOUNTER_FILTER_EN_BASE_IDX                                                           0
5537 #define mmTCP_PERFCOUNTER_FILTER2                                                                      0x205b
5538 #define mmTCP_PERFCOUNTER_FILTER2_BASE_IDX                                                             0
5539 
5540 
5541 // addressBlock: gc_gdspdec
5542 // base address: 0xcc00
5543 #define mmGDS_VMID0_BASE                                                                               0x20a0
5544 #define mmGDS_VMID0_BASE_BASE_IDX                                                                      0
5545 #define mmGDS_VMID0_SIZE                                                                               0x20a1
5546 #define mmGDS_VMID0_SIZE_BASE_IDX                                                                      0
5547 #define mmGDS_VMID1_BASE                                                                               0x20a2
5548 #define mmGDS_VMID1_BASE_BASE_IDX                                                                      0
5549 #define mmGDS_VMID1_SIZE                                                                               0x20a3
5550 #define mmGDS_VMID1_SIZE_BASE_IDX                                                                      0
5551 #define mmGDS_VMID2_BASE                                                                               0x20a4
5552 #define mmGDS_VMID2_BASE_BASE_IDX                                                                      0
5553 #define mmGDS_VMID2_SIZE                                                                               0x20a5
5554 #define mmGDS_VMID2_SIZE_BASE_IDX                                                                      0
5555 #define mmGDS_VMID3_BASE                                                                               0x20a6
5556 #define mmGDS_VMID3_BASE_BASE_IDX                                                                      0
5557 #define mmGDS_VMID3_SIZE                                                                               0x20a7
5558 #define mmGDS_VMID3_SIZE_BASE_IDX                                                                      0
5559 #define mmGDS_VMID4_BASE                                                                               0x20a8
5560 #define mmGDS_VMID4_BASE_BASE_IDX                                                                      0
5561 #define mmGDS_VMID4_SIZE                                                                               0x20a9
5562 #define mmGDS_VMID4_SIZE_BASE_IDX                                                                      0
5563 #define mmGDS_VMID5_BASE                                                                               0x20aa
5564 #define mmGDS_VMID5_BASE_BASE_IDX                                                                      0
5565 #define mmGDS_VMID5_SIZE                                                                               0x20ab
5566 #define mmGDS_VMID5_SIZE_BASE_IDX                                                                      0
5567 #define mmGDS_VMID6_BASE                                                                               0x20ac
5568 #define mmGDS_VMID6_BASE_BASE_IDX                                                                      0
5569 #define mmGDS_VMID6_SIZE                                                                               0x20ad
5570 #define mmGDS_VMID6_SIZE_BASE_IDX                                                                      0
5571 #define mmGDS_VMID7_BASE                                                                               0x20ae
5572 #define mmGDS_VMID7_BASE_BASE_IDX                                                                      0
5573 #define mmGDS_VMID7_SIZE                                                                               0x20af
5574 #define mmGDS_VMID7_SIZE_BASE_IDX                                                                      0
5575 #define mmGDS_VMID8_BASE                                                                               0x20b0
5576 #define mmGDS_VMID8_BASE_BASE_IDX                                                                      0
5577 #define mmGDS_VMID8_SIZE                                                                               0x20b1
5578 #define mmGDS_VMID8_SIZE_BASE_IDX                                                                      0
5579 #define mmGDS_VMID9_BASE                                                                               0x20b2
5580 #define mmGDS_VMID9_BASE_BASE_IDX                                                                      0
5581 #define mmGDS_VMID9_SIZE                                                                               0x20b3
5582 #define mmGDS_VMID9_SIZE_BASE_IDX                                                                      0
5583 #define mmGDS_VMID10_BASE                                                                              0x20b4
5584 #define mmGDS_VMID10_BASE_BASE_IDX                                                                     0
5585 #define mmGDS_VMID10_SIZE                                                                              0x20b5
5586 #define mmGDS_VMID10_SIZE_BASE_IDX                                                                     0
5587 #define mmGDS_VMID11_BASE                                                                              0x20b6
5588 #define mmGDS_VMID11_BASE_BASE_IDX                                                                     0
5589 #define mmGDS_VMID11_SIZE                                                                              0x20b7
5590 #define mmGDS_VMID11_SIZE_BASE_IDX                                                                     0
5591 #define mmGDS_VMID12_BASE                                                                              0x20b8
5592 #define mmGDS_VMID12_BASE_BASE_IDX                                                                     0
5593 #define mmGDS_VMID12_SIZE                                                                              0x20b9
5594 #define mmGDS_VMID12_SIZE_BASE_IDX                                                                     0
5595 #define mmGDS_VMID13_BASE                                                                              0x20ba
5596 #define mmGDS_VMID13_BASE_BASE_IDX                                                                     0
5597 #define mmGDS_VMID13_SIZE                                                                              0x20bb
5598 #define mmGDS_VMID13_SIZE_BASE_IDX                                                                     0
5599 #define mmGDS_VMID14_BASE                                                                              0x20bc
5600 #define mmGDS_VMID14_BASE_BASE_IDX                                                                     0
5601 #define mmGDS_VMID14_SIZE                                                                              0x20bd
5602 #define mmGDS_VMID14_SIZE_BASE_IDX                                                                     0
5603 #define mmGDS_VMID15_BASE                                                                              0x20be
5604 #define mmGDS_VMID15_BASE_BASE_IDX                                                                     0
5605 #define mmGDS_VMID15_SIZE                                                                              0x20bf
5606 #define mmGDS_VMID15_SIZE_BASE_IDX                                                                     0
5607 #define mmGDS_GWS_VMID0                                                                                0x20c0
5608 #define mmGDS_GWS_VMID0_BASE_IDX                                                                       0
5609 #define mmGDS_GWS_VMID1                                                                                0x20c1
5610 #define mmGDS_GWS_VMID1_BASE_IDX                                                                       0
5611 #define mmGDS_GWS_VMID2                                                                                0x20c2
5612 #define mmGDS_GWS_VMID2_BASE_IDX                                                                       0
5613 #define mmGDS_GWS_VMID3                                                                                0x20c3
5614 #define mmGDS_GWS_VMID3_BASE_IDX                                                                       0
5615 #define mmGDS_GWS_VMID4                                                                                0x20c4
5616 #define mmGDS_GWS_VMID4_BASE_IDX                                                                       0
5617 #define mmGDS_GWS_VMID5                                                                                0x20c5
5618 #define mmGDS_GWS_VMID5_BASE_IDX                                                                       0
5619 #define mmGDS_GWS_VMID6                                                                                0x20c6
5620 #define mmGDS_GWS_VMID6_BASE_IDX                                                                       0
5621 #define mmGDS_GWS_VMID7                                                                                0x20c7
5622 #define mmGDS_GWS_VMID7_BASE_IDX                                                                       0
5623 #define mmGDS_GWS_VMID8                                                                                0x20c8
5624 #define mmGDS_GWS_VMID8_BASE_IDX                                                                       0
5625 #define mmGDS_GWS_VMID9                                                                                0x20c9
5626 #define mmGDS_GWS_VMID9_BASE_IDX                                                                       0
5627 #define mmGDS_GWS_VMID10                                                                               0x20ca
5628 #define mmGDS_GWS_VMID10_BASE_IDX                                                                      0
5629 #define mmGDS_GWS_VMID11                                                                               0x20cb
5630 #define mmGDS_GWS_VMID11_BASE_IDX                                                                      0
5631 #define mmGDS_GWS_VMID12                                                                               0x20cc
5632 #define mmGDS_GWS_VMID12_BASE_IDX                                                                      0
5633 #define mmGDS_GWS_VMID13                                                                               0x20cd
5634 #define mmGDS_GWS_VMID13_BASE_IDX                                                                      0
5635 #define mmGDS_GWS_VMID14                                                                               0x20ce
5636 #define mmGDS_GWS_VMID14_BASE_IDX                                                                      0
5637 #define mmGDS_GWS_VMID15                                                                               0x20cf
5638 #define mmGDS_GWS_VMID15_BASE_IDX                                                                      0
5639 #define mmGDS_OA_VMID0                                                                                 0x20d0
5640 #define mmGDS_OA_VMID0_BASE_IDX                                                                        0
5641 #define mmGDS_OA_VMID1                                                                                 0x20d1
5642 #define mmGDS_OA_VMID1_BASE_IDX                                                                        0
5643 #define mmGDS_OA_VMID2                                                                                 0x20d2
5644 #define mmGDS_OA_VMID2_BASE_IDX                                                                        0
5645 #define mmGDS_OA_VMID3                                                                                 0x20d3
5646 #define mmGDS_OA_VMID3_BASE_IDX                                                                        0
5647 #define mmGDS_OA_VMID4                                                                                 0x20d4
5648 #define mmGDS_OA_VMID4_BASE_IDX                                                                        0
5649 #define mmGDS_OA_VMID5                                                                                 0x20d5
5650 #define mmGDS_OA_VMID5_BASE_IDX                                                                        0
5651 #define mmGDS_OA_VMID6                                                                                 0x20d6
5652 #define mmGDS_OA_VMID6_BASE_IDX                                                                        0
5653 #define mmGDS_OA_VMID7                                                                                 0x20d7
5654 #define mmGDS_OA_VMID7_BASE_IDX                                                                        0
5655 #define mmGDS_OA_VMID8                                                                                 0x20d8
5656 #define mmGDS_OA_VMID8_BASE_IDX                                                                        0
5657 #define mmGDS_OA_VMID9                                                                                 0x20d9
5658 #define mmGDS_OA_VMID9_BASE_IDX                                                                        0
5659 #define mmGDS_OA_VMID10                                                                                0x20da
5660 #define mmGDS_OA_VMID10_BASE_IDX                                                                       0
5661 #define mmGDS_OA_VMID11                                                                                0x20db
5662 #define mmGDS_OA_VMID11_BASE_IDX                                                                       0
5663 #define mmGDS_OA_VMID12                                                                                0x20dc
5664 #define mmGDS_OA_VMID12_BASE_IDX                                                                       0
5665 #define mmGDS_OA_VMID13                                                                                0x20dd
5666 #define mmGDS_OA_VMID13_BASE_IDX                                                                       0
5667 #define mmGDS_OA_VMID14                                                                                0x20de
5668 #define mmGDS_OA_VMID14_BASE_IDX                                                                       0
5669 #define mmGDS_OA_VMID15                                                                                0x20df
5670 #define mmGDS_OA_VMID15_BASE_IDX                                                                       0
5671 #define mmGDS_GWS_RESET0                                                                               0x20e4
5672 #define mmGDS_GWS_RESET0_BASE_IDX                                                                      0
5673 #define mmGDS_GWS_RESET1                                                                               0x20e5
5674 #define mmGDS_GWS_RESET1_BASE_IDX                                                                      0
5675 #define mmGDS_GWS_RESOURCE_RESET                                                                       0x20e6
5676 #define mmGDS_GWS_RESOURCE_RESET_BASE_IDX                                                              0
5677 #define mmGDS_COMPUTE_MAX_WAVE_ID                                                                      0x20e8
5678 #define mmGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX                                                             0
5679 #define mmGDS_OA_RESET_MASK                                                                            0x20e9
5680 #define mmGDS_OA_RESET_MASK_BASE_IDX                                                                   0
5681 #define mmGDS_OA_RESET                                                                                 0x20ea
5682 #define mmGDS_OA_RESET_BASE_IDX                                                                        0
5683 #define mmGDS_ENHANCE2                                                                                 0x20eb
5684 #define mmGDS_ENHANCE2_BASE_IDX                                                                        0
5685 #define mmGDS_OA_CGPG_RESTORE                                                                          0x20ec
5686 #define mmGDS_OA_CGPG_RESTORE_BASE_IDX                                                                 0
5687 #define mmGDS_CS_CTXSW_STATUS                                                                          0x20ed
5688 #define mmGDS_CS_CTXSW_STATUS_BASE_IDX                                                                 0
5689 #define mmGDS_CS_CTXSW_CNT0                                                                            0x20ee
5690 #define mmGDS_CS_CTXSW_CNT0_BASE_IDX                                                                   0
5691 #define mmGDS_CS_CTXSW_CNT1                                                                            0x20ef
5692 #define mmGDS_CS_CTXSW_CNT1_BASE_IDX                                                                   0
5693 #define mmGDS_CS_CTXSW_CNT2                                                                            0x20f0
5694 #define mmGDS_CS_CTXSW_CNT2_BASE_IDX                                                                   0
5695 #define mmGDS_CS_CTXSW_CNT3                                                                            0x20f1
5696 #define mmGDS_CS_CTXSW_CNT3_BASE_IDX                                                                   0
5697 #define mmGDS_GFX_CTXSW_STATUS                                                                         0x20f2
5698 #define mmGDS_GFX_CTXSW_STATUS_BASE_IDX                                                                0
5699 #define mmGDS_VS_CTXSW_CNT0                                                                            0x20f3
5700 #define mmGDS_VS_CTXSW_CNT0_BASE_IDX                                                                   0
5701 #define mmGDS_VS_CTXSW_CNT1                                                                            0x20f4
5702 #define mmGDS_VS_CTXSW_CNT1_BASE_IDX                                                                   0
5703 #define mmGDS_VS_CTXSW_CNT2                                                                            0x20f5
5704 #define mmGDS_VS_CTXSW_CNT2_BASE_IDX                                                                   0
5705 #define mmGDS_VS_CTXSW_CNT3                                                                            0x20f6
5706 #define mmGDS_VS_CTXSW_CNT3_BASE_IDX                                                                   0
5707 #define mmGDS_PS_CTXSW_CNT0                                                                            0x20f7
5708 #define mmGDS_PS_CTXSW_CNT0_BASE_IDX                                                                   0
5709 #define mmGDS_PS_CTXSW_CNT1                                                                            0x20f8
5710 #define mmGDS_PS_CTXSW_CNT1_BASE_IDX                                                                   0
5711 #define mmGDS_PS_CTXSW_CNT2                                                                            0x20f9
5712 #define mmGDS_PS_CTXSW_CNT2_BASE_IDX                                                                   0
5713 #define mmGDS_PS_CTXSW_CNT3                                                                            0x20fa
5714 #define mmGDS_PS_CTXSW_CNT3_BASE_IDX                                                                   0
5715 #define mmGDS_PS_CTXSW_IDX                                                                             0x20fb
5716 #define mmGDS_PS_CTXSW_IDX_BASE_IDX                                                                    0
5717 #define mmGDS_GS_CTXSW_CNT0                                                                            0x2117
5718 #define mmGDS_GS_CTXSW_CNT0_BASE_IDX                                                                   0
5719 #define mmGDS_GS_CTXSW_CNT1                                                                            0x2118
5720 #define mmGDS_GS_CTXSW_CNT1_BASE_IDX                                                                   0
5721 #define mmGDS_GS_CTXSW_CNT2                                                                            0x2119
5722 #define mmGDS_GS_CTXSW_CNT2_BASE_IDX                                                                   0
5723 #define mmGDS_GS_CTXSW_CNT3                                                                            0x211a
5724 #define mmGDS_GS_CTXSW_CNT3_BASE_IDX                                                                   0
5725 
5726 
5727 // addressBlock: gc_gfxdec0
5728 // base address: 0x28000
5729 #define mmDB_RENDER_CONTROL                                                                            0x0000
5730 #define mmDB_RENDER_CONTROL_BASE_IDX                                                                   1
5731 #define mmDB_COUNT_CONTROL                                                                             0x0001
5732 #define mmDB_COUNT_CONTROL_BASE_IDX                                                                    1
5733 #define mmDB_DEPTH_VIEW                                                                                0x0002
5734 #define mmDB_DEPTH_VIEW_BASE_IDX                                                                       1
5735 #define mmDB_RENDER_OVERRIDE                                                                           0x0003
5736 #define mmDB_RENDER_OVERRIDE_BASE_IDX                                                                  1
5737 #define mmDB_RENDER_OVERRIDE2                                                                          0x0004
5738 #define mmDB_RENDER_OVERRIDE2_BASE_IDX                                                                 1
5739 #define mmDB_HTILE_DATA_BASE                                                                           0x0005
5740 #define mmDB_HTILE_DATA_BASE_BASE_IDX                                                                  1
5741 #define mmDB_DEPTH_SIZE_XY                                                                             0x0007
5742 #define mmDB_DEPTH_SIZE_XY_BASE_IDX                                                                    1
5743 #define mmDB_DEPTH_BOUNDS_MIN                                                                          0x0008
5744 #define mmDB_DEPTH_BOUNDS_MIN_BASE_IDX                                                                 1
5745 #define mmDB_DEPTH_BOUNDS_MAX                                                                          0x0009
5746 #define mmDB_DEPTH_BOUNDS_MAX_BASE_IDX                                                                 1
5747 #define mmDB_STENCIL_CLEAR                                                                             0x000a
5748 #define mmDB_STENCIL_CLEAR_BASE_IDX                                                                    1
5749 #define mmDB_DEPTH_CLEAR                                                                               0x000b
5750 #define mmDB_DEPTH_CLEAR_BASE_IDX                                                                      1
5751 #define mmPA_SC_SCREEN_SCISSOR_TL                                                                      0x000c
5752 #define mmPA_SC_SCREEN_SCISSOR_TL_BASE_IDX                                                             1
5753 #define mmPA_SC_SCREEN_SCISSOR_BR                                                                      0x000d
5754 #define mmPA_SC_SCREEN_SCISSOR_BR_BASE_IDX                                                             1
5755 #define mmDB_DFSM_CONTROL                                                                              0x000e
5756 #define mmDB_DFSM_CONTROL_BASE_IDX                                                                     1
5757 #define mmDB_RESERVED_REG_2                                                                            0x000f
5758 #define mmDB_RESERVED_REG_2_BASE_IDX                                                                   1
5759 #define mmDB_Z_INFO                                                                                    0x0010
5760 #define mmDB_Z_INFO_BASE_IDX                                                                           1
5761 #define mmDB_STENCIL_INFO                                                                              0x0011
5762 #define mmDB_STENCIL_INFO_BASE_IDX                                                                     1
5763 #define mmDB_Z_READ_BASE                                                                               0x0012
5764 #define mmDB_Z_READ_BASE_BASE_IDX                                                                      1
5765 #define mmDB_STENCIL_READ_BASE                                                                         0x0013
5766 #define mmDB_STENCIL_READ_BASE_BASE_IDX                                                                1
5767 #define mmDB_Z_WRITE_BASE                                                                              0x0014
5768 #define mmDB_Z_WRITE_BASE_BASE_IDX                                                                     1
5769 #define mmDB_STENCIL_WRITE_BASE                                                                        0x0015
5770 #define mmDB_STENCIL_WRITE_BASE_BASE_IDX                                                               1
5771 #define mmDB_RESERVED_REG_1                                                                            0x0016
5772 #define mmDB_RESERVED_REG_1_BASE_IDX                                                                   1
5773 #define mmDB_RESERVED_REG_3                                                                            0x0017
5774 #define mmDB_RESERVED_REG_3_BASE_IDX                                                                   1
5775 #define mmDB_Z_READ_BASE_HI                                                                            0x001a
5776 #define mmDB_Z_READ_BASE_HI_BASE_IDX                                                                   1
5777 #define mmDB_STENCIL_READ_BASE_HI                                                                      0x001b
5778 #define mmDB_STENCIL_READ_BASE_HI_BASE_IDX                                                             1
5779 #define mmDB_Z_WRITE_BASE_HI                                                                           0x001c
5780 #define mmDB_Z_WRITE_BASE_HI_BASE_IDX                                                                  1
5781 #define mmDB_STENCIL_WRITE_BASE_HI                                                                     0x001d
5782 #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX                                                            1
5783 #define mmDB_HTILE_DATA_BASE_HI                                                                        0x001e
5784 #define mmDB_HTILE_DATA_BASE_HI_BASE_IDX                                                               1
5785 #define mmDB_RMI_L2_CACHE_CONTROL                                                                      0x001f
5786 #define mmDB_RMI_L2_CACHE_CONTROL_BASE_IDX                                                             1
5787 #define mmTA_BC_BASE_ADDR                                                                              0x0020
5788 #define mmTA_BC_BASE_ADDR_BASE_IDX                                                                     1
5789 #define mmTA_BC_BASE_ADDR_HI                                                                           0x0021
5790 #define mmTA_BC_BASE_ADDR_HI_BASE_IDX                                                                  1
5791 #define mmCOHER_DEST_BASE_HI_0                                                                         0x007a
5792 #define mmCOHER_DEST_BASE_HI_0_BASE_IDX                                                                1
5793 #define mmCOHER_DEST_BASE_HI_1                                                                         0x007b
5794 #define mmCOHER_DEST_BASE_HI_1_BASE_IDX                                                                1
5795 #define mmCOHER_DEST_BASE_HI_2                                                                         0x007c
5796 #define mmCOHER_DEST_BASE_HI_2_BASE_IDX                                                                1
5797 #define mmCOHER_DEST_BASE_HI_3                                                                         0x007d
5798 #define mmCOHER_DEST_BASE_HI_3_BASE_IDX                                                                1
5799 #define mmCOHER_DEST_BASE_2                                                                            0x007e
5800 #define mmCOHER_DEST_BASE_2_BASE_IDX                                                                   1
5801 #define mmCOHER_DEST_BASE_3                                                                            0x007f
5802 #define mmCOHER_DEST_BASE_3_BASE_IDX                                                                   1
5803 #define mmPA_SC_WINDOW_OFFSET                                                                          0x0080
5804 #define mmPA_SC_WINDOW_OFFSET_BASE_IDX                                                                 1
5805 #define mmPA_SC_WINDOW_SCISSOR_TL                                                                      0x0081
5806 #define mmPA_SC_WINDOW_SCISSOR_TL_BASE_IDX                                                             1
5807 #define mmPA_SC_WINDOW_SCISSOR_BR                                                                      0x0082
5808 #define mmPA_SC_WINDOW_SCISSOR_BR_BASE_IDX                                                             1
5809 #define mmPA_SC_CLIPRECT_RULE                                                                          0x0083
5810 #define mmPA_SC_CLIPRECT_RULE_BASE_IDX                                                                 1
5811 #define mmPA_SC_CLIPRECT_0_TL                                                                          0x0084
5812 #define mmPA_SC_CLIPRECT_0_TL_BASE_IDX                                                                 1
5813 #define mmPA_SC_CLIPRECT_0_BR                                                                          0x0085
5814 #define mmPA_SC_CLIPRECT_0_BR_BASE_IDX                                                                 1
5815 #define mmPA_SC_CLIPRECT_1_TL                                                                          0x0086
5816 #define mmPA_SC_CLIPRECT_1_TL_BASE_IDX                                                                 1
5817 #define mmPA_SC_CLIPRECT_1_BR                                                                          0x0087
5818 #define mmPA_SC_CLIPRECT_1_BR_BASE_IDX                                                                 1
5819 #define mmPA_SC_CLIPRECT_2_TL                                                                          0x0088
5820 #define mmPA_SC_CLIPRECT_2_TL_BASE_IDX                                                                 1
5821 #define mmPA_SC_CLIPRECT_2_BR                                                                          0x0089
5822 #define mmPA_SC_CLIPRECT_2_BR_BASE_IDX                                                                 1
5823 #define mmPA_SC_CLIPRECT_3_TL                                                                          0x008a
5824 #define mmPA_SC_CLIPRECT_3_TL_BASE_IDX                                                                 1
5825 #define mmPA_SC_CLIPRECT_3_BR                                                                          0x008b
5826 #define mmPA_SC_CLIPRECT_3_BR_BASE_IDX                                                                 1
5827 #define mmPA_SC_EDGERULE                                                                               0x008c
5828 #define mmPA_SC_EDGERULE_BASE_IDX                                                                      1
5829 #define mmPA_SU_HARDWARE_SCREEN_OFFSET                                                                 0x008d
5830 #define mmPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX                                                        1
5831 #define mmCB_TARGET_MASK                                                                               0x008e
5832 #define mmCB_TARGET_MASK_BASE_IDX                                                                      1
5833 #define mmCB_SHADER_MASK                                                                               0x008f
5834 #define mmCB_SHADER_MASK_BASE_IDX                                                                      1
5835 #define mmPA_SC_GENERIC_SCISSOR_TL                                                                     0x0090
5836 #define mmPA_SC_GENERIC_SCISSOR_TL_BASE_IDX                                                            1
5837 #define mmPA_SC_GENERIC_SCISSOR_BR                                                                     0x0091
5838 #define mmPA_SC_GENERIC_SCISSOR_BR_BASE_IDX                                                            1
5839 #define mmCOHER_DEST_BASE_0                                                                            0x0092
5840 #define mmCOHER_DEST_BASE_0_BASE_IDX                                                                   1
5841 #define mmCOHER_DEST_BASE_1                                                                            0x0093
5842 #define mmCOHER_DEST_BASE_1_BASE_IDX                                                                   1
5843 #define mmPA_SC_VPORT_SCISSOR_0_TL                                                                     0x0094
5844 #define mmPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX                                                            1
5845 #define mmPA_SC_VPORT_SCISSOR_0_BR                                                                     0x0095
5846 #define mmPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX                                                            1
5847 #define mmPA_SC_VPORT_SCISSOR_1_TL                                                                     0x0096
5848 #define mmPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX                                                            1
5849 #define mmPA_SC_VPORT_SCISSOR_1_BR                                                                     0x0097
5850 #define mmPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX                                                            1
5851 #define mmPA_SC_VPORT_SCISSOR_2_TL                                                                     0x0098
5852 #define mmPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX                                                            1
5853 #define mmPA_SC_VPORT_SCISSOR_2_BR                                                                     0x0099
5854 #define mmPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX                                                            1
5855 #define mmPA_SC_VPORT_SCISSOR_3_TL                                                                     0x009a
5856 #define mmPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX                                                            1
5857 #define mmPA_SC_VPORT_SCISSOR_3_BR                                                                     0x009b
5858 #define mmPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX                                                            1
5859 #define mmPA_SC_VPORT_SCISSOR_4_TL                                                                     0x009c
5860 #define mmPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX                                                            1
5861 #define mmPA_SC_VPORT_SCISSOR_4_BR                                                                     0x009d
5862 #define mmPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX                                                            1
5863 #define mmPA_SC_VPORT_SCISSOR_5_TL                                                                     0x009e
5864 #define mmPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX                                                            1
5865 #define mmPA_SC_VPORT_SCISSOR_5_BR                                                                     0x009f
5866 #define mmPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX                                                            1
5867 #define mmPA_SC_VPORT_SCISSOR_6_TL                                                                     0x00a0
5868 #define mmPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX                                                            1
5869 #define mmPA_SC_VPORT_SCISSOR_6_BR                                                                     0x00a1
5870 #define mmPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX                                                            1
5871 #define mmPA_SC_VPORT_SCISSOR_7_TL                                                                     0x00a2
5872 #define mmPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX                                                            1
5873 #define mmPA_SC_VPORT_SCISSOR_7_BR                                                                     0x00a3
5874 #define mmPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX                                                            1
5875 #define mmPA_SC_VPORT_SCISSOR_8_TL                                                                     0x00a4
5876 #define mmPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX                                                            1
5877 #define mmPA_SC_VPORT_SCISSOR_8_BR                                                                     0x00a5
5878 #define mmPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX                                                            1
5879 #define mmPA_SC_VPORT_SCISSOR_9_TL                                                                     0x00a6
5880 #define mmPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX                                                            1
5881 #define mmPA_SC_VPORT_SCISSOR_9_BR                                                                     0x00a7
5882 #define mmPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX                                                            1
5883 #define mmPA_SC_VPORT_SCISSOR_10_TL                                                                    0x00a8
5884 #define mmPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX                                                           1
5885 #define mmPA_SC_VPORT_SCISSOR_10_BR                                                                    0x00a9
5886 #define mmPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX                                                           1
5887 #define mmPA_SC_VPORT_SCISSOR_11_TL                                                                    0x00aa
5888 #define mmPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX                                                           1
5889 #define mmPA_SC_VPORT_SCISSOR_11_BR                                                                    0x00ab
5890 #define mmPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX                                                           1
5891 #define mmPA_SC_VPORT_SCISSOR_12_TL                                                                    0x00ac
5892 #define mmPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX                                                           1
5893 #define mmPA_SC_VPORT_SCISSOR_12_BR                                                                    0x00ad
5894 #define mmPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX                                                           1
5895 #define mmPA_SC_VPORT_SCISSOR_13_TL                                                                    0x00ae
5896 #define mmPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX                                                           1
5897 #define mmPA_SC_VPORT_SCISSOR_13_BR                                                                    0x00af
5898 #define mmPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX                                                           1
5899 #define mmPA_SC_VPORT_SCISSOR_14_TL                                                                    0x00b0
5900 #define mmPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX                                                           1
5901 #define mmPA_SC_VPORT_SCISSOR_14_BR                                                                    0x00b1
5902 #define mmPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX                                                           1
5903 #define mmPA_SC_VPORT_SCISSOR_15_TL                                                                    0x00b2
5904 #define mmPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX                                                           1
5905 #define mmPA_SC_VPORT_SCISSOR_15_BR                                                                    0x00b3
5906 #define mmPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX                                                           1
5907 #define mmPA_SC_VPORT_ZMIN_0                                                                           0x00b4
5908 #define mmPA_SC_VPORT_ZMIN_0_BASE_IDX                                                                  1
5909 #define mmPA_SC_VPORT_ZMAX_0                                                                           0x00b5
5910 #define mmPA_SC_VPORT_ZMAX_0_BASE_IDX                                                                  1
5911 #define mmPA_SC_VPORT_ZMIN_1                                                                           0x00b6
5912 #define mmPA_SC_VPORT_ZMIN_1_BASE_IDX                                                                  1
5913 #define mmPA_SC_VPORT_ZMAX_1                                                                           0x00b7
5914 #define mmPA_SC_VPORT_ZMAX_1_BASE_IDX                                                                  1
5915 #define mmPA_SC_VPORT_ZMIN_2                                                                           0x00b8
5916 #define mmPA_SC_VPORT_ZMIN_2_BASE_IDX                                                                  1
5917 #define mmPA_SC_VPORT_ZMAX_2                                                                           0x00b9
5918 #define mmPA_SC_VPORT_ZMAX_2_BASE_IDX                                                                  1
5919 #define mmPA_SC_VPORT_ZMIN_3                                                                           0x00ba
5920 #define mmPA_SC_VPORT_ZMIN_3_BASE_IDX                                                                  1
5921 #define mmPA_SC_VPORT_ZMAX_3                                                                           0x00bb
5922 #define mmPA_SC_VPORT_ZMAX_3_BASE_IDX                                                                  1
5923 #define mmPA_SC_VPORT_ZMIN_4                                                                           0x00bc
5924 #define mmPA_SC_VPORT_ZMIN_4_BASE_IDX                                                                  1
5925 #define mmPA_SC_VPORT_ZMAX_4                                                                           0x00bd
5926 #define mmPA_SC_VPORT_ZMAX_4_BASE_IDX                                                                  1
5927 #define mmPA_SC_VPORT_ZMIN_5                                                                           0x00be
5928 #define mmPA_SC_VPORT_ZMIN_5_BASE_IDX                                                                  1
5929 #define mmPA_SC_VPORT_ZMAX_5                                                                           0x00bf
5930 #define mmPA_SC_VPORT_ZMAX_5_BASE_IDX                                                                  1
5931 #define mmPA_SC_VPORT_ZMIN_6                                                                           0x00c0
5932 #define mmPA_SC_VPORT_ZMIN_6_BASE_IDX                                                                  1
5933 #define mmPA_SC_VPORT_ZMAX_6                                                                           0x00c1
5934 #define mmPA_SC_VPORT_ZMAX_6_BASE_IDX                                                                  1
5935 #define mmPA_SC_VPORT_ZMIN_7                                                                           0x00c2
5936 #define mmPA_SC_VPORT_ZMIN_7_BASE_IDX                                                                  1
5937 #define mmPA_SC_VPORT_ZMAX_7                                                                           0x00c3
5938 #define mmPA_SC_VPORT_ZMAX_7_BASE_IDX                                                                  1
5939 #define mmPA_SC_VPORT_ZMIN_8                                                                           0x00c4
5940 #define mmPA_SC_VPORT_ZMIN_8_BASE_IDX                                                                  1
5941 #define mmPA_SC_VPORT_ZMAX_8                                                                           0x00c5
5942 #define mmPA_SC_VPORT_ZMAX_8_BASE_IDX                                                                  1
5943 #define mmPA_SC_VPORT_ZMIN_9                                                                           0x00c6
5944 #define mmPA_SC_VPORT_ZMIN_9_BASE_IDX                                                                  1
5945 #define mmPA_SC_VPORT_ZMAX_9                                                                           0x00c7
5946 #define mmPA_SC_VPORT_ZMAX_9_BASE_IDX                                                                  1
5947 #define mmPA_SC_VPORT_ZMIN_10                                                                          0x00c8
5948 #define mmPA_SC_VPORT_ZMIN_10_BASE_IDX                                                                 1
5949 #define mmPA_SC_VPORT_ZMAX_10                                                                          0x00c9
5950 #define mmPA_SC_VPORT_ZMAX_10_BASE_IDX                                                                 1
5951 #define mmPA_SC_VPORT_ZMIN_11                                                                          0x00ca
5952 #define mmPA_SC_VPORT_ZMIN_11_BASE_IDX                                                                 1
5953 #define mmPA_SC_VPORT_ZMAX_11                                                                          0x00cb
5954 #define mmPA_SC_VPORT_ZMAX_11_BASE_IDX                                                                 1
5955 #define mmPA_SC_VPORT_ZMIN_12                                                                          0x00cc
5956 #define mmPA_SC_VPORT_ZMIN_12_BASE_IDX                                                                 1
5957 #define mmPA_SC_VPORT_ZMAX_12                                                                          0x00cd
5958 #define mmPA_SC_VPORT_ZMAX_12_BASE_IDX                                                                 1
5959 #define mmPA_SC_VPORT_ZMIN_13                                                                          0x00ce
5960 #define mmPA_SC_VPORT_ZMIN_13_BASE_IDX                                                                 1
5961 #define mmPA_SC_VPORT_ZMAX_13                                                                          0x00cf
5962 #define mmPA_SC_VPORT_ZMAX_13_BASE_IDX                                                                 1
5963 #define mmPA_SC_VPORT_ZMIN_14                                                                          0x00d0
5964 #define mmPA_SC_VPORT_ZMIN_14_BASE_IDX                                                                 1
5965 #define mmPA_SC_VPORT_ZMAX_14                                                                          0x00d1
5966 #define mmPA_SC_VPORT_ZMAX_14_BASE_IDX                                                                 1
5967 #define mmPA_SC_VPORT_ZMIN_15                                                                          0x00d2
5968 #define mmPA_SC_VPORT_ZMIN_15_BASE_IDX                                                                 1
5969 #define mmPA_SC_VPORT_ZMAX_15                                                                          0x00d3
5970 #define mmPA_SC_VPORT_ZMAX_15_BASE_IDX                                                                 1
5971 #define mmPA_SC_RASTER_CONFIG                                                                          0x00d4
5972 #define mmPA_SC_RASTER_CONFIG_BASE_IDX                                                                 1
5973 #define mmPA_SC_RASTER_CONFIG_1                                                                        0x00d5
5974 #define mmPA_SC_RASTER_CONFIG_1_BASE_IDX                                                               1
5975 #define mmPA_SC_SCREEN_EXTENT_CONTROL                                                                  0x00d6
5976 #define mmPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX                                                         1
5977 #define mmPA_SC_TILE_STEERING_OVERRIDE                                                                 0x00d7
5978 #define mmPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX                                                        1
5979 #define mmCP_PERFMON_CNTX_CNTL                                                                         0x00d8
5980 #define mmCP_PERFMON_CNTX_CNTL_BASE_IDX                                                                1
5981 #define mmCP_PIPEID                                                                                    0x00d9
5982 #define mmCP_PIPEID_BASE_IDX                                                                           1
5983 #define mmCP_RINGID                                                                                    0x00d9
5984 #define mmCP_RINGID_BASE_IDX                                                                           1
5985 #define mmCP_VMID                                                                                      0x00da
5986 #define mmCP_VMID_BASE_IDX                                                                             1
5987 #define mmPA_SC_RIGHT_VERT_GRID                                                                        0x00e8
5988 #define mmPA_SC_RIGHT_VERT_GRID_BASE_IDX                                                               1
5989 #define mmPA_SC_LEFT_VERT_GRID                                                                         0x00e9
5990 #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX                                                                1
5991 #define mmPA_SC_HORIZ_GRID                                                                             0x00ea
5992 #define mmPA_SC_HORIZ_GRID_BASE_IDX                                                                    1
5993 #define mmVGT_MAX_VTX_INDX                                                                             0x0100
5994 #define mmVGT_MAX_VTX_INDX_BASE_IDX                                                                    1
5995 #define mmVGT_MIN_VTX_INDX                                                                             0x0101
5996 #define mmVGT_MIN_VTX_INDX_BASE_IDX                                                                    1
5997 #define mmVGT_INDX_OFFSET                                                                              0x0102
5998 #define mmVGT_INDX_OFFSET_BASE_IDX                                                                     1
5999 #define mmVGT_MULTI_PRIM_IB_RESET_INDX                                                                 0x0103
6000 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX                                                        1
6001 #define mmCB_RMI_GL2_CACHE_CONTROL                                                                     0x0104
6002 #define mmCB_RMI_GL2_CACHE_CONTROL_BASE_IDX                                                            1
6003 #define mmCB_BLEND_RED                                                                                 0x0105
6004 #define mmCB_BLEND_RED_BASE_IDX                                                                        1
6005 #define mmCB_BLEND_GREEN                                                                               0x0106
6006 #define mmCB_BLEND_GREEN_BASE_IDX                                                                      1
6007 #define mmCB_BLEND_BLUE                                                                                0x0107
6008 #define mmCB_BLEND_BLUE_BASE_IDX                                                                       1
6009 #define mmCB_BLEND_ALPHA                                                                               0x0108
6010 #define mmCB_BLEND_ALPHA_BASE_IDX                                                                      1
6011 #define mmCB_DCC_CONTROL                                                                               0x0109
6012 #define mmCB_DCC_CONTROL_BASE_IDX                                                                      1
6013 #define mmCB_COVERAGE_OUT_CONTROL                                                                      0x010a
6014 #define mmCB_COVERAGE_OUT_CONTROL_BASE_IDX                                                             1
6015 #define mmDB_STENCIL_CONTROL                                                                           0x010b
6016 #define mmDB_STENCIL_CONTROL_BASE_IDX                                                                  1
6017 #define mmDB_STENCILREFMASK                                                                            0x010c
6018 #define mmDB_STENCILREFMASK_BASE_IDX                                                                   1
6019 #define mmDB_STENCILREFMASK_BF                                                                         0x010d
6020 #define mmDB_STENCILREFMASK_BF_BASE_IDX                                                                1
6021 #define mmPA_CL_VPORT_XSCALE                                                                           0x010f
6022 #define mmPA_CL_VPORT_XSCALE_BASE_IDX                                                                  1
6023 #define mmPA_CL_VPORT_XOFFSET                                                                          0x0110
6024 #define mmPA_CL_VPORT_XOFFSET_BASE_IDX                                                                 1
6025 #define mmPA_CL_VPORT_YSCALE                                                                           0x0111
6026 #define mmPA_CL_VPORT_YSCALE_BASE_IDX                                                                  1
6027 #define mmPA_CL_VPORT_YOFFSET                                                                          0x0112
6028 #define mmPA_CL_VPORT_YOFFSET_BASE_IDX                                                                 1
6029 #define mmPA_CL_VPORT_ZSCALE                                                                           0x0113
6030 #define mmPA_CL_VPORT_ZSCALE_BASE_IDX                                                                  1
6031 #define mmPA_CL_VPORT_ZOFFSET                                                                          0x0114
6032 #define mmPA_CL_VPORT_ZOFFSET_BASE_IDX                                                                 1
6033 #define mmPA_CL_VPORT_XSCALE_1                                                                         0x0115
6034 #define mmPA_CL_VPORT_XSCALE_1_BASE_IDX                                                                1
6035 #define mmPA_CL_VPORT_XOFFSET_1                                                                        0x0116
6036 #define mmPA_CL_VPORT_XOFFSET_1_BASE_IDX                                                               1
6037 #define mmPA_CL_VPORT_YSCALE_1                                                                         0x0117
6038 #define mmPA_CL_VPORT_YSCALE_1_BASE_IDX                                                                1
6039 #define mmPA_CL_VPORT_YOFFSET_1                                                                        0x0118
6040 #define mmPA_CL_VPORT_YOFFSET_1_BASE_IDX                                                               1
6041 #define mmPA_CL_VPORT_ZSCALE_1                                                                         0x0119
6042 #define mmPA_CL_VPORT_ZSCALE_1_BASE_IDX                                                                1
6043 #define mmPA_CL_VPORT_ZOFFSET_1                                                                        0x011a
6044 #define mmPA_CL_VPORT_ZOFFSET_1_BASE_IDX                                                               1
6045 #define mmPA_CL_VPORT_XSCALE_2                                                                         0x011b
6046 #define mmPA_CL_VPORT_XSCALE_2_BASE_IDX                                                                1
6047 #define mmPA_CL_VPORT_XOFFSET_2                                                                        0x011c
6048 #define mmPA_CL_VPORT_XOFFSET_2_BASE_IDX                                                               1
6049 #define mmPA_CL_VPORT_YSCALE_2                                                                         0x011d
6050 #define mmPA_CL_VPORT_YSCALE_2_BASE_IDX                                                                1
6051 #define mmPA_CL_VPORT_YOFFSET_2                                                                        0x011e
6052 #define mmPA_CL_VPORT_YOFFSET_2_BASE_IDX                                                               1
6053 #define mmPA_CL_VPORT_ZSCALE_2                                                                         0x011f
6054 #define mmPA_CL_VPORT_ZSCALE_2_BASE_IDX                                                                1
6055 #define mmPA_CL_VPORT_ZOFFSET_2                                                                        0x0120
6056 #define mmPA_CL_VPORT_ZOFFSET_2_BASE_IDX                                                               1
6057 #define mmPA_CL_VPORT_XSCALE_3                                                                         0x0121
6058 #define mmPA_CL_VPORT_XSCALE_3_BASE_IDX                                                                1
6059 #define mmPA_CL_VPORT_XOFFSET_3                                                                        0x0122
6060 #define mmPA_CL_VPORT_XOFFSET_3_BASE_IDX                                                               1
6061 #define mmPA_CL_VPORT_YSCALE_3                                                                         0x0123
6062 #define mmPA_CL_VPORT_YSCALE_3_BASE_IDX                                                                1
6063 #define mmPA_CL_VPORT_YOFFSET_3                                                                        0x0124
6064 #define mmPA_CL_VPORT_YOFFSET_3_BASE_IDX                                                               1
6065 #define mmPA_CL_VPORT_ZSCALE_3                                                                         0x0125
6066 #define mmPA_CL_VPORT_ZSCALE_3_BASE_IDX                                                                1
6067 #define mmPA_CL_VPORT_ZOFFSET_3                                                                        0x0126
6068 #define mmPA_CL_VPORT_ZOFFSET_3_BASE_IDX                                                               1
6069 #define mmPA_CL_VPORT_XSCALE_4                                                                         0x0127
6070 #define mmPA_CL_VPORT_XSCALE_4_BASE_IDX                                                                1
6071 #define mmPA_CL_VPORT_XOFFSET_4                                                                        0x0128
6072 #define mmPA_CL_VPORT_XOFFSET_4_BASE_IDX                                                               1
6073 #define mmPA_CL_VPORT_YSCALE_4                                                                         0x0129
6074 #define mmPA_CL_VPORT_YSCALE_4_BASE_IDX                                                                1
6075 #define mmPA_CL_VPORT_YOFFSET_4                                                                        0x012a
6076 #define mmPA_CL_VPORT_YOFFSET_4_BASE_IDX                                                               1
6077 #define mmPA_CL_VPORT_ZSCALE_4                                                                         0x012b
6078 #define mmPA_CL_VPORT_ZSCALE_4_BASE_IDX                                                                1
6079 #define mmPA_CL_VPORT_ZOFFSET_4                                                                        0x012c
6080 #define mmPA_CL_VPORT_ZOFFSET_4_BASE_IDX                                                               1
6081 #define mmPA_CL_VPORT_XSCALE_5                                                                         0x012d
6082 #define mmPA_CL_VPORT_XSCALE_5_BASE_IDX                                                                1
6083 #define mmPA_CL_VPORT_XOFFSET_5                                                                        0x012e
6084 #define mmPA_CL_VPORT_XOFFSET_5_BASE_IDX                                                               1
6085 #define mmPA_CL_VPORT_YSCALE_5                                                                         0x012f
6086 #define mmPA_CL_VPORT_YSCALE_5_BASE_IDX                                                                1
6087 #define mmPA_CL_VPORT_YOFFSET_5                                                                        0x0130
6088 #define mmPA_CL_VPORT_YOFFSET_5_BASE_IDX                                                               1
6089 #define mmPA_CL_VPORT_ZSCALE_5                                                                         0x0131
6090 #define mmPA_CL_VPORT_ZSCALE_5_BASE_IDX                                                                1
6091 #define mmPA_CL_VPORT_ZOFFSET_5                                                                        0x0132
6092 #define mmPA_CL_VPORT_ZOFFSET_5_BASE_IDX                                                               1
6093 #define mmPA_CL_VPORT_XSCALE_6                                                                         0x0133
6094 #define mmPA_CL_VPORT_XSCALE_6_BASE_IDX                                                                1
6095 #define mmPA_CL_VPORT_XOFFSET_6                                                                        0x0134
6096 #define mmPA_CL_VPORT_XOFFSET_6_BASE_IDX                                                               1
6097 #define mmPA_CL_VPORT_YSCALE_6                                                                         0x0135
6098 #define mmPA_CL_VPORT_YSCALE_6_BASE_IDX                                                                1
6099 #define mmPA_CL_VPORT_YOFFSET_6                                                                        0x0136
6100 #define mmPA_CL_VPORT_YOFFSET_6_BASE_IDX                                                               1
6101 #define mmPA_CL_VPORT_ZSCALE_6                                                                         0x0137
6102 #define mmPA_CL_VPORT_ZSCALE_6_BASE_IDX                                                                1
6103 #define mmPA_CL_VPORT_ZOFFSET_6                                                                        0x0138
6104 #define mmPA_CL_VPORT_ZOFFSET_6_BASE_IDX                                                               1
6105 #define mmPA_CL_VPORT_XSCALE_7                                                                         0x0139
6106 #define mmPA_CL_VPORT_XSCALE_7_BASE_IDX                                                                1
6107 #define mmPA_CL_VPORT_XOFFSET_7                                                                        0x013a
6108 #define mmPA_CL_VPORT_XOFFSET_7_BASE_IDX                                                               1
6109 #define mmPA_CL_VPORT_YSCALE_7                                                                         0x013b
6110 #define mmPA_CL_VPORT_YSCALE_7_BASE_IDX                                                                1
6111 #define mmPA_CL_VPORT_YOFFSET_7                                                                        0x013c
6112 #define mmPA_CL_VPORT_YOFFSET_7_BASE_IDX                                                               1
6113 #define mmPA_CL_VPORT_ZSCALE_7                                                                         0x013d
6114 #define mmPA_CL_VPORT_ZSCALE_7_BASE_IDX                                                                1
6115 #define mmPA_CL_VPORT_ZOFFSET_7                                                                        0x013e
6116 #define mmPA_CL_VPORT_ZOFFSET_7_BASE_IDX                                                               1
6117 #define mmPA_CL_VPORT_XSCALE_8                                                                         0x013f
6118 #define mmPA_CL_VPORT_XSCALE_8_BASE_IDX                                                                1
6119 #define mmPA_CL_VPORT_XOFFSET_8                                                                        0x0140
6120 #define mmPA_CL_VPORT_XOFFSET_8_BASE_IDX                                                               1
6121 #define mmPA_CL_VPORT_YSCALE_8                                                                         0x0141
6122 #define mmPA_CL_VPORT_YSCALE_8_BASE_IDX                                                                1
6123 #define mmPA_CL_VPORT_YOFFSET_8                                                                        0x0142
6124 #define mmPA_CL_VPORT_YOFFSET_8_BASE_IDX                                                               1
6125 #define mmPA_CL_VPORT_ZSCALE_8                                                                         0x0143
6126 #define mmPA_CL_VPORT_ZSCALE_8_BASE_IDX                                                                1
6127 #define mmPA_CL_VPORT_ZOFFSET_8                                                                        0x0144
6128 #define mmPA_CL_VPORT_ZOFFSET_8_BASE_IDX                                                               1
6129 #define mmPA_CL_VPORT_XSCALE_9                                                                         0x0145
6130 #define mmPA_CL_VPORT_XSCALE_9_BASE_IDX                                                                1
6131 #define mmPA_CL_VPORT_XOFFSET_9                                                                        0x0146
6132 #define mmPA_CL_VPORT_XOFFSET_9_BASE_IDX                                                               1
6133 #define mmPA_CL_VPORT_YSCALE_9                                                                         0x0147
6134 #define mmPA_CL_VPORT_YSCALE_9_BASE_IDX                                                                1
6135 #define mmPA_CL_VPORT_YOFFSET_9                                                                        0x0148
6136 #define mmPA_CL_VPORT_YOFFSET_9_BASE_IDX                                                               1
6137 #define mmPA_CL_VPORT_ZSCALE_9                                                                         0x0149
6138 #define mmPA_CL_VPORT_ZSCALE_9_BASE_IDX                                                                1
6139 #define mmPA_CL_VPORT_ZOFFSET_9                                                                        0x014a
6140 #define mmPA_CL_VPORT_ZOFFSET_9_BASE_IDX                                                               1
6141 #define mmPA_CL_VPORT_XSCALE_10                                                                        0x014b
6142 #define mmPA_CL_VPORT_XSCALE_10_BASE_IDX                                                               1
6143 #define mmPA_CL_VPORT_XOFFSET_10                                                                       0x014c
6144 #define mmPA_CL_VPORT_XOFFSET_10_BASE_IDX                                                              1
6145 #define mmPA_CL_VPORT_YSCALE_10                                                                        0x014d
6146 #define mmPA_CL_VPORT_YSCALE_10_BASE_IDX                                                               1
6147 #define mmPA_CL_VPORT_YOFFSET_10                                                                       0x014e
6148 #define mmPA_CL_VPORT_YOFFSET_10_BASE_IDX                                                              1
6149 #define mmPA_CL_VPORT_ZSCALE_10                                                                        0x014f
6150 #define mmPA_CL_VPORT_ZSCALE_10_BASE_IDX                                                               1
6151 #define mmPA_CL_VPORT_ZOFFSET_10                                                                       0x0150
6152 #define mmPA_CL_VPORT_ZOFFSET_10_BASE_IDX                                                              1
6153 #define mmPA_CL_VPORT_XSCALE_11                                                                        0x0151
6154 #define mmPA_CL_VPORT_XSCALE_11_BASE_IDX                                                               1
6155 #define mmPA_CL_VPORT_XOFFSET_11                                                                       0x0152
6156 #define mmPA_CL_VPORT_XOFFSET_11_BASE_IDX                                                              1
6157 #define mmPA_CL_VPORT_YSCALE_11                                                                        0x0153
6158 #define mmPA_CL_VPORT_YSCALE_11_BASE_IDX                                                               1
6159 #define mmPA_CL_VPORT_YOFFSET_11                                                                       0x0154
6160 #define mmPA_CL_VPORT_YOFFSET_11_BASE_IDX                                                              1
6161 #define mmPA_CL_VPORT_ZSCALE_11                                                                        0x0155
6162 #define mmPA_CL_VPORT_ZSCALE_11_BASE_IDX                                                               1
6163 #define mmPA_CL_VPORT_ZOFFSET_11                                                                       0x0156
6164 #define mmPA_CL_VPORT_ZOFFSET_11_BASE_IDX                                                              1
6165 #define mmPA_CL_VPORT_XSCALE_12                                                                        0x0157
6166 #define mmPA_CL_VPORT_XSCALE_12_BASE_IDX                                                               1
6167 #define mmPA_CL_VPORT_XOFFSET_12                                                                       0x0158
6168 #define mmPA_CL_VPORT_XOFFSET_12_BASE_IDX                                                              1
6169 #define mmPA_CL_VPORT_YSCALE_12                                                                        0x0159
6170 #define mmPA_CL_VPORT_YSCALE_12_BASE_IDX                                                               1
6171 #define mmPA_CL_VPORT_YOFFSET_12                                                                       0x015a
6172 #define mmPA_CL_VPORT_YOFFSET_12_BASE_IDX                                                              1
6173 #define mmPA_CL_VPORT_ZSCALE_12                                                                        0x015b
6174 #define mmPA_CL_VPORT_ZSCALE_12_BASE_IDX                                                               1
6175 #define mmPA_CL_VPORT_ZOFFSET_12                                                                       0x015c
6176 #define mmPA_CL_VPORT_ZOFFSET_12_BASE_IDX                                                              1
6177 #define mmPA_CL_VPORT_XSCALE_13                                                                        0x015d
6178 #define mmPA_CL_VPORT_XSCALE_13_BASE_IDX                                                               1
6179 #define mmPA_CL_VPORT_XOFFSET_13                                                                       0x015e
6180 #define mmPA_CL_VPORT_XOFFSET_13_BASE_IDX                                                              1
6181 #define mmPA_CL_VPORT_YSCALE_13                                                                        0x015f
6182 #define mmPA_CL_VPORT_YSCALE_13_BASE_IDX                                                               1
6183 #define mmPA_CL_VPORT_YOFFSET_13                                                                       0x0160
6184 #define mmPA_CL_VPORT_YOFFSET_13_BASE_IDX                                                              1
6185 #define mmPA_CL_VPORT_ZSCALE_13                                                                        0x0161
6186 #define mmPA_CL_VPORT_ZSCALE_13_BASE_IDX                                                               1
6187 #define mmPA_CL_VPORT_ZOFFSET_13                                                                       0x0162
6188 #define mmPA_CL_VPORT_ZOFFSET_13_BASE_IDX                                                              1
6189 #define mmPA_CL_VPORT_XSCALE_14                                                                        0x0163
6190 #define mmPA_CL_VPORT_XSCALE_14_BASE_IDX                                                               1
6191 #define mmPA_CL_VPORT_XOFFSET_14                                                                       0x0164
6192 #define mmPA_CL_VPORT_XOFFSET_14_BASE_IDX                                                              1
6193 #define mmPA_CL_VPORT_YSCALE_14                                                                        0x0165
6194 #define mmPA_CL_VPORT_YSCALE_14_BASE_IDX                                                               1
6195 #define mmPA_CL_VPORT_YOFFSET_14                                                                       0x0166
6196 #define mmPA_CL_VPORT_YOFFSET_14_BASE_IDX                                                              1
6197 #define mmPA_CL_VPORT_ZSCALE_14                                                                        0x0167
6198 #define mmPA_CL_VPORT_ZSCALE_14_BASE_IDX                                                               1
6199 #define mmPA_CL_VPORT_ZOFFSET_14                                                                       0x0168
6200 #define mmPA_CL_VPORT_ZOFFSET_14_BASE_IDX                                                              1
6201 #define mmPA_CL_VPORT_XSCALE_15                                                                        0x0169
6202 #define mmPA_CL_VPORT_XSCALE_15_BASE_IDX                                                               1
6203 #define mmPA_CL_VPORT_XOFFSET_15                                                                       0x016a
6204 #define mmPA_CL_VPORT_XOFFSET_15_BASE_IDX                                                              1
6205 #define mmPA_CL_VPORT_YSCALE_15                                                                        0x016b
6206 #define mmPA_CL_VPORT_YSCALE_15_BASE_IDX                                                               1
6207 #define mmPA_CL_VPORT_YOFFSET_15                                                                       0x016c
6208 #define mmPA_CL_VPORT_YOFFSET_15_BASE_IDX                                                              1
6209 #define mmPA_CL_VPORT_ZSCALE_15                                                                        0x016d
6210 #define mmPA_CL_VPORT_ZSCALE_15_BASE_IDX                                                               1
6211 #define mmPA_CL_VPORT_ZOFFSET_15                                                                       0x016e
6212 #define mmPA_CL_VPORT_ZOFFSET_15_BASE_IDX                                                              1
6213 #define mmPA_CL_UCP_0_X                                                                                0x016f
6214 #define mmPA_CL_UCP_0_X_BASE_IDX                                                                       1
6215 #define mmPA_CL_UCP_0_Y                                                                                0x0170
6216 #define mmPA_CL_UCP_0_Y_BASE_IDX                                                                       1
6217 #define mmPA_CL_UCP_0_Z                                                                                0x0171
6218 #define mmPA_CL_UCP_0_Z_BASE_IDX                                                                       1
6219 #define mmPA_CL_UCP_0_W                                                                                0x0172
6220 #define mmPA_CL_UCP_0_W_BASE_IDX                                                                       1
6221 #define mmPA_CL_UCP_1_X                                                                                0x0173
6222 #define mmPA_CL_UCP_1_X_BASE_IDX                                                                       1
6223 #define mmPA_CL_UCP_1_Y                                                                                0x0174
6224 #define mmPA_CL_UCP_1_Y_BASE_IDX                                                                       1
6225 #define mmPA_CL_UCP_1_Z                                                                                0x0175
6226 #define mmPA_CL_UCP_1_Z_BASE_IDX                                                                       1
6227 #define mmPA_CL_UCP_1_W                                                                                0x0176
6228 #define mmPA_CL_UCP_1_W_BASE_IDX                                                                       1
6229 #define mmPA_CL_UCP_2_X                                                                                0x0177
6230 #define mmPA_CL_UCP_2_X_BASE_IDX                                                                       1
6231 #define mmPA_CL_UCP_2_Y                                                                                0x0178
6232 #define mmPA_CL_UCP_2_Y_BASE_IDX                                                                       1
6233 #define mmPA_CL_UCP_2_Z                                                                                0x0179
6234 #define mmPA_CL_UCP_2_Z_BASE_IDX                                                                       1
6235 #define mmPA_CL_UCP_2_W                                                                                0x017a
6236 #define mmPA_CL_UCP_2_W_BASE_IDX                                                                       1
6237 #define mmPA_CL_UCP_3_X                                                                                0x017b
6238 #define mmPA_CL_UCP_3_X_BASE_IDX                                                                       1
6239 #define mmPA_CL_UCP_3_Y                                                                                0x017c
6240 #define mmPA_CL_UCP_3_Y_BASE_IDX                                                                       1
6241 #define mmPA_CL_UCP_3_Z                                                                                0x017d
6242 #define mmPA_CL_UCP_3_Z_BASE_IDX                                                                       1
6243 #define mmPA_CL_UCP_3_W                                                                                0x017e
6244 #define mmPA_CL_UCP_3_W_BASE_IDX                                                                       1
6245 #define mmPA_CL_UCP_4_X                                                                                0x017f
6246 #define mmPA_CL_UCP_4_X_BASE_IDX                                                                       1
6247 #define mmPA_CL_UCP_4_Y                                                                                0x0180
6248 #define mmPA_CL_UCP_4_Y_BASE_IDX                                                                       1
6249 #define mmPA_CL_UCP_4_Z                                                                                0x0181
6250 #define mmPA_CL_UCP_4_Z_BASE_IDX                                                                       1
6251 #define mmPA_CL_UCP_4_W                                                                                0x0182
6252 #define mmPA_CL_UCP_4_W_BASE_IDX                                                                       1
6253 #define mmPA_CL_UCP_5_X                                                                                0x0183
6254 #define mmPA_CL_UCP_5_X_BASE_IDX                                                                       1
6255 #define mmPA_CL_UCP_5_Y                                                                                0x0184
6256 #define mmPA_CL_UCP_5_Y_BASE_IDX                                                                       1
6257 #define mmPA_CL_UCP_5_Z                                                                                0x0185
6258 #define mmPA_CL_UCP_5_Z_BASE_IDX                                                                       1
6259 #define mmPA_CL_UCP_5_W                                                                                0x0186
6260 #define mmPA_CL_UCP_5_W_BASE_IDX                                                                       1
6261 #define mmPA_CL_PROG_NEAR_CLIP_Z                                                                       0x0187
6262 #define mmPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX                                                              1
6263 #define mmSPI_PS_INPUT_CNTL_0                                                                          0x0191
6264 #define mmSPI_PS_INPUT_CNTL_0_BASE_IDX                                                                 1
6265 #define mmSPI_PS_INPUT_CNTL_1                                                                          0x0192
6266 #define mmSPI_PS_INPUT_CNTL_1_BASE_IDX                                                                 1
6267 #define mmSPI_PS_INPUT_CNTL_2                                                                          0x0193
6268 #define mmSPI_PS_INPUT_CNTL_2_BASE_IDX                                                                 1
6269 #define mmSPI_PS_INPUT_CNTL_3                                                                          0x0194
6270 #define mmSPI_PS_INPUT_CNTL_3_BASE_IDX                                                                 1
6271 #define mmSPI_PS_INPUT_CNTL_4                                                                          0x0195
6272 #define mmSPI_PS_INPUT_CNTL_4_BASE_IDX                                                                 1
6273 #define mmSPI_PS_INPUT_CNTL_5                                                                          0x0196
6274 #define mmSPI_PS_INPUT_CNTL_5_BASE_IDX                                                                 1
6275 #define mmSPI_PS_INPUT_CNTL_6                                                                          0x0197
6276 #define mmSPI_PS_INPUT_CNTL_6_BASE_IDX                                                                 1
6277 #define mmSPI_PS_INPUT_CNTL_7                                                                          0x0198
6278 #define mmSPI_PS_INPUT_CNTL_7_BASE_IDX                                                                 1
6279 #define mmSPI_PS_INPUT_CNTL_8                                                                          0x0199
6280 #define mmSPI_PS_INPUT_CNTL_8_BASE_IDX                                                                 1
6281 #define mmSPI_PS_INPUT_CNTL_9                                                                          0x019a
6282 #define mmSPI_PS_INPUT_CNTL_9_BASE_IDX                                                                 1
6283 #define mmSPI_PS_INPUT_CNTL_10                                                                         0x019b
6284 #define mmSPI_PS_INPUT_CNTL_10_BASE_IDX                                                                1
6285 #define mmSPI_PS_INPUT_CNTL_11                                                                         0x019c
6286 #define mmSPI_PS_INPUT_CNTL_11_BASE_IDX                                                                1
6287 #define mmSPI_PS_INPUT_CNTL_12                                                                         0x019d
6288 #define mmSPI_PS_INPUT_CNTL_12_BASE_IDX                                                                1
6289 #define mmSPI_PS_INPUT_CNTL_13                                                                         0x019e
6290 #define mmSPI_PS_INPUT_CNTL_13_BASE_IDX                                                                1
6291 #define mmSPI_PS_INPUT_CNTL_14                                                                         0x019f
6292 #define mmSPI_PS_INPUT_CNTL_14_BASE_IDX                                                                1
6293 #define mmSPI_PS_INPUT_CNTL_15                                                                         0x01a0
6294 #define mmSPI_PS_INPUT_CNTL_15_BASE_IDX                                                                1
6295 #define mmSPI_PS_INPUT_CNTL_16                                                                         0x01a1
6296 #define mmSPI_PS_INPUT_CNTL_16_BASE_IDX                                                                1
6297 #define mmSPI_PS_INPUT_CNTL_17                                                                         0x01a2
6298 #define mmSPI_PS_INPUT_CNTL_17_BASE_IDX                                                                1
6299 #define mmSPI_PS_INPUT_CNTL_18                                                                         0x01a3
6300 #define mmSPI_PS_INPUT_CNTL_18_BASE_IDX                                                                1
6301 #define mmSPI_PS_INPUT_CNTL_19                                                                         0x01a4
6302 #define mmSPI_PS_INPUT_CNTL_19_BASE_IDX                                                                1
6303 #define mmSPI_PS_INPUT_CNTL_20                                                                         0x01a5
6304 #define mmSPI_PS_INPUT_CNTL_20_BASE_IDX                                                                1
6305 #define mmSPI_PS_INPUT_CNTL_21                                                                         0x01a6
6306 #define mmSPI_PS_INPUT_CNTL_21_BASE_IDX                                                                1
6307 #define mmSPI_PS_INPUT_CNTL_22                                                                         0x01a7
6308 #define mmSPI_PS_INPUT_CNTL_22_BASE_IDX                                                                1
6309 #define mmSPI_PS_INPUT_CNTL_23                                                                         0x01a8
6310 #define mmSPI_PS_INPUT_CNTL_23_BASE_IDX                                                                1
6311 #define mmSPI_PS_INPUT_CNTL_24                                                                         0x01a9
6312 #define mmSPI_PS_INPUT_CNTL_24_BASE_IDX                                                                1
6313 #define mmSPI_PS_INPUT_CNTL_25                                                                         0x01aa
6314 #define mmSPI_PS_INPUT_CNTL_25_BASE_IDX                                                                1
6315 #define mmSPI_PS_INPUT_CNTL_26                                                                         0x01ab
6316 #define mmSPI_PS_INPUT_CNTL_26_BASE_IDX                                                                1
6317 #define mmSPI_PS_INPUT_CNTL_27                                                                         0x01ac
6318 #define mmSPI_PS_INPUT_CNTL_27_BASE_IDX                                                                1
6319 #define mmSPI_PS_INPUT_CNTL_28                                                                         0x01ad
6320 #define mmSPI_PS_INPUT_CNTL_28_BASE_IDX                                                                1
6321 #define mmSPI_PS_INPUT_CNTL_29                                                                         0x01ae
6322 #define mmSPI_PS_INPUT_CNTL_29_BASE_IDX                                                                1
6323 #define mmSPI_PS_INPUT_CNTL_30                                                                         0x01af
6324 #define mmSPI_PS_INPUT_CNTL_30_BASE_IDX                                                                1
6325 #define mmSPI_PS_INPUT_CNTL_31                                                                         0x01b0
6326 #define mmSPI_PS_INPUT_CNTL_31_BASE_IDX                                                                1
6327 #define mmSPI_VS_OUT_CONFIG                                                                            0x01b1
6328 #define mmSPI_VS_OUT_CONFIG_BASE_IDX                                                                   1
6329 #define mmSPI_PS_INPUT_ENA                                                                             0x01b3
6330 #define mmSPI_PS_INPUT_ENA_BASE_IDX                                                                    1
6331 #define mmSPI_PS_INPUT_ADDR                                                                            0x01b4
6332 #define mmSPI_PS_INPUT_ADDR_BASE_IDX                                                                   1
6333 #define mmSPI_INTERP_CONTROL_0                                                                         0x01b5
6334 #define mmSPI_INTERP_CONTROL_0_BASE_IDX                                                                1
6335 #define mmSPI_PS_IN_CONTROL                                                                            0x01b6
6336 #define mmSPI_PS_IN_CONTROL_BASE_IDX                                                                   1
6337 #define mmSPI_BARYC_CNTL                                                                               0x01b8
6338 #define mmSPI_BARYC_CNTL_BASE_IDX                                                                      1
6339 #define mmSPI_TMPRING_SIZE                                                                             0x01ba
6340 #define mmSPI_TMPRING_SIZE_BASE_IDX                                                                    1
6341 #define mmSPI_SHADER_IDX_FORMAT                                                                        0x01c2
6342 #define mmSPI_SHADER_IDX_FORMAT_BASE_IDX                                                               1
6343 #define mmSPI_SHADER_POS_FORMAT                                                                        0x01c3
6344 #define mmSPI_SHADER_POS_FORMAT_BASE_IDX                                                               1
6345 #define mmSPI_SHADER_Z_FORMAT                                                                          0x01c4
6346 #define mmSPI_SHADER_Z_FORMAT_BASE_IDX                                                                 1
6347 #define mmSPI_SHADER_COL_FORMAT                                                                        0x01c5
6348 #define mmSPI_SHADER_COL_FORMAT_BASE_IDX                                                               1
6349 #define mmSX_PS_DOWNCONVERT                                                                            0x01d5
6350 #define mmSX_PS_DOWNCONVERT_BASE_IDX                                                                   1
6351 #define mmSX_BLEND_OPT_EPSILON                                                                         0x01d6
6352 #define mmSX_BLEND_OPT_EPSILON_BASE_IDX                                                                1
6353 #define mmSX_BLEND_OPT_CONTROL                                                                         0x01d7
6354 #define mmSX_BLEND_OPT_CONTROL_BASE_IDX                                                                1
6355 #define mmSX_MRT0_BLEND_OPT                                                                            0x01d8
6356 #define mmSX_MRT0_BLEND_OPT_BASE_IDX                                                                   1
6357 #define mmSX_MRT1_BLEND_OPT                                                                            0x01d9
6358 #define mmSX_MRT1_BLEND_OPT_BASE_IDX                                                                   1
6359 #define mmSX_MRT2_BLEND_OPT                                                                            0x01da
6360 #define mmSX_MRT2_BLEND_OPT_BASE_IDX                                                                   1
6361 #define mmSX_MRT3_BLEND_OPT                                                                            0x01db
6362 #define mmSX_MRT3_BLEND_OPT_BASE_IDX                                                                   1
6363 #define mmSX_MRT4_BLEND_OPT                                                                            0x01dc
6364 #define mmSX_MRT4_BLEND_OPT_BASE_IDX                                                                   1
6365 #define mmSX_MRT5_BLEND_OPT                                                                            0x01dd
6366 #define mmSX_MRT5_BLEND_OPT_BASE_IDX                                                                   1
6367 #define mmSX_MRT6_BLEND_OPT                                                                            0x01de
6368 #define mmSX_MRT6_BLEND_OPT_BASE_IDX                                                                   1
6369 #define mmSX_MRT7_BLEND_OPT                                                                            0x01df
6370 #define mmSX_MRT7_BLEND_OPT_BASE_IDX                                                                   1
6371 #define mmCB_BLEND0_CONTROL                                                                            0x01e0
6372 #define mmCB_BLEND0_CONTROL_BASE_IDX                                                                   1
6373 #define mmCB_BLEND1_CONTROL                                                                            0x01e1
6374 #define mmCB_BLEND1_CONTROL_BASE_IDX                                                                   1
6375 #define mmCB_BLEND2_CONTROL                                                                            0x01e2
6376 #define mmCB_BLEND2_CONTROL_BASE_IDX                                                                   1
6377 #define mmCB_BLEND3_CONTROL                                                                            0x01e3
6378 #define mmCB_BLEND3_CONTROL_BASE_IDX                                                                   1
6379 #define mmCB_BLEND4_CONTROL                                                                            0x01e4
6380 #define mmCB_BLEND4_CONTROL_BASE_IDX                                                                   1
6381 #define mmCB_BLEND5_CONTROL                                                                            0x01e5
6382 #define mmCB_BLEND5_CONTROL_BASE_IDX                                                                   1
6383 #define mmCB_BLEND6_CONTROL                                                                            0x01e6
6384 #define mmCB_BLEND6_CONTROL_BASE_IDX                                                                   1
6385 #define mmCB_BLEND7_CONTROL                                                                            0x01e7
6386 #define mmCB_BLEND7_CONTROL_BASE_IDX                                                                   1
6387 #define mmCS_COPY_STATE                                                                                0x01f3
6388 #define mmCS_COPY_STATE_BASE_IDX                                                                       1
6389 #define mmGFX_COPY_STATE                                                                               0x01f4
6390 #define mmGFX_COPY_STATE_BASE_IDX                                                                      1
6391 #define mmPA_CL_POINT_X_RAD                                                                            0x01f5
6392 #define mmPA_CL_POINT_X_RAD_BASE_IDX                                                                   1
6393 #define mmPA_CL_POINT_Y_RAD                                                                            0x01f6
6394 #define mmPA_CL_POINT_Y_RAD_BASE_IDX                                                                   1
6395 #define mmPA_CL_POINT_SIZE                                                                             0x01f7
6396 #define mmPA_CL_POINT_SIZE_BASE_IDX                                                                    1
6397 #define mmPA_CL_POINT_CULL_RAD                                                                         0x01f8
6398 #define mmPA_CL_POINT_CULL_RAD_BASE_IDX                                                                1
6399 #define mmVGT_DMA_BASE_HI                                                                              0x01f9
6400 #define mmVGT_DMA_BASE_HI_BASE_IDX                                                                     1
6401 #define mmVGT_DMA_BASE                                                                                 0x01fa
6402 #define mmVGT_DMA_BASE_BASE_IDX                                                                        1
6403 #define mmVGT_DRAW_INITIATOR                                                                           0x01fc
6404 #define mmVGT_DRAW_INITIATOR_BASE_IDX                                                                  1
6405 #define mmVGT_IMMED_DATA                                                                               0x01fd
6406 #define mmVGT_IMMED_DATA_BASE_IDX                                                                      1
6407 #define mmVGT_EVENT_ADDRESS_REG                                                                        0x01fe
6408 #define mmVGT_EVENT_ADDRESS_REG_BASE_IDX                                                               1
6409 #define mmGE_MAX_OUTPUT_PER_SUBGROUP                                                                   0x01ff
6410 #define mmGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX                                                          1
6411 #define mmDB_DEPTH_CONTROL                                                                             0x0200
6412 #define mmDB_DEPTH_CONTROL_BASE_IDX                                                                    1
6413 #define mmDB_EQAA                                                                                      0x0201
6414 #define mmDB_EQAA_BASE_IDX                                                                             1
6415 #define mmCB_COLOR_CONTROL                                                                             0x0202
6416 #define mmCB_COLOR_CONTROL_BASE_IDX                                                                    1
6417 #define mmDB_SHADER_CONTROL                                                                            0x0203
6418 #define mmDB_SHADER_CONTROL_BASE_IDX                                                                   1
6419 #define mmPA_CL_CLIP_CNTL                                                                              0x0204
6420 #define mmPA_CL_CLIP_CNTL_BASE_IDX                                                                     1
6421 #define mmPA_SU_SC_MODE_CNTL                                                                           0x0205
6422 #define mmPA_SU_SC_MODE_CNTL_BASE_IDX                                                                  1
6423 #define mmPA_CL_VTE_CNTL                                                                               0x0206
6424 #define mmPA_CL_VTE_CNTL_BASE_IDX                                                                      1
6425 #define mmPA_CL_VS_OUT_CNTL                                                                            0x0207
6426 #define mmPA_CL_VS_OUT_CNTL_BASE_IDX                                                                   1
6427 #define mmPA_CL_NANINF_CNTL                                                                            0x0208
6428 #define mmPA_CL_NANINF_CNTL_BASE_IDX                                                                   1
6429 #define mmPA_SU_LINE_STIPPLE_CNTL                                                                      0x0209
6430 #define mmPA_SU_LINE_STIPPLE_CNTL_BASE_IDX                                                             1
6431 #define mmPA_SU_LINE_STIPPLE_SCALE                                                                     0x020a
6432 #define mmPA_SU_LINE_STIPPLE_SCALE_BASE_IDX                                                            1
6433 #define mmPA_SU_PRIM_FILTER_CNTL                                                                       0x020b
6434 #define mmPA_SU_PRIM_FILTER_CNTL_BASE_IDX                                                              1
6435 #define mmPA_SU_SMALL_PRIM_FILTER_CNTL                                                                 0x020c
6436 #define mmPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX                                                        1
6437 #define mmPA_CL_OBJPRIM_ID_CNTL                                                                        0x020d
6438 #define mmPA_CL_OBJPRIM_ID_CNTL_BASE_IDX                                                               1
6439 #define mmPA_CL_NGG_CNTL                                                                               0x020e
6440 #define mmPA_CL_NGG_CNTL_BASE_IDX                                                                      1
6441 #define mmPA_SU_OVER_RASTERIZATION_CNTL                                                                0x020f
6442 #define mmPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX                                                       1
6443 #define mmPA_STEREO_CNTL                                                                               0x0210
6444 #define mmPA_STEREO_CNTL_BASE_IDX                                                                      1
6445 #define mmPA_STATE_STEREO_X                                                                            0x0211
6446 #define mmPA_STATE_STEREO_X_BASE_IDX                                                                   1
6447 #define mmPA_SU_POINT_SIZE                                                                             0x0280
6448 #define mmPA_SU_POINT_SIZE_BASE_IDX                                                                    1
6449 #define mmPA_SU_POINT_MINMAX                                                                           0x0281
6450 #define mmPA_SU_POINT_MINMAX_BASE_IDX                                                                  1
6451 #define mmPA_SU_LINE_CNTL                                                                              0x0282
6452 #define mmPA_SU_LINE_CNTL_BASE_IDX                                                                     1
6453 #define mmPA_SC_LINE_STIPPLE                                                                           0x0283
6454 #define mmPA_SC_LINE_STIPPLE_BASE_IDX                                                                  1
6455 #define mmVGT_OUTPUT_PATH_CNTL                                                                         0x0284
6456 #define mmVGT_OUTPUT_PATH_CNTL_BASE_IDX                                                                1
6457 #define mmVGT_HOS_CNTL                                                                                 0x0285
6458 #define mmVGT_HOS_CNTL_BASE_IDX                                                                        1
6459 #define mmVGT_HOS_MAX_TESS_LEVEL                                                                       0x0286
6460 #define mmVGT_HOS_MAX_TESS_LEVEL_BASE_IDX                                                              1
6461 #define mmVGT_HOS_MIN_TESS_LEVEL                                                                       0x0287
6462 #define mmVGT_HOS_MIN_TESS_LEVEL_BASE_IDX                                                              1
6463 #define mmVGT_HOS_REUSE_DEPTH                                                                          0x0288
6464 #define mmVGT_HOS_REUSE_DEPTH_BASE_IDX                                                                 1
6465 #define mmVGT_GROUP_PRIM_TYPE                                                                          0x0289
6466 #define mmVGT_GROUP_PRIM_TYPE_BASE_IDX                                                                 1
6467 #define mmVGT_GROUP_FIRST_DECR                                                                         0x028a
6468 #define mmVGT_GROUP_FIRST_DECR_BASE_IDX                                                                1
6469 #define mmVGT_GROUP_DECR                                                                               0x028b
6470 #define mmVGT_GROUP_DECR_BASE_IDX                                                                      1
6471 #define mmVGT_GROUP_VECT_0_CNTL                                                                        0x028c
6472 #define mmVGT_GROUP_VECT_0_CNTL_BASE_IDX                                                               1
6473 #define mmVGT_GROUP_VECT_1_CNTL                                                                        0x028d
6474 #define mmVGT_GROUP_VECT_1_CNTL_BASE_IDX                                                               1
6475 #define mmVGT_GROUP_VECT_0_FMT_CNTL                                                                    0x028e
6476 #define mmVGT_GROUP_VECT_0_FMT_CNTL_BASE_IDX                                                           1
6477 #define mmVGT_GROUP_VECT_1_FMT_CNTL                                                                    0x028f
6478 #define mmVGT_GROUP_VECT_1_FMT_CNTL_BASE_IDX                                                           1
6479 #define mmVGT_GS_MODE                                                                                  0x0290
6480 #define mmVGT_GS_MODE_BASE_IDX                                                                         1
6481 #define mmVGT_GS_ONCHIP_CNTL                                                                           0x0291
6482 #define mmVGT_GS_ONCHIP_CNTL_BASE_IDX                                                                  1
6483 #define mmPA_SC_MODE_CNTL_0                                                                            0x0292
6484 #define mmPA_SC_MODE_CNTL_0_BASE_IDX                                                                   1
6485 #define mmPA_SC_MODE_CNTL_1                                                                            0x0293
6486 #define mmPA_SC_MODE_CNTL_1_BASE_IDX                                                                   1
6487 #define mmVGT_ENHANCE                                                                                  0x0294
6488 #define mmVGT_ENHANCE_BASE_IDX                                                                         1
6489 #define mmVGT_GS_PER_ES                                                                                0x0295
6490 #define mmVGT_GS_PER_ES_BASE_IDX                                                                       1
6491 #define mmVGT_ES_PER_GS                                                                                0x0296
6492 #define mmVGT_ES_PER_GS_BASE_IDX                                                                       1
6493 #define mmVGT_GS_PER_VS                                                                                0x0297
6494 #define mmVGT_GS_PER_VS_BASE_IDX                                                                       1
6495 #define mmVGT_GSVS_RING_OFFSET_1                                                                       0x0298
6496 #define mmVGT_GSVS_RING_OFFSET_1_BASE_IDX                                                              1
6497 #define mmVGT_GSVS_RING_OFFSET_2                                                                       0x0299
6498 #define mmVGT_GSVS_RING_OFFSET_2_BASE_IDX                                                              1
6499 #define mmVGT_GSVS_RING_OFFSET_3                                                                       0x029a
6500 #define mmVGT_GSVS_RING_OFFSET_3_BASE_IDX                                                              1
6501 #define mmVGT_GS_OUT_PRIM_TYPE                                                                         0x029b
6502 #define mmVGT_GS_OUT_PRIM_TYPE_BASE_IDX                                                                1
6503 #define mmIA_ENHANCE                                                                                   0x029c
6504 #define mmIA_ENHANCE_BASE_IDX                                                                          1
6505 #define mmVGT_DMA_SIZE                                                                                 0x029d
6506 #define mmVGT_DMA_SIZE_BASE_IDX                                                                        1
6507 #define mmVGT_DMA_MAX_SIZE                                                                             0x029e
6508 #define mmVGT_DMA_MAX_SIZE_BASE_IDX                                                                    1
6509 #define mmVGT_DMA_INDEX_TYPE                                                                           0x029f
6510 #define mmVGT_DMA_INDEX_TYPE_BASE_IDX                                                                  1
6511 #define mmWD_ENHANCE                                                                                   0x02a0
6512 #define mmWD_ENHANCE_BASE_IDX                                                                          1
6513 #define mmVGT_PRIMITIVEID_EN                                                                           0x02a1
6514 #define mmVGT_PRIMITIVEID_EN_BASE_IDX                                                                  1
6515 #define mmVGT_DMA_NUM_INSTANCES                                                                        0x02a2
6516 #define mmVGT_DMA_NUM_INSTANCES_BASE_IDX                                                               1
6517 #define mmVGT_PRIMITIVEID_RESET                                                                        0x02a3
6518 #define mmVGT_PRIMITIVEID_RESET_BASE_IDX                                                               1
6519 #define mmVGT_EVENT_INITIATOR                                                                          0x02a4
6520 #define mmVGT_EVENT_INITIATOR_BASE_IDX                                                                 1
6521 #define mmVGT_MULTI_PRIM_IB_RESET_EN                                                                   0x02a5
6522 #define mmVGT_MULTI_PRIM_IB_RESET_EN_BASE_IDX                                                          1
6523 #define mmVGT_DRAW_PAYLOAD_CNTL                                                                        0x02a6
6524 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX                                                               1
6525 #define mmVGT_INSTANCE_STEP_RATE_0                                                                     0x02a8
6526 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX                                                            1
6527 #define mmVGT_INSTANCE_STEP_RATE_1                                                                     0x02a9
6528 #define mmVGT_INSTANCE_STEP_RATE_1_BASE_IDX                                                            1
6529 #define mmIA_MULTI_VGT_PARAM                                                                           0x02aa
6530 #define mmIA_MULTI_VGT_PARAM_BASE_IDX                                                                  1
6531 #define mmVGT_ESGS_RING_ITEMSIZE                                                                       0x02ab
6532 #define mmVGT_ESGS_RING_ITEMSIZE_BASE_IDX                                                              1
6533 #define mmVGT_GSVS_RING_ITEMSIZE                                                                       0x02ac
6534 #define mmVGT_GSVS_RING_ITEMSIZE_BASE_IDX                                                              1
6535 #define mmVGT_REUSE_OFF                                                                                0x02ad
6536 #define mmVGT_REUSE_OFF_BASE_IDX                                                                       1
6537 #define mmVGT_VTX_CNT_EN                                                                               0x02ae
6538 #define mmVGT_VTX_CNT_EN_BASE_IDX                                                                      1
6539 #define mmDB_HTILE_SURFACE                                                                             0x02af
6540 #define mmDB_HTILE_SURFACE_BASE_IDX                                                                    1
6541 #define mmDB_SRESULTS_COMPARE_STATE0                                                                   0x02b0
6542 #define mmDB_SRESULTS_COMPARE_STATE0_BASE_IDX                                                          1
6543 #define mmDB_SRESULTS_COMPARE_STATE1                                                                   0x02b1
6544 #define mmDB_SRESULTS_COMPARE_STATE1_BASE_IDX                                                          1
6545 #define mmDB_PRELOAD_CONTROL                                                                           0x02b2
6546 #define mmDB_PRELOAD_CONTROL_BASE_IDX                                                                  1
6547 #define mmVGT_STRMOUT_BUFFER_SIZE_0                                                                    0x02b4
6548 #define mmVGT_STRMOUT_BUFFER_SIZE_0_BASE_IDX                                                           1
6549 #define mmVGT_STRMOUT_VTX_STRIDE_0                                                                     0x02b5
6550 #define mmVGT_STRMOUT_VTX_STRIDE_0_BASE_IDX                                                            1
6551 #define mmVGT_STRMOUT_BUFFER_OFFSET_0                                                                  0x02b7
6552 #define mmVGT_STRMOUT_BUFFER_OFFSET_0_BASE_IDX                                                         1
6553 #define mmVGT_STRMOUT_BUFFER_SIZE_1                                                                    0x02b8
6554 #define mmVGT_STRMOUT_BUFFER_SIZE_1_BASE_IDX                                                           1
6555 #define mmVGT_STRMOUT_VTX_STRIDE_1                                                                     0x02b9
6556 #define mmVGT_STRMOUT_VTX_STRIDE_1_BASE_IDX                                                            1
6557 #define mmVGT_STRMOUT_BUFFER_OFFSET_1                                                                  0x02bb
6558 #define mmVGT_STRMOUT_BUFFER_OFFSET_1_BASE_IDX                                                         1
6559 #define mmVGT_STRMOUT_BUFFER_SIZE_2                                                                    0x02bc
6560 #define mmVGT_STRMOUT_BUFFER_SIZE_2_BASE_IDX                                                           1
6561 #define mmVGT_STRMOUT_VTX_STRIDE_2                                                                     0x02bd
6562 #define mmVGT_STRMOUT_VTX_STRIDE_2_BASE_IDX                                                            1
6563 #define mmVGT_STRMOUT_BUFFER_OFFSET_2                                                                  0x02bf
6564 #define mmVGT_STRMOUT_BUFFER_OFFSET_2_BASE_IDX                                                         1
6565 #define mmVGT_STRMOUT_BUFFER_SIZE_3                                                                    0x02c0
6566 #define mmVGT_STRMOUT_BUFFER_SIZE_3_BASE_IDX                                                           1
6567 #define mmVGT_STRMOUT_VTX_STRIDE_3                                                                     0x02c1
6568 #define mmVGT_STRMOUT_VTX_STRIDE_3_BASE_IDX                                                            1
6569 #define mmVGT_STRMOUT_BUFFER_OFFSET_3                                                                  0x02c3
6570 #define mmVGT_STRMOUT_BUFFER_OFFSET_3_BASE_IDX                                                         1
6571 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET                                                               0x02ca
6572 #define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX                                                      1
6573 #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE                                                   0x02cb
6574 #define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX                                          1
6575 #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE                                                        0x02cc
6576 #define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX                                               1
6577 #define mmVGT_GS_MAX_VERT_OUT                                                                          0x02ce
6578 #define mmVGT_GS_MAX_VERT_OUT_BASE_IDX                                                                 1
6579 #define mmGE_NGG_SUBGRP_CNTL                                                                           0x02d3
6580 #define mmGE_NGG_SUBGRP_CNTL_BASE_IDX                                                                  1
6581 #define mmVGT_TESS_DISTRIBUTION                                                                        0x02d4
6582 #define mmVGT_TESS_DISTRIBUTION_BASE_IDX                                                               1
6583 #define mmVGT_SHADER_STAGES_EN                                                                         0x02d5
6584 #define mmVGT_SHADER_STAGES_EN_BASE_IDX                                                                1
6585 #define mmVGT_LS_HS_CONFIG                                                                             0x02d6
6586 #define mmVGT_LS_HS_CONFIG_BASE_IDX                                                                    1
6587 #define mmVGT_GS_VERT_ITEMSIZE                                                                         0x02d7
6588 #define mmVGT_GS_VERT_ITEMSIZE_BASE_IDX                                                                1
6589 #define mmVGT_GS_VERT_ITEMSIZE_1                                                                       0x02d8
6590 #define mmVGT_GS_VERT_ITEMSIZE_1_BASE_IDX                                                              1
6591 #define mmVGT_GS_VERT_ITEMSIZE_2                                                                       0x02d9
6592 #define mmVGT_GS_VERT_ITEMSIZE_2_BASE_IDX                                                              1
6593 #define mmVGT_GS_VERT_ITEMSIZE_3                                                                       0x02da
6594 #define mmVGT_GS_VERT_ITEMSIZE_3_BASE_IDX                                                              1
6595 #define mmVGT_TF_PARAM                                                                                 0x02db
6596 #define mmVGT_TF_PARAM_BASE_IDX                                                                        1
6597 #define mmDB_ALPHA_TO_MASK                                                                             0x02dc
6598 #define mmDB_ALPHA_TO_MASK_BASE_IDX                                                                    1
6599 #define mmVGT_DISPATCH_DRAW_INDEX                                                                      0x02dd
6600 #define mmVGT_DISPATCH_DRAW_INDEX_BASE_IDX                                                             1
6601 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL                                                                0x02de
6602 #define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX                                                       1
6603 #define mmPA_SU_POLY_OFFSET_CLAMP                                                                      0x02df
6604 #define mmPA_SU_POLY_OFFSET_CLAMP_BASE_IDX                                                             1
6605 #define mmPA_SU_POLY_OFFSET_FRONT_SCALE                                                                0x02e0
6606 #define mmPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX                                                       1
6607 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET                                                               0x02e1
6608 #define mmPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX                                                      1
6609 #define mmPA_SU_POLY_OFFSET_BACK_SCALE                                                                 0x02e2
6610 #define mmPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX                                                        1
6611 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET                                                                0x02e3
6612 #define mmPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX                                                       1
6613 #define mmVGT_GS_INSTANCE_CNT                                                                          0x02e4
6614 #define mmVGT_GS_INSTANCE_CNT_BASE_IDX                                                                 1
6615 #define mmVGT_STRMOUT_CONFIG                                                                           0x02e5
6616 #define mmVGT_STRMOUT_CONFIG_BASE_IDX                                                                  1
6617 #define mmVGT_STRMOUT_BUFFER_CONFIG                                                                    0x02e6
6618 #define mmVGT_STRMOUT_BUFFER_CONFIG_BASE_IDX                                                           1
6619 #define mmVGT_DMA_EVENT_INITIATOR                                                                      0x02e7
6620 #define mmVGT_DMA_EVENT_INITIATOR_BASE_IDX                                                             1
6621 #define mmPA_SC_CENTROID_PRIORITY_0                                                                    0x02f5
6622 #define mmPA_SC_CENTROID_PRIORITY_0_BASE_IDX                                                           1
6623 #define mmPA_SC_CENTROID_PRIORITY_1                                                                    0x02f6
6624 #define mmPA_SC_CENTROID_PRIORITY_1_BASE_IDX                                                           1
6625 #define mmPA_SC_LINE_CNTL                                                                              0x02f7
6626 #define mmPA_SC_LINE_CNTL_BASE_IDX                                                                     1
6627 #define mmPA_SC_AA_CONFIG                                                                              0x02f8
6628 #define mmPA_SC_AA_CONFIG_BASE_IDX                                                                     1
6629 #define mmPA_SU_VTX_CNTL                                                                               0x02f9
6630 #define mmPA_SU_VTX_CNTL_BASE_IDX                                                                      1
6631 #define mmPA_CL_GB_VERT_CLIP_ADJ                                                                       0x02fa
6632 #define mmPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX                                                              1
6633 #define mmPA_CL_GB_VERT_DISC_ADJ                                                                       0x02fb
6634 #define mmPA_CL_GB_VERT_DISC_ADJ_BASE_IDX                                                              1
6635 #define mmPA_CL_GB_HORZ_CLIP_ADJ                                                                       0x02fc
6636 #define mmPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX                                                              1
6637 #define mmPA_CL_GB_HORZ_DISC_ADJ                                                                       0x02fd
6638 #define mmPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX                                                              1
6639 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0                                                            0x02fe
6640 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX                                                   1
6641 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1                                                            0x02ff
6642 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX                                                   1
6643 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2                                                            0x0300
6644 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX                                                   1
6645 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3                                                            0x0301
6646 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX                                                   1
6647 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0                                                            0x0302
6648 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX                                                   1
6649 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1                                                            0x0303
6650 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX                                                   1
6651 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2                                                            0x0304
6652 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX                                                   1
6653 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3                                                            0x0305
6654 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX                                                   1
6655 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0                                                            0x0306
6656 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX                                                   1
6657 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1                                                            0x0307
6658 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX                                                   1
6659 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2                                                            0x0308
6660 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX                                                   1
6661 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3                                                            0x0309
6662 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX                                                   1
6663 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0                                                            0x030a
6664 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX                                                   1
6665 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1                                                            0x030b
6666 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX                                                   1
6667 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2                                                            0x030c
6668 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX                                                   1
6669 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3                                                            0x030d
6670 #define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX                                                   1
6671 #define mmPA_SC_AA_MASK_X0Y0_X1Y0                                                                      0x030e
6672 #define mmPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX                                                             1
6673 #define mmPA_SC_AA_MASK_X0Y1_X1Y1                                                                      0x030f
6674 #define mmPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX                                                             1
6675 #define mmPA_SC_SHADER_CONTROL                                                                         0x0310
6676 #define mmPA_SC_SHADER_CONTROL_BASE_IDX                                                                1
6677 #define mmPA_SC_BINNER_CNTL_0                                                                          0x0311
6678 #define mmPA_SC_BINNER_CNTL_0_BASE_IDX                                                                 1
6679 #define mmPA_SC_BINNER_CNTL_1                                                                          0x0312
6680 #define mmPA_SC_BINNER_CNTL_1_BASE_IDX                                                                 1
6681 #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL                                                        0x0313
6682 #define mmPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX                                               1
6683 #define mmPA_SC_NGG_MODE_CNTL                                                                          0x0314
6684 #define mmPA_SC_NGG_MODE_CNTL_BASE_IDX                                                                 1
6685 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL                                                                  0x0316
6686 #define mmVGT_VERTEX_REUSE_BLOCK_CNTL_BASE_IDX                                                         1
6687 #define mmVGT_OUT_DEALLOC_CNTL                                                                         0x0317
6688 #define mmVGT_OUT_DEALLOC_CNTL_BASE_IDX                                                                1
6689 #define mmCB_COLOR0_BASE                                                                               0x0318
6690 #define mmCB_COLOR0_BASE_BASE_IDX                                                                      1
6691 #define mmCB_COLOR0_PITCH                                                                              0x0319
6692 #define mmCB_COLOR0_PITCH_BASE_IDX                                                                     1
6693 #define mmCB_COLOR0_SLICE                                                                              0x031a
6694 #define mmCB_COLOR0_SLICE_BASE_IDX                                                                     1
6695 #define mmCB_COLOR0_VIEW                                                                               0x031b
6696 #define mmCB_COLOR0_VIEW_BASE_IDX                                                                      1
6697 #define mmCB_COLOR0_INFO                                                                               0x031c
6698 #define mmCB_COLOR0_INFO_BASE_IDX                                                                      1
6699 #define mmCB_COLOR0_ATTRIB                                                                             0x031d
6700 #define mmCB_COLOR0_ATTRIB_BASE_IDX                                                                    1
6701 #define mmCB_COLOR0_DCC_CONTROL                                                                        0x031e
6702 #define mmCB_COLOR0_DCC_CONTROL_BASE_IDX                                                               1
6703 #define mmCB_COLOR0_CMASK                                                                              0x031f
6704 #define mmCB_COLOR0_CMASK_BASE_IDX                                                                     1
6705 #define mmCB_COLOR0_CMASK_SLICE                                                                        0x0320
6706 #define mmCB_COLOR0_CMASK_SLICE_BASE_IDX                                                               1
6707 #define mmCB_COLOR0_FMASK                                                                              0x0321
6708 #define mmCB_COLOR0_FMASK_BASE_IDX                                                                     1
6709 #define mmCB_COLOR0_FMASK_SLICE                                                                        0x0322
6710 #define mmCB_COLOR0_FMASK_SLICE_BASE_IDX                                                               1
6711 #define mmCB_COLOR0_CLEAR_WORD0                                                                        0x0323
6712 #define mmCB_COLOR0_CLEAR_WORD0_BASE_IDX                                                               1
6713 #define mmCB_COLOR0_CLEAR_WORD1                                                                        0x0324
6714 #define mmCB_COLOR0_CLEAR_WORD1_BASE_IDX                                                               1
6715 #define mmCB_COLOR0_DCC_BASE                                                                           0x0325
6716 #define mmCB_COLOR0_DCC_BASE_BASE_IDX                                                                  1
6717 #define mmCB_COLOR1_BASE                                                                               0x0327
6718 #define mmCB_COLOR1_BASE_BASE_IDX                                                                      1
6719 #define mmCB_COLOR1_PITCH                                                                              0x0328
6720 #define mmCB_COLOR1_PITCH_BASE_IDX                                                                     1
6721 #define mmCB_COLOR1_SLICE                                                                              0x0329
6722 #define mmCB_COLOR1_SLICE_BASE_IDX                                                                     1
6723 #define mmCB_COLOR1_VIEW                                                                               0x032a
6724 #define mmCB_COLOR1_VIEW_BASE_IDX                                                                      1
6725 #define mmCB_COLOR1_INFO                                                                               0x032b
6726 #define mmCB_COLOR1_INFO_BASE_IDX                                                                      1
6727 #define mmCB_COLOR1_ATTRIB                                                                             0x032c
6728 #define mmCB_COLOR1_ATTRIB_BASE_IDX                                                                    1
6729 #define mmCB_COLOR1_DCC_CONTROL                                                                        0x032d
6730 #define mmCB_COLOR1_DCC_CONTROL_BASE_IDX                                                               1
6731 #define mmCB_COLOR1_CMASK                                                                              0x032e
6732 #define mmCB_COLOR1_CMASK_BASE_IDX                                                                     1
6733 #define mmCB_COLOR1_CMASK_SLICE                                                                        0x032f
6734 #define mmCB_COLOR1_CMASK_SLICE_BASE_IDX                                                               1
6735 #define mmCB_COLOR1_FMASK                                                                              0x0330
6736 #define mmCB_COLOR1_FMASK_BASE_IDX                                                                     1
6737 #define mmCB_COLOR1_FMASK_SLICE                                                                        0x0331
6738 #define mmCB_COLOR1_FMASK_SLICE_BASE_IDX                                                               1
6739 #define mmCB_COLOR1_CLEAR_WORD0                                                                        0x0332
6740 #define mmCB_COLOR1_CLEAR_WORD0_BASE_IDX                                                               1
6741 #define mmCB_COLOR1_CLEAR_WORD1                                                                        0x0333
6742 #define mmCB_COLOR1_CLEAR_WORD1_BASE_IDX                                                               1
6743 #define mmCB_COLOR1_DCC_BASE                                                                           0x0334
6744 #define mmCB_COLOR1_DCC_BASE_BASE_IDX                                                                  1
6745 #define mmCB_COLOR2_BASE                                                                               0x0336
6746 #define mmCB_COLOR2_BASE_BASE_IDX                                                                      1
6747 #define mmCB_COLOR2_PITCH                                                                              0x0337
6748 #define mmCB_COLOR2_PITCH_BASE_IDX                                                                     1
6749 #define mmCB_COLOR2_SLICE                                                                              0x0338
6750 #define mmCB_COLOR2_SLICE_BASE_IDX                                                                     1
6751 #define mmCB_COLOR2_VIEW                                                                               0x0339
6752 #define mmCB_COLOR2_VIEW_BASE_IDX                                                                      1
6753 #define mmCB_COLOR2_INFO                                                                               0x033a
6754 #define mmCB_COLOR2_INFO_BASE_IDX                                                                      1
6755 #define mmCB_COLOR2_ATTRIB                                                                             0x033b
6756 #define mmCB_COLOR2_ATTRIB_BASE_IDX                                                                    1
6757 #define mmCB_COLOR2_DCC_CONTROL                                                                        0x033c
6758 #define mmCB_COLOR2_DCC_CONTROL_BASE_IDX                                                               1
6759 #define mmCB_COLOR2_CMASK                                                                              0x033d
6760 #define mmCB_COLOR2_CMASK_BASE_IDX                                                                     1
6761 #define mmCB_COLOR2_CMASK_SLICE                                                                        0x033e
6762 #define mmCB_COLOR2_CMASK_SLICE_BASE_IDX                                                               1
6763 #define mmCB_COLOR2_FMASK                                                                              0x033f
6764 #define mmCB_COLOR2_FMASK_BASE_IDX                                                                     1
6765 #define mmCB_COLOR2_FMASK_SLICE                                                                        0x0340
6766 #define mmCB_COLOR2_FMASK_SLICE_BASE_IDX                                                               1
6767 #define mmCB_COLOR2_CLEAR_WORD0                                                                        0x0341
6768 #define mmCB_COLOR2_CLEAR_WORD0_BASE_IDX                                                               1
6769 #define mmCB_COLOR2_CLEAR_WORD1                                                                        0x0342
6770 #define mmCB_COLOR2_CLEAR_WORD1_BASE_IDX                                                               1
6771 #define mmCB_COLOR2_DCC_BASE                                                                           0x0343
6772 #define mmCB_COLOR2_DCC_BASE_BASE_IDX                                                                  1
6773 #define mmCB_COLOR3_BASE                                                                               0x0345
6774 #define mmCB_COLOR3_BASE_BASE_IDX                                                                      1
6775 #define mmCB_COLOR3_PITCH                                                                              0x0346
6776 #define mmCB_COLOR3_PITCH_BASE_IDX                                                                     1
6777 #define mmCB_COLOR3_SLICE                                                                              0x0347
6778 #define mmCB_COLOR3_SLICE_BASE_IDX                                                                     1
6779 #define mmCB_COLOR3_VIEW                                                                               0x0348
6780 #define mmCB_COLOR3_VIEW_BASE_IDX                                                                      1
6781 #define mmCB_COLOR3_INFO                                                                               0x0349
6782 #define mmCB_COLOR3_INFO_BASE_IDX                                                                      1
6783 #define mmCB_COLOR3_ATTRIB                                                                             0x034a
6784 #define mmCB_COLOR3_ATTRIB_BASE_IDX                                                                    1
6785 #define mmCB_COLOR3_DCC_CONTROL                                                                        0x034b
6786 #define mmCB_COLOR3_DCC_CONTROL_BASE_IDX                                                               1
6787 #define mmCB_COLOR3_CMASK                                                                              0x034c
6788 #define mmCB_COLOR3_CMASK_BASE_IDX                                                                     1
6789 #define mmCB_COLOR3_CMASK_SLICE                                                                        0x034d
6790 #define mmCB_COLOR3_CMASK_SLICE_BASE_IDX                                                               1
6791 #define mmCB_COLOR3_FMASK                                                                              0x034e
6792 #define mmCB_COLOR3_FMASK_BASE_IDX                                                                     1
6793 #define mmCB_COLOR3_FMASK_SLICE                                                                        0x034f
6794 #define mmCB_COLOR3_FMASK_SLICE_BASE_IDX                                                               1
6795 #define mmCB_COLOR3_CLEAR_WORD0                                                                        0x0350
6796 #define mmCB_COLOR3_CLEAR_WORD0_BASE_IDX                                                               1
6797 #define mmCB_COLOR3_CLEAR_WORD1                                                                        0x0351
6798 #define mmCB_COLOR3_CLEAR_WORD1_BASE_IDX                                                               1
6799 #define mmCB_COLOR3_DCC_BASE                                                                           0x0352
6800 #define mmCB_COLOR3_DCC_BASE_BASE_IDX                                                                  1
6801 #define mmCB_COLOR4_BASE                                                                               0x0354
6802 #define mmCB_COLOR4_BASE_BASE_IDX                                                                      1
6803 #define mmCB_COLOR4_PITCH                                                                              0x0355
6804 #define mmCB_COLOR4_PITCH_BASE_IDX                                                                     1
6805 #define mmCB_COLOR4_SLICE                                                                              0x0356
6806 #define mmCB_COLOR4_SLICE_BASE_IDX                                                                     1
6807 #define mmCB_COLOR4_VIEW                                                                               0x0357
6808 #define mmCB_COLOR4_VIEW_BASE_IDX                                                                      1
6809 #define mmCB_COLOR4_INFO                                                                               0x0358
6810 #define mmCB_COLOR4_INFO_BASE_IDX                                                                      1
6811 #define mmCB_COLOR4_ATTRIB                                                                             0x0359
6812 #define mmCB_COLOR4_ATTRIB_BASE_IDX                                                                    1
6813 #define mmCB_COLOR4_DCC_CONTROL                                                                        0x035a
6814 #define mmCB_COLOR4_DCC_CONTROL_BASE_IDX                                                               1
6815 #define mmCB_COLOR4_CMASK                                                                              0x035b
6816 #define mmCB_COLOR4_CMASK_BASE_IDX                                                                     1
6817 #define mmCB_COLOR4_CMASK_SLICE                                                                        0x035c
6818 #define mmCB_COLOR4_CMASK_SLICE_BASE_IDX                                                               1
6819 #define mmCB_COLOR4_FMASK                                                                              0x035d
6820 #define mmCB_COLOR4_FMASK_BASE_IDX                                                                     1
6821 #define mmCB_COLOR4_FMASK_SLICE                                                                        0x035e
6822 #define mmCB_COLOR4_FMASK_SLICE_BASE_IDX                                                               1
6823 #define mmCB_COLOR4_CLEAR_WORD0                                                                        0x035f
6824 #define mmCB_COLOR4_CLEAR_WORD0_BASE_IDX                                                               1
6825 #define mmCB_COLOR4_CLEAR_WORD1                                                                        0x0360
6826 #define mmCB_COLOR4_CLEAR_WORD1_BASE_IDX                                                               1
6827 #define mmCB_COLOR4_DCC_BASE                                                                           0x0361
6828 #define mmCB_COLOR4_DCC_BASE_BASE_IDX                                                                  1
6829 #define mmCB_COLOR5_BASE                                                                               0x0363
6830 #define mmCB_COLOR5_BASE_BASE_IDX                                                                      1
6831 #define mmCB_COLOR5_PITCH                                                                              0x0364
6832 #define mmCB_COLOR5_PITCH_BASE_IDX                                                                     1
6833 #define mmCB_COLOR5_SLICE                                                                              0x0365
6834 #define mmCB_COLOR5_SLICE_BASE_IDX                                                                     1
6835 #define mmCB_COLOR5_VIEW                                                                               0x0366
6836 #define mmCB_COLOR5_VIEW_BASE_IDX                                                                      1
6837 #define mmCB_COLOR5_INFO                                                                               0x0367
6838 #define mmCB_COLOR5_INFO_BASE_IDX                                                                      1
6839 #define mmCB_COLOR5_ATTRIB                                                                             0x0368
6840 #define mmCB_COLOR5_ATTRIB_BASE_IDX                                                                    1
6841 #define mmCB_COLOR5_DCC_CONTROL                                                                        0x0369
6842 #define mmCB_COLOR5_DCC_CONTROL_BASE_IDX                                                               1
6843 #define mmCB_COLOR5_CMASK                                                                              0x036a
6844 #define mmCB_COLOR5_CMASK_BASE_IDX                                                                     1
6845 #define mmCB_COLOR5_CMASK_SLICE                                                                        0x036b
6846 #define mmCB_COLOR5_CMASK_SLICE_BASE_IDX                                                               1
6847 #define mmCB_COLOR5_FMASK                                                                              0x036c
6848 #define mmCB_COLOR5_FMASK_BASE_IDX                                                                     1
6849 #define mmCB_COLOR5_FMASK_SLICE                                                                        0x036d
6850 #define mmCB_COLOR5_FMASK_SLICE_BASE_IDX                                                               1
6851 #define mmCB_COLOR5_CLEAR_WORD0                                                                        0x036e
6852 #define mmCB_COLOR5_CLEAR_WORD0_BASE_IDX                                                               1
6853 #define mmCB_COLOR5_CLEAR_WORD1                                                                        0x036f
6854 #define mmCB_COLOR5_CLEAR_WORD1_BASE_IDX                                                               1
6855 #define mmCB_COLOR5_DCC_BASE                                                                           0x0370
6856 #define mmCB_COLOR5_DCC_BASE_BASE_IDX                                                                  1
6857 #define mmCB_COLOR6_BASE                                                                               0x0372
6858 #define mmCB_COLOR6_BASE_BASE_IDX                                                                      1
6859 #define mmCB_COLOR6_PITCH                                                                              0x0373
6860 #define mmCB_COLOR6_PITCH_BASE_IDX                                                                     1
6861 #define mmCB_COLOR6_SLICE                                                                              0x0374
6862 #define mmCB_COLOR6_SLICE_BASE_IDX                                                                     1
6863 #define mmCB_COLOR6_VIEW                                                                               0x0375
6864 #define mmCB_COLOR6_VIEW_BASE_IDX                                                                      1
6865 #define mmCB_COLOR6_INFO                                                                               0x0376
6866 #define mmCB_COLOR6_INFO_BASE_IDX                                                                      1
6867 #define mmCB_COLOR6_ATTRIB                                                                             0x0377
6868 #define mmCB_COLOR6_ATTRIB_BASE_IDX                                                                    1
6869 #define mmCB_COLOR6_DCC_CONTROL                                                                        0x0378
6870 #define mmCB_COLOR6_DCC_CONTROL_BASE_IDX                                                               1
6871 #define mmCB_COLOR6_CMASK                                                                              0x0379
6872 #define mmCB_COLOR6_CMASK_BASE_IDX                                                                     1
6873 #define mmCB_COLOR6_CMASK_SLICE                                                                        0x037a
6874 #define mmCB_COLOR6_CMASK_SLICE_BASE_IDX                                                               1
6875 #define mmCB_COLOR6_FMASK                                                                              0x037b
6876 #define mmCB_COLOR6_FMASK_BASE_IDX                                                                     1
6877 #define mmCB_COLOR6_FMASK_SLICE                                                                        0x037c
6878 #define mmCB_COLOR6_FMASK_SLICE_BASE_IDX                                                               1
6879 #define mmCB_COLOR6_CLEAR_WORD0                                                                        0x037d
6880 #define mmCB_COLOR6_CLEAR_WORD0_BASE_IDX                                                               1
6881 #define mmCB_COLOR6_CLEAR_WORD1                                                                        0x037e
6882 #define mmCB_COLOR6_CLEAR_WORD1_BASE_IDX                                                               1
6883 #define mmCB_COLOR6_DCC_BASE                                                                           0x037f
6884 #define mmCB_COLOR6_DCC_BASE_BASE_IDX                                                                  1
6885 #define mmCB_COLOR7_BASE                                                                               0x0381
6886 #define mmCB_COLOR7_BASE_BASE_IDX                                                                      1
6887 #define mmCB_COLOR7_PITCH                                                                              0x0382
6888 #define mmCB_COLOR7_PITCH_BASE_IDX                                                                     1
6889 #define mmCB_COLOR7_SLICE                                                                              0x0383
6890 #define mmCB_COLOR7_SLICE_BASE_IDX                                                                     1
6891 #define mmCB_COLOR7_VIEW                                                                               0x0384
6892 #define mmCB_COLOR7_VIEW_BASE_IDX                                                                      1
6893 #define mmCB_COLOR7_INFO                                                                               0x0385
6894 #define mmCB_COLOR7_INFO_BASE_IDX                                                                      1
6895 #define mmCB_COLOR7_ATTRIB                                                                             0x0386
6896 #define mmCB_COLOR7_ATTRIB_BASE_IDX                                                                    1
6897 #define mmCB_COLOR7_DCC_CONTROL                                                                        0x0387
6898 #define mmCB_COLOR7_DCC_CONTROL_BASE_IDX                                                               1
6899 #define mmCB_COLOR7_CMASK                                                                              0x0388
6900 #define mmCB_COLOR7_CMASK_BASE_IDX                                                                     1
6901 #define mmCB_COLOR7_CMASK_SLICE                                                                        0x0389
6902 #define mmCB_COLOR7_CMASK_SLICE_BASE_IDX                                                               1
6903 #define mmCB_COLOR7_FMASK                                                                              0x038a
6904 #define mmCB_COLOR7_FMASK_BASE_IDX                                                                     1
6905 #define mmCB_COLOR7_FMASK_SLICE                                                                        0x038b
6906 #define mmCB_COLOR7_FMASK_SLICE_BASE_IDX                                                               1
6907 #define mmCB_COLOR7_CLEAR_WORD0                                                                        0x038c
6908 #define mmCB_COLOR7_CLEAR_WORD0_BASE_IDX                                                               1
6909 #define mmCB_COLOR7_CLEAR_WORD1                                                                        0x038d
6910 #define mmCB_COLOR7_CLEAR_WORD1_BASE_IDX                                                               1
6911 #define mmCB_COLOR7_DCC_BASE                                                                           0x038e
6912 #define mmCB_COLOR7_DCC_BASE_BASE_IDX                                                                  1
6913 #define mmCB_COLOR0_BASE_EXT                                                                           0x0390
6914 #define mmCB_COLOR0_BASE_EXT_BASE_IDX                                                                  1
6915 #define mmCB_COLOR1_BASE_EXT                                                                           0x0391
6916 #define mmCB_COLOR1_BASE_EXT_BASE_IDX                                                                  1
6917 #define mmCB_COLOR2_BASE_EXT                                                                           0x0392
6918 #define mmCB_COLOR2_BASE_EXT_BASE_IDX                                                                  1
6919 #define mmCB_COLOR3_BASE_EXT                                                                           0x0393
6920 #define mmCB_COLOR3_BASE_EXT_BASE_IDX                                                                  1
6921 #define mmCB_COLOR4_BASE_EXT                                                                           0x0394
6922 #define mmCB_COLOR4_BASE_EXT_BASE_IDX                                                                  1
6923 #define mmCB_COLOR5_BASE_EXT                                                                           0x0395
6924 #define mmCB_COLOR5_BASE_EXT_BASE_IDX                                                                  1
6925 #define mmCB_COLOR6_BASE_EXT                                                                           0x0396
6926 #define mmCB_COLOR6_BASE_EXT_BASE_IDX                                                                  1
6927 #define mmCB_COLOR7_BASE_EXT                                                                           0x0397
6928 #define mmCB_COLOR7_BASE_EXT_BASE_IDX                                                                  1
6929 #define mmCB_COLOR0_CMASK_BASE_EXT                                                                     0x0398
6930 #define mmCB_COLOR0_CMASK_BASE_EXT_BASE_IDX                                                            1
6931 #define mmCB_COLOR1_CMASK_BASE_EXT                                                                     0x0399
6932 #define mmCB_COLOR1_CMASK_BASE_EXT_BASE_IDX                                                            1
6933 #define mmCB_COLOR2_CMASK_BASE_EXT                                                                     0x039a
6934 #define mmCB_COLOR2_CMASK_BASE_EXT_BASE_IDX                                                            1
6935 #define mmCB_COLOR3_CMASK_BASE_EXT                                                                     0x039b
6936 #define mmCB_COLOR3_CMASK_BASE_EXT_BASE_IDX                                                            1
6937 #define mmCB_COLOR4_CMASK_BASE_EXT                                                                     0x039c
6938 #define mmCB_COLOR4_CMASK_BASE_EXT_BASE_IDX                                                            1
6939 #define mmCB_COLOR5_CMASK_BASE_EXT                                                                     0x039d
6940 #define mmCB_COLOR5_CMASK_BASE_EXT_BASE_IDX                                                            1
6941 #define mmCB_COLOR6_CMASK_BASE_EXT                                                                     0x039e
6942 #define mmCB_COLOR6_CMASK_BASE_EXT_BASE_IDX                                                            1
6943 #define mmCB_COLOR7_CMASK_BASE_EXT                                                                     0x039f
6944 #define mmCB_COLOR7_CMASK_BASE_EXT_BASE_IDX                                                            1
6945 #define mmCB_COLOR0_FMASK_BASE_EXT                                                                     0x03a0
6946 #define mmCB_COLOR0_FMASK_BASE_EXT_BASE_IDX                                                            1
6947 #define mmCB_COLOR1_FMASK_BASE_EXT                                                                     0x03a1
6948 #define mmCB_COLOR1_FMASK_BASE_EXT_BASE_IDX                                                            1
6949 #define mmCB_COLOR2_FMASK_BASE_EXT                                                                     0x03a2
6950 #define mmCB_COLOR2_FMASK_BASE_EXT_BASE_IDX                                                            1
6951 #define mmCB_COLOR3_FMASK_BASE_EXT                                                                     0x03a3
6952 #define mmCB_COLOR3_FMASK_BASE_EXT_BASE_IDX                                                            1
6953 #define mmCB_COLOR4_FMASK_BASE_EXT                                                                     0x03a4
6954 #define mmCB_COLOR4_FMASK_BASE_EXT_BASE_IDX                                                            1
6955 #define mmCB_COLOR5_FMASK_BASE_EXT                                                                     0x03a5
6956 #define mmCB_COLOR5_FMASK_BASE_EXT_BASE_IDX                                                            1
6957 #define mmCB_COLOR6_FMASK_BASE_EXT                                                                     0x03a6
6958 #define mmCB_COLOR6_FMASK_BASE_EXT_BASE_IDX                                                            1
6959 #define mmCB_COLOR7_FMASK_BASE_EXT                                                                     0x03a7
6960 #define mmCB_COLOR7_FMASK_BASE_EXT_BASE_IDX                                                            1
6961 #define mmCB_COLOR0_DCC_BASE_EXT                                                                       0x03a8
6962 #define mmCB_COLOR0_DCC_BASE_EXT_BASE_IDX                                                              1
6963 #define mmCB_COLOR1_DCC_BASE_EXT                                                                       0x03a9
6964 #define mmCB_COLOR1_DCC_BASE_EXT_BASE_IDX                                                              1
6965 #define mmCB_COLOR2_DCC_BASE_EXT                                                                       0x03aa
6966 #define mmCB_COLOR2_DCC_BASE_EXT_BASE_IDX                                                              1
6967 #define mmCB_COLOR3_DCC_BASE_EXT                                                                       0x03ab
6968 #define mmCB_COLOR3_DCC_BASE_EXT_BASE_IDX                                                              1
6969 #define mmCB_COLOR4_DCC_BASE_EXT                                                                       0x03ac
6970 #define mmCB_COLOR4_DCC_BASE_EXT_BASE_IDX                                                              1
6971 #define mmCB_COLOR5_DCC_BASE_EXT                                                                       0x03ad
6972 #define mmCB_COLOR5_DCC_BASE_EXT_BASE_IDX                                                              1
6973 #define mmCB_COLOR6_DCC_BASE_EXT                                                                       0x03ae
6974 #define mmCB_COLOR6_DCC_BASE_EXT_BASE_IDX                                                              1
6975 #define mmCB_COLOR7_DCC_BASE_EXT                                                                       0x03af
6976 #define mmCB_COLOR7_DCC_BASE_EXT_BASE_IDX                                                              1
6977 #define mmCB_COLOR0_ATTRIB2                                                                            0x03b0
6978 #define mmCB_COLOR0_ATTRIB2_BASE_IDX                                                                   1
6979 #define mmCB_COLOR1_ATTRIB2                                                                            0x03b1
6980 #define mmCB_COLOR1_ATTRIB2_BASE_IDX                                                                   1
6981 #define mmCB_COLOR2_ATTRIB2                                                                            0x03b2
6982 #define mmCB_COLOR2_ATTRIB2_BASE_IDX                                                                   1
6983 #define mmCB_COLOR3_ATTRIB2                                                                            0x03b3
6984 #define mmCB_COLOR3_ATTRIB2_BASE_IDX                                                                   1
6985 #define mmCB_COLOR4_ATTRIB2                                                                            0x03b4
6986 #define mmCB_COLOR4_ATTRIB2_BASE_IDX                                                                   1
6987 #define mmCB_COLOR5_ATTRIB2                                                                            0x03b5
6988 #define mmCB_COLOR5_ATTRIB2_BASE_IDX                                                                   1
6989 #define mmCB_COLOR6_ATTRIB2                                                                            0x03b6
6990 #define mmCB_COLOR6_ATTRIB2_BASE_IDX                                                                   1
6991 #define mmCB_COLOR7_ATTRIB2                                                                            0x03b7
6992 #define mmCB_COLOR7_ATTRIB2_BASE_IDX                                                                   1
6993 #define mmCB_COLOR0_ATTRIB3                                                                            0x03b8
6994 #define mmCB_COLOR0_ATTRIB3_BASE_IDX                                                                   1
6995 #define mmCB_COLOR1_ATTRIB3                                                                            0x03b9
6996 #define mmCB_COLOR1_ATTRIB3_BASE_IDX                                                                   1
6997 #define mmCB_COLOR2_ATTRIB3                                                                            0x03ba
6998 #define mmCB_COLOR2_ATTRIB3_BASE_IDX                                                                   1
6999 #define mmCB_COLOR3_ATTRIB3                                                                            0x03bb
7000 #define mmCB_COLOR3_ATTRIB3_BASE_IDX                                                                   1
7001 #define mmCB_COLOR4_ATTRIB3                                                                            0x03bc
7002 #define mmCB_COLOR4_ATTRIB3_BASE_IDX                                                                   1
7003 #define mmCB_COLOR5_ATTRIB3                                                                            0x03bd
7004 #define mmCB_COLOR5_ATTRIB3_BASE_IDX                                                                   1
7005 #define mmCB_COLOR6_ATTRIB3                                                                            0x03be
7006 #define mmCB_COLOR6_ATTRIB3_BASE_IDX                                                                   1
7007 #define mmCB_COLOR7_ATTRIB3                                                                            0x03bf
7008 #define mmCB_COLOR7_ATTRIB3_BASE_IDX                                                                   1
7009 
7010 
7011 // addressBlock: gc_gfxudec
7012 // base address: 0x30000
7013 #define mmCP_EOP_DONE_ADDR_LO                                                                          0x2000
7014 #define mmCP_EOP_DONE_ADDR_LO_BASE_IDX                                                                 1
7015 #define mmCP_EOP_DONE_ADDR_HI                                                                          0x2001
7016 #define mmCP_EOP_DONE_ADDR_HI_BASE_IDX                                                                 1
7017 #define mmCP_EOP_DONE_DATA_LO                                                                          0x2002
7018 #define mmCP_EOP_DONE_DATA_LO_BASE_IDX                                                                 1
7019 #define mmCP_EOP_DONE_DATA_HI                                                                          0x2003
7020 #define mmCP_EOP_DONE_DATA_HI_BASE_IDX                                                                 1
7021 #define mmCP_EOP_LAST_FENCE_LO                                                                         0x2004
7022 #define mmCP_EOP_LAST_FENCE_LO_BASE_IDX                                                                1
7023 #define mmCP_EOP_LAST_FENCE_HI                                                                         0x2005
7024 #define mmCP_EOP_LAST_FENCE_HI_BASE_IDX                                                                1
7025 #define mmCP_STREAM_OUT_ADDR_LO                                                                        0x2006
7026 #define mmCP_STREAM_OUT_ADDR_LO_BASE_IDX                                                               1
7027 #define mmCP_STREAM_OUT_ADDR_HI                                                                        0x2007
7028 #define mmCP_STREAM_OUT_ADDR_HI_BASE_IDX                                                               1
7029 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO                                                                0x2008
7030 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO_BASE_IDX                                                       1
7031 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI                                                                0x2009
7032 #define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI_BASE_IDX                                                       1
7033 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO                                                                 0x200a
7034 #define mmCP_NUM_PRIM_NEEDED_COUNT0_LO_BASE_IDX                                                        1
7035 #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI                                                                 0x200b
7036 #define mmCP_NUM_PRIM_NEEDED_COUNT0_HI_BASE_IDX                                                        1
7037 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO                                                                0x200c
7038 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO_BASE_IDX                                                       1
7039 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI                                                                0x200d
7040 #define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI_BASE_IDX                                                       1
7041 #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO                                                                 0x200e
7042 #define mmCP_NUM_PRIM_NEEDED_COUNT1_LO_BASE_IDX                                                        1
7043 #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI                                                                 0x200f
7044 #define mmCP_NUM_PRIM_NEEDED_COUNT1_HI_BASE_IDX                                                        1
7045 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO                                                                0x2010
7046 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO_BASE_IDX                                                       1
7047 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI                                                                0x2011
7048 #define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI_BASE_IDX                                                       1
7049 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO                                                                 0x2012
7050 #define mmCP_NUM_PRIM_NEEDED_COUNT2_LO_BASE_IDX                                                        1
7051 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI                                                                 0x2013
7052 #define mmCP_NUM_PRIM_NEEDED_COUNT2_HI_BASE_IDX                                                        1
7053 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO                                                                0x2014
7054 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO_BASE_IDX                                                       1
7055 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI                                                                0x2015
7056 #define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI_BASE_IDX                                                       1
7057 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO                                                                 0x2016
7058 #define mmCP_NUM_PRIM_NEEDED_COUNT3_LO_BASE_IDX                                                        1
7059 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI                                                                 0x2017
7060 #define mmCP_NUM_PRIM_NEEDED_COUNT3_HI_BASE_IDX                                                        1
7061 #define mmCP_PIPE_STATS_ADDR_LO                                                                        0x2018
7062 #define mmCP_PIPE_STATS_ADDR_LO_BASE_IDX                                                               1
7063 #define mmCP_PIPE_STATS_ADDR_HI                                                                        0x2019
7064 #define mmCP_PIPE_STATS_ADDR_HI_BASE_IDX                                                               1
7065 #define mmCP_VGT_IAVERT_COUNT_LO                                                                       0x201a
7066 #define mmCP_VGT_IAVERT_COUNT_LO_BASE_IDX                                                              1
7067 #define mmCP_VGT_IAVERT_COUNT_HI                                                                       0x201b
7068 #define mmCP_VGT_IAVERT_COUNT_HI_BASE_IDX                                                              1
7069 #define mmCP_VGT_IAPRIM_COUNT_LO                                                                       0x201c
7070 #define mmCP_VGT_IAPRIM_COUNT_LO_BASE_IDX                                                              1
7071 #define mmCP_VGT_IAPRIM_COUNT_HI                                                                       0x201d
7072 #define mmCP_VGT_IAPRIM_COUNT_HI_BASE_IDX                                                              1
7073 #define mmCP_VGT_GSPRIM_COUNT_LO                                                                       0x201e
7074 #define mmCP_VGT_GSPRIM_COUNT_LO_BASE_IDX                                                              1
7075 #define mmCP_VGT_GSPRIM_COUNT_HI                                                                       0x201f
7076 #define mmCP_VGT_GSPRIM_COUNT_HI_BASE_IDX                                                              1
7077 #define mmCP_VGT_VSINVOC_COUNT_LO                                                                      0x2020
7078 #define mmCP_VGT_VSINVOC_COUNT_LO_BASE_IDX                                                             1
7079 #define mmCP_VGT_VSINVOC_COUNT_HI                                                                      0x2021
7080 #define mmCP_VGT_VSINVOC_COUNT_HI_BASE_IDX                                                             1
7081 #define mmCP_VGT_GSINVOC_COUNT_LO                                                                      0x2022
7082 #define mmCP_VGT_GSINVOC_COUNT_LO_BASE_IDX                                                             1
7083 #define mmCP_VGT_GSINVOC_COUNT_HI                                                                      0x2023
7084 #define mmCP_VGT_GSINVOC_COUNT_HI_BASE_IDX                                                             1
7085 #define mmCP_VGT_HSINVOC_COUNT_LO                                                                      0x2024
7086 #define mmCP_VGT_HSINVOC_COUNT_LO_BASE_IDX                                                             1
7087 #define mmCP_VGT_HSINVOC_COUNT_HI                                                                      0x2025
7088 #define mmCP_VGT_HSINVOC_COUNT_HI_BASE_IDX                                                             1
7089 #define mmCP_VGT_DSINVOC_COUNT_LO                                                                      0x2026
7090 #define mmCP_VGT_DSINVOC_COUNT_LO_BASE_IDX                                                             1
7091 #define mmCP_VGT_DSINVOC_COUNT_HI                                                                      0x2027
7092 #define mmCP_VGT_DSINVOC_COUNT_HI_BASE_IDX                                                             1
7093 #define mmCP_PA_CINVOC_COUNT_LO                                                                        0x2028
7094 #define mmCP_PA_CINVOC_COUNT_LO_BASE_IDX                                                               1
7095 #define mmCP_PA_CINVOC_COUNT_HI                                                                        0x2029
7096 #define mmCP_PA_CINVOC_COUNT_HI_BASE_IDX                                                               1
7097 #define mmCP_PA_CPRIM_COUNT_LO                                                                         0x202a
7098 #define mmCP_PA_CPRIM_COUNT_LO_BASE_IDX                                                                1
7099 #define mmCP_PA_CPRIM_COUNT_HI                                                                         0x202b
7100 #define mmCP_PA_CPRIM_COUNT_HI_BASE_IDX                                                                1
7101 #define mmCP_SC_PSINVOC_COUNT0_LO                                                                      0x202c
7102 #define mmCP_SC_PSINVOC_COUNT0_LO_BASE_IDX                                                             1
7103 #define mmCP_SC_PSINVOC_COUNT0_HI                                                                      0x202d
7104 #define mmCP_SC_PSINVOC_COUNT0_HI_BASE_IDX                                                             1
7105 #define mmCP_SC_PSINVOC_COUNT1_LO                                                                      0x202e
7106 #define mmCP_SC_PSINVOC_COUNT1_LO_BASE_IDX                                                             1
7107 #define mmCP_SC_PSINVOC_COUNT1_HI                                                                      0x202f
7108 #define mmCP_SC_PSINVOC_COUNT1_HI_BASE_IDX                                                             1
7109 #define mmCP_VGT_CSINVOC_COUNT_LO                                                                      0x2030
7110 #define mmCP_VGT_CSINVOC_COUNT_LO_BASE_IDX                                                             1
7111 #define mmCP_VGT_CSINVOC_COUNT_HI                                                                      0x2031
7112 #define mmCP_VGT_CSINVOC_COUNT_HI_BASE_IDX                                                             1
7113 #define mmCP_EOP_DONE_DOORBELL                                                                         0x2032
7114 #define mmCP_EOP_DONE_DOORBELL_BASE_IDX                                                                1
7115 #define mmCP_STREAM_OUT_DOORBELL                                                                       0x2033
7116 #define mmCP_STREAM_OUT_DOORBELL_BASE_IDX                                                              1
7117 #define mmCP_SEM_DOORBELL                                                                              0x2034
7118 #define mmCP_SEM_DOORBELL_BASE_IDX                                                                     1
7119 #define mmCP_PIPE_STATS_CONTROL                                                                        0x203d
7120 #define mmCP_PIPE_STATS_CONTROL_BASE_IDX                                                               1
7121 #define mmCP_STREAM_OUT_CONTROL                                                                        0x203e
7122 #define mmCP_STREAM_OUT_CONTROL_BASE_IDX                                                               1
7123 #define mmCP_STRMOUT_CNTL                                                                              0x203f
7124 #define mmCP_STRMOUT_CNTL_BASE_IDX                                                                     1
7125 #define mmSCRATCH_REG0                                                                                 0x2040
7126 #define mmSCRATCH_REG0_BASE_IDX                                                                        1
7127 #define mmSCRATCH_REG1                                                                                 0x2041
7128 #define mmSCRATCH_REG1_BASE_IDX                                                                        1
7129 #define mmSCRATCH_REG2                                                                                 0x2042
7130 #define mmSCRATCH_REG2_BASE_IDX                                                                        1
7131 #define mmSCRATCH_REG3                                                                                 0x2043
7132 #define mmSCRATCH_REG3_BASE_IDX                                                                        1
7133 #define mmSCRATCH_REG4                                                                                 0x2044
7134 #define mmSCRATCH_REG4_BASE_IDX                                                                        1
7135 #define mmSCRATCH_REG5                                                                                 0x2045
7136 #define mmSCRATCH_REG5_BASE_IDX                                                                        1
7137 #define mmSCRATCH_REG6                                                                                 0x2046
7138 #define mmSCRATCH_REG6_BASE_IDX                                                                        1
7139 #define mmSCRATCH_REG7                                                                                 0x2047
7140 #define mmSCRATCH_REG7_BASE_IDX                                                                        1
7141 #define mmCP_PIPE_STATS_DOORBELL                                                                       0x2048
7142 #define mmCP_PIPE_STATS_DOORBELL_BASE_IDX                                                              1
7143 #define mmCP_APPEND_DDID_CNT                                                                           0x204b
7144 #define mmCP_APPEND_DDID_CNT_BASE_IDX                                                                  1
7145 #define mmCP_APPEND_DATA_HI                                                                            0x204c
7146 #define mmCP_APPEND_DATA_HI_BASE_IDX                                                                   1
7147 #define mmCP_APPEND_LAST_CS_FENCE_HI                                                                   0x204d
7148 #define mmCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX                                                          1
7149 #define mmCP_APPEND_LAST_PS_FENCE_HI                                                                   0x204e
7150 #define mmCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX                                                          1
7151 #define mmSCRATCH_UMSK                                                                                 0x2050
7152 #define mmSCRATCH_UMSK_BASE_IDX                                                                        1
7153 #define mmSCRATCH_ADDR                                                                                 0x2051
7154 #define mmSCRATCH_ADDR_BASE_IDX                                                                        1
7155 #define mmCP_PFP_ATOMIC_PREOP_LO                                                                       0x2052
7156 #define mmCP_PFP_ATOMIC_PREOP_LO_BASE_IDX                                                              1
7157 #define mmCP_PFP_ATOMIC_PREOP_HI                                                                       0x2053
7158 #define mmCP_PFP_ATOMIC_PREOP_HI_BASE_IDX                                                              1
7159 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO                                                                  0x2054
7160 #define mmCP_PFP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                         1
7161 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI                                                                  0x2055
7162 #define mmCP_PFP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                         1
7163 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO                                                                  0x2056
7164 #define mmCP_PFP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                         1
7165 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI                                                                  0x2057
7166 #define mmCP_PFP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                         1
7167 #define mmCP_APPEND_ADDR_LO                                                                            0x2058
7168 #define mmCP_APPEND_ADDR_LO_BASE_IDX                                                                   1
7169 #define mmCP_APPEND_ADDR_HI                                                                            0x2059
7170 #define mmCP_APPEND_ADDR_HI_BASE_IDX                                                                   1
7171 #define mmCP_APPEND_DATA                                                                               0x205a
7172 #define mmCP_APPEND_DATA_BASE_IDX                                                                      1
7173 #define mmCP_APPEND_DATA_LO                                                                            0x205a
7174 #define mmCP_APPEND_DATA_LO_BASE_IDX                                                                   1
7175 #define mmCP_APPEND_LAST_CS_FENCE                                                                      0x205b
7176 #define mmCP_APPEND_LAST_CS_FENCE_BASE_IDX                                                             1
7177 #define mmCP_APPEND_LAST_CS_FENCE_LO                                                                   0x205b
7178 #define mmCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX                                                          1
7179 #define mmCP_APPEND_LAST_PS_FENCE                                                                      0x205c
7180 #define mmCP_APPEND_LAST_PS_FENCE_BASE_IDX                                                             1
7181 #define mmCP_APPEND_LAST_PS_FENCE_LO                                                                   0x205c
7182 #define mmCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX                                                          1
7183 #define mmCP_ATOMIC_PREOP_LO                                                                           0x205d
7184 #define mmCP_ATOMIC_PREOP_LO_BASE_IDX                                                                  1
7185 #define mmCP_ME_ATOMIC_PREOP_LO                                                                        0x205d
7186 #define mmCP_ME_ATOMIC_PREOP_LO_BASE_IDX                                                               1
7187 #define mmCP_ATOMIC_PREOP_HI                                                                           0x205e
7188 #define mmCP_ATOMIC_PREOP_HI_BASE_IDX                                                                  1
7189 #define mmCP_ME_ATOMIC_PREOP_HI                                                                        0x205e
7190 #define mmCP_ME_ATOMIC_PREOP_HI_BASE_IDX                                                               1
7191 #define mmCP_GDS_ATOMIC0_PREOP_LO                                                                      0x205f
7192 #define mmCP_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                             1
7193 #define mmCP_ME_GDS_ATOMIC0_PREOP_LO                                                                   0x205f
7194 #define mmCP_ME_GDS_ATOMIC0_PREOP_LO_BASE_IDX                                                          1
7195 #define mmCP_GDS_ATOMIC0_PREOP_HI                                                                      0x2060
7196 #define mmCP_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                             1
7197 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI                                                                   0x2060
7198 #define mmCP_ME_GDS_ATOMIC0_PREOP_HI_BASE_IDX                                                          1
7199 #define mmCP_GDS_ATOMIC1_PREOP_LO                                                                      0x2061
7200 #define mmCP_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                             1
7201 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO                                                                   0x2061
7202 #define mmCP_ME_GDS_ATOMIC1_PREOP_LO_BASE_IDX                                                          1
7203 #define mmCP_GDS_ATOMIC1_PREOP_HI                                                                      0x2062
7204 #define mmCP_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                             1
7205 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI                                                                   0x2062
7206 #define mmCP_ME_GDS_ATOMIC1_PREOP_HI_BASE_IDX                                                          1
7207 #define mmCP_ME_MC_WADDR_LO                                                                            0x2069
7208 #define mmCP_ME_MC_WADDR_LO_BASE_IDX                                                                   1
7209 #define mmCP_ME_MC_WADDR_HI                                                                            0x206a
7210 #define mmCP_ME_MC_WADDR_HI_BASE_IDX                                                                   1
7211 #define mmCP_ME_MC_WDATA_LO                                                                            0x206b
7212 #define mmCP_ME_MC_WDATA_LO_BASE_IDX                                                                   1
7213 #define mmCP_ME_MC_WDATA_HI                                                                            0x206c
7214 #define mmCP_ME_MC_WDATA_HI_BASE_IDX                                                                   1
7215 #define mmCP_ME_MC_RADDR_LO                                                                            0x206d
7216 #define mmCP_ME_MC_RADDR_LO_BASE_IDX                                                                   1
7217 #define mmCP_ME_MC_RADDR_HI                                                                            0x206e
7218 #define mmCP_ME_MC_RADDR_HI_BASE_IDX                                                                   1
7219 #define mmCP_SEM_WAIT_TIMER                                                                            0x206f
7220 #define mmCP_SEM_WAIT_TIMER_BASE_IDX                                                                   1
7221 #define mmCP_SIG_SEM_ADDR_LO                                                                           0x2070
7222 #define mmCP_SIG_SEM_ADDR_LO_BASE_IDX                                                                  1
7223 #define mmCP_SIG_SEM_ADDR_HI                                                                           0x2071
7224 #define mmCP_SIG_SEM_ADDR_HI_BASE_IDX                                                                  1
7225 #define mmCP_WAIT_REG_MEM_TIMEOUT                                                                      0x2074
7226 #define mmCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX                                                             1
7227 #define mmCP_WAIT_SEM_ADDR_LO                                                                          0x2075
7228 #define mmCP_WAIT_SEM_ADDR_LO_BASE_IDX                                                                 1
7229 #define mmCP_WAIT_SEM_ADDR_HI                                                                          0x2076
7230 #define mmCP_WAIT_SEM_ADDR_HI_BASE_IDX                                                                 1
7231 #define mmCP_DMA_PFP_CONTROL                                                                           0x2077
7232 #define mmCP_DMA_PFP_CONTROL_BASE_IDX                                                                  1
7233 #define mmCP_DMA_ME_CONTROL                                                                            0x2078
7234 #define mmCP_DMA_ME_CONTROL_BASE_IDX                                                                   1
7235 #define mmCP_COHER_BASE_HI                                                                             0x2079
7236 #define mmCP_COHER_BASE_HI_BASE_IDX                                                                    1
7237 #define mmCP_COHER_START_DELAY                                                                         0x207b
7238 #define mmCP_COHER_START_DELAY_BASE_IDX                                                                1
7239 #define mmCP_COHER_CNTL                                                                                0x207c
7240 #define mmCP_COHER_CNTL_BASE_IDX                                                                       1
7241 #define mmCP_COHER_SIZE                                                                                0x207d
7242 #define mmCP_COHER_SIZE_BASE_IDX                                                                       1
7243 #define mmCP_COHER_BASE                                                                                0x207e
7244 #define mmCP_COHER_BASE_BASE_IDX                                                                       1
7245 #define mmCP_COHER_STATUS                                                                              0x207f
7246 #define mmCP_COHER_STATUS_BASE_IDX                                                                     1
7247 #define mmCP_DMA_ME_SRC_ADDR                                                                           0x2080
7248 #define mmCP_DMA_ME_SRC_ADDR_BASE_IDX                                                                  1
7249 #define mmCP_DMA_ME_SRC_ADDR_HI                                                                        0x2081
7250 #define mmCP_DMA_ME_SRC_ADDR_HI_BASE_IDX                                                               1
7251 #define mmCP_DMA_ME_DST_ADDR                                                                           0x2082
7252 #define mmCP_DMA_ME_DST_ADDR_BASE_IDX                                                                  1
7253 #define mmCP_DMA_ME_DST_ADDR_HI                                                                        0x2083
7254 #define mmCP_DMA_ME_DST_ADDR_HI_BASE_IDX                                                               1
7255 #define mmCP_DMA_ME_COMMAND                                                                            0x2084
7256 #define mmCP_DMA_ME_COMMAND_BASE_IDX                                                                   1
7257 #define mmCP_DMA_PFP_SRC_ADDR                                                                          0x2085
7258 #define mmCP_DMA_PFP_SRC_ADDR_BASE_IDX                                                                 1
7259 #define mmCP_DMA_PFP_SRC_ADDR_HI                                                                       0x2086
7260 #define mmCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX                                                              1
7261 #define mmCP_DMA_PFP_DST_ADDR                                                                          0x2087
7262 #define mmCP_DMA_PFP_DST_ADDR_BASE_IDX                                                                 1
7263 #define mmCP_DMA_PFP_DST_ADDR_HI                                                                       0x2088
7264 #define mmCP_DMA_PFP_DST_ADDR_HI_BASE_IDX                                                              1
7265 #define mmCP_DMA_PFP_COMMAND                                                                           0x2089
7266 #define mmCP_DMA_PFP_COMMAND_BASE_IDX                                                                  1
7267 #define mmCP_DMA_CNTL                                                                                  0x208a
7268 #define mmCP_DMA_CNTL_BASE_IDX                                                                         1
7269 #define mmCP_DMA_READ_TAGS                                                                             0x208b
7270 #define mmCP_DMA_READ_TAGS_BASE_IDX                                                                    1
7271 #define mmCP_COHER_SIZE_HI                                                                             0x208c
7272 #define mmCP_COHER_SIZE_HI_BASE_IDX                                                                    1
7273 #define mmCP_PFP_IB_CONTROL                                                                            0x208d
7274 #define mmCP_PFP_IB_CONTROL_BASE_IDX                                                                   1
7275 #define mmCP_PFP_LOAD_CONTROL                                                                          0x208e
7276 #define mmCP_PFP_LOAD_CONTROL_BASE_IDX                                                                 1
7277 #define mmCP_SCRATCH_INDEX                                                                             0x208f
7278 #define mmCP_SCRATCH_INDEX_BASE_IDX                                                                    1
7279 #define mmCP_SCRATCH_DATA                                                                              0x2090
7280 #define mmCP_SCRATCH_DATA_BASE_IDX                                                                     1
7281 #define mmCP_RB_OFFSET                                                                                 0x2091
7282 #define mmCP_RB_OFFSET_BASE_IDX                                                                        1
7283 #define mmCP_IB1_OFFSET                                                                                0x2092
7284 #define mmCP_IB1_OFFSET_BASE_IDX                                                                       1
7285 #define mmCP_IB2_OFFSET                                                                                0x2093
7286 #define mmCP_IB2_OFFSET_BASE_IDX                                                                       1
7287 #define mmCP_IB1_PREAMBLE_BEGIN                                                                        0x2094
7288 #define mmCP_IB1_PREAMBLE_BEGIN_BASE_IDX                                                               1
7289 #define mmCP_IB1_PREAMBLE_END                                                                          0x2095
7290 #define mmCP_IB1_PREAMBLE_END_BASE_IDX                                                                 1
7291 #define mmCP_IB2_PREAMBLE_BEGIN                                                                        0x2096
7292 #define mmCP_IB2_PREAMBLE_BEGIN_BASE_IDX                                                               1
7293 #define mmCP_IB2_PREAMBLE_END                                                                          0x2097
7294 #define mmCP_IB2_PREAMBLE_END_BASE_IDX                                                                 1
7295 #define mmCP_CE_IB1_OFFSET                                                                             0x2098
7296 #define mmCP_CE_IB1_OFFSET_BASE_IDX                                                                    1
7297 #define mmCP_CE_IB2_OFFSET                                                                             0x2099
7298 #define mmCP_CE_IB2_OFFSET_BASE_IDX                                                                    1
7299 #define mmCP_CE_COUNTER                                                                                0x209a
7300 #define mmCP_CE_COUNTER_BASE_IDX                                                                       1
7301 #define mmCP_DMA_ME_CMD_ADDR_LO                                                                        0x209c
7302 #define mmCP_DMA_ME_CMD_ADDR_LO_BASE_IDX                                                               1
7303 #define mmCP_DMA_ME_CMD_ADDR_HI                                                                        0x209d
7304 #define mmCP_DMA_ME_CMD_ADDR_HI_BASE_IDX                                                               1
7305 #define mmCP_DMA_PFP_CMD_ADDR_LO                                                                       0x209e
7306 #define mmCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX                                                              1
7307 #define mmCP_DMA_PFP_CMD_ADDR_HI                                                                       0x209f
7308 #define mmCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX                                                              1
7309 #define mmCP_APPEND_CMD_ADDR_LO                                                                        0x20a0
7310 #define mmCP_APPEND_CMD_ADDR_LO_BASE_IDX                                                               1
7311 #define mmCP_APPEND_CMD_ADDR_HI                                                                        0x20a1
7312 #define mmCP_APPEND_CMD_ADDR_HI_BASE_IDX                                                               1
7313 #define mmCP_CE_INIT_CMD_BUFSZ                                                                         0x20bd
7314 #define mmCP_CE_INIT_CMD_BUFSZ_BASE_IDX                                                                1
7315 #define mmCP_CE_IB1_CMD_BUFSZ                                                                          0x20be
7316 #define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX                                                                 1
7317 #define mmCP_CE_IB2_CMD_BUFSZ                                                                          0x20bf
7318 #define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX                                                                 1
7319 #define mmCP_IB1_CMD_BUFSZ                                                                             0x20c0
7320 #define mmCP_IB1_CMD_BUFSZ_BASE_IDX                                                                    1
7321 #define mmCP_IB2_CMD_BUFSZ                                                                             0x20c1
7322 #define mmCP_IB2_CMD_BUFSZ_BASE_IDX                                                                    1
7323 #define mmCP_ST_CMD_BUFSZ                                                                              0x20c2
7324 #define mmCP_ST_CMD_BUFSZ_BASE_IDX                                                                     1
7325 #define mmCP_CE_INIT_BASE_LO                                                                           0x20c3
7326 #define mmCP_CE_INIT_BASE_LO_BASE_IDX                                                                  1
7327 #define mmCP_CE_INIT_BASE_HI                                                                           0x20c4
7328 #define mmCP_CE_INIT_BASE_HI_BASE_IDX                                                                  1
7329 #define mmCP_CE_INIT_BUFSZ                                                                             0x20c5
7330 #define mmCP_CE_INIT_BUFSZ_BASE_IDX                                                                    1
7331 #define mmCP_CE_IB1_BASE_LO                                                                            0x20c6
7332 #define mmCP_CE_IB1_BASE_LO_BASE_IDX                                                                   1
7333 #define mmCP_CE_IB1_BASE_HI                                                                            0x20c7
7334 #define mmCP_CE_IB1_BASE_HI_BASE_IDX                                                                   1
7335 #define mmCP_CE_IB1_BUFSZ                                                                              0x20c8
7336 #define mmCP_CE_IB1_BUFSZ_BASE_IDX                                                                     1
7337 #define mmCP_CE_IB2_BASE_LO                                                                            0x20c9
7338 #define mmCP_CE_IB2_BASE_LO_BASE_IDX                                                                   1
7339 #define mmCP_CE_IB2_BASE_HI                                                                            0x20ca
7340 #define mmCP_CE_IB2_BASE_HI_BASE_IDX                                                                   1
7341 #define mmCP_CE_IB2_BUFSZ                                                                              0x20cb
7342 #define mmCP_CE_IB2_BUFSZ_BASE_IDX                                                                     1
7343 #define mmCP_IB1_BASE_LO                                                                               0x20cc
7344 #define mmCP_IB1_BASE_LO_BASE_IDX                                                                      1
7345 #define mmCP_IB1_BASE_HI                                                                               0x20cd
7346 #define mmCP_IB1_BASE_HI_BASE_IDX                                                                      1
7347 #define mmCP_IB1_BUFSZ                                                                                 0x20ce
7348 #define mmCP_IB1_BUFSZ_BASE_IDX                                                                        1
7349 #define mmCP_IB2_BASE_LO                                                                               0x20cf
7350 #define mmCP_IB2_BASE_LO_BASE_IDX                                                                      1
7351 #define mmCP_IB2_BASE_HI                                                                               0x20d0
7352 #define mmCP_IB2_BASE_HI_BASE_IDX                                                                      1
7353 #define mmCP_IB2_BUFSZ                                                                                 0x20d1
7354 #define mmCP_IB2_BUFSZ_BASE_IDX                                                                        1
7355 #define mmCP_ST_BASE_LO                                                                                0x20d2
7356 #define mmCP_ST_BASE_LO_BASE_IDX                                                                       1
7357 #define mmCP_ST_BASE_HI                                                                                0x20d3
7358 #define mmCP_ST_BASE_HI_BASE_IDX                                                                       1
7359 #define mmCP_ST_BUFSZ                                                                                  0x20d4
7360 #define mmCP_ST_BUFSZ_BASE_IDX                                                                         1
7361 #define mmCP_EOP_DONE_EVENT_CNTL                                                                       0x20d5
7362 #define mmCP_EOP_DONE_EVENT_CNTL_BASE_IDX                                                              1
7363 #define mmCP_EOP_DONE_DATA_CNTL                                                                        0x20d6
7364 #define mmCP_EOP_DONE_DATA_CNTL_BASE_IDX                                                               1
7365 #define mmCP_EOP_DONE_CNTX_ID                                                                          0x20d7
7366 #define mmCP_EOP_DONE_CNTX_ID_BASE_IDX                                                                 1
7367 #define mmCP_DB_BASE_LO                                                                                0x20d8
7368 #define mmCP_DB_BASE_LO_BASE_IDX                                                                       1
7369 #define mmCP_DB_BASE_HI                                                                                0x20d9
7370 #define mmCP_DB_BASE_HI_BASE_IDX                                                                       1
7371 #define mmCP_DB_BUFSZ                                                                                  0x20da
7372 #define mmCP_DB_BUFSZ_BASE_IDX                                                                         1
7373 #define mmCP_DB_CMD_BUFSZ                                                                              0x20db
7374 #define mmCP_DB_CMD_BUFSZ_BASE_IDX                                                                     1
7375 #define mmCP_CE_DB_BASE_LO                                                                             0x20dc
7376 #define mmCP_CE_DB_BASE_LO_BASE_IDX                                                                    1
7377 #define mmCP_CE_DB_BASE_HI                                                                             0x20dd
7378 #define mmCP_CE_DB_BASE_HI_BASE_IDX                                                                    1
7379 #define mmCP_CE_DB_BUFSZ                                                                               0x20de
7380 #define mmCP_CE_DB_BUFSZ_BASE_IDX                                                                      1
7381 #define mmCP_CE_DB_CMD_BUFSZ                                                                           0x20df
7382 #define mmCP_CE_DB_CMD_BUFSZ_BASE_IDX                                                                  1
7383 #define mmCP_PFP_COMPLETION_STATUS                                                                     0x20ec
7384 #define mmCP_PFP_COMPLETION_STATUS_BASE_IDX                                                            1
7385 #define mmCP_CE_COMPLETION_STATUS                                                                      0x20ed
7386 #define mmCP_CE_COMPLETION_STATUS_BASE_IDX                                                             1
7387 #define mmCP_PRED_NOT_VISIBLE                                                                          0x20ee
7388 #define mmCP_PRED_NOT_VISIBLE_BASE_IDX                                                                 1
7389 #define mmCP_PFP_METADATA_BASE_ADDR                                                                    0x20f0
7390 #define mmCP_PFP_METADATA_BASE_ADDR_BASE_IDX                                                           1
7391 #define mmCP_PFP_METADATA_BASE_ADDR_HI                                                                 0x20f1
7392 #define mmCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX                                                        1
7393 #define mmCP_CE_METADATA_BASE_ADDR                                                                     0x20f2
7394 #define mmCP_CE_METADATA_BASE_ADDR_BASE_IDX                                                            1
7395 #define mmCP_CE_METADATA_BASE_ADDR_HI                                                                  0x20f3
7396 #define mmCP_CE_METADATA_BASE_ADDR_HI_BASE_IDX                                                         1
7397 #define mmCP_DRAW_INDX_INDR_ADDR                                                                       0x20f4
7398 #define mmCP_DRAW_INDX_INDR_ADDR_BASE_IDX                                                              1
7399 #define mmCP_DRAW_INDX_INDR_ADDR_HI                                                                    0x20f5
7400 #define mmCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX                                                           1
7401 #define mmCP_DISPATCH_INDR_ADDR                                                                        0x20f6
7402 #define mmCP_DISPATCH_INDR_ADDR_BASE_IDX                                                               1
7403 #define mmCP_DISPATCH_INDR_ADDR_HI                                                                     0x20f7
7404 #define mmCP_DISPATCH_INDR_ADDR_HI_BASE_IDX                                                            1
7405 #define mmCP_INDEX_BASE_ADDR                                                                           0x20f8
7406 #define mmCP_INDEX_BASE_ADDR_BASE_IDX                                                                  1
7407 #define mmCP_INDEX_BASE_ADDR_HI                                                                        0x20f9
7408 #define mmCP_INDEX_BASE_ADDR_HI_BASE_IDX                                                               1
7409 #define mmCP_INDEX_TYPE                                                                                0x20fa
7410 #define mmCP_INDEX_TYPE_BASE_IDX                                                                       1
7411 #define mmCP_GDS_BKUP_ADDR                                                                             0x20fb
7412 #define mmCP_GDS_BKUP_ADDR_BASE_IDX                                                                    1
7413 #define mmCP_GDS_BKUP_ADDR_HI                                                                          0x20fc
7414 #define mmCP_GDS_BKUP_ADDR_HI_BASE_IDX                                                                 1
7415 #define mmCP_SAMPLE_STATUS                                                                             0x20fd
7416 #define mmCP_SAMPLE_STATUS_BASE_IDX                                                                    1
7417 #define mmCP_ME_COHER_CNTL                                                                             0x20fe
7418 #define mmCP_ME_COHER_CNTL_BASE_IDX                                                                    1
7419 #define mmCP_ME_COHER_SIZE                                                                             0x20ff
7420 #define mmCP_ME_COHER_SIZE_BASE_IDX                                                                    1
7421 #define mmCP_ME_COHER_SIZE_HI                                                                          0x2100
7422 #define mmCP_ME_COHER_SIZE_HI_BASE_IDX                                                                 1
7423 #define mmCP_ME_COHER_BASE                                                                             0x2101
7424 #define mmCP_ME_COHER_BASE_BASE_IDX                                                                    1
7425 #define mmCP_ME_COHER_BASE_HI                                                                          0x2102
7426 #define mmCP_ME_COHER_BASE_HI_BASE_IDX                                                                 1
7427 #define mmCP_ME_COHER_STATUS                                                                           0x2103
7428 #define mmCP_ME_COHER_STATUS_BASE_IDX                                                                  1
7429 #define mmRLC_GPM_PERF_COUNT_0                                                                         0x2140
7430 #define mmRLC_GPM_PERF_COUNT_0_BASE_IDX                                                                1
7431 #define mmRLC_GPM_PERF_COUNT_1                                                                         0x2141
7432 #define mmRLC_GPM_PERF_COUNT_1_BASE_IDX                                                                1
7433 #define mmGRBM_GFX_INDEX                                                                               0x2200
7434 #define mmGRBM_GFX_INDEX_BASE_IDX                                                                      1
7435 #define mmVGT_ESGS_RING_SIZE_UMD                                                                       0x2240
7436 #define mmVGT_ESGS_RING_SIZE_UMD_BASE_IDX                                                              1
7437 #define mmVGT_GSVS_RING_SIZE_UMD                                                                       0x2241
7438 #define mmVGT_GSVS_RING_SIZE_UMD_BASE_IDX                                                              1
7439 #define mmVGT_PRIMITIVE_TYPE                                                                           0x2242
7440 #define mmVGT_PRIMITIVE_TYPE_BASE_IDX                                                                  1
7441 #define mmVGT_INDEX_TYPE                                                                               0x2243
7442 #define mmVGT_INDEX_TYPE_BASE_IDX                                                                      1
7443 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0                                                             0x2244
7444 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0_BASE_IDX                                                    1
7445 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1                                                             0x2245
7446 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1_BASE_IDX                                                    1
7447 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2                                                             0x2246
7448 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2_BASE_IDX                                                    1
7449 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3                                                             0x2247
7450 #define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3_BASE_IDX                                                    1
7451 #define mmGE_MIN_VTX_INDX                                                                              0x2249
7452 #define mmGE_MIN_VTX_INDX_BASE_IDX                                                                     1
7453 #define mmGE_INDX_OFFSET                                                                               0x224a
7454 #define mmGE_INDX_OFFSET_BASE_IDX                                                                      1
7455 #define mmGE_MULTI_PRIM_IB_RESET_EN                                                                    0x224b
7456 #define mmGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX                                                           1
7457 #define mmVGT_NUM_INDICES                                                                              0x224c
7458 #define mmVGT_NUM_INDICES_BASE_IDX                                                                     1
7459 #define mmVGT_NUM_INSTANCES                                                                            0x224d
7460 #define mmVGT_NUM_INSTANCES_BASE_IDX                                                                   1
7461 #define mmVGT_TF_RING_SIZE_UMD                                                                         0x224e
7462 #define mmVGT_TF_RING_SIZE_UMD_BASE_IDX                                                                1
7463 #define mmVGT_HS_OFFCHIP_PARAM_UMD                                                                     0x224f
7464 #define mmVGT_HS_OFFCHIP_PARAM_UMD_BASE_IDX                                                            1
7465 #define mmVGT_TF_MEMORY_BASE_UMD                                                                       0x2250
7466 #define mmVGT_TF_MEMORY_BASE_UMD_BASE_IDX                                                              1
7467 #define mmGE_DMA_FIRST_INDEX                                                                           0x2251
7468 #define mmGE_DMA_FIRST_INDEX_BASE_IDX                                                                  1
7469 #define mmWD_POS_BUF_BASE                                                                              0x2252
7470 #define mmWD_POS_BUF_BASE_BASE_IDX                                                                     1
7471 #define mmWD_POS_BUF_BASE_HI                                                                           0x2253
7472 #define mmWD_POS_BUF_BASE_HI_BASE_IDX                                                                  1
7473 #define mmWD_CNTL_SB_BUF_BASE                                                                          0x2254
7474 #define mmWD_CNTL_SB_BUF_BASE_BASE_IDX                                                                 1
7475 #define mmWD_CNTL_SB_BUF_BASE_HI                                                                       0x2255
7476 #define mmWD_CNTL_SB_BUF_BASE_HI_BASE_IDX                                                              1
7477 #define mmWD_INDEX_BUF_BASE                                                                            0x2256
7478 #define mmWD_INDEX_BUF_BASE_BASE_IDX                                                                   1
7479 #define mmWD_INDEX_BUF_BASE_HI                                                                         0x2257
7480 #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX                                                                1
7481 #define mmIA_MULTI_VGT_PARAM_PIPED                                                                     0x2258
7482 #define mmIA_MULTI_VGT_PARAM_PIPED_BASE_IDX                                                            1
7483 #define mmGE_MAX_VTX_INDX                                                                              0x2259
7484 #define mmGE_MAX_VTX_INDX_BASE_IDX                                                                     1
7485 #define mmVGT_INSTANCE_BASE_ID                                                                         0x225a
7486 #define mmVGT_INSTANCE_BASE_ID_BASE_IDX                                                                1
7487 #define mmGE_CNTL                                                                                      0x225b
7488 #define mmGE_CNTL_BASE_IDX                                                                             1
7489 #define mmGE_USER_VGPR1                                                                                0x225c
7490 #define mmGE_USER_VGPR1_BASE_IDX                                                                       1
7491 #define mmGE_USER_VGPR2                                                                                0x225d
7492 #define mmGE_USER_VGPR2_BASE_IDX                                                                       1
7493 #define mmGE_USER_VGPR3                                                                                0x225e
7494 #define mmGE_USER_VGPR3_BASE_IDX                                                                       1
7495 #define mmGE_STEREO_CNTL                                                                               0x225f
7496 #define mmGE_STEREO_CNTL_BASE_IDX                                                                      1
7497 #define mmGE_PC_ALLOC                                                                                  0x2260
7498 #define mmGE_PC_ALLOC_BASE_IDX                                                                         1
7499 #define mmVGT_TF_MEMORY_BASE_HI_UMD                                                                    0x2261
7500 #define mmVGT_TF_MEMORY_BASE_HI_UMD_BASE_IDX                                                           1
7501 #define mmGE_USER_VGPR_EN                                                                              0x2262
7502 #define mmGE_USER_VGPR_EN_BASE_IDX                                                                     1
7503 #define mmPA_SU_LINE_STIPPLE_VALUE                                                                     0x2280
7504 #define mmPA_SU_LINE_STIPPLE_VALUE_BASE_IDX                                                            1
7505 #define mmPA_SC_LINE_STIPPLE_STATE                                                                     0x2281
7506 #define mmPA_SC_LINE_STIPPLE_STATE_BASE_IDX                                                            1
7507 #define mmPA_SC_SCREEN_EXTENT_MIN_0                                                                    0x2284
7508 #define mmPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX                                                           1
7509 #define mmPA_SC_SCREEN_EXTENT_MAX_0                                                                    0x2285
7510 #define mmPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX                                                           1
7511 #define mmPA_SC_SCREEN_EXTENT_MIN_1                                                                    0x2286
7512 #define mmPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX                                                           1
7513 #define mmPA_SC_SCREEN_EXTENT_MAX_1                                                                    0x228b
7514 #define mmPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX                                                           1
7515 #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN                                                                  0x22a0
7516 #define mmPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                         1
7517 #define mmPA_SC_P3D_TRAP_SCREEN_H                                                                      0x22a1
7518 #define mmPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX                                                             1
7519 #define mmPA_SC_P3D_TRAP_SCREEN_V                                                                      0x22a2
7520 #define mmPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX                                                             1
7521 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE                                                             0x22a3
7522 #define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                    1
7523 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT                                                                  0x22a4
7524 #define mmPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX                                                         1
7525 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN                                                                 0x22a8
7526 #define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX                                                        1
7527 #define mmPA_SC_HP3D_TRAP_SCREEN_H                                                                     0x22a9
7528 #define mmPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX                                                            1
7529 #define mmPA_SC_HP3D_TRAP_SCREEN_V                                                                     0x22aa
7530 #define mmPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX                                                            1
7531 #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE                                                            0x22ab
7532 #define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                   1
7533 #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT                                                                 0x22ac
7534 #define mmPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX                                                        1
7535 #define mmPA_SC_TRAP_SCREEN_HV_EN                                                                      0x22b0
7536 #define mmPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX                                                             1
7537 #define mmPA_SC_TRAP_SCREEN_H                                                                          0x22b1
7538 #define mmPA_SC_TRAP_SCREEN_H_BASE_IDX                                                                 1
7539 #define mmPA_SC_TRAP_SCREEN_V                                                                          0x22b2
7540 #define mmPA_SC_TRAP_SCREEN_V_BASE_IDX                                                                 1
7541 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE                                                                 0x22b3
7542 #define mmPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX                                                        1
7543 #define mmPA_SC_TRAP_SCREEN_COUNT                                                                      0x22b4
7544 #define mmPA_SC_TRAP_SCREEN_COUNT_BASE_IDX                                                             1
7545 #define mmSQ_THREAD_TRACE_USERDATA_0                                                                   0x2340
7546 #define mmSQ_THREAD_TRACE_USERDATA_0_BASE_IDX                                                          1
7547 #define mmSQ_THREAD_TRACE_USERDATA_1                                                                   0x2341
7548 #define mmSQ_THREAD_TRACE_USERDATA_1_BASE_IDX                                                          1
7549 #define mmSQ_THREAD_TRACE_USERDATA_2                                                                   0x2342
7550 #define mmSQ_THREAD_TRACE_USERDATA_2_BASE_IDX                                                          1
7551 #define mmSQ_THREAD_TRACE_USERDATA_3                                                                   0x2343
7552 #define mmSQ_THREAD_TRACE_USERDATA_3_BASE_IDX                                                          1
7553 #define mmSQ_THREAD_TRACE_USERDATA_4                                                                   0x2344
7554 #define mmSQ_THREAD_TRACE_USERDATA_4_BASE_IDX                                                          1
7555 #define mmSQ_THREAD_TRACE_USERDATA_5                                                                   0x2345
7556 #define mmSQ_THREAD_TRACE_USERDATA_5_BASE_IDX                                                          1
7557 #define mmSQ_THREAD_TRACE_USERDATA_6                                                                   0x2346
7558 #define mmSQ_THREAD_TRACE_USERDATA_6_BASE_IDX                                                          1
7559 #define mmSQ_THREAD_TRACE_USERDATA_7                                                                   0x2347
7560 #define mmSQ_THREAD_TRACE_USERDATA_7_BASE_IDX                                                          1
7561 #define mmSQC_CACHES                                                                                   0x2348
7562 #define mmSQC_CACHES_BASE_IDX                                                                          1
7563 #define mmSQC_WRITEBACK                                                                                0x2349
7564 #define mmSQC_WRITEBACK_BASE_IDX                                                                       1
7565 #define mmTA_CS_BC_BASE_ADDR                                                                           0x2380
7566 #define mmTA_CS_BC_BASE_ADDR_BASE_IDX                                                                  1
7567 #define mmTA_CS_BC_BASE_ADDR_HI                                                                        0x2381
7568 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX                                                               1
7569 #define mmDB_OCCLUSION_COUNT0_LOW                                                                      0x23c0
7570 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX                                                             1
7571 #define mmDB_OCCLUSION_COUNT0_HI                                                                       0x23c1
7572 #define mmDB_OCCLUSION_COUNT0_HI_BASE_IDX                                                              1
7573 #define mmDB_OCCLUSION_COUNT1_LOW                                                                      0x23c2
7574 #define mmDB_OCCLUSION_COUNT1_LOW_BASE_IDX                                                             1
7575 #define mmDB_OCCLUSION_COUNT1_HI                                                                       0x23c3
7576 #define mmDB_OCCLUSION_COUNT1_HI_BASE_IDX                                                              1
7577 #define mmDB_OCCLUSION_COUNT2_LOW                                                                      0x23c4
7578 #define mmDB_OCCLUSION_COUNT2_LOW_BASE_IDX                                                             1
7579 #define mmDB_OCCLUSION_COUNT2_HI                                                                       0x23c5
7580 #define mmDB_OCCLUSION_COUNT2_HI_BASE_IDX                                                              1
7581 #define mmDB_OCCLUSION_COUNT3_LOW                                                                      0x23c6
7582 #define mmDB_OCCLUSION_COUNT3_LOW_BASE_IDX                                                             1
7583 #define mmDB_OCCLUSION_COUNT3_HI                                                                       0x23c7
7584 #define mmDB_OCCLUSION_COUNT3_HI_BASE_IDX                                                              1
7585 #define mmDB_ZPASS_COUNT_LOW                                                                           0x23fe
7586 #define mmDB_ZPASS_COUNT_LOW_BASE_IDX                                                                  1
7587 #define mmDB_ZPASS_COUNT_HI                                                                            0x23ff
7588 #define mmDB_ZPASS_COUNT_HI_BASE_IDX                                                                   1
7589 #define mmGDS_RD_ADDR                                                                                  0x2400
7590 #define mmGDS_RD_ADDR_BASE_IDX                                                                         1
7591 #define mmGDS_RD_DATA                                                                                  0x2401
7592 #define mmGDS_RD_DATA_BASE_IDX                                                                         1
7593 #define mmGDS_RD_BURST_ADDR                                                                            0x2402
7594 #define mmGDS_RD_BURST_ADDR_BASE_IDX                                                                   1
7595 #define mmGDS_RD_BURST_COUNT                                                                           0x2403
7596 #define mmGDS_RD_BURST_COUNT_BASE_IDX                                                                  1
7597 #define mmGDS_RD_BURST_DATA                                                                            0x2404
7598 #define mmGDS_RD_BURST_DATA_BASE_IDX                                                                   1
7599 #define mmGDS_WR_ADDR                                                                                  0x2405
7600 #define mmGDS_WR_ADDR_BASE_IDX                                                                         1
7601 #define mmGDS_WR_DATA                                                                                  0x2406
7602 #define mmGDS_WR_DATA_BASE_IDX                                                                         1
7603 #define mmGDS_WR_BURST_ADDR                                                                            0x2407
7604 #define mmGDS_WR_BURST_ADDR_BASE_IDX                                                                   1
7605 #define mmGDS_WR_BURST_DATA                                                                            0x2408
7606 #define mmGDS_WR_BURST_DATA_BASE_IDX                                                                   1
7607 #define mmGDS_WRITE_COMPLETE                                                                           0x2409
7608 #define mmGDS_WRITE_COMPLETE_BASE_IDX                                                                  1
7609 #define mmGDS_ATOM_CNTL                                                                                0x240a
7610 #define mmGDS_ATOM_CNTL_BASE_IDX                                                                       1
7611 #define mmGDS_ATOM_COMPLETE                                                                            0x240b
7612 #define mmGDS_ATOM_COMPLETE_BASE_IDX                                                                   1
7613 #define mmGDS_ATOM_BASE                                                                                0x240c
7614 #define mmGDS_ATOM_BASE_BASE_IDX                                                                       1
7615 #define mmGDS_ATOM_SIZE                                                                                0x240d
7616 #define mmGDS_ATOM_SIZE_BASE_IDX                                                                       1
7617 #define mmGDS_ATOM_OFFSET0                                                                             0x240e
7618 #define mmGDS_ATOM_OFFSET0_BASE_IDX                                                                    1
7619 #define mmGDS_ATOM_OFFSET1                                                                             0x240f
7620 #define mmGDS_ATOM_OFFSET1_BASE_IDX                                                                    1
7621 #define mmGDS_ATOM_DST                                                                                 0x2410
7622 #define mmGDS_ATOM_DST_BASE_IDX                                                                        1
7623 #define mmGDS_ATOM_OP                                                                                  0x2411
7624 #define mmGDS_ATOM_OP_BASE_IDX                                                                         1
7625 #define mmGDS_ATOM_SRC0                                                                                0x2412
7626 #define mmGDS_ATOM_SRC0_BASE_IDX                                                                       1
7627 #define mmGDS_ATOM_SRC0_U                                                                              0x2413
7628 #define mmGDS_ATOM_SRC0_U_BASE_IDX                                                                     1
7629 #define mmGDS_ATOM_SRC1                                                                                0x2414
7630 #define mmGDS_ATOM_SRC1_BASE_IDX                                                                       1
7631 #define mmGDS_ATOM_SRC1_U                                                                              0x2415
7632 #define mmGDS_ATOM_SRC1_U_BASE_IDX                                                                     1
7633 #define mmGDS_ATOM_READ0                                                                               0x2416
7634 #define mmGDS_ATOM_READ0_BASE_IDX                                                                      1
7635 #define mmGDS_ATOM_READ0_U                                                                             0x2417
7636 #define mmGDS_ATOM_READ0_U_BASE_IDX                                                                    1
7637 #define mmGDS_ATOM_READ1                                                                               0x2418
7638 #define mmGDS_ATOM_READ1_BASE_IDX                                                                      1
7639 #define mmGDS_ATOM_READ1_U                                                                             0x2419
7640 #define mmGDS_ATOM_READ1_U_BASE_IDX                                                                    1
7641 #define mmGDS_GWS_RESOURCE_CNTL                                                                        0x241a
7642 #define mmGDS_GWS_RESOURCE_CNTL_BASE_IDX                                                               1
7643 #define mmGDS_GWS_RESOURCE                                                                             0x241b
7644 #define mmGDS_GWS_RESOURCE_BASE_IDX                                                                    1
7645 #define mmGDS_GWS_RESOURCE_CNT                                                                         0x241c
7646 #define mmGDS_GWS_RESOURCE_CNT_BASE_IDX                                                                1
7647 #define mmGDS_OA_CNTL                                                                                  0x241d
7648 #define mmGDS_OA_CNTL_BASE_IDX                                                                         1
7649 #define mmGDS_OA_COUNTER                                                                               0x241e
7650 #define mmGDS_OA_COUNTER_BASE_IDX                                                                      1
7651 #define mmGDS_OA_ADDRESS                                                                               0x241f
7652 #define mmGDS_OA_ADDRESS_BASE_IDX                                                                      1
7653 #define mmGDS_OA_INCDEC                                                                                0x2420
7654 #define mmGDS_OA_INCDEC_BASE_IDX                                                                       1
7655 #define mmGDS_OA_RING_SIZE                                                                             0x2421
7656 #define mmGDS_OA_RING_SIZE_BASE_IDX                                                                    1
7657 #define mmSPI_CONFIG_CNTL_REMAP                                                                        0x2440
7658 #define mmSPI_CONFIG_CNTL_REMAP_BASE_IDX                                                               1
7659 #define mmSPI_CONFIG_CNTL_1_REMAP                                                                      0x2441
7660 #define mmSPI_CONFIG_CNTL_1_REMAP_BASE_IDX                                                             1
7661 #define mmSPI_CONFIG_CNTL_2_REMAP                                                                      0x2442
7662 #define mmSPI_CONFIG_CNTL_2_REMAP_BASE_IDX                                                             1
7663 #define mmSPI_WAVE_LIMIT_CNTL_REMAP                                                                    0x2443
7664 #define mmSPI_WAVE_LIMIT_CNTL_REMAP_BASE_IDX                                                           1
7665 
7666 
7667 // addressBlock: gc_cprs64dec
7668 // base address: 0x32000
7669 #define mmCP_MES_PRGRM_CNTR_START                                                                      0x2800
7670 #define mmCP_MES_PRGRM_CNTR_START_BASE_IDX                                                             1
7671 #define mmCP_MES_INTR_ROUTINE_START                                                                    0x2801
7672 #define mmCP_MES_INTR_ROUTINE_START_BASE_IDX                                                           1
7673 #define mmCP_MES_MTVEC_LO                                                                              0x2801
7674 #define mmCP_MES_MTVEC_LO_BASE_IDX                                                                     1
7675 #define mmCP_MES_MTVEC_HI                                                                              0x2802
7676 #define mmCP_MES_MTVEC_HI_BASE_IDX                                                                     1
7677 #define mmCP_MES_CNTL                                                                                  0x2807
7678 #define mmCP_MES_CNTL_BASE_IDX                                                                         1
7679 #define mmCP_MES_PIPE_PRIORITY_CNTS                                                                    0x2808
7680 #define mmCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX                                                           1
7681 #define mmCP_MES_PIPE0_PRIORITY                                                                        0x2809
7682 #define mmCP_MES_PIPE0_PRIORITY_BASE_IDX                                                               1
7683 #define mmCP_MES_PIPE1_PRIORITY                                                                        0x280a
7684 #define mmCP_MES_PIPE1_PRIORITY_BASE_IDX                                                               1
7685 #define mmCP_MES_PIPE2_PRIORITY                                                                        0x280b
7686 #define mmCP_MES_PIPE2_PRIORITY_BASE_IDX                                                               1
7687 #define mmCP_MES_PIPE3_PRIORITY                                                                        0x280c
7688 #define mmCP_MES_PIPE3_PRIORITY_BASE_IDX                                                               1
7689 #define mmCP_MES_HEADER_DUMP                                                                           0x280d
7690 #define mmCP_MES_HEADER_DUMP_BASE_IDX                                                                  1
7691 #define mmCP_MES_MIE_LO                                                                                0x280e
7692 #define mmCP_MES_MIE_LO_BASE_IDX                                                                       1
7693 #define mmCP_MES_MIE_HI                                                                                0x280f
7694 #define mmCP_MES_MIE_HI_BASE_IDX                                                                       1
7695 #define mmCP_MES_INTERRUPT                                                                             0x2810
7696 #define mmCP_MES_INTERRUPT_BASE_IDX                                                                    1
7697 #define mmCP_MES_SCRATCH_INDEX                                                                         0x2811
7698 #define mmCP_MES_SCRATCH_INDEX_BASE_IDX                                                                1
7699 #define mmCP_MES_SCRATCH_DATA                                                                          0x2812
7700 #define mmCP_MES_SCRATCH_DATA_BASE_IDX                                                                 1
7701 #define mmCP_MES_INSTR_PNTR                                                                            0x2813
7702 #define mmCP_MES_INSTR_PNTR_BASE_IDX                                                                   1
7703 #define mmCP_MES_MSCRATCH_HI                                                                           0x2814
7704 #define mmCP_MES_MSCRATCH_HI_BASE_IDX                                                                  1
7705 #define mmCP_MES_MSCRATCH_LO                                                                           0x2815
7706 #define mmCP_MES_MSCRATCH_LO_BASE_IDX                                                                  1
7707 #define mmCP_MES_MSTATUS_LO                                                                            0x2816
7708 #define mmCP_MES_MSTATUS_LO_BASE_IDX                                                                   1
7709 #define mmCP_MES_MSTATUS_HI                                                                            0x2817
7710 #define mmCP_MES_MSTATUS_HI_BASE_IDX                                                                   1
7711 #define mmCP_MES_MEPC_LO                                                                               0x2818
7712 #define mmCP_MES_MEPC_LO_BASE_IDX                                                                      1
7713 #define mmCP_MES_MEPC_HI                                                                               0x2819
7714 #define mmCP_MES_MEPC_HI_BASE_IDX                                                                      1
7715 #define mmCP_MES_MCAUSE_LO                                                                             0x281a
7716 #define mmCP_MES_MCAUSE_LO_BASE_IDX                                                                    1
7717 #define mmCP_MES_MCAUSE_HI                                                                             0x281b
7718 #define mmCP_MES_MCAUSE_HI_BASE_IDX                                                                    1
7719 #define mmCP_MES_MBADADDR_LO                                                                           0x281c
7720 #define mmCP_MES_MBADADDR_LO_BASE_IDX                                                                  1
7721 #define mmCP_MES_MBADADDR_HI                                                                           0x281d
7722 #define mmCP_MES_MBADADDR_HI_BASE_IDX                                                                  1
7723 #define mmCP_MES_MIP_LO                                                                                0x281e
7724 #define mmCP_MES_MIP_LO_BASE_IDX                                                                       1
7725 #define mmCP_MES_MIP_HI                                                                                0x281f
7726 #define mmCP_MES_MIP_HI_BASE_IDX                                                                       1
7727 #define mmCP_MES_MCYCLE_LO                                                                             0x2826
7728 #define mmCP_MES_MCYCLE_LO_BASE_IDX                                                                    1
7729 #define mmCP_MES_MCYCLE_HI                                                                             0x2827
7730 #define mmCP_MES_MCYCLE_HI_BASE_IDX                                                                    1
7731 #define mmCP_MES_MTIME_LO                                                                              0x2828
7732 #define mmCP_MES_MTIME_LO_BASE_IDX                                                                     1
7733 #define mmCP_MES_MTIME_HI                                                                              0x2829
7734 #define mmCP_MES_MTIME_HI_BASE_IDX                                                                     1
7735 #define mmCP_MES_MINSTRET_LO                                                                           0x282a
7736 #define mmCP_MES_MINSTRET_LO_BASE_IDX                                                                  1
7737 #define mmCP_MES_MINSTRET_HI                                                                           0x282b
7738 #define mmCP_MES_MINSTRET_HI_BASE_IDX                                                                  1
7739 #define mmCP_MES_MISA_LO                                                                               0x282c
7740 #define mmCP_MES_MISA_LO_BASE_IDX                                                                      1
7741 #define mmCP_MES_MISA_HI                                                                               0x282d
7742 #define mmCP_MES_MISA_HI_BASE_IDX                                                                      1
7743 #define mmCP_MES_MVENDORID_LO                                                                          0x282e
7744 #define mmCP_MES_MVENDORID_LO_BASE_IDX                                                                 1
7745 #define mmCP_MES_MVENDORID_HI                                                                          0x282f
7746 #define mmCP_MES_MVENDORID_HI_BASE_IDX                                                                 1
7747 #define mmCP_MES_MARCHID_LO                                                                            0x2830
7748 #define mmCP_MES_MARCHID_LO_BASE_IDX                                                                   1
7749 #define mmCP_MES_MARCHID_HI                                                                            0x2831
7750 #define mmCP_MES_MARCHID_HI_BASE_IDX                                                                   1
7751 #define mmCP_MES_MIMPID_LO                                                                             0x2832
7752 #define mmCP_MES_MIMPID_LO_BASE_IDX                                                                    1
7753 #define mmCP_MES_MIMPID_HI                                                                             0x2833
7754 #define mmCP_MES_MIMPID_HI_BASE_IDX                                                                    1
7755 #define mmCP_MES_MHARTID_LO                                                                            0x2834
7756 #define mmCP_MES_MHARTID_LO_BASE_IDX                                                                   1
7757 #define mmCP_MES_MHARTID_HI                                                                            0x2835
7758 #define mmCP_MES_MHARTID_HI_BASE_IDX                                                                   1
7759 #define mmCP_MES_DC_BASE_CNTL                                                                          0x2836
7760 #define mmCP_MES_DC_BASE_CNTL_BASE_IDX                                                                 1
7761 #define mmCP_MES_DC_OP_CNTL                                                                            0x2837
7762 #define mmCP_MES_DC_OP_CNTL_BASE_IDX                                                                   1
7763 #define mmCP_MES_MTIMECMP_LO                                                                           0x2838
7764 #define mmCP_MES_MTIMECMP_LO_BASE_IDX                                                                  1
7765 #define mmCP_MES_MTIMECMP_HI                                                                           0x2839
7766 #define mmCP_MES_MTIMECMP_HI_BASE_IDX                                                                  1
7767 #define mmCP_MES_PROCESS_QUANTUM_PIPE0                                                                 0x283a
7768 #define mmCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX                                                        1
7769 #define mmCP_MES_PROCESS_QUANTUM_PIPE1                                                                 0x283b
7770 #define mmCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX                                                        1
7771 #define mmCP_MES_DOORBELL_CONTROL1                                                                     0x283c
7772 #define mmCP_MES_DOORBELL_CONTROL1_BASE_IDX                                                            1
7773 #define mmCP_MES_DOORBELL_CONTROL2                                                                     0x283d
7774 #define mmCP_MES_DOORBELL_CONTROL2_BASE_IDX                                                            1
7775 #define mmCP_MES_DOORBELL_CONTROL3                                                                     0x283e
7776 #define mmCP_MES_DOORBELL_CONTROL3_BASE_IDX                                                            1
7777 #define mmCP_MES_DOORBELL_CONTROL4                                                                     0x283f
7778 #define mmCP_MES_DOORBELL_CONTROL4_BASE_IDX                                                            1
7779 #define mmCP_MES_DOORBELL_CONTROL5                                                                     0x2840
7780 #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX                                                            1
7781 #define mmCP_MES_DOORBELL_CONTROL6                                                                     0x2841
7782 #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX                                                            1
7783 #define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR                                                            0x2842
7784 #define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX                                                   1
7785 #define mmCP_MES_GP0_LO                                                                                0x2843
7786 #define mmCP_MES_GP0_LO_BASE_IDX                                                                       1
7787 #define mmCP_MES_GP0_HI                                                                                0x2844
7788 #define mmCP_MES_GP0_HI_BASE_IDX                                                                       1
7789 #define mmCP_MES_GP1_LO                                                                                0x2845
7790 #define mmCP_MES_GP1_LO_BASE_IDX                                                                       1
7791 #define mmCP_MES_GP1_HI                                                                                0x2846
7792 #define mmCP_MES_GP1_HI_BASE_IDX                                                                       1
7793 #define mmCP_MES_GP2_LO                                                                                0x2847
7794 #define mmCP_MES_GP2_LO_BASE_IDX                                                                       1
7795 #define mmCP_MES_GP2_HI                                                                                0x2848
7796 #define mmCP_MES_GP2_HI_BASE_IDX                                                                       1
7797 #define mmCP_MES_GP3_LO                                                                                0x2849
7798 #define mmCP_MES_GP3_LO_BASE_IDX                                                                       1
7799 #define mmCP_MES_GP3_HI                                                                                0x284a
7800 #define mmCP_MES_GP3_HI_BASE_IDX                                                                       1
7801 #define mmCP_MES_GP4_LO                                                                                0x284b
7802 #define mmCP_MES_GP4_LO_BASE_IDX                                                                       1
7803 #define mmCP_MES_GP4_HI                                                                                0x284c
7804 #define mmCP_MES_GP4_HI_BASE_IDX                                                                       1
7805 #define mmCP_MES_GP5_LO                                                                                0x284d
7806 #define mmCP_MES_GP5_LO_BASE_IDX                                                                       1
7807 #define mmCP_MES_GP5_HI                                                                                0x284e
7808 #define mmCP_MES_GP5_HI_BASE_IDX                                                                       1
7809 #define mmCP_MES_GP6_LO                                                                                0x284f
7810 #define mmCP_MES_GP6_LO_BASE_IDX                                                                       1
7811 #define mmCP_MES_GP6_HI                                                                                0x2850
7812 #define mmCP_MES_GP6_HI_BASE_IDX                                                                       1
7813 #define mmCP_MES_GP7_LO                                                                                0x2851
7814 #define mmCP_MES_GP7_LO_BASE_IDX                                                                       1
7815 #define mmCP_MES_GP7_HI                                                                                0x2852
7816 #define mmCP_MES_GP7_HI_BASE_IDX                                                                       1
7817 #define mmCP_MES_GP8_LO                                                                                0x2853
7818 #define mmCP_MES_GP8_LO_BASE_IDX                                                                       1
7819 #define mmCP_MES_GP8_HI                                                                                0x2854
7820 #define mmCP_MES_GP8_HI_BASE_IDX                                                                       1
7821 #define mmCP_MES_GP9_LO                                                                                0x2855
7822 #define mmCP_MES_GP9_LO_BASE_IDX                                                                       1
7823 #define mmCP_MES_GP9_HI                                                                                0x2856
7824 #define mmCP_MES_GP9_HI_BASE_IDX                                                                       1
7825 #define mmCP_MES_DM_INDEX_ADDR                                                                         0x2880
7826 #define mmCP_MES_DM_INDEX_ADDR_BASE_IDX                                                                1
7827 #define mmCP_MES_DM_INDEX_DATA                                                                         0x2881
7828 #define mmCP_MES_DM_INDEX_DATA_BASE_IDX                                                                1
7829 #define mmCP_MES_DMCONTROL                                                                             0x2882
7830 #define mmCP_MES_DMCONTROL_BASE_IDX                                                                    1
7831 #define mmCP_MES_DMINFO                                                                                0x2883
7832 #define mmCP_MES_DMINFO_BASE_IDX                                                                       1
7833 #define mmCP_MES_SETHALTNOTIFICATION                                                                   0x2885
7834 #define mmCP_MES_SETHALTNOTIFICATION_BASE_IDX                                                          1
7835 #define mmCP_MES_TSELCT_LOW                                                                            0x2886
7836 #define mmCP_MES_TSELCT_LOW_BASE_IDX                                                                   1
7837 #define mmCP_MES_TSELCT_HIGH                                                                           0x2887
7838 #define mmCP_MES_TSELCT_HIGH_BASE_IDX                                                                  1
7839 #define mmCP_MES_TDATA1_LOW                                                                            0x2888
7840 #define mmCP_MES_TDATA1_LOW_BASE_IDX                                                                   1
7841 #define mmCP_MES_TDATA1_HIGH                                                                           0x2889
7842 #define mmCP_MES_TDATA1_HIGH_BASE_IDX                                                                  1
7843 #define mmCP_MES_TDATA2_LOW                                                                            0x288a
7844 #define mmCP_MES_TDATA2_LOW_BASE_IDX                                                                   1
7845 #define mmCP_MES_TDATA2_HIGH                                                                           0x288b
7846 #define mmCP_MES_TDATA2_HIGH_BASE_IDX                                                                  1
7847 #define mmCP_MES_TDATA3_LOW                                                                            0x288c
7848 #define mmCP_MES_TDATA3_LOW_BASE_IDX                                                                   1
7849 #define mmCP_MES_TDATA3_HIH                                                                            0x288d
7850 #define mmCP_MES_TDATA3_HIH_BASE_IDX                                                                   1
7851 #define mmCP_MES_DCSR                                                                                  0x288e
7852 #define mmCP_MES_DCSR_BASE_IDX                                                                         1
7853 #define mmCP_MES_DPC_LOW                                                                               0x288f
7854 #define mmCP_MES_DPC_LOW_BASE_IDX                                                                      1
7855 #define mmCP_MES_DPC_HIGH                                                                              0x2890
7856 #define mmCP_MES_DPC_HIGH_BASE_IDX                                                                     1
7857 #define mmCP_MES_DSCRATCH_LOW                                                                          0x2891
7858 #define mmCP_MES_DSCRATCH_LOW_BASE_IDX                                                                 1
7859 #define mmCP_MES_DSCRATCH_HIGH                                                                         0x2892
7860 #define mmCP_MES_DSCRATCH_HIGH_BASE_IDX                                                                1
7861 #define mmCP_MES_PERFCOUNT_CNTL                                                                        0x2899
7862 #define mmCP_MES_PERFCOUNT_CNTL_BASE_IDX                                                               1
7863 
7864 
7865 // addressBlock: gc_gusdec
7866 // base address: 0x33000
7867 #define mmGUS_IO_RD_COMBINE_FLUSH                                                                      0x2c00
7868 #define mmGUS_IO_RD_COMBINE_FLUSH_BASE_IDX                                                             1
7869 #define mmGUS_IO_WR_COMBINE_FLUSH                                                                      0x2c01
7870 #define mmGUS_IO_WR_COMBINE_FLUSH_BASE_IDX                                                             1
7871 #define mmGUS_IO_RD_PRI_AGE_RATE                                                                       0x2c02
7872 #define mmGUS_IO_RD_PRI_AGE_RATE_BASE_IDX                                                              1
7873 #define mmGUS_IO_WR_PRI_AGE_RATE                                                                       0x2c03
7874 #define mmGUS_IO_WR_PRI_AGE_RATE_BASE_IDX                                                              1
7875 #define mmGUS_IO_RD_PRI_AGE_COEFF                                                                      0x2c04
7876 #define mmGUS_IO_RD_PRI_AGE_COEFF_BASE_IDX                                                             1
7877 #define mmGUS_IO_WR_PRI_AGE_COEFF                                                                      0x2c05
7878 #define mmGUS_IO_WR_PRI_AGE_COEFF_BASE_IDX                                                             1
7879 #define mmGUS_IO_RD_PRI_QUEUING                                                                        0x2c06
7880 #define mmGUS_IO_RD_PRI_QUEUING_BASE_IDX                                                               1
7881 #define mmGUS_IO_WR_PRI_QUEUING                                                                        0x2c07
7882 #define mmGUS_IO_WR_PRI_QUEUING_BASE_IDX                                                               1
7883 #define mmGUS_IO_RD_PRI_FIXED                                                                          0x2c08
7884 #define mmGUS_IO_RD_PRI_FIXED_BASE_IDX                                                                 1
7885 #define mmGUS_IO_WR_PRI_FIXED                                                                          0x2c09
7886 #define mmGUS_IO_WR_PRI_FIXED_BASE_IDX                                                                 1
7887 #define mmGUS_IO_RD_PRI_URGENCY_COEFF                                                                  0x2c0a
7888 #define mmGUS_IO_RD_PRI_URGENCY_COEFF_BASE_IDX                                                         1
7889 #define mmGUS_IO_WR_PRI_URGENCY_COEFF                                                                  0x2c0b
7890 #define mmGUS_IO_WR_PRI_URGENCY_COEFF_BASE_IDX                                                         1
7891 #define mmGUS_IO_RD_PRI_URGENCY_MODE                                                                   0x2c0c
7892 #define mmGUS_IO_RD_PRI_URGENCY_MODE_BASE_IDX                                                          1
7893 #define mmGUS_IO_WR_PRI_URGENCY_MODE                                                                   0x2c0d
7894 #define mmGUS_IO_WR_PRI_URGENCY_MODE_BASE_IDX                                                          1
7895 #define mmGUS_IO_RD_PRI_QUANT_PRI1                                                                     0x2c0e
7896 #define mmGUS_IO_RD_PRI_QUANT_PRI1_BASE_IDX                                                            1
7897 #define mmGUS_IO_RD_PRI_QUANT_PRI2                                                                     0x2c0f
7898 #define mmGUS_IO_RD_PRI_QUANT_PRI2_BASE_IDX                                                            1
7899 #define mmGUS_IO_RD_PRI_QUANT_PRI3                                                                     0x2c10
7900 #define mmGUS_IO_RD_PRI_QUANT_PRI3_BASE_IDX                                                            1
7901 #define mmGUS_IO_RD_PRI_QUANT_PRI4                                                                     0x2c11
7902 #define mmGUS_IO_RD_PRI_QUANT_PRI4_BASE_IDX                                                            1
7903 #define mmGUS_IO_WR_PRI_QUANT_PRI1                                                                     0x2c12
7904 #define mmGUS_IO_WR_PRI_QUANT_PRI1_BASE_IDX                                                            1
7905 #define mmGUS_IO_WR_PRI_QUANT_PRI2                                                                     0x2c13
7906 #define mmGUS_IO_WR_PRI_QUANT_PRI2_BASE_IDX                                                            1
7907 #define mmGUS_IO_WR_PRI_QUANT_PRI3                                                                     0x2c14
7908 #define mmGUS_IO_WR_PRI_QUANT_PRI3_BASE_IDX                                                            1
7909 #define mmGUS_IO_WR_PRI_QUANT_PRI4                                                                     0x2c15
7910 #define mmGUS_IO_WR_PRI_QUANT_PRI4_BASE_IDX                                                            1
7911 #define mmGUS_IO_RD_PRI_QUANT1_PRI1                                                                    0x2c16
7912 #define mmGUS_IO_RD_PRI_QUANT1_PRI1_BASE_IDX                                                           1
7913 #define mmGUS_IO_RD_PRI_QUANT1_PRI2                                                                    0x2c17
7914 #define mmGUS_IO_RD_PRI_QUANT1_PRI2_BASE_IDX                                                           1
7915 #define mmGUS_IO_RD_PRI_QUANT1_PRI3                                                                    0x2c18
7916 #define mmGUS_IO_RD_PRI_QUANT1_PRI3_BASE_IDX                                                           1
7917 #define mmGUS_IO_RD_PRI_QUANT1_PRI4                                                                    0x2c19
7918 #define mmGUS_IO_RD_PRI_QUANT1_PRI4_BASE_IDX                                                           1
7919 #define mmGUS_IO_WR_PRI_QUANT1_PRI1                                                                    0x2c1a
7920 #define mmGUS_IO_WR_PRI_QUANT1_PRI1_BASE_IDX                                                           1
7921 #define mmGUS_IO_WR_PRI_QUANT1_PRI2                                                                    0x2c1b
7922 #define mmGUS_IO_WR_PRI_QUANT1_PRI2_BASE_IDX                                                           1
7923 #define mmGUS_IO_WR_PRI_QUANT1_PRI3                                                                    0x2c1c
7924 #define mmGUS_IO_WR_PRI_QUANT1_PRI3_BASE_IDX                                                           1
7925 #define mmGUS_IO_WR_PRI_QUANT1_PRI4                                                                    0x2c1d
7926 #define mmGUS_IO_WR_PRI_QUANT1_PRI4_BASE_IDX                                                           1
7927 #define mmGUS_DRAM_COMBINE_FLUSH                                                                       0x2c1e
7928 #define mmGUS_DRAM_COMBINE_FLUSH_BASE_IDX                                                              1
7929 #define mmGUS_DRAM_COMBINE_RD_WR_EN                                                                    0x2c1f
7930 #define mmGUS_DRAM_COMBINE_RD_WR_EN_BASE_IDX                                                           1
7931 #define mmGUS_DRAM_PRI_AGE_RATE                                                                        0x2c20
7932 #define mmGUS_DRAM_PRI_AGE_RATE_BASE_IDX                                                               1
7933 #define mmGUS_DRAM_PRI_AGE_COEFF                                                                       0x2c21
7934 #define mmGUS_DRAM_PRI_AGE_COEFF_BASE_IDX                                                              1
7935 #define mmGUS_DRAM_PRI_QUEUING                                                                         0x2c22
7936 #define mmGUS_DRAM_PRI_QUEUING_BASE_IDX                                                                1
7937 #define mmGUS_DRAM_PRI_FIXED                                                                           0x2c23
7938 #define mmGUS_DRAM_PRI_FIXED_BASE_IDX                                                                  1
7939 #define mmGUS_DRAM_PRI_URGENCY_COEFF                                                                   0x2c24
7940 #define mmGUS_DRAM_PRI_URGENCY_COEFF_BASE_IDX                                                          1
7941 #define mmGUS_DRAM_PRI_URGENCY_MODE                                                                    0x2c25
7942 #define mmGUS_DRAM_PRI_URGENCY_MODE_BASE_IDX                                                           1
7943 #define mmGUS_DRAM_PRI_QUANT_PRI1                                                                      0x2c26
7944 #define mmGUS_DRAM_PRI_QUANT_PRI1_BASE_IDX                                                             1
7945 #define mmGUS_DRAM_PRI_QUANT_PRI2                                                                      0x2c27
7946 #define mmGUS_DRAM_PRI_QUANT_PRI2_BASE_IDX                                                             1
7947 #define mmGUS_DRAM_PRI_QUANT_PRI3                                                                      0x2c28
7948 #define mmGUS_DRAM_PRI_QUANT_PRI3_BASE_IDX                                                             1
7949 #define mmGUS_DRAM_PRI_QUANT_PRI4                                                                      0x2c29
7950 #define mmGUS_DRAM_PRI_QUANT_PRI4_BASE_IDX                                                             1
7951 #define mmGUS_DRAM_PRI_QUANT_PRI5                                                                      0x2c2a
7952 #define mmGUS_DRAM_PRI_QUANT_PRI5_BASE_IDX                                                             1
7953 #define mmGUS_DRAM_PRI_QUANT1_PRI1                                                                     0x2c2b
7954 #define mmGUS_DRAM_PRI_QUANT1_PRI1_BASE_IDX                                                            1
7955 #define mmGUS_DRAM_PRI_QUANT1_PRI2                                                                     0x2c2c
7956 #define mmGUS_DRAM_PRI_QUANT1_PRI2_BASE_IDX                                                            1
7957 #define mmGUS_DRAM_PRI_QUANT1_PRI3                                                                     0x2c2d
7958 #define mmGUS_DRAM_PRI_QUANT1_PRI3_BASE_IDX                                                            1
7959 #define mmGUS_DRAM_PRI_QUANT1_PRI4                                                                     0x2c2e
7960 #define mmGUS_DRAM_PRI_QUANT1_PRI4_BASE_IDX                                                            1
7961 #define mmGUS_DRAM_PRI_QUANT1_PRI5                                                                     0x2c2f
7962 #define mmGUS_DRAM_PRI_QUANT1_PRI5_BASE_IDX                                                            1
7963 #define mmGUS_IO_GROUP_BURST                                                                           0x2c30
7964 #define mmGUS_IO_GROUP_BURST_BASE_IDX                                                                  1
7965 #define mmGUS_DRAM_GROUP_BURST                                                                         0x2c31
7966 #define mmGUS_DRAM_GROUP_BURST_BASE_IDX                                                                1
7967 #define mmGUS_SDP_ARB_FINAL                                                                            0x2c32
7968 #define mmGUS_SDP_ARB_FINAL_BASE_IDX                                                                   1
7969 #define mmGUS_SDP_QOS_VC_PRIORITY                                                                      0x2c33
7970 #define mmGUS_SDP_QOS_VC_PRIORITY_BASE_IDX                                                             1
7971 #define mmGUS_SDP_CREDITS                                                                              0x2c34
7972 #define mmGUS_SDP_CREDITS_BASE_IDX                                                                     1
7973 #define mmGUS_SDP_TAG_RESERVE0                                                                         0x2c35
7974 #define mmGUS_SDP_TAG_RESERVE0_BASE_IDX                                                                1
7975 #define mmGUS_SDP_TAG_RESERVE1                                                                         0x2c36
7976 #define mmGUS_SDP_TAG_RESERVE1_BASE_IDX                                                                1
7977 #define mmGUS_SDP_VCC_RESERVE0                                                                         0x2c37
7978 #define mmGUS_SDP_VCC_RESERVE0_BASE_IDX                                                                1
7979 #define mmGUS_SDP_VCC_RESERVE1                                                                         0x2c38
7980 #define mmGUS_SDP_VCC_RESERVE1_BASE_IDX                                                                1
7981 #define mmGUS_SDP_VCD_RESERVE0                                                                         0x2c39
7982 #define mmGUS_SDP_VCD_RESERVE0_BASE_IDX                                                                1
7983 #define mmGUS_SDP_VCD_RESERVE1                                                                         0x2c3a
7984 #define mmGUS_SDP_VCD_RESERVE1_BASE_IDX                                                                1
7985 #define mmGUS_SDP_REQ_CNTL                                                                             0x2c3b
7986 #define mmGUS_SDP_REQ_CNTL_BASE_IDX                                                                    1
7987 #define mmGUS_MISC                                                                                     0x2c3c
7988 #define mmGUS_MISC_BASE_IDX                                                                            1
7989 #define mmGUS_LATENCY_SAMPLING                                                                         0x2c3d
7990 #define mmGUS_LATENCY_SAMPLING_BASE_IDX                                                                1
7991 #define mmGUS_PERFCOUNTER_LO                                                                           0x2c3e
7992 #define mmGUS_PERFCOUNTER_LO_BASE_IDX                                                                  1
7993 #define mmGUS_PERFCOUNTER_HI                                                                           0x2c3f
7994 #define mmGUS_PERFCOUNTER_HI_BASE_IDX                                                                  1
7995 #define mmGUS_PERFCOUNTER0_CFG                                                                         0x2c40
7996 #define mmGUS_PERFCOUNTER0_CFG_BASE_IDX                                                                1
7997 #define mmGUS_PERFCOUNTER1_CFG                                                                         0x2c41
7998 #define mmGUS_PERFCOUNTER1_CFG_BASE_IDX                                                                1
7999 #define mmGUS_PERFCOUNTER_RSLT_CNTL                                                                    0x2c42
8000 #define mmGUS_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                           1
8001 #define mmGUS_ERR_STATUS                                                                               0x2c43
8002 #define mmGUS_ERR_STATUS_BASE_IDX                                                                      1
8003 #define mmGUS_MISC2                                                                                    0x2c44
8004 #define mmGUS_MISC2_BASE_IDX                                                                           1
8005 #define mmGUS_SDP_BACKDOOR_CMDCREDITS0                                                                 0x2c45
8006 #define mmGUS_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX                                                        1
8007 #define mmGUS_SDP_BACKDOOR_CMDCREDITS1                                                                 0x2c46
8008 #define mmGUS_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX                                                        1
8009 #define mmGUS_SDP_BACKDOOR_DATACREDITS0                                                                0x2c47
8010 #define mmGUS_SDP_BACKDOOR_DATACREDITS0_BASE_IDX                                                       1
8011 #define mmGUS_SDP_BACKDOOR_DATACREDITS1                                                                0x2c48
8012 #define mmGUS_SDP_BACKDOOR_DATACREDITS1_BASE_IDX                                                       1
8013 #define mmGUS_SDP_BACKDOOR_MISCCREDITS                                                                 0x2c49
8014 #define mmGUS_SDP_BACKDOOR_MISCCREDITS_BASE_IDX                                                        1
8015 #define mmGUS_SDP_ENABLE                                                                               0x2c4a
8016 #define mmGUS_SDP_ENABLE_BASE_IDX                                                                      1
8017 #define mmGUS_L1_CH0_CMD_IN                                                                            0x2c4b
8018 #define mmGUS_L1_CH0_CMD_IN_BASE_IDX                                                                   1
8019 #define mmGUS_L1_CH0_CMD_OUT                                                                           0x2c4c
8020 #define mmGUS_L1_CH0_CMD_OUT_BASE_IDX                                                                  1
8021 #define mmGUS_L1_CH0_DATA_IN                                                                           0x2c4d
8022 #define mmGUS_L1_CH0_DATA_IN_BASE_IDX                                                                  1
8023 #define mmGUS_L1_CH0_DATA_OUT                                                                          0x2c4e
8024 #define mmGUS_L1_CH0_DATA_OUT_BASE_IDX                                                                 1
8025 #define mmGUS_L1_CH1_CMD_IN                                                                            0x2c4f
8026 #define mmGUS_L1_CH1_CMD_IN_BASE_IDX                                                                   1
8027 #define mmGUS_L1_CH1_CMD_OUT                                                                           0x2c50
8028 #define mmGUS_L1_CH1_CMD_OUT_BASE_IDX                                                                  1
8029 #define mmGUS_L1_CH1_DATA_IN                                                                           0x2c51
8030 #define mmGUS_L1_CH1_DATA_IN_BASE_IDX                                                                  1
8031 #define mmGUS_L1_CH1_DATA_OUT                                                                          0x2c52
8032 #define mmGUS_L1_CH1_DATA_OUT_BASE_IDX                                                                 1
8033 #define mmGUS_L1_SA0_CMD_IN                                                                            0x2c53
8034 #define mmGUS_L1_SA0_CMD_IN_BASE_IDX                                                                   1
8035 #define mmGUS_L1_SA0_CMD_OUT                                                                           0x2c54
8036 #define mmGUS_L1_SA0_CMD_OUT_BASE_IDX                                                                  1
8037 #define mmGUS_L1_SA0_DATA_IN                                                                           0x2c55
8038 #define mmGUS_L1_SA0_DATA_IN_BASE_IDX                                                                  1
8039 #define mmGUS_L1_SA0_DATA_OUT                                                                          0x2c56
8040 #define mmGUS_L1_SA0_DATA_OUT_BASE_IDX                                                                 1
8041 #define mmGUS_L1_SA0_DATA_U_IN                                                                         0x2c57
8042 #define mmGUS_L1_SA0_DATA_U_IN_BASE_IDX                                                                1
8043 #define mmGUS_L1_SA0_DATA_U_OUT                                                                        0x2c58
8044 #define mmGUS_L1_SA0_DATA_U_OUT_BASE_IDX                                                               1
8045 #define mmGUS_L1_SA1_CMD_IN                                                                            0x2c59
8046 #define mmGUS_L1_SA1_CMD_IN_BASE_IDX                                                                   1
8047 #define mmGUS_L1_SA1_CMD_OUT                                                                           0x2c5a
8048 #define mmGUS_L1_SA1_CMD_OUT_BASE_IDX                                                                  1
8049 #define mmGUS_L1_SA1_DATA_IN                                                                           0x2c5b
8050 #define mmGUS_L1_SA1_DATA_IN_BASE_IDX                                                                  1
8051 #define mmGUS_L1_SA1_DATA_OUT                                                                          0x2c5c
8052 #define mmGUS_L1_SA1_DATA_OUT_BASE_IDX                                                                 1
8053 #define mmGUS_L1_SA1_DATA_U_IN                                                                         0x2c5d
8054 #define mmGUS_L1_SA1_DATA_U_IN_BASE_IDX                                                                1
8055 #define mmGUS_L1_SA1_DATA_U_OUT                                                                        0x2c5e
8056 #define mmGUS_L1_SA1_DATA_U_OUT_BASE_IDX                                                               1
8057 #define mmGUS_L1_SA2_CMD_IN                                                                            0x2c5f
8058 #define mmGUS_L1_SA2_CMD_IN_BASE_IDX                                                                   1
8059 #define mmGUS_L1_SA2_CMD_OUT                                                                           0x2c60
8060 #define mmGUS_L1_SA2_CMD_OUT_BASE_IDX                                                                  1
8061 #define mmGUS_L1_SA2_DATA_IN                                                                           0x2c61
8062 #define mmGUS_L1_SA2_DATA_IN_BASE_IDX                                                                  1
8063 #define mmGUS_L1_SA2_DATA_OUT                                                                          0x2c62
8064 #define mmGUS_L1_SA2_DATA_OUT_BASE_IDX                                                                 1
8065 #define mmGUS_L1_SA2_DATA_U_IN                                                                         0x2c63
8066 #define mmGUS_L1_SA2_DATA_U_IN_BASE_IDX                                                                1
8067 #define mmGUS_L1_SA2_DATA_U_OUT                                                                        0x2c64
8068 #define mmGUS_L1_SA2_DATA_U_OUT_BASE_IDX                                                               1
8069 #define mmGUS_L1_SA3_CMD_IN                                                                            0x2c65
8070 #define mmGUS_L1_SA3_CMD_IN_BASE_IDX                                                                   1
8071 #define mmGUS_L1_SA3_CMD_OUT                                                                           0x2c66
8072 #define mmGUS_L1_SA3_CMD_OUT_BASE_IDX                                                                  1
8073 #define mmGUS_L1_SA3_DATA_IN                                                                           0x2c67
8074 #define mmGUS_L1_SA3_DATA_IN_BASE_IDX                                                                  1
8075 #define mmGUS_L1_SA3_DATA_OUT                                                                          0x2c68
8076 #define mmGUS_L1_SA3_DATA_OUT_BASE_IDX                                                                 1
8077 #define mmGUS_L1_SA3_DATA_U_IN                                                                         0x2c69
8078 #define mmGUS_L1_SA3_DATA_U_IN_BASE_IDX                                                                1
8079 #define mmGUS_L1_SA3_DATA_U_OUT                                                                        0x2c6a
8080 #define mmGUS_L1_SA3_DATA_U_OUT_BASE_IDX                                                               1
8081 #define mmGUS_MISC3                                                                                    0x2c6b
8082 #define mmGUS_MISC3_BASE_IDX                                                                           1
8083 #define mmGUS_WRRSP_FIFO_CNTL                                                                          0x2c6c
8084 #define mmGUS_WRRSP_FIFO_CNTL_BASE_IDX                                                                 1
8085 
8086 
8087 // addressBlock: gc_gl1dec
8088 // base address: 0x33400
8089 #define mmGL1_ARB_CTRL                                                                                 0x2d00
8090 #define mmGL1_ARB_CTRL_BASE_IDX                                                                        1
8091 #define mmGL1_DRAM_BURST_MASK                                                                          0x2d02
8092 #define mmGL1_DRAM_BURST_MASK_BASE_IDX                                                                 1
8093 #define mmGL1_ARB_STATUS                                                                               0x2d03
8094 #define mmGL1_ARB_STATUS_BASE_IDX                                                                      1
8095 #define mmGL1_DRAM_BURST_CTRL                                                                          0x2d04
8096 #define mmGL1_DRAM_BURST_CTRL_BASE_IDX                                                                 1
8097 #define mmGL1_PIPE_STEER                                                                               0x2d10
8098 #define mmGL1_PIPE_STEER_BASE_IDX                                                                      1
8099 #define mmGL1C_CTRL                                                                                    0x2d40
8100 #define mmGL1C_CTRL_BASE_IDX                                                                           1
8101 #define mmGL1C_STATUS                                                                                  0x2d41
8102 #define mmGL1C_STATUS_BASE_IDX                                                                         1
8103 
8104 
8105 // addressBlock: gc_chdec
8106 // base address: 0x33600
8107 #define mmCH_ARB_CTRL                                                                                  0x2d80
8108 #define mmCH_ARB_CTRL_BASE_IDX                                                                         1
8109 #define mmCH_DRAM_BURST_MASK                                                                           0x2d82
8110 #define mmCH_DRAM_BURST_MASK_BASE_IDX                                                                  1
8111 #define mmCH_ARB_STATUS                                                                                0x2d83
8112 #define mmCH_ARB_STATUS_BASE_IDX                                                                       1
8113 #define mmCH_DRAM_BURST_CTRL                                                                           0x2d84
8114 #define mmCH_DRAM_BURST_CTRL_BASE_IDX                                                                  1
8115 #define mmCH_PIPE_STEER                                                                                0x2d90
8116 #define mmCH_PIPE_STEER_BASE_IDX                                                                       1
8117 #define mmCH_VC5_ENABLE                                                                                0x2d94
8118 #define mmCH_VC5_ENABLE_BASE_IDX                                                                       1
8119 #define mmCHC_CTRL                                                                                     0x2dc0
8120 #define mmCHC_CTRL_BASE_IDX                                                                            1
8121 #define mmCHC_STATUS                                                                                   0x2dc1
8122 #define mmCHC_STATUS_BASE_IDX                                                                          1
8123 #define mmCHCG_CTRL                                                                                    0x2dc2
8124 #define mmCHCG_CTRL_BASE_IDX                                                                           1
8125 #define mmCHCG_STATUS                                                                                  0x2dc3
8126 #define mmCHCG_STATUS_BASE_IDX                                                                         1
8127 
8128 
8129 // addressBlock: gc_gl2dec
8130 // base address: 0x33800
8131 #define mmGL2C_CTRL                                                                                    0x2e00
8132 #define mmGL2C_CTRL_BASE_IDX                                                                           1
8133 #define mmGL2C_CTRL2                                                                                   0x2e01
8134 #define mmGL2C_CTRL2_BASE_IDX                                                                          1
8135 #define mmGL2C_STATUS                                                                                  0x2e02
8136 #define mmGL2C_STATUS_BASE_IDX                                                                         1
8137 #define mmGL2C_ADDR_MATCH_MASK                                                                         0x2e03
8138 #define mmGL2C_ADDR_MATCH_MASK_BASE_IDX                                                                1
8139 #define mmGL2C_ADDR_MATCH_SIZE                                                                         0x2e04
8140 #define mmGL2C_ADDR_MATCH_SIZE_BASE_IDX                                                                1
8141 #define mmGL2C_WBINVL2                                                                                 0x2e05
8142 #define mmGL2C_WBINVL2_BASE_IDX                                                                        1
8143 #define mmGL2C_SOFT_RESET                                                                              0x2e06
8144 #define mmGL2C_SOFT_RESET_BASE_IDX                                                                     1
8145 #define mmGL2C_CM_CTRL0                                                                                0x2e07
8146 #define mmGL2C_CM_CTRL0_BASE_IDX                                                                       1
8147 #define mmGL2C_CM_CTRL1                                                                                0x2e08
8148 #define mmGL2C_CM_CTRL1_BASE_IDX                                                                       1
8149 #define mmGL2C_CM_STALL                                                                                0x2e09
8150 #define mmGL2C_CM_STALL_BASE_IDX                                                                       1
8151 #define mmGL2C_MDC_PF_FLAG_CTRL                                                                        0x2e0a
8152 #define mmGL2C_MDC_PF_FLAG_CTRL_BASE_IDX                                                               1
8153 #define mmGL2C_CM_CTRL2                                                                                0x2e0b
8154 #define mmGL2C_CM_CTRL2_BASE_IDX                                                                       1
8155 #define mmGL2C_CTRL3                                                                                   0x2e0c
8156 #define mmGL2C_CTRL3_BASE_IDX                                                                          1
8157 #define mmGL2C_LB_CTR_CTRL                                                                             0x2e0d
8158 #define mmGL2C_LB_CTR_CTRL_BASE_IDX                                                                    1
8159 #define mmGL2C_LB_DATA0                                                                                0x2e0e
8160 #define mmGL2C_LB_DATA0_BASE_IDX                                                                       1
8161 #define mmGL2C_LB_DATA1                                                                                0x2e0f
8162 #define mmGL2C_LB_DATA1_BASE_IDX                                                                       1
8163 #define mmGL2C_LB_DATA2                                                                                0x2e10
8164 #define mmGL2C_LB_DATA2_BASE_IDX                                                                       1
8165 #define mmGL2C_LB_DATA3                                                                                0x2e11
8166 #define mmGL2C_LB_DATA3_BASE_IDX                                                                       1
8167 #define mmGL2C_LB_CTR_SEL0                                                                             0x2e12
8168 #define mmGL2C_LB_CTR_SEL0_BASE_IDX                                                                    1
8169 #define mmGL2C_LB_CTR_SEL1                                                                             0x2e13
8170 #define mmGL2C_LB_CTR_SEL1_BASE_IDX                                                                    1
8171 #define mmGL2A_ADDR_MATCH_CTRL                                                                         0x2e20
8172 #define mmGL2A_ADDR_MATCH_CTRL_BASE_IDX                                                                1
8173 #define mmGL2A_ADDR_MATCH_MASK                                                                         0x2e21
8174 #define mmGL2A_ADDR_MATCH_MASK_BASE_IDX                                                                1
8175 #define mmGL2A_ADDR_MATCH_SIZE                                                                         0x2e22
8176 #define mmGL2A_ADDR_MATCH_SIZE_BASE_IDX                                                                1
8177 #define mmGL2A_PRIORITY_CTRL                                                                           0x2e23
8178 #define mmGL2A_PRIORITY_CTRL_BASE_IDX                                                                  1
8179 #define mmGL2A_CTRL                                                                                    0x2e24
8180 #define mmGL2A_CTRL_BASE_IDX                                                                           1
8181 #define mmGL2_PIPE_STEER_0                                                                             0x2e25
8182 #define mmGL2_PIPE_STEER_0_BASE_IDX                                                                    1
8183 #define mmGL2_PIPE_STEER_1                                                                             0x2e26
8184 #define mmGL2_PIPE_STEER_1_BASE_IDX                                                                    1
8185 
8186 
8187 // addressBlock: gc_perfddec
8188 // base address: 0x34000
8189 #define mmCPG_PERFCOUNTER1_LO                                                                          0x3000
8190 #define mmCPG_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8191 #define mmCPG_PERFCOUNTER1_HI                                                                          0x3001
8192 #define mmCPG_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8193 #define mmCPG_PERFCOUNTER0_LO                                                                          0x3002
8194 #define mmCPG_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8195 #define mmCPG_PERFCOUNTER0_HI                                                                          0x3003
8196 #define mmCPG_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8197 #define mmCPC_PERFCOUNTER1_LO                                                                          0x3004
8198 #define mmCPC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8199 #define mmCPC_PERFCOUNTER1_HI                                                                          0x3005
8200 #define mmCPC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8201 #define mmCPC_PERFCOUNTER0_LO                                                                          0x3006
8202 #define mmCPC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8203 #define mmCPC_PERFCOUNTER0_HI                                                                          0x3007
8204 #define mmCPC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8205 #define mmCPF_PERFCOUNTER1_LO                                                                          0x3008
8206 #define mmCPF_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8207 #define mmCPF_PERFCOUNTER1_HI                                                                          0x3009
8208 #define mmCPF_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8209 #define mmCPF_PERFCOUNTER0_LO                                                                          0x300a
8210 #define mmCPF_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8211 #define mmCPF_PERFCOUNTER0_HI                                                                          0x300b
8212 #define mmCPF_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8213 #define mmCPF_LATENCY_STATS_DATA                                                                       0x300c
8214 #define mmCPF_LATENCY_STATS_DATA_BASE_IDX                                                              1
8215 #define mmCPG_LATENCY_STATS_DATA                                                                       0x300d
8216 #define mmCPG_LATENCY_STATS_DATA_BASE_IDX                                                              1
8217 #define mmCPC_LATENCY_STATS_DATA                                                                       0x300e
8218 #define mmCPC_LATENCY_STATS_DATA_BASE_IDX                                                              1
8219 #define mmGRBM_PERFCOUNTER0_LO                                                                         0x3040
8220 #define mmGRBM_PERFCOUNTER0_LO_BASE_IDX                                                                1
8221 #define mmGRBM_PERFCOUNTER0_HI                                                                         0x3041
8222 #define mmGRBM_PERFCOUNTER0_HI_BASE_IDX                                                                1
8223 #define mmGRBM_PERFCOUNTER1_LO                                                                         0x3043
8224 #define mmGRBM_PERFCOUNTER1_LO_BASE_IDX                                                                1
8225 #define mmGRBM_PERFCOUNTER1_HI                                                                         0x3044
8226 #define mmGRBM_PERFCOUNTER1_HI_BASE_IDX                                                                1
8227 #define mmGRBM_SE0_PERFCOUNTER_LO                                                                      0x3045
8228 #define mmGRBM_SE0_PERFCOUNTER_LO_BASE_IDX                                                             1
8229 #define mmGRBM_SE0_PERFCOUNTER_HI                                                                      0x3046
8230 #define mmGRBM_SE0_PERFCOUNTER_HI_BASE_IDX                                                             1
8231 #define mmGRBM_SE1_PERFCOUNTER_LO                                                                      0x3047
8232 #define mmGRBM_SE1_PERFCOUNTER_LO_BASE_IDX                                                             1
8233 #define mmGRBM_SE1_PERFCOUNTER_HI                                                                      0x3048
8234 #define mmGRBM_SE1_PERFCOUNTER_HI_BASE_IDX                                                             1
8235 #define mmGRBM_SE2_PERFCOUNTER_LO                                                                      0x3049
8236 #define mmGRBM_SE2_PERFCOUNTER_LO_BASE_IDX                                                             1
8237 #define mmGRBM_SE2_PERFCOUNTER_HI                                                                      0x304a
8238 #define mmGRBM_SE2_PERFCOUNTER_HI_BASE_IDX                                                             1
8239 #define mmGRBM_SE3_PERFCOUNTER_LO                                                                      0x304b
8240 #define mmGRBM_SE3_PERFCOUNTER_LO_BASE_IDX                                                             1
8241 #define mmGRBM_SE3_PERFCOUNTER_HI                                                                      0x304c
8242 #define mmGRBM_SE3_PERFCOUNTER_HI_BASE_IDX                                                             1
8243 #define mmGE_PERFCOUNTER0_LO                                                                           0x3080
8244 #define mmGE_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8245 #define mmGE_PERFCOUNTER0_HI                                                                           0x3081
8246 #define mmGE_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8247 #define mmGE_PERFCOUNTER1_LO                                                                           0x3082
8248 #define mmGE_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8249 #define mmGE_PERFCOUNTER1_HI                                                                           0x3083
8250 #define mmGE_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8251 #define mmGE_PERFCOUNTER2_LO                                                                           0x3084
8252 #define mmGE_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8253 #define mmGE_PERFCOUNTER2_HI                                                                           0x3085
8254 #define mmGE_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8255 #define mmGE_PERFCOUNTER3_LO                                                                           0x3086
8256 #define mmGE_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8257 #define mmGE_PERFCOUNTER3_HI                                                                           0x3087
8258 #define mmGE_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8259 #define mmGE_PERFCOUNTER4_LO                                                                           0x3088
8260 #define mmGE_PERFCOUNTER4_LO_BASE_IDX                                                                  1
8261 #define mmGE_PERFCOUNTER4_HI                                                                           0x3089
8262 #define mmGE_PERFCOUNTER4_HI_BASE_IDX                                                                  1
8263 #define mmGE_PERFCOUNTER5_LO                                                                           0x308a
8264 #define mmGE_PERFCOUNTER5_LO_BASE_IDX                                                                  1
8265 #define mmGE_PERFCOUNTER5_HI                                                                           0x308b
8266 #define mmGE_PERFCOUNTER5_HI_BASE_IDX                                                                  1
8267 #define mmGE_PERFCOUNTER6_LO                                                                           0x308c
8268 #define mmGE_PERFCOUNTER6_LO_BASE_IDX                                                                  1
8269 #define mmGE_PERFCOUNTER6_HI                                                                           0x308d
8270 #define mmGE_PERFCOUNTER6_HI_BASE_IDX                                                                  1
8271 #define mmGE_PERFCOUNTER7_LO                                                                           0x308e
8272 #define mmGE_PERFCOUNTER7_LO_BASE_IDX                                                                  1
8273 #define mmGE_PERFCOUNTER7_HI                                                                           0x308f
8274 #define mmGE_PERFCOUNTER7_HI_BASE_IDX                                                                  1
8275 #define mmGE_PERFCOUNTER8_LO                                                                           0x3090
8276 #define mmGE_PERFCOUNTER8_LO_BASE_IDX                                                                  1
8277 #define mmGE_PERFCOUNTER8_HI                                                                           0x3091
8278 #define mmGE_PERFCOUNTER8_HI_BASE_IDX                                                                  1
8279 #define mmGE_PERFCOUNTER9_LO                                                                           0x3092
8280 #define mmGE_PERFCOUNTER9_LO_BASE_IDX                                                                  1
8281 #define mmGE_PERFCOUNTER9_HI                                                                           0x3093
8282 #define mmGE_PERFCOUNTER9_HI_BASE_IDX                                                                  1
8283 #define mmGE_PERFCOUNTER10_LO                                                                          0x3094
8284 #define mmGE_PERFCOUNTER10_LO_BASE_IDX                                                                 1
8285 #define mmGE_PERFCOUNTER10_HI                                                                          0x3095
8286 #define mmGE_PERFCOUNTER10_HI_BASE_IDX                                                                 1
8287 #define mmGE_PERFCOUNTER11_LO                                                                          0x3096
8288 #define mmGE_PERFCOUNTER11_LO_BASE_IDX                                                                 1
8289 #define mmGE_PERFCOUNTER11_HI                                                                          0x3097
8290 #define mmGE_PERFCOUNTER11_HI_BASE_IDX                                                                 1
8291 #define mmPA_SU_PERFCOUNTER0_LO                                                                        0x3100
8292 #define mmPA_SU_PERFCOUNTER0_LO_BASE_IDX                                                               1
8293 #define mmPA_SU_PERFCOUNTER0_HI                                                                        0x3101
8294 #define mmPA_SU_PERFCOUNTER0_HI_BASE_IDX                                                               1
8295 #define mmPA_SU_PERFCOUNTER1_LO                                                                        0x3102
8296 #define mmPA_SU_PERFCOUNTER1_LO_BASE_IDX                                                               1
8297 #define mmPA_SU_PERFCOUNTER1_HI                                                                        0x3103
8298 #define mmPA_SU_PERFCOUNTER1_HI_BASE_IDX                                                               1
8299 #define mmPA_SU_PERFCOUNTER2_LO                                                                        0x3104
8300 #define mmPA_SU_PERFCOUNTER2_LO_BASE_IDX                                                               1
8301 #define mmPA_SU_PERFCOUNTER2_HI                                                                        0x3105
8302 #define mmPA_SU_PERFCOUNTER2_HI_BASE_IDX                                                               1
8303 #define mmPA_SU_PERFCOUNTER3_LO                                                                        0x3106
8304 #define mmPA_SU_PERFCOUNTER3_LO_BASE_IDX                                                               1
8305 #define mmPA_SU_PERFCOUNTER3_HI                                                                        0x3107
8306 #define mmPA_SU_PERFCOUNTER3_HI_BASE_IDX                                                               1
8307 #define mmPA_SC_PERFCOUNTER0_LO                                                                        0x3140
8308 #define mmPA_SC_PERFCOUNTER0_LO_BASE_IDX                                                               1
8309 #define mmPA_SC_PERFCOUNTER0_HI                                                                        0x3141
8310 #define mmPA_SC_PERFCOUNTER0_HI_BASE_IDX                                                               1
8311 #define mmPA_SC_PERFCOUNTER1_LO                                                                        0x3142
8312 #define mmPA_SC_PERFCOUNTER1_LO_BASE_IDX                                                               1
8313 #define mmPA_SC_PERFCOUNTER1_HI                                                                        0x3143
8314 #define mmPA_SC_PERFCOUNTER1_HI_BASE_IDX                                                               1
8315 #define mmPA_SC_PERFCOUNTER2_LO                                                                        0x3144
8316 #define mmPA_SC_PERFCOUNTER2_LO_BASE_IDX                                                               1
8317 #define mmPA_SC_PERFCOUNTER2_HI                                                                        0x3145
8318 #define mmPA_SC_PERFCOUNTER2_HI_BASE_IDX                                                               1
8319 #define mmPA_SC_PERFCOUNTER3_LO                                                                        0x3146
8320 #define mmPA_SC_PERFCOUNTER3_LO_BASE_IDX                                                               1
8321 #define mmPA_SC_PERFCOUNTER3_HI                                                                        0x3147
8322 #define mmPA_SC_PERFCOUNTER3_HI_BASE_IDX                                                               1
8323 #define mmPA_SC_PERFCOUNTER4_LO                                                                        0x3148
8324 #define mmPA_SC_PERFCOUNTER4_LO_BASE_IDX                                                               1
8325 #define mmPA_SC_PERFCOUNTER4_HI                                                                        0x3149
8326 #define mmPA_SC_PERFCOUNTER4_HI_BASE_IDX                                                               1
8327 #define mmPA_SC_PERFCOUNTER5_LO                                                                        0x314a
8328 #define mmPA_SC_PERFCOUNTER5_LO_BASE_IDX                                                               1
8329 #define mmPA_SC_PERFCOUNTER5_HI                                                                        0x314b
8330 #define mmPA_SC_PERFCOUNTER5_HI_BASE_IDX                                                               1
8331 #define mmPA_SC_PERFCOUNTER6_LO                                                                        0x314c
8332 #define mmPA_SC_PERFCOUNTER6_LO_BASE_IDX                                                               1
8333 #define mmPA_SC_PERFCOUNTER6_HI                                                                        0x314d
8334 #define mmPA_SC_PERFCOUNTER6_HI_BASE_IDX                                                               1
8335 #define mmPA_SC_PERFCOUNTER7_LO                                                                        0x314e
8336 #define mmPA_SC_PERFCOUNTER7_LO_BASE_IDX                                                               1
8337 #define mmPA_SC_PERFCOUNTER7_HI                                                                        0x314f
8338 #define mmPA_SC_PERFCOUNTER7_HI_BASE_IDX                                                               1
8339 #define mmSPI_PERFCOUNTER0_HI                                                                          0x3180
8340 #define mmSPI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8341 #define mmSPI_PERFCOUNTER0_LO                                                                          0x3181
8342 #define mmSPI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8343 #define mmSPI_PERFCOUNTER1_HI                                                                          0x3182
8344 #define mmSPI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8345 #define mmSPI_PERFCOUNTER1_LO                                                                          0x3183
8346 #define mmSPI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8347 #define mmSPI_PERFCOUNTER2_HI                                                                          0x3184
8348 #define mmSPI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8349 #define mmSPI_PERFCOUNTER2_LO                                                                          0x3185
8350 #define mmSPI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8351 #define mmSPI_PERFCOUNTER3_HI                                                                          0x3186
8352 #define mmSPI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8353 #define mmSPI_PERFCOUNTER3_LO                                                                          0x3187
8354 #define mmSPI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8355 #define mmSPI_PERFCOUNTER4_HI                                                                          0x3188
8356 #define mmSPI_PERFCOUNTER4_HI_BASE_IDX                                                                 1
8357 #define mmSPI_PERFCOUNTER4_LO                                                                          0x3189
8358 #define mmSPI_PERFCOUNTER4_LO_BASE_IDX                                                                 1
8359 #define mmSPI_PERFCOUNTER5_HI                                                                          0x318a
8360 #define mmSPI_PERFCOUNTER5_HI_BASE_IDX                                                                 1
8361 #define mmSPI_PERFCOUNTER5_LO                                                                          0x318b
8362 #define mmSPI_PERFCOUNTER5_LO_BASE_IDX                                                                 1
8363 #define mmSQ_PERFCOUNTER0_LO                                                                           0x31c0
8364 #define mmSQ_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8365 #define mmSQ_PERFCOUNTER0_HI                                                                           0x31c1
8366 #define mmSQ_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8367 #define mmSQ_PERFCOUNTER1_LO                                                                           0x31c2
8368 #define mmSQ_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8369 #define mmSQ_PERFCOUNTER1_HI                                                                           0x31c3
8370 #define mmSQ_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8371 #define mmSQ_PERFCOUNTER2_LO                                                                           0x31c4
8372 #define mmSQ_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8373 #define mmSQ_PERFCOUNTER2_HI                                                                           0x31c5
8374 #define mmSQ_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8375 #define mmSQ_PERFCOUNTER3_LO                                                                           0x31c6
8376 #define mmSQ_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8377 #define mmSQ_PERFCOUNTER3_HI                                                                           0x31c7
8378 #define mmSQ_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8379 #define mmSQ_PERFCOUNTER4_LO                                                                           0x31c8
8380 #define mmSQ_PERFCOUNTER4_LO_BASE_IDX                                                                  1
8381 #define mmSQ_PERFCOUNTER4_HI                                                                           0x31c9
8382 #define mmSQ_PERFCOUNTER4_HI_BASE_IDX                                                                  1
8383 #define mmSQ_PERFCOUNTER5_LO                                                                           0x31ca
8384 #define mmSQ_PERFCOUNTER5_LO_BASE_IDX                                                                  1
8385 #define mmSQ_PERFCOUNTER5_HI                                                                           0x31cb
8386 #define mmSQ_PERFCOUNTER5_HI_BASE_IDX                                                                  1
8387 #define mmSQ_PERFCOUNTER6_LO                                                                           0x31cc
8388 #define mmSQ_PERFCOUNTER6_LO_BASE_IDX                                                                  1
8389 #define mmSQ_PERFCOUNTER6_HI                                                                           0x31cd
8390 #define mmSQ_PERFCOUNTER6_HI_BASE_IDX                                                                  1
8391 #define mmSQ_PERFCOUNTER7_LO                                                                           0x31ce
8392 #define mmSQ_PERFCOUNTER7_LO_BASE_IDX                                                                  1
8393 #define mmSQ_PERFCOUNTER7_HI                                                                           0x31cf
8394 #define mmSQ_PERFCOUNTER7_HI_BASE_IDX                                                                  1
8395 #define mmSQ_PERFCOUNTER8_LO                                                                           0x31d0
8396 #define mmSQ_PERFCOUNTER8_LO_BASE_IDX                                                                  1
8397 #define mmSQ_PERFCOUNTER8_HI                                                                           0x31d1
8398 #define mmSQ_PERFCOUNTER8_HI_BASE_IDX                                                                  1
8399 #define mmSQ_PERFCOUNTER9_LO                                                                           0x31d2
8400 #define mmSQ_PERFCOUNTER9_LO_BASE_IDX                                                                  1
8401 #define mmSQ_PERFCOUNTER9_HI                                                                           0x31d3
8402 #define mmSQ_PERFCOUNTER9_HI_BASE_IDX                                                                  1
8403 #define mmSQ_PERFCOUNTER10_LO                                                                          0x31d4
8404 #define mmSQ_PERFCOUNTER10_LO_BASE_IDX                                                                 1
8405 #define mmSQ_PERFCOUNTER10_HI                                                                          0x31d5
8406 #define mmSQ_PERFCOUNTER10_HI_BASE_IDX                                                                 1
8407 #define mmSQ_PERFCOUNTER11_LO                                                                          0x31d6
8408 #define mmSQ_PERFCOUNTER11_LO_BASE_IDX                                                                 1
8409 #define mmSQ_PERFCOUNTER11_HI                                                                          0x31d7
8410 #define mmSQ_PERFCOUNTER11_HI_BASE_IDX                                                                 1
8411 #define mmSQ_PERFCOUNTER12_LO                                                                          0x31d8
8412 #define mmSQ_PERFCOUNTER12_LO_BASE_IDX                                                                 1
8413 #define mmSQ_PERFCOUNTER12_HI                                                                          0x31d9
8414 #define mmSQ_PERFCOUNTER12_HI_BASE_IDX                                                                 1
8415 #define mmSQ_PERFCOUNTER13_LO                                                                          0x31da
8416 #define mmSQ_PERFCOUNTER13_LO_BASE_IDX                                                                 1
8417 #define mmSQ_PERFCOUNTER13_HI                                                                          0x31db
8418 #define mmSQ_PERFCOUNTER13_HI_BASE_IDX                                                                 1
8419 #define mmSQ_PERFCOUNTER14_LO                                                                          0x31dc
8420 #define mmSQ_PERFCOUNTER14_LO_BASE_IDX                                                                 1
8421 #define mmSQ_PERFCOUNTER14_HI                                                                          0x31dd
8422 #define mmSQ_PERFCOUNTER14_HI_BASE_IDX                                                                 1
8423 #define mmSQ_PERFCOUNTER15_LO                                                                          0x31de
8424 #define mmSQ_PERFCOUNTER15_LO_BASE_IDX                                                                 1
8425 #define mmSQ_PERFCOUNTER15_HI                                                                          0x31df
8426 #define mmSQ_PERFCOUNTER15_HI_BASE_IDX                                                                 1
8427 #define mmSX_PERFCOUNTER0_LO                                                                           0x3240
8428 #define mmSX_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8429 #define mmSX_PERFCOUNTER0_HI                                                                           0x3241
8430 #define mmSX_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8431 #define mmSX_PERFCOUNTER1_LO                                                                           0x3242
8432 #define mmSX_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8433 #define mmSX_PERFCOUNTER1_HI                                                                           0x3243
8434 #define mmSX_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8435 #define mmSX_PERFCOUNTER2_LO                                                                           0x3244
8436 #define mmSX_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8437 #define mmSX_PERFCOUNTER2_HI                                                                           0x3245
8438 #define mmSX_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8439 #define mmSX_PERFCOUNTER3_LO                                                                           0x3246
8440 #define mmSX_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8441 #define mmSX_PERFCOUNTER3_HI                                                                           0x3247
8442 #define mmSX_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8443 #define mmGCEA_PERFCOUNTER2_LO                                                                         0x3260
8444 #define mmGCEA_PERFCOUNTER2_LO_BASE_IDX                                                                1
8445 #define mmGCEA_PERFCOUNTER2_HI                                                                         0x3261
8446 #define mmGCEA_PERFCOUNTER2_HI_BASE_IDX                                                                1
8447 #define mmGDS_PERFCOUNTER0_LO                                                                          0x3280
8448 #define mmGDS_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8449 #define mmGDS_PERFCOUNTER0_HI                                                                          0x3281
8450 #define mmGDS_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8451 #define mmGDS_PERFCOUNTER1_LO                                                                          0x3282
8452 #define mmGDS_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8453 #define mmGDS_PERFCOUNTER1_HI                                                                          0x3283
8454 #define mmGDS_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8455 #define mmGDS_PERFCOUNTER2_LO                                                                          0x3284
8456 #define mmGDS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8457 #define mmGDS_PERFCOUNTER2_HI                                                                          0x3285
8458 #define mmGDS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8459 #define mmGDS_PERFCOUNTER3_LO                                                                          0x3286
8460 #define mmGDS_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8461 #define mmGDS_PERFCOUNTER3_HI                                                                          0x3287
8462 #define mmGDS_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8463 #define mmTA_PERFCOUNTER0_LO                                                                           0x32c0
8464 #define mmTA_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8465 #define mmTA_PERFCOUNTER0_HI                                                                           0x32c1
8466 #define mmTA_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8467 #define mmTA_PERFCOUNTER1_LO                                                                           0x32c2
8468 #define mmTA_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8469 #define mmTA_PERFCOUNTER1_HI                                                                           0x32c3
8470 #define mmTA_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8471 #define mmTD_PERFCOUNTER0_LO                                                                           0x3300
8472 #define mmTD_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8473 #define mmTD_PERFCOUNTER0_HI                                                                           0x3301
8474 #define mmTD_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8475 #define mmTD_PERFCOUNTER1_LO                                                                           0x3302
8476 #define mmTD_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8477 #define mmTD_PERFCOUNTER1_HI                                                                           0x3303
8478 #define mmTD_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8479 #define mmTCP_PERFCOUNTER0_LO                                                                          0x3340
8480 #define mmTCP_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8481 #define mmTCP_PERFCOUNTER0_HI                                                                          0x3341
8482 #define mmTCP_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8483 #define mmTCP_PERFCOUNTER1_LO                                                                          0x3342
8484 #define mmTCP_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8485 #define mmTCP_PERFCOUNTER1_HI                                                                          0x3343
8486 #define mmTCP_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8487 #define mmTCP_PERFCOUNTER2_LO                                                                          0x3344
8488 #define mmTCP_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8489 #define mmTCP_PERFCOUNTER2_HI                                                                          0x3345
8490 #define mmTCP_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8491 #define mmTCP_PERFCOUNTER3_LO                                                                          0x3346
8492 #define mmTCP_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8493 #define mmTCP_PERFCOUNTER3_HI                                                                          0x3347
8494 #define mmTCP_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8495 #define mmGL2C_PERFCOUNTER0_LO                                                                         0x3380
8496 #define mmGL2C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8497 #define mmGL2C_PERFCOUNTER0_HI                                                                         0x3381
8498 #define mmGL2C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8499 #define mmGL2C_PERFCOUNTER1_LO                                                                         0x3382
8500 #define mmGL2C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8501 #define mmGL2C_PERFCOUNTER1_HI                                                                         0x3383
8502 #define mmGL2C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8503 #define mmGL2C_PERFCOUNTER2_LO                                                                         0x3384
8504 #define mmGL2C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8505 #define mmGL2C_PERFCOUNTER2_HI                                                                         0x3385
8506 #define mmGL2C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8507 #define mmGL2C_PERFCOUNTER3_LO                                                                         0x3386
8508 #define mmGL2C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8509 #define mmGL2C_PERFCOUNTER3_HI                                                                         0x3387
8510 #define mmGL2C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8511 #define mmGL2A_PERFCOUNTER0_LO                                                                         0x3390
8512 #define mmGL2A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8513 #define mmGL2A_PERFCOUNTER0_HI                                                                         0x3391
8514 #define mmGL2A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8515 #define mmGL2A_PERFCOUNTER1_LO                                                                         0x3392
8516 #define mmGL2A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8517 #define mmGL2A_PERFCOUNTER1_HI                                                                         0x3393
8518 #define mmGL2A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8519 #define mmGL2A_PERFCOUNTER2_LO                                                                         0x3394
8520 #define mmGL2A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8521 #define mmGL2A_PERFCOUNTER2_HI                                                                         0x3395
8522 #define mmGL2A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8523 #define mmGL2A_PERFCOUNTER3_LO                                                                         0x3396
8524 #define mmGL2A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8525 #define mmGL2A_PERFCOUNTER3_HI                                                                         0x3397
8526 #define mmGL2A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8527 #define mmGL1C_PERFCOUNTER0_LO                                                                         0x33a0
8528 #define mmGL1C_PERFCOUNTER0_LO_BASE_IDX                                                                1
8529 #define mmGL1C_PERFCOUNTER0_HI                                                                         0x33a1
8530 #define mmGL1C_PERFCOUNTER0_HI_BASE_IDX                                                                1
8531 #define mmGL1C_PERFCOUNTER1_LO                                                                         0x33a2
8532 #define mmGL1C_PERFCOUNTER1_LO_BASE_IDX                                                                1
8533 #define mmGL1C_PERFCOUNTER1_HI                                                                         0x33a3
8534 #define mmGL1C_PERFCOUNTER1_HI_BASE_IDX                                                                1
8535 #define mmGL1C_PERFCOUNTER2_LO                                                                         0x33a4
8536 #define mmGL1C_PERFCOUNTER2_LO_BASE_IDX                                                                1
8537 #define mmGL1C_PERFCOUNTER2_HI                                                                         0x33a5
8538 #define mmGL1C_PERFCOUNTER2_HI_BASE_IDX                                                                1
8539 #define mmGL1C_PERFCOUNTER3_LO                                                                         0x33a6
8540 #define mmGL1C_PERFCOUNTER3_LO_BASE_IDX                                                                1
8541 #define mmGL1C_PERFCOUNTER3_HI                                                                         0x33a7
8542 #define mmGL1C_PERFCOUNTER3_HI_BASE_IDX                                                                1
8543 #define mmCHC_PERFCOUNTER0_LO                                                                          0x33c0
8544 #define mmCHC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8545 #define mmCHC_PERFCOUNTER0_HI                                                                          0x33c1
8546 #define mmCHC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8547 #define mmCHC_PERFCOUNTER1_LO                                                                          0x33c2
8548 #define mmCHC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8549 #define mmCHC_PERFCOUNTER1_HI                                                                          0x33c3
8550 #define mmCHC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8551 #define mmCHC_PERFCOUNTER2_LO                                                                          0x33c4
8552 #define mmCHC_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8553 #define mmCHC_PERFCOUNTER2_HI                                                                          0x33c5
8554 #define mmCHC_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8555 #define mmCHC_PERFCOUNTER3_LO                                                                          0x33c6
8556 #define mmCHC_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8557 #define mmCHC_PERFCOUNTER3_HI                                                                          0x33c7
8558 #define mmCHC_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8559 #define mmCHCG_PERFCOUNTER0_LO                                                                         0x33c8
8560 #define mmCHCG_PERFCOUNTER0_LO_BASE_IDX                                                                1
8561 #define mmCHCG_PERFCOUNTER0_HI                                                                         0x33c9
8562 #define mmCHCG_PERFCOUNTER0_HI_BASE_IDX                                                                1
8563 #define mmCHCG_PERFCOUNTER1_LO                                                                         0x33ca
8564 #define mmCHCG_PERFCOUNTER1_LO_BASE_IDX                                                                1
8565 #define mmCHCG_PERFCOUNTER1_HI                                                                         0x33cb
8566 #define mmCHCG_PERFCOUNTER1_HI_BASE_IDX                                                                1
8567 #define mmCHCG_PERFCOUNTER2_LO                                                                         0x33cc
8568 #define mmCHCG_PERFCOUNTER2_LO_BASE_IDX                                                                1
8569 #define mmCHCG_PERFCOUNTER2_HI                                                                         0x33cd
8570 #define mmCHCG_PERFCOUNTER2_HI_BASE_IDX                                                                1
8571 #define mmCHCG_PERFCOUNTER3_LO                                                                         0x33ce
8572 #define mmCHCG_PERFCOUNTER3_LO_BASE_IDX                                                                1
8573 #define mmCHCG_PERFCOUNTER3_HI                                                                         0x33cf
8574 #define mmCHCG_PERFCOUNTER3_HI_BASE_IDX                                                                1
8575 #define mmCB_PERFCOUNTER0_LO                                                                           0x3406
8576 #define mmCB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8577 #define mmCB_PERFCOUNTER0_HI                                                                           0x3407
8578 #define mmCB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8579 #define mmCB_PERFCOUNTER1_LO                                                                           0x3408
8580 #define mmCB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8581 #define mmCB_PERFCOUNTER1_HI                                                                           0x3409
8582 #define mmCB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8583 #define mmCB_PERFCOUNTER2_LO                                                                           0x340a
8584 #define mmCB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8585 #define mmCB_PERFCOUNTER2_HI                                                                           0x340b
8586 #define mmCB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8587 #define mmCB_PERFCOUNTER3_LO                                                                           0x340c
8588 #define mmCB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8589 #define mmCB_PERFCOUNTER3_HI                                                                           0x340d
8590 #define mmCB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8591 #define mmDB_PERFCOUNTER0_LO                                                                           0x3440
8592 #define mmDB_PERFCOUNTER0_LO_BASE_IDX                                                                  1
8593 #define mmDB_PERFCOUNTER0_HI                                                                           0x3441
8594 #define mmDB_PERFCOUNTER0_HI_BASE_IDX                                                                  1
8595 #define mmDB_PERFCOUNTER1_LO                                                                           0x3442
8596 #define mmDB_PERFCOUNTER1_LO_BASE_IDX                                                                  1
8597 #define mmDB_PERFCOUNTER1_HI                                                                           0x3443
8598 #define mmDB_PERFCOUNTER1_HI_BASE_IDX                                                                  1
8599 #define mmDB_PERFCOUNTER2_LO                                                                           0x3444
8600 #define mmDB_PERFCOUNTER2_LO_BASE_IDX                                                                  1
8601 #define mmDB_PERFCOUNTER2_HI                                                                           0x3445
8602 #define mmDB_PERFCOUNTER2_HI_BASE_IDX                                                                  1
8603 #define mmDB_PERFCOUNTER3_LO                                                                           0x3446
8604 #define mmDB_PERFCOUNTER3_LO_BASE_IDX                                                                  1
8605 #define mmDB_PERFCOUNTER3_HI                                                                           0x3447
8606 #define mmDB_PERFCOUNTER3_HI_BASE_IDX                                                                  1
8607 #define mmRLC_PERFCOUNTER0_LO                                                                          0x3480
8608 #define mmRLC_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8609 #define mmRLC_PERFCOUNTER0_HI                                                                          0x3481
8610 #define mmRLC_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8611 #define mmRLC_PERFCOUNTER1_LO                                                                          0x3482
8612 #define mmRLC_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8613 #define mmRLC_PERFCOUNTER1_HI                                                                          0x3483
8614 #define mmRLC_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8615 #define mmRMI_PERFCOUNTER0_LO                                                                          0x34c0
8616 #define mmRMI_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8617 #define mmRMI_PERFCOUNTER0_HI                                                                          0x34c1
8618 #define mmRMI_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8619 #define mmRMI_PERFCOUNTER1_LO                                                                          0x34c2
8620 #define mmRMI_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8621 #define mmRMI_PERFCOUNTER1_HI                                                                          0x34c3
8622 #define mmRMI_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8623 #define mmRMI_PERFCOUNTER2_LO                                                                          0x34c4
8624 #define mmRMI_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8625 #define mmRMI_PERFCOUNTER2_HI                                                                          0x34c5
8626 #define mmRMI_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8627 #define mmRMI_PERFCOUNTER3_LO                                                                          0x34c6
8628 #define mmRMI_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8629 #define mmRMI_PERFCOUNTER3_HI                                                                          0x34c7
8630 #define mmRMI_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8631 #define mmUTCL1_PERFCOUNTER0_LO                                                                        0x351c
8632 #define mmUTCL1_PERFCOUNTER0_LO_BASE_IDX                                                               1
8633 #define mmUTCL1_PERFCOUNTER0_HI                                                                        0x351d
8634 #define mmUTCL1_PERFCOUNTER0_HI_BASE_IDX                                                               1
8635 #define mmUTCL1_PERFCOUNTER1_LO                                                                        0x351e
8636 #define mmUTCL1_PERFCOUNTER1_LO_BASE_IDX                                                               1
8637 #define mmUTCL1_PERFCOUNTER1_HI                                                                        0x351f
8638 #define mmUTCL1_PERFCOUNTER1_HI_BASE_IDX                                                               1
8639 #define mmGCR_PERFCOUNTER0_LO                                                                          0x3520
8640 #define mmGCR_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8641 #define mmGCR_PERFCOUNTER0_HI                                                                          0x3521
8642 #define mmGCR_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8643 #define mmGCR_PERFCOUNTER1_LO                                                                          0x3522
8644 #define mmGCR_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8645 #define mmGCR_PERFCOUNTER1_HI                                                                          0x3523
8646 #define mmGCR_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8647 #define mmPA_PH_PERFCOUNTER0_LO                                                                        0x3580
8648 #define mmPA_PH_PERFCOUNTER0_LO_BASE_IDX                                                               1
8649 #define mmPA_PH_PERFCOUNTER0_HI                                                                        0x3581
8650 #define mmPA_PH_PERFCOUNTER0_HI_BASE_IDX                                                               1
8651 #define mmPA_PH_PERFCOUNTER1_LO                                                                        0x3582
8652 #define mmPA_PH_PERFCOUNTER1_LO_BASE_IDX                                                               1
8653 #define mmPA_PH_PERFCOUNTER1_HI                                                                        0x3583
8654 #define mmPA_PH_PERFCOUNTER1_HI_BASE_IDX                                                               1
8655 #define mmPA_PH_PERFCOUNTER2_LO                                                                        0x3584
8656 #define mmPA_PH_PERFCOUNTER2_LO_BASE_IDX                                                               1
8657 #define mmPA_PH_PERFCOUNTER2_HI                                                                        0x3585
8658 #define mmPA_PH_PERFCOUNTER2_HI_BASE_IDX                                                               1
8659 #define mmPA_PH_PERFCOUNTER3_LO                                                                        0x3586
8660 #define mmPA_PH_PERFCOUNTER3_LO_BASE_IDX                                                               1
8661 #define mmPA_PH_PERFCOUNTER3_HI                                                                        0x3587
8662 #define mmPA_PH_PERFCOUNTER3_HI_BASE_IDX                                                               1
8663 #define mmPA_PH_PERFCOUNTER4_LO                                                                        0x3588
8664 #define mmPA_PH_PERFCOUNTER4_LO_BASE_IDX                                                               1
8665 #define mmPA_PH_PERFCOUNTER4_HI                                                                        0x3589
8666 #define mmPA_PH_PERFCOUNTER4_HI_BASE_IDX                                                               1
8667 #define mmPA_PH_PERFCOUNTER5_LO                                                                        0x358a
8668 #define mmPA_PH_PERFCOUNTER5_LO_BASE_IDX                                                               1
8669 #define mmPA_PH_PERFCOUNTER5_HI                                                                        0x358b
8670 #define mmPA_PH_PERFCOUNTER5_HI_BASE_IDX                                                               1
8671 #define mmPA_PH_PERFCOUNTER6_LO                                                                        0x358c
8672 #define mmPA_PH_PERFCOUNTER6_LO_BASE_IDX                                                               1
8673 #define mmPA_PH_PERFCOUNTER6_HI                                                                        0x358d
8674 #define mmPA_PH_PERFCOUNTER6_HI_BASE_IDX                                                               1
8675 #define mmPA_PH_PERFCOUNTER7_LO                                                                        0x358e
8676 #define mmPA_PH_PERFCOUNTER7_LO_BASE_IDX                                                               1
8677 #define mmPA_PH_PERFCOUNTER7_HI                                                                        0x358f
8678 #define mmPA_PH_PERFCOUNTER7_HI_BASE_IDX                                                               1
8679 #define mmGL1A_PERFCOUNTER0_LO                                                                         0x35c0
8680 #define mmGL1A_PERFCOUNTER0_LO_BASE_IDX                                                                1
8681 #define mmGL1A_PERFCOUNTER0_HI                                                                         0x35c1
8682 #define mmGL1A_PERFCOUNTER0_HI_BASE_IDX                                                                1
8683 #define mmGL1A_PERFCOUNTER1_LO                                                                         0x35c2
8684 #define mmGL1A_PERFCOUNTER1_LO_BASE_IDX                                                                1
8685 #define mmGL1A_PERFCOUNTER1_HI                                                                         0x35c3
8686 #define mmGL1A_PERFCOUNTER1_HI_BASE_IDX                                                                1
8687 #define mmGL1A_PERFCOUNTER2_LO                                                                         0x35c4
8688 #define mmGL1A_PERFCOUNTER2_LO_BASE_IDX                                                                1
8689 #define mmGL1A_PERFCOUNTER2_HI                                                                         0x35c5
8690 #define mmGL1A_PERFCOUNTER2_HI_BASE_IDX                                                                1
8691 #define mmGL1A_PERFCOUNTER3_LO                                                                         0x35c6
8692 #define mmGL1A_PERFCOUNTER3_LO_BASE_IDX                                                                1
8693 #define mmGL1A_PERFCOUNTER3_HI                                                                         0x35c7
8694 #define mmGL1A_PERFCOUNTER3_HI_BASE_IDX                                                                1
8695 #define mmCHA_PERFCOUNTER0_LO                                                                          0x3600
8696 #define mmCHA_PERFCOUNTER0_LO_BASE_IDX                                                                 1
8697 #define mmCHA_PERFCOUNTER0_HI                                                                          0x3601
8698 #define mmCHA_PERFCOUNTER0_HI_BASE_IDX                                                                 1
8699 #define mmCHA_PERFCOUNTER1_LO                                                                          0x3602
8700 #define mmCHA_PERFCOUNTER1_LO_BASE_IDX                                                                 1
8701 #define mmCHA_PERFCOUNTER1_HI                                                                          0x3603
8702 #define mmCHA_PERFCOUNTER1_HI_BASE_IDX                                                                 1
8703 #define mmCHA_PERFCOUNTER2_LO                                                                          0x3604
8704 #define mmCHA_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8705 #define mmCHA_PERFCOUNTER2_HI                                                                          0x3605
8706 #define mmCHA_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8707 #define mmCHA_PERFCOUNTER3_LO                                                                          0x3606
8708 #define mmCHA_PERFCOUNTER3_LO_BASE_IDX                                                                 1
8709 #define mmCHA_PERFCOUNTER3_HI                                                                          0x3607
8710 #define mmCHA_PERFCOUNTER3_HI_BASE_IDX                                                                 1
8711 #define mmGUS_PERFCOUNTER2_LO                                                                          0x3640
8712 #define mmGUS_PERFCOUNTER2_LO_BASE_IDX                                                                 1
8713 #define mmGUS_PERFCOUNTER2_HI                                                                          0x3641
8714 #define mmGUS_PERFCOUNTER2_HI_BASE_IDX                                                                 1
8715 
8716 
8717 // addressBlock: gc_gcatcl2pfcntrdec
8718 // base address: 0x35380
8719 #define mmGC_ATC_L2_PERFCOUNTER_LO                                                                     0x34e0
8720 #define mmGC_ATC_L2_PERFCOUNTER_LO_BASE_IDX                                                            1
8721 #define mmGC_ATC_L2_PERFCOUNTER_HI                                                                     0x34e1
8722 #define mmGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                            1
8723 
8724 
8725 // addressBlock: gc_gcvml2prdec
8726 // base address: 0x353a0
8727 #define mmGCMC_VM_L2_PERFCOUNTER_LO                                                                    0x34e8
8728 #define mmGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX                                                           1
8729 #define mmGCMC_VM_L2_PERFCOUNTER_HI                                                                    0x34e9
8730 #define mmGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX                                                           1
8731 
8732 
8733 // addressBlock: gc_gcvml2perfddec
8734 // base address: 0x353e0
8735 #define mmGCVML2_PERFCOUNTER2_0_LO                                                                     0x34f8
8736 #define mmGCVML2_PERFCOUNTER2_0_LO_BASE_IDX                                                            1
8737 #define mmGCVML2_PERFCOUNTER2_1_LO                                                                     0x34f9
8738 #define mmGCVML2_PERFCOUNTER2_1_LO_BASE_IDX                                                            1
8739 #define mmGCVML2_PERFCOUNTER2_0_HI                                                                     0x34fa
8740 #define mmGCVML2_PERFCOUNTER2_0_HI_BASE_IDX                                                            1
8741 #define mmGCVML2_PERFCOUNTER2_1_HI                                                                     0x34fb
8742 #define mmGCVML2_PERFCOUNTER2_1_HI_BASE_IDX                                                            1
8743 
8744 
8745 // addressBlock: gc_gcatcl2perfddec
8746 // base address: 0x353f0
8747 #define mmGC_ATC_L2_PERFCOUNTER2_LO                                                                    0x34fc
8748 #define mmGC_ATC_L2_PERFCOUNTER2_LO_BASE_IDX                                                           1
8749 #define mmGC_ATC_L2_PERFCOUNTER2_HI                                                                    0x34fd
8750 #define mmGC_ATC_L2_PERFCOUNTER2_HI_BASE_IDX                                                           1
8751 
8752 
8753 // addressBlock: gc_perfsdec
8754 // base address: 0x36000
8755 #define mmCPG_PERFCOUNTER1_SELECT                                                                      0x3800
8756 #define mmCPG_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8757 #define mmCPG_PERFCOUNTER0_SELECT1                                                                     0x3801
8758 #define mmCPG_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8759 #define mmCPG_PERFCOUNTER0_SELECT                                                                      0x3802
8760 #define mmCPG_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8761 #define mmCPC_PERFCOUNTER1_SELECT                                                                      0x3803
8762 #define mmCPC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8763 #define mmCPC_PERFCOUNTER0_SELECT1                                                                     0x3804
8764 #define mmCPC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8765 #define mmCPF_PERFCOUNTER1_SELECT                                                                      0x3805
8766 #define mmCPF_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8767 #define mmCPF_PERFCOUNTER0_SELECT1                                                                     0x3806
8768 #define mmCPF_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8769 #define mmCPF_PERFCOUNTER0_SELECT                                                                      0x3807
8770 #define mmCPF_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8771 #define mmCP_PERFMON_CNTL                                                                              0x3808
8772 #define mmCP_PERFMON_CNTL_BASE_IDX                                                                     1
8773 #define mmCPC_PERFCOUNTER0_SELECT                                                                      0x3809
8774 #define mmCPC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8775 #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380a
8776 #define mmCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
8777 #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT                                                            0x380b
8778 #define mmCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX                                                   1
8779 #define mmCPF_LATENCY_STATS_SELECT                                                                     0x380c
8780 #define mmCPF_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8781 #define mmCPG_LATENCY_STATS_SELECT                                                                     0x380d
8782 #define mmCPG_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8783 #define mmCPC_LATENCY_STATS_SELECT                                                                     0x380e
8784 #define mmCPC_LATENCY_STATS_SELECT_BASE_IDX                                                            1
8785 #define mmCP_DRAW_OBJECT                                                                               0x3810
8786 #define mmCP_DRAW_OBJECT_BASE_IDX                                                                      1
8787 #define mmCP_DRAW_OBJECT_COUNTER                                                                       0x3811
8788 #define mmCP_DRAW_OBJECT_COUNTER_BASE_IDX                                                              1
8789 #define mmCP_DRAW_WINDOW_MASK_HI                                                                       0x3812
8790 #define mmCP_DRAW_WINDOW_MASK_HI_BASE_IDX                                                              1
8791 #define mmCP_DRAW_WINDOW_HI                                                                            0x3813
8792 #define mmCP_DRAW_WINDOW_HI_BASE_IDX                                                                   1
8793 #define mmCP_DRAW_WINDOW_LO                                                                            0x3814
8794 #define mmCP_DRAW_WINDOW_LO_BASE_IDX                                                                   1
8795 #define mmCP_DRAW_WINDOW_CNTL                                                                          0x3815
8796 #define mmCP_DRAW_WINDOW_CNTL_BASE_IDX                                                                 1
8797 #define mmGRBM_PERFCOUNTER0_SELECT                                                                     0x3840
8798 #define mmGRBM_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8799 #define mmGRBM_PERFCOUNTER1_SELECT                                                                     0x3841
8800 #define mmGRBM_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8801 #define mmGRBM_SE0_PERFCOUNTER_SELECT                                                                  0x3842
8802 #define mmGRBM_SE0_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8803 #define mmGRBM_SE1_PERFCOUNTER_SELECT                                                                  0x3843
8804 #define mmGRBM_SE1_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8805 #define mmGRBM_SE2_PERFCOUNTER_SELECT                                                                  0x3844
8806 #define mmGRBM_SE2_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8807 #define mmGRBM_SE3_PERFCOUNTER_SELECT                                                                  0x3845
8808 #define mmGRBM_SE3_PERFCOUNTER_SELECT_BASE_IDX                                                         1
8809 #define mmGRBM_PERFCOUNTER0_SELECT_HI                                                                  0x384d
8810 #define mmGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX                                                         1
8811 #define mmGRBM_PERFCOUNTER1_SELECT_HI                                                                  0x384e
8812 #define mmGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX                                                         1
8813 #define mmGE_PERFCOUNTER0_SELECT                                                                       0x3880
8814 #define mmGE_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8815 #define mmGE_PERFCOUNTER0_SELECT1                                                                      0x3881
8816 #define mmGE_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8817 #define mmGE_PERFCOUNTER1_SELECT                                                                       0x3882
8818 #define mmGE_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8819 #define mmGE_PERFCOUNTER1_SELECT1                                                                      0x3883
8820 #define mmGE_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
8821 #define mmGE_PERFCOUNTER2_SELECT                                                                       0x3884
8822 #define mmGE_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8823 #define mmGE_PERFCOUNTER2_SELECT1                                                                      0x3885
8824 #define mmGE_PERFCOUNTER2_SELECT1_BASE_IDX                                                             1
8825 #define mmGE_PERFCOUNTER3_SELECT                                                                       0x3886
8826 #define mmGE_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8827 #define mmGE_PERFCOUNTER3_SELECT1                                                                      0x3887
8828 #define mmGE_PERFCOUNTER3_SELECT1_BASE_IDX                                                             1
8829 #define mmGE_PERFCOUNTER4_SELECT                                                                       0x3888
8830 #define mmGE_PERFCOUNTER4_SELECT_BASE_IDX                                                              1
8831 #define mmGE_PERFCOUNTER5_SELECT                                                                       0x388a
8832 #define mmGE_PERFCOUNTER5_SELECT_BASE_IDX                                                              1
8833 #define mmGE_PERFCOUNTER6_SELECT                                                                       0x388c
8834 #define mmGE_PERFCOUNTER6_SELECT_BASE_IDX                                                              1
8835 #define mmGE_PERFCOUNTER7_SELECT                                                                       0x388e
8836 #define mmGE_PERFCOUNTER7_SELECT_BASE_IDX                                                              1
8837 #define mmGE_PERFCOUNTER8_SELECT                                                                       0x3890
8838 #define mmGE_PERFCOUNTER8_SELECT_BASE_IDX                                                              1
8839 #define mmGE_PERFCOUNTER9_SELECT                                                                       0x3892
8840 #define mmGE_PERFCOUNTER9_SELECT_BASE_IDX                                                              1
8841 #define mmGE_PERFCOUNTER10_SELECT                                                                      0x3894
8842 #define mmGE_PERFCOUNTER10_SELECT_BASE_IDX                                                             1
8843 #define mmGE_PERFCOUNTER11_SELECT                                                                      0x3896
8844 #define mmGE_PERFCOUNTER11_SELECT_BASE_IDX                                                             1
8845 #define mmPA_SU_PERFCOUNTER0_SELECT                                                                    0x3900
8846 #define mmPA_SU_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8847 #define mmPA_SU_PERFCOUNTER0_SELECT1                                                                   0x3901
8848 #define mmPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8849 #define mmPA_SU_PERFCOUNTER1_SELECT                                                                    0x3902
8850 #define mmPA_SU_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8851 #define mmPA_SU_PERFCOUNTER1_SELECT1                                                                   0x3903
8852 #define mmPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
8853 #define mmPA_SU_PERFCOUNTER2_SELECT                                                                    0x3904
8854 #define mmPA_SU_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
8855 #define mmPA_SU_PERFCOUNTER2_SELECT1                                                                   0x3905
8856 #define mmPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
8857 #define mmPA_SU_PERFCOUNTER3_SELECT                                                                    0x3906
8858 #define mmPA_SU_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
8859 #define mmPA_SU_PERFCOUNTER3_SELECT1                                                                   0x3907
8860 #define mmPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
8861 #define mmPA_SC_PERFCOUNTER0_SELECT                                                                    0x3940
8862 #define mmPA_SC_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
8863 #define mmPA_SC_PERFCOUNTER0_SELECT1                                                                   0x3941
8864 #define mmPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
8865 #define mmPA_SC_PERFCOUNTER1_SELECT                                                                    0x3942
8866 #define mmPA_SC_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
8867 #define mmPA_SC_PERFCOUNTER2_SELECT                                                                    0x3943
8868 #define mmPA_SC_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
8869 #define mmPA_SC_PERFCOUNTER3_SELECT                                                                    0x3944
8870 #define mmPA_SC_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
8871 #define mmPA_SC_PERFCOUNTER4_SELECT                                                                    0x3945
8872 #define mmPA_SC_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
8873 #define mmPA_SC_PERFCOUNTER5_SELECT                                                                    0x3946
8874 #define mmPA_SC_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
8875 #define mmPA_SC_PERFCOUNTER6_SELECT                                                                    0x3947
8876 #define mmPA_SC_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
8877 #define mmPA_SC_PERFCOUNTER7_SELECT                                                                    0x3948
8878 #define mmPA_SC_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
8879 #define mmSPI_PERFCOUNTER0_SELECT                                                                      0x3980
8880 #define mmSPI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8881 #define mmSPI_PERFCOUNTER1_SELECT                                                                      0x3981
8882 #define mmSPI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8883 #define mmSPI_PERFCOUNTER2_SELECT                                                                      0x3982
8884 #define mmSPI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8885 #define mmSPI_PERFCOUNTER3_SELECT                                                                      0x3983
8886 #define mmSPI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8887 #define mmSPI_PERFCOUNTER0_SELECT1                                                                     0x3984
8888 #define mmSPI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8889 #define mmSPI_PERFCOUNTER1_SELECT1                                                                     0x3985
8890 #define mmSPI_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8891 #define mmSPI_PERFCOUNTER2_SELECT1                                                                     0x3986
8892 #define mmSPI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
8893 #define mmSPI_PERFCOUNTER3_SELECT1                                                                     0x3987
8894 #define mmSPI_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
8895 #define mmSPI_PERFCOUNTER4_SELECT                                                                      0x3988
8896 #define mmSPI_PERFCOUNTER4_SELECT_BASE_IDX                                                             1
8897 #define mmSPI_PERFCOUNTER5_SELECT                                                                      0x3989
8898 #define mmSPI_PERFCOUNTER5_SELECT_BASE_IDX                                                             1
8899 #define mmSPI_PERFCOUNTER_BINS                                                                         0x398a
8900 #define mmSPI_PERFCOUNTER_BINS_BASE_IDX                                                                1
8901 #define mmSQ_PERFCOUNTER0_SELECT                                                                       0x39c0
8902 #define mmSQ_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8903 #define mmSQ_PERFCOUNTER1_SELECT                                                                       0x39c1
8904 #define mmSQ_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8905 #define mmSQ_PERFCOUNTER2_SELECT                                                                       0x39c2
8906 #define mmSQ_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8907 #define mmSQ_PERFCOUNTER3_SELECT                                                                       0x39c3
8908 #define mmSQ_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8909 #define mmSQ_PERFCOUNTER4_SELECT                                                                       0x39c4
8910 #define mmSQ_PERFCOUNTER4_SELECT_BASE_IDX                                                              1
8911 #define mmSQ_PERFCOUNTER5_SELECT                                                                       0x39c5
8912 #define mmSQ_PERFCOUNTER5_SELECT_BASE_IDX                                                              1
8913 #define mmSQ_PERFCOUNTER6_SELECT                                                                       0x39c6
8914 #define mmSQ_PERFCOUNTER6_SELECT_BASE_IDX                                                              1
8915 #define mmSQ_PERFCOUNTER7_SELECT                                                                       0x39c7
8916 #define mmSQ_PERFCOUNTER7_SELECT_BASE_IDX                                                              1
8917 #define mmSQ_PERFCOUNTER8_SELECT                                                                       0x39c8
8918 #define mmSQ_PERFCOUNTER8_SELECT_BASE_IDX                                                              1
8919 #define mmSQ_PERFCOUNTER9_SELECT                                                                       0x39c9
8920 #define mmSQ_PERFCOUNTER9_SELECT_BASE_IDX                                                              1
8921 #define mmSQ_PERFCOUNTER10_SELECT                                                                      0x39ca
8922 #define mmSQ_PERFCOUNTER10_SELECT_BASE_IDX                                                             1
8923 #define mmSQ_PERFCOUNTER11_SELECT                                                                      0x39cb
8924 #define mmSQ_PERFCOUNTER11_SELECT_BASE_IDX                                                             1
8925 #define mmSQ_PERFCOUNTER12_SELECT                                                                      0x39cc
8926 #define mmSQ_PERFCOUNTER12_SELECT_BASE_IDX                                                             1
8927 #define mmSQ_PERFCOUNTER13_SELECT                                                                      0x39cd
8928 #define mmSQ_PERFCOUNTER13_SELECT_BASE_IDX                                                             1
8929 #define mmSQ_PERFCOUNTER14_SELECT                                                                      0x39ce
8930 #define mmSQ_PERFCOUNTER14_SELECT_BASE_IDX                                                             1
8931 #define mmSQ_PERFCOUNTER15_SELECT                                                                      0x39cf
8932 #define mmSQ_PERFCOUNTER15_SELECT_BASE_IDX                                                             1
8933 #define mmSQ_PERFCOUNTER_CTRL                                                                          0x39e0
8934 #define mmSQ_PERFCOUNTER_CTRL_BASE_IDX                                                                 1
8935 #define mmSQ_PERFCOUNTER_CTRL2                                                                         0x39e2
8936 #define mmSQ_PERFCOUNTER_CTRL2_BASE_IDX                                                                1
8937 #define mmGCEA_PERFCOUNTER2_SELECT                                                                     0x3a00
8938 #define mmGCEA_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8939 #define mmGCEA_PERFCOUNTER2_SELECT1                                                                    0x3a01
8940 #define mmGCEA_PERFCOUNTER2_SELECT1_BASE_IDX                                                           1
8941 #define mmGCEA_PERFCOUNTER2_MODE                                                                       0x3a02
8942 #define mmGCEA_PERFCOUNTER2_MODE_BASE_IDX                                                              1
8943 #define mmSX_PERFCOUNTER0_SELECT                                                                       0x3a40
8944 #define mmSX_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8945 #define mmSX_PERFCOUNTER1_SELECT                                                                       0x3a41
8946 #define mmSX_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8947 #define mmSX_PERFCOUNTER2_SELECT                                                                       0x3a42
8948 #define mmSX_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
8949 #define mmSX_PERFCOUNTER3_SELECT                                                                       0x3a43
8950 #define mmSX_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
8951 #define mmSX_PERFCOUNTER0_SELECT1                                                                      0x3a44
8952 #define mmSX_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8953 #define mmSX_PERFCOUNTER1_SELECT1                                                                      0x3a45
8954 #define mmSX_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
8955 #define mmGDS_PERFCOUNTER0_SELECT                                                                      0x3a80
8956 #define mmGDS_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8957 #define mmGDS_PERFCOUNTER1_SELECT                                                                      0x3a81
8958 #define mmGDS_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8959 #define mmGDS_PERFCOUNTER2_SELECT                                                                      0x3a82
8960 #define mmGDS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8961 #define mmGDS_PERFCOUNTER3_SELECT                                                                      0x3a83
8962 #define mmGDS_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8963 #define mmGDS_PERFCOUNTER0_SELECT1                                                                     0x3a84
8964 #define mmGDS_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8965 #define mmTA_PERFCOUNTER0_SELECT                                                                       0x3ac0
8966 #define mmTA_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8967 #define mmTA_PERFCOUNTER0_SELECT1                                                                      0x3ac1
8968 #define mmTA_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8969 #define mmTA_PERFCOUNTER1_SELECT                                                                       0x3ac2
8970 #define mmTA_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8971 #define mmTD_PERFCOUNTER0_SELECT                                                                       0x3b00
8972 #define mmTD_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
8973 #define mmTD_PERFCOUNTER0_SELECT1                                                                      0x3b01
8974 #define mmTD_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
8975 #define mmTD_PERFCOUNTER1_SELECT                                                                       0x3b02
8976 #define mmTD_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
8977 #define mmTCP_PERFCOUNTER0_SELECT                                                                      0x3b40
8978 #define mmTCP_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
8979 #define mmTCP_PERFCOUNTER0_SELECT1                                                                     0x3b41
8980 #define mmTCP_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
8981 #define mmTCP_PERFCOUNTER1_SELECT                                                                      0x3b42
8982 #define mmTCP_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
8983 #define mmTCP_PERFCOUNTER1_SELECT1                                                                     0x3b43
8984 #define mmTCP_PERFCOUNTER1_SELECT1_BASE_IDX                                                            1
8985 #define mmTCP_PERFCOUNTER2_SELECT                                                                      0x3b44
8986 #define mmTCP_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
8987 #define mmTCP_PERFCOUNTER3_SELECT                                                                      0x3b45
8988 #define mmTCP_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
8989 #define mmGL2C_PERFCOUNTER0_SELECT                                                                     0x3b80
8990 #define mmGL2C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
8991 #define mmGL2C_PERFCOUNTER0_SELECT1                                                                    0x3b81
8992 #define mmGL2C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
8993 #define mmGL2C_PERFCOUNTER1_SELECT                                                                     0x3b82
8994 #define mmGL2C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
8995 #define mmGL2C_PERFCOUNTER1_SELECT1                                                                    0x3b83
8996 #define mmGL2C_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
8997 #define mmGL2C_PERFCOUNTER2_SELECT                                                                     0x3b84
8998 #define mmGL2C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
8999 #define mmGL2C_PERFCOUNTER3_SELECT                                                                     0x3b85
9000 #define mmGL2C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9001 #define mmGL2A_PERFCOUNTER0_SELECT                                                                     0x3b90
9002 #define mmGL2A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9003 #define mmGL2A_PERFCOUNTER0_SELECT1                                                                    0x3b91
9004 #define mmGL2A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9005 #define mmGL2A_PERFCOUNTER1_SELECT                                                                     0x3b92
9006 #define mmGL2A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9007 #define mmGL2A_PERFCOUNTER1_SELECT1                                                                    0x3b93
9008 #define mmGL2A_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
9009 #define mmGL2A_PERFCOUNTER2_SELECT                                                                     0x3b94
9010 #define mmGL2A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9011 #define mmGL2A_PERFCOUNTER3_SELECT                                                                     0x3b95
9012 #define mmGL2A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9013 #define mmGL1C_PERFCOUNTER0_SELECT                                                                     0x3ba0
9014 #define mmGL1C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9015 #define mmGL1C_PERFCOUNTER0_SELECT1                                                                    0x3ba1
9016 #define mmGL1C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9017 #define mmGL1C_PERFCOUNTER1_SELECT                                                                     0x3ba2
9018 #define mmGL1C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9019 #define mmGL1C_PERFCOUNTER2_SELECT                                                                     0x3ba3
9020 #define mmGL1C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9021 #define mmGL1C_PERFCOUNTER3_SELECT                                                                     0x3ba4
9022 #define mmGL1C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9023 #define mmCHC_PERFCOUNTER0_SELECT                                                                      0x3bc0
9024 #define mmCHC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9025 #define mmCHC_PERFCOUNTER0_SELECT1                                                                     0x3bc1
9026 #define mmCHC_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9027 #define mmCHC_PERFCOUNTER1_SELECT                                                                      0x3bc2
9028 #define mmCHC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9029 #define mmCHC_PERFCOUNTER2_SELECT                                                                      0x3bc3
9030 #define mmCHC_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9031 #define mmCHC_PERFCOUNTER3_SELECT                                                                      0x3bc4
9032 #define mmCHC_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9033 #define mmCHCG_PERFCOUNTER0_SELECT                                                                     0x3bc6
9034 #define mmCHCG_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9035 #define mmCHCG_PERFCOUNTER0_SELECT1                                                                    0x3bc7
9036 #define mmCHCG_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9037 #define mmCHCG_PERFCOUNTER1_SELECT                                                                     0x3bc8
9038 #define mmCHCG_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9039 #define mmCHCG_PERFCOUNTER2_SELECT                                                                     0x3bc9
9040 #define mmCHCG_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9041 #define mmCHCG_PERFCOUNTER3_SELECT                                                                     0x3bca
9042 #define mmCHCG_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9043 #define mmCB_PERFCOUNTER_FILTER                                                                        0x3c00
9044 #define mmCB_PERFCOUNTER_FILTER_BASE_IDX                                                               1
9045 #define mmCB_PERFCOUNTER0_SELECT                                                                       0x3c01
9046 #define mmCB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9047 #define mmCB_PERFCOUNTER0_SELECT1                                                                      0x3c02
9048 #define mmCB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9049 #define mmCB_PERFCOUNTER1_SELECT                                                                       0x3c03
9050 #define mmCB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9051 #define mmCB_PERFCOUNTER2_SELECT                                                                       0x3c04
9052 #define mmCB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9053 #define mmCB_PERFCOUNTER3_SELECT                                                                       0x3c05
9054 #define mmCB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9055 #define mmDB_PERFCOUNTER0_SELECT                                                                       0x3c40
9056 #define mmDB_PERFCOUNTER0_SELECT_BASE_IDX                                                              1
9057 #define mmDB_PERFCOUNTER0_SELECT1                                                                      0x3c41
9058 #define mmDB_PERFCOUNTER0_SELECT1_BASE_IDX                                                             1
9059 #define mmDB_PERFCOUNTER1_SELECT                                                                       0x3c42
9060 #define mmDB_PERFCOUNTER1_SELECT_BASE_IDX                                                              1
9061 #define mmDB_PERFCOUNTER1_SELECT1                                                                      0x3c43
9062 #define mmDB_PERFCOUNTER1_SELECT1_BASE_IDX                                                             1
9063 #define mmDB_PERFCOUNTER2_SELECT                                                                       0x3c44
9064 #define mmDB_PERFCOUNTER2_SELECT_BASE_IDX                                                              1
9065 #define mmDB_PERFCOUNTER3_SELECT                                                                       0x3c46
9066 #define mmDB_PERFCOUNTER3_SELECT_BASE_IDX                                                              1
9067 #define mmRLC_SPM_PERFMON_CNTL                                                                         0x3c80
9068 #define mmRLC_SPM_PERFMON_CNTL_BASE_IDX                                                                1
9069 #define mmRLC_SPM_PERFMON_RING_BASE_LO                                                                 0x3c81
9070 #define mmRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX                                                        1
9071 #define mmRLC_SPM_PERFMON_RING_BASE_HI                                                                 0x3c82
9072 #define mmRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX                                                        1
9073 #define mmRLC_SPM_PERFMON_RING_SIZE                                                                    0x3c83
9074 #define mmRLC_SPM_PERFMON_RING_SIZE_BASE_IDX                                                           1
9075 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE                                                                 0x3c84
9076 #define mmRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX                                                        1
9077 #define mmRLC_SPM_RING_RDPTR                                                                           0x3c85
9078 #define mmRLC_SPM_RING_RDPTR_BASE_IDX                                                                  1
9079 #define mmRLC_SPM_SEGMENT_THRESHOLD                                                                    0x3c86
9080 #define mmRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX                                                           1
9081 #define mmRLC_SPM_SE_MUXSEL_ADDR                                                                       0x3c87
9082 #define mmRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX                                                              1
9083 #define mmRLC_SPM_SE_MUXSEL_DATA                                                                       0x3c88
9084 #define mmRLC_SPM_SE_MUXSEL_DATA_BASE_IDX                                                              1
9085 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR                                                                   0x3c89
9086 #define mmRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX                                                          1
9087 #define mmRLC_SPM_GLOBAL_MUXSEL_DATA                                                                   0x3c8a
9088 #define mmRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX                                                          1
9089 #define mmRLC_SPM_DESER_START_SKEW                                                                     0x3c8b
9090 #define mmRLC_SPM_DESER_START_SKEW_BASE_IDX                                                            1
9091 #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW                                                                  0x3c8c
9092 #define mmRLC_SPM_GLOBALS_SAMPLE_SKEW_BASE_IDX                                                         1
9093 #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW                                                                  0x3c8d
9094 #define mmRLC_SPM_GLOBALS_MUXSEL_SKEW_BASE_IDX                                                         1
9095 #define mmRLC_SPM_SE_SAMPLE_SKEW                                                                       0x3c8e
9096 #define mmRLC_SPM_SE_SAMPLE_SKEW_BASE_IDX                                                              1
9097 #define mmRLC_SPM_SE_MUXSEL_SKEW                                                                       0x3c8f
9098 #define mmRLC_SPM_SE_MUXSEL_SKEW_BASE_IDX                                                              1
9099 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR                                                             0x3c90
9100 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR_BASE_IDX                                                    1
9101 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA                                                             0x3c91
9102 #define mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA_BASE_IDX                                                    1
9103 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR                                                              0x3c92
9104 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR_BASE_IDX                                                     1
9105 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA                                                              0x3c93
9106 #define mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA_BASE_IDX                                                     1
9107 #define mmRLC_SPM_RING_WRPTR                                                                           0x3c94
9108 #define mmRLC_SPM_RING_WRPTR_BASE_IDX                                                                  1
9109 #define mmRLC_SPM_ACCUM_DATARAM_ADDR                                                                   0x3c95
9110 #define mmRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX                                                          1
9111 #define mmRLC_SPM_ACCUM_DATARAM_DATA                                                                   0x3c96
9112 #define mmRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX                                                          1
9113 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR                                                                   0x3c97
9114 #define mmRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX                                                          1
9115 #define mmRLC_SPM_ACCUM_CTRLRAM_DATA                                                                   0x3c98
9116 #define mmRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX                                                          1
9117 #define mmRLC_SPM_ACCUM_STATUS                                                                         0x3c99
9118 #define mmRLC_SPM_ACCUM_STATUS_BASE_IDX                                                                1
9119 #define mmRLC_SPM_ACCUM_CTRL                                                                           0x3c9a
9120 #define mmRLC_SPM_ACCUM_CTRL_BASE_IDX                                                                  1
9121 #define mmRLC_SPM_ACCUM_MODE                                                                           0x3c9b
9122 #define mmRLC_SPM_ACCUM_MODE_BASE_IDX                                                                  1
9123 #define mmRLC_SPM_ACCUM_THRESHOLD                                                                      0x3c9c
9124 #define mmRLC_SPM_ACCUM_THRESHOLD_BASE_IDX                                                             1
9125 #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED                                                              0x3c9d
9126 #define mmRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX                                                     1
9127 #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT                                                                0x3c9e
9128 #define mmRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX                                                       1
9129 #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE                                                          0x3c9f
9130 #define mmRLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE_BASE_IDX                                                 1
9131 #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE                                                             0x3ca0
9132 #define mmRLC_SPM_PERFMON_GLB_SEGMENT_SIZE_BASE_IDX                                                    1
9133 #define mmRLC_SPM_VIRT_CTRL                                                                            0x3ca1
9134 #define mmRLC_SPM_VIRT_CTRL_BASE_IDX                                                                   1
9135 #define mmRLC_SPM_VIRT_STATUS                                                                          0x3ca3
9136 #define mmRLC_SPM_VIRT_STATUS_BASE_IDX                                                                 1
9137 #define mmRLC_PERFMON_CNTL                                                                             0x3cc0
9138 #define mmRLC_PERFMON_CNTL_BASE_IDX                                                                    1
9139 #define mmRLC_PERFCOUNTER0_SELECT                                                                      0x3cc1
9140 #define mmRLC_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9141 #define mmRLC_PERFCOUNTER1_SELECT                                                                      0x3cc2
9142 #define mmRLC_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9143 #define mmRLC_GPU_IOV_PERF_CNT_CNTL                                                                    0x3cc3
9144 #define mmRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX                                                           1
9145 #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR                                                                 0x3cc4
9146 #define mmRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX                                                        1
9147 #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA                                                                 0x3cc5
9148 #define mmRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX                                                        1
9149 #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR                                                                 0x3cc6
9150 #define mmRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX                                                        1
9151 #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA                                                                 0x3cc7
9152 #define mmRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX                                                        1
9153 #define mmRLC_PERFMON_CLK_CNTL                                                                         0x3ce4
9154 #define mmRLC_PERFMON_CLK_CNTL_BASE_IDX                                                                1
9155 #define mmRLC_PERFMON_CLK_CNTL_UCODE                                                                   0x3ce5
9156 #define mmRLC_PERFMON_CLK_CNTL_UCODE_BASE_IDX                                                          1
9157 #define mmRMI_PERFCOUNTER0_SELECT                                                                      0x3d00
9158 #define mmRMI_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9159 #define mmRMI_PERFCOUNTER0_SELECT1                                                                     0x3d01
9160 #define mmRMI_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9161 #define mmRMI_PERFCOUNTER1_SELECT                                                                      0x3d02
9162 #define mmRMI_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9163 #define mmRMI_PERFCOUNTER2_SELECT                                                                      0x3d03
9164 #define mmRMI_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9165 #define mmRMI_PERFCOUNTER2_SELECT1                                                                     0x3d04
9166 #define mmRMI_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9167 #define mmRMI_PERFCOUNTER3_SELECT                                                                      0x3d05
9168 #define mmRMI_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9169 #define mmRMI_PERF_COUNTER_CNTL                                                                        0x3d06
9170 #define mmRMI_PERF_COUNTER_CNTL_BASE_IDX                                                               1
9171 #define mmGCR_PERFCOUNTER0_SELECT                                                                      0x3d60
9172 #define mmGCR_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9173 #define mmGCR_PERFCOUNTER0_SELECT1                                                                     0x3d61
9174 #define mmGCR_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9175 #define mmGCR_PERFCOUNTER1_SELECT                                                                      0x3d62
9176 #define mmGCR_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9177 #define mmUTCL1_PERFCOUNTER0_SELECT                                                                    0x3d63
9178 #define mmUTCL1_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9179 #define mmUTCL1_PERFCOUNTER1_SELECT                                                                    0x3d64
9180 #define mmUTCL1_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9181 #define mmPA_PH_PERFCOUNTER0_SELECT                                                                    0x3d80
9182 #define mmPA_PH_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
9183 #define mmPA_PH_PERFCOUNTER0_SELECT1                                                                   0x3d81
9184 #define mmPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX                                                          1
9185 #define mmPA_PH_PERFCOUNTER1_SELECT                                                                    0x3d82
9186 #define mmPA_PH_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
9187 #define mmPA_PH_PERFCOUNTER2_SELECT                                                                    0x3d83
9188 #define mmPA_PH_PERFCOUNTER2_SELECT_BASE_IDX                                                           1
9189 #define mmPA_PH_PERFCOUNTER3_SELECT                                                                    0x3d84
9190 #define mmPA_PH_PERFCOUNTER3_SELECT_BASE_IDX                                                           1
9191 #define mmPA_PH_PERFCOUNTER4_SELECT                                                                    0x3d85
9192 #define mmPA_PH_PERFCOUNTER4_SELECT_BASE_IDX                                                           1
9193 #define mmPA_PH_PERFCOUNTER5_SELECT                                                                    0x3d86
9194 #define mmPA_PH_PERFCOUNTER5_SELECT_BASE_IDX                                                           1
9195 #define mmPA_PH_PERFCOUNTER6_SELECT                                                                    0x3d87
9196 #define mmPA_PH_PERFCOUNTER6_SELECT_BASE_IDX                                                           1
9197 #define mmPA_PH_PERFCOUNTER7_SELECT                                                                    0x3d88
9198 #define mmPA_PH_PERFCOUNTER7_SELECT_BASE_IDX                                                           1
9199 #define mmPA_PH_PERFCOUNTER1_SELECT1                                                                   0x3d90
9200 #define mmPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX                                                          1
9201 #define mmPA_PH_PERFCOUNTER2_SELECT1                                                                   0x3d91
9202 #define mmPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX                                                          1
9203 #define mmPA_PH_PERFCOUNTER3_SELECT1                                                                   0x3d92
9204 #define mmPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX                                                          1
9205 #define mmGL1A_PERFCOUNTER0_SELECT                                                                     0x3dc0
9206 #define mmGL1A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
9207 #define mmGL1A_PERFCOUNTER0_SELECT1                                                                    0x3dc1
9208 #define mmGL1A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
9209 #define mmGL1A_PERFCOUNTER1_SELECT                                                                     0x3dc2
9210 #define mmGL1A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
9211 #define mmGL1A_PERFCOUNTER2_SELECT                                                                     0x3dc3
9212 #define mmGL1A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
9213 #define mmGL1A_PERFCOUNTER3_SELECT                                                                     0x3dc4
9214 #define mmGL1A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
9215 #define mmCHA_PERFCOUNTER0_SELECT                                                                      0x3de0
9216 #define mmCHA_PERFCOUNTER0_SELECT_BASE_IDX                                                             1
9217 #define mmCHA_PERFCOUNTER0_SELECT1                                                                     0x3de1
9218 #define mmCHA_PERFCOUNTER0_SELECT1_BASE_IDX                                                            1
9219 #define mmCHA_PERFCOUNTER1_SELECT                                                                      0x3de2
9220 #define mmCHA_PERFCOUNTER1_SELECT_BASE_IDX                                                             1
9221 #define mmCHA_PERFCOUNTER2_SELECT                                                                      0x3de3
9222 #define mmCHA_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9223 #define mmCHA_PERFCOUNTER3_SELECT                                                                      0x3de4
9224 #define mmCHA_PERFCOUNTER3_SELECT_BASE_IDX                                                             1
9225 #define mmGUS_PERFCOUNTER2_SELECT                                                                      0x3e00
9226 #define mmGUS_PERFCOUNTER2_SELECT_BASE_IDX                                                             1
9227 #define mmGUS_PERFCOUNTER2_SELECT1                                                                     0x3e01
9228 #define mmGUS_PERFCOUNTER2_SELECT1_BASE_IDX                                                            1
9229 #define mmGUS_PERFCOUNTER2_MODE                                                                        0x3e02
9230 #define mmGUS_PERFCOUNTER2_MODE_BASE_IDX                                                               1
9231 
9232 
9233 // addressBlock: gc_gcatcl2pfcntldec
9234 // base address: 0x37480
9235 #define mmGC_ATC_L2_PERFCOUNTER0_CFG                                                                   0x3d20
9236 #define mmGC_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX                                                          1
9237 #define mmGC_ATC_L2_PERFCOUNTER1_CFG                                                                   0x3d21
9238 #define mmGC_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX                                                          1
9239 #define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL                                                              0x3d22
9240 #define mmGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                     1
9241 
9242 
9243 // addressBlock: gc_gcvml2pldec
9244 // base address: 0x374b0
9245 #define mmGCMC_VM_L2_PERFCOUNTER0_CFG                                                                  0x3d2c
9246 #define mmGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX                                                         1
9247 #define mmGCMC_VM_L2_PERFCOUNTER1_CFG                                                                  0x3d2d
9248 #define mmGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX                                                         1
9249 #define mmGCMC_VM_L2_PERFCOUNTER2_CFG                                                                  0x3d2e
9250 #define mmGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX                                                         1
9251 #define mmGCMC_VM_L2_PERFCOUNTER3_CFG                                                                  0x3d2f
9252 #define mmGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX                                                         1
9253 #define mmGCMC_VM_L2_PERFCOUNTER4_CFG                                                                  0x3d30
9254 #define mmGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX                                                         1
9255 #define mmGCMC_VM_L2_PERFCOUNTER5_CFG                                                                  0x3d31
9256 #define mmGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX                                                         1
9257 #define mmGCMC_VM_L2_PERFCOUNTER6_CFG                                                                  0x3d32
9258 #define mmGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX                                                         1
9259 #define mmGCMC_VM_L2_PERFCOUNTER7_CFG                                                                  0x3d33
9260 #define mmGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX                                                         1
9261 #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL                                                             0x3d34
9262 #define mmGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                    1
9263 
9264 
9265 // addressBlock: gc_gcvml2perfsdec
9266 // base address: 0x374f0
9267 #define mmGCVML2_PERFCOUNTER2_0_SELECT                                                                 0x3d3c
9268 #define mmGCVML2_PERFCOUNTER2_0_SELECT_BASE_IDX                                                        1
9269 #define mmGCVML2_PERFCOUNTER2_1_SELECT                                                                 0x3d3d
9270 #define mmGCVML2_PERFCOUNTER2_1_SELECT_BASE_IDX                                                        1
9271 #define mmGCVML2_PERFCOUNTER2_0_SELECT1                                                                0x3d3e
9272 #define mmGCVML2_PERFCOUNTER2_0_SELECT1_BASE_IDX                                                       1
9273 #define mmGCVML2_PERFCOUNTER2_1_SELECT1                                                                0x3d3f
9274 #define mmGCVML2_PERFCOUNTER2_1_SELECT1_BASE_IDX                                                       1
9275 #define mmGCVML2_PERFCOUNTER2_0_MODE                                                                   0x3d40
9276 #define mmGCVML2_PERFCOUNTER2_0_MODE_BASE_IDX                                                          1
9277 #define mmGCVML2_PERFCOUNTER2_1_MODE                                                                   0x3d41
9278 #define mmGCVML2_PERFCOUNTER2_1_MODE_BASE_IDX                                                          1
9279 
9280 
9281 // addressBlock: gc_gcatcl2perfsdec
9282 // base address: 0x37530
9283 #define mmGC_ATC_L2_PERFCOUNTER2_SELECT                                                                0x3d4c
9284 #define mmGC_ATC_L2_PERFCOUNTER2_SELECT_BASE_IDX                                                       1
9285 #define mmGC_ATC_L2_PERFCOUNTER2_SELECT1                                                               0x3d4d
9286 #define mmGC_ATC_L2_PERFCOUNTER2_SELECT1_BASE_IDX                                                      1
9287 #define mmGC_ATC_L2_PERFCOUNTER2_MODE                                                                  0x3d4e
9288 #define mmGC_ATC_L2_PERFCOUNTER2_MODE_BASE_IDX                                                         1
9289 
9290 
9291 // addressBlock: gc_rlcdec
9292 // base address: 0x3b000
9293 #define mmRLC_CNTL                                                                                     0x4c00
9294 #define mmRLC_CNTL_BASE_IDX                                                                            1
9295 #define mmRLC_F32_UCODE_VERSION                                                                        0x4c03
9296 #define mmRLC_F32_UCODE_VERSION_BASE_IDX                                                               1
9297 #define mmRLC_STAT                                                                                     0x4c04
9298 #define mmRLC_STAT_BASE_IDX                                                                            1
9299 #define mmRLC_SAFE_MODE                                                                                0x4c05
9300 #define mmRLC_SAFE_MODE_BASE_IDX                                                                       1
9301 #define mmRLC_MEM_SLP_CNTL                                                                             0x4c06
9302 #define mmRLC_MEM_SLP_CNTL_BASE_IDX                                                                    1
9303 #define mmSMU_RLC_RESPONSE                                                                             0x4c07
9304 #define mmSMU_RLC_RESPONSE_BASE_IDX                                                                    1
9305 #define mmRLC_RLCV_SAFE_MODE                                                                           0x4c08
9306 #define mmRLC_RLCV_SAFE_MODE_BASE_IDX                                                                  1
9307 #define mmRLC_SMU_SAFE_MODE                                                                            0x4c09
9308 #define mmRLC_SMU_SAFE_MODE_BASE_IDX                                                                   1
9309 #define mmRLC_RLCV_COMMAND                                                                             0x4c0a
9310 #define mmRLC_RLCV_COMMAND_BASE_IDX                                                                    1
9311 #define mmRLC_REFCLOCK_TIMESTAMP_LSB                                                                   0x4c0c
9312 #define mmRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX                                                          1
9313 #define mmRLC_REFCLOCK_TIMESTAMP_MSB                                                                   0x4c0d
9314 #define mmRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX                                                          1
9315 #define mmRLC_GPM_TIMER_INT_0                                                                          0x4c0e
9316 #define mmRLC_GPM_TIMER_INT_0_BASE_IDX                                                                 1
9317 #define mmRLC_GPM_TIMER_INT_1                                                                          0x4c0f
9318 #define mmRLC_GPM_TIMER_INT_1_BASE_IDX                                                                 1
9319 #define mmRLC_GPM_TIMER_INT_2                                                                          0x4c10
9320 #define mmRLC_GPM_TIMER_INT_2_BASE_IDX                                                                 1
9321 #define mmRLC_GPM_TIMER_CTRL                                                                           0x4c11
9322 #define mmRLC_GPM_TIMER_CTRL_BASE_IDX                                                                  1
9323 #define mmRLC_LB_CNTR_MAX_1                                                                            0x4c12
9324 #define mmRLC_LB_CNTR_MAX_1_BASE_IDX                                                                   1
9325 #define mmRLC_GPM_TIMER_STAT                                                                           0x4c13
9326 #define mmRLC_GPM_TIMER_STAT_BASE_IDX                                                                  1
9327 #define mmRLC_GPM_TIMER_INT_3                                                                          0x4c15
9328 #define mmRLC_GPM_TIMER_INT_3_BASE_IDX                                                                 1
9329 #define mmRLC_INT_STAT                                                                                 0x4c18
9330 #define mmRLC_INT_STAT_BASE_IDX                                                                        1
9331 #define mmRLC_LB_CNTL                                                                                  0x4c19
9332 #define mmRLC_LB_CNTL_BASE_IDX                                                                         1
9333 #define mmRLC_MGCG_CTRL                                                                                0x4c1a
9334 #define mmRLC_MGCG_CTRL_BASE_IDX                                                                       1
9335 #define mmRLC_LB_CNTR_INIT_1                                                                           0x4c1b
9336 #define mmRLC_LB_CNTR_INIT_1_BASE_IDX                                                                  1
9337 #define mmRLC_LB_CNTR_1                                                                                0x4c1c
9338 #define mmRLC_LB_CNTR_1_BASE_IDX                                                                       1
9339 #define mmRLC_GPM_DEBUG_INST_ADDR                                                                      0x4c1d
9340 #define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX                                                             1
9341 #define mmRLC_JUMP_TABLE_RESTORE                                                                       0x4c1e
9342 #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX                                                              1
9343 #define mmRLC_PG_DELAY_2                                                                               0x4c1f
9344 #define mmRLC_PG_DELAY_2_BASE_IDX                                                                      1
9345 #define mmRLC_GPM_DEBUG_INST_A                                                                         0x4c22
9346 #define mmRLC_GPM_DEBUG_INST_A_BASE_IDX                                                                1
9347 #define mmRLC_GPM_DEBUG_INST_B                                                                         0x4c23
9348 #define mmRLC_GPM_DEBUG_INST_B_BASE_IDX                                                                1
9349 #define mmRLC_GPU_CLOCK_COUNT_LSB                                                                      0x4c24
9350 #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX                                                             1
9351 #define mmRLC_GPU_CLOCK_COUNT_MSB                                                                      0x4c25
9352 #define mmRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX                                                             1
9353 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT                                                                  0x4c26
9354 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX                                                         1
9355 #define mmRLC_UCODE_CNTL                                                                               0x4c27
9356 #define mmRLC_UCODE_CNTL_BASE_IDX                                                                      1
9357 #define mmRLC_GPM_THREAD_RESET                                                                         0x4c28
9358 #define mmRLC_GPM_THREAD_RESET_BASE_IDX                                                                1
9359 #define mmRLC_GPM_CP_DMA_COMPLETE_T0                                                                   0x4c29
9360 #define mmRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX                                                          1
9361 #define mmRLC_GPM_CP_DMA_COMPLETE_T1                                                                   0x4c2a
9362 #define mmRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX                                                          1
9363 #define mmRLC_LB_CNTR_INIT_2                                                                           0x4c2b
9364 #define mmRLC_LB_CNTR_INIT_2_BASE_IDX                                                                  1
9365 #define mmRLC_LB_CNTR_MAX_2                                                                            0x4c2c
9366 #define mmRLC_LB_CNTR_MAX_2_BASE_IDX                                                                   1
9367 #define mmRLC_LB_CONFIG_5                                                                              0x4c2e
9368 #define mmRLC_LB_CONFIG_5_BASE_IDX                                                                     1
9369 #define mmRLC_CLK_COUNT_GFXCLK_LSB                                                                     0x4c30
9370 #define mmRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX                                                            1
9371 #define mmRLC_CLK_COUNT_GFXCLK_MSB                                                                     0x4c31
9372 #define mmRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX                                                            1
9373 #define mmRLC_CLK_COUNT_REFCLK_LSB                                                                     0x4c32
9374 #define mmRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX                                                            1
9375 #define mmRLC_CLK_COUNT_REFCLK_MSB                                                                     0x4c33
9376 #define mmRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX                                                            1
9377 #define mmRLC_CLK_COUNT_CTRL                                                                           0x4c34
9378 #define mmRLC_CLK_COUNT_CTRL_BASE_IDX                                                                  1
9379 #define mmRLC_CLK_COUNT_STAT                                                                           0x4c35
9380 #define mmRLC_CLK_COUNT_STAT_BASE_IDX                                                                  1
9381 #define mmRLC_GPU_CLOCK_32_RES_SEL                                                                     0x4c41
9382 #define mmRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX                                                            1
9383 #define mmRLC_GPU_CLOCK_32                                                                             0x4c42
9384 #define mmRLC_GPU_CLOCK_32_BASE_IDX                                                                    1
9385 #define mmRLC_PG_CNTL                                                                                  0x4c43
9386 #define mmRLC_PG_CNTL_BASE_IDX                                                                         1
9387 #define mmRLC_GPM_THREAD_PRIORITY                                                                      0x4c44
9388 #define mmRLC_GPM_THREAD_PRIORITY_BASE_IDX                                                             1
9389 #define mmRLC_GPM_THREAD_ENABLE                                                                        0x4c45
9390 #define mmRLC_GPM_THREAD_ENABLE_BASE_IDX                                                               1
9391 #define mmRLC_CGTT_MGCG_OVERRIDE                                                                       0x4c48
9392 #define mmRLC_CGTT_MGCG_OVERRIDE_BASE_IDX                                                              1
9393 #define mmRLC_CGCG_CGLS_CTRL                                                                           0x4c49
9394 #define mmRLC_CGCG_CGLS_CTRL_BASE_IDX                                                                  1
9395 #define mmRLC_CGCG_RAMP_CTRL                                                                           0x4c4a
9396 #define mmRLC_CGCG_RAMP_CTRL_BASE_IDX                                                                  1
9397 #define mmRLC_DYN_PG_STATUS                                                                            0x4c4b
9398 #define mmRLC_DYN_PG_STATUS_BASE_IDX                                                                   1
9399 #define mmRLC_DYN_PG_REQUEST                                                                           0x4c4c
9400 #define mmRLC_DYN_PG_REQUEST_BASE_IDX                                                                  1
9401 #define mmRLC_PG_DELAY                                                                                 0x4c4d
9402 #define mmRLC_PG_DELAY_BASE_IDX                                                                        1
9403 #define mmRLC_WGP_STATUS                                                                               0x4c4e
9404 #define mmRLC_WGP_STATUS_BASE_IDX                                                                      1
9405 #define mmRLC_LB_INIT_WGP_MASK                                                                         0x4c4f
9406 #define mmRLC_LB_INIT_WGP_MASK_BASE_IDX                                                                1
9407 #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK                                                                0x4c50
9408 #define mmRLC_LB_ALWAYS_ACTIVE_WGP_MASK_BASE_IDX                                                       1
9409 #define mmRLC_LB_PARAMS                                                                                0x4c51
9410 #define mmRLC_LB_PARAMS_BASE_IDX                                                                       1
9411 #define mmRLC_LB_DELAY                                                                                 0x4c52
9412 #define mmRLC_LB_DELAY_BASE_IDX                                                                        1
9413 #define mmRLC_PG_ALWAYS_ON_WGP_MASK                                                                    0x4c53
9414 #define mmRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX                                                           1
9415 #define mmRLC_MAX_PG_WGP                                                                               0x4c54
9416 #define mmRLC_MAX_PG_WGP_BASE_IDX                                                                      1
9417 #define mmRLC_AUTO_PG_CTRL                                                                             0x4c55
9418 #define mmRLC_AUTO_PG_CTRL_BASE_IDX                                                                    1
9419 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL                                                                   0x4c56
9420 #define mmRLC_SMU_GRBM_REG_SAVE_CTRL_BASE_IDX                                                          1
9421 #define mmRLC_SERDES_RD_INDEX                                                                          0x4c59
9422 #define mmRLC_SERDES_RD_INDEX_BASE_IDX                                                                 1
9423 #define mmRLC_SERDES_RD_DATA_0                                                                         0x4c5a
9424 #define mmRLC_SERDES_RD_DATA_0_BASE_IDX                                                                1
9425 #define mmRLC_SERDES_RD_DATA_1                                                                         0x4c5b
9426 #define mmRLC_SERDES_RD_DATA_1_BASE_IDX                                                                1
9427 #define mmRLC_SERDES_RD_DATA_2                                                                         0x4c5c
9428 #define mmRLC_SERDES_RD_DATA_2_BASE_IDX                                                                1
9429 #define mmRLC_SERDES_RD_DATA_3                                                                         0x4c5d
9430 #define mmRLC_SERDES_RD_DATA_3_BASE_IDX                                                                1
9431 #define mmRLC_SERDES_MASK                                                                              0x4c5e
9432 #define mmRLC_SERDES_MASK_BASE_IDX                                                                     1
9433 #define mmRLC_SERDES_CTRL                                                                              0x4c5f
9434 #define mmRLC_SERDES_CTRL_BASE_IDX                                                                     1
9435 #define mmRLC_SERDES_DATA                                                                              0x4c60
9436 #define mmRLC_SERDES_DATA_BASE_IDX                                                                     1
9437 #define mmRLC_SERDES_BUSY                                                                              0x4c61
9438 #define mmRLC_SERDES_BUSY_BASE_IDX                                                                     1
9439 #define mmRLC_GPM_GENERAL_0                                                                            0x4c63
9440 #define mmRLC_GPM_GENERAL_0_BASE_IDX                                                                   1
9441 #define mmRLC_GPM_GENERAL_1                                                                            0x4c64
9442 #define mmRLC_GPM_GENERAL_1_BASE_IDX                                                                   1
9443 #define mmRLC_GPM_GENERAL_2                                                                            0x4c65
9444 #define mmRLC_GPM_GENERAL_2_BASE_IDX                                                                   1
9445 #define mmRLC_GPM_GENERAL_3                                                                            0x4c66
9446 #define mmRLC_GPM_GENERAL_3_BASE_IDX                                                                   1
9447 #define mmRLC_GPM_GENERAL_4                                                                            0x4c67
9448 #define mmRLC_GPM_GENERAL_4_BASE_IDX                                                                   1
9449 #define mmRLC_GPM_GENERAL_5                                                                            0x4c68
9450 #define mmRLC_GPM_GENERAL_5_BASE_IDX                                                                   1
9451 #define mmRLC_GPM_GENERAL_6                                                                            0x4c69
9452 #define mmRLC_GPM_GENERAL_6_BASE_IDX                                                                   1
9453 #define mmRLC_GPM_GENERAL_7                                                                            0x4c6a
9454 #define mmRLC_GPM_GENERAL_7_BASE_IDX                                                                   1
9455 #define mmRLC_STATIC_PG_STATUS                                                                         0x4c6e
9456 #define mmRLC_STATIC_PG_STATUS_BASE_IDX                                                                1
9457 #define mmRLC_SPM_INT_INFO_1                                                                           0x4c6f
9458 #define mmRLC_SPM_INT_INFO_1_BASE_IDX                                                                  1
9459 #define mmRLC_SPM_INT_INFO_2                                                                           0x4c70
9460 #define mmRLC_SPM_INT_INFO_2_BASE_IDX                                                                  1
9461 #define mmRLC_SPM_MC_CNTL                                                                              0x4c71
9462 #define mmRLC_SPM_MC_CNTL_BASE_IDX                                                                     1
9463 #define mmRLC_SPM_INT_CNTL                                                                             0x4c72
9464 #define mmRLC_SPM_INT_CNTL_BASE_IDX                                                                    1
9465 #define mmRLC_SPM_INT_STATUS                                                                           0x4c73
9466 #define mmRLC_SPM_INT_STATUS_BASE_IDX                                                                  1
9467 #define mmRLC_SMU_MESSAGE                                                                              0x4c76
9468 #define mmRLC_SMU_MESSAGE_BASE_IDX                                                                     1
9469 #define mmRLC_GPM_LOG_SIZE                                                                             0x4c77
9470 #define mmRLC_GPM_LOG_SIZE_BASE_IDX                                                                    1
9471 #define mmRLC_PG_DELAY_3                                                                               0x4c78
9472 #define mmRLC_PG_DELAY_3_BASE_IDX                                                                      1
9473 #define mmRLC_GPR_REG1                                                                                 0x4c79
9474 #define mmRLC_GPR_REG1_BASE_IDX                                                                        1
9475 #define mmRLC_GPR_REG2                                                                                 0x4c7a
9476 #define mmRLC_GPR_REG2_BASE_IDX                                                                        1
9477 #define mmRLC_GPM_LOG_CONT                                                                             0x4c7b
9478 #define mmRLC_GPM_LOG_CONT_BASE_IDX                                                                    1
9479 #define mmRLC_GPM_INT_DISABLE_TH0                                                                      0x4c7c
9480 #define mmRLC_GPM_INT_DISABLE_TH0_BASE_IDX                                                             1
9481 #define mmRLC_GPM_INT_FORCE_TH0                                                                        0x4c7e
9482 #define mmRLC_GPM_INT_FORCE_TH0_BASE_IDX                                                               1
9483 #define mmRLC_SRM_CNTL                                                                                 0x4c80
9484 #define mmRLC_SRM_CNTL_BASE_IDX                                                                        1
9485 #define mmRLC_SRM_GPM_COMMAND                                                                          0x4c87
9486 #define mmRLC_SRM_GPM_COMMAND_BASE_IDX                                                                 1
9487 #define mmRLC_SRM_GPM_COMMAND_STATUS                                                                   0x4c88
9488 #define mmRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX                                                          1
9489 #define mmRLC_SRM_RLCV_COMMAND                                                                         0x4c89
9490 #define mmRLC_SRM_RLCV_COMMAND_BASE_IDX                                                                1
9491 #define mmRLC_SRM_RLCV_COMMAND_STATUS                                                                  0x4c8a
9492 #define mmRLC_SRM_RLCV_COMMAND_STATUS_BASE_IDX                                                         1
9493 #define mmRLC_SRM_INDEX_CNTL_ADDR_0                                                                    0x4c8b
9494 #define mmRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX                                                           1
9495 #define mmRLC_SRM_INDEX_CNTL_ADDR_1                                                                    0x4c8c
9496 #define mmRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX                                                           1
9497 #define mmRLC_SRM_INDEX_CNTL_ADDR_2                                                                    0x4c8d
9498 #define mmRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX                                                           1
9499 #define mmRLC_SRM_INDEX_CNTL_ADDR_3                                                                    0x4c8e
9500 #define mmRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX                                                           1
9501 #define mmRLC_SRM_INDEX_CNTL_ADDR_4                                                                    0x4c8f
9502 #define mmRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX                                                           1
9503 #define mmRLC_SRM_INDEX_CNTL_ADDR_5                                                                    0x4c90
9504 #define mmRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX                                                           1
9505 #define mmRLC_SRM_INDEX_CNTL_ADDR_6                                                                    0x4c91
9506 #define mmRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX                                                           1
9507 #define mmRLC_SRM_INDEX_CNTL_ADDR_7                                                                    0x4c92
9508 #define mmRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX                                                           1
9509 #define mmRLC_SRM_INDEX_CNTL_DATA_0                                                                    0x4c93
9510 #define mmRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX                                                           1
9511 #define mmRLC_SRM_INDEX_CNTL_DATA_1                                                                    0x4c94
9512 #define mmRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX                                                           1
9513 #define mmRLC_SRM_INDEX_CNTL_DATA_2                                                                    0x4c95
9514 #define mmRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX                                                           1
9515 #define mmRLC_SRM_INDEX_CNTL_DATA_3                                                                    0x4c96
9516 #define mmRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX                                                           1
9517 #define mmRLC_SRM_INDEX_CNTL_DATA_4                                                                    0x4c97
9518 #define mmRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX                                                           1
9519 #define mmRLC_SRM_INDEX_CNTL_DATA_5                                                                    0x4c98
9520 #define mmRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX                                                           1
9521 #define mmRLC_SRM_INDEX_CNTL_DATA_6                                                                    0x4c99
9522 #define mmRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX                                                           1
9523 #define mmRLC_SRM_INDEX_CNTL_DATA_7                                                                    0x4c9a
9524 #define mmRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX                                                           1
9525 #define mmRLC_SRM_STAT                                                                                 0x4c9b
9526 #define mmRLC_SRM_STAT_BASE_IDX                                                                        1
9527 #define mmRLC_SRM_GPM_ABORT                                                                            0x4c9c
9528 #define mmRLC_SRM_GPM_ABORT_BASE_IDX                                                                   1
9529 #define mmRLC_CSIB_ADDR_LO                                                                             0x4ca2
9530 #define mmRLC_CSIB_ADDR_LO_BASE_IDX                                                                    1
9531 #define mmRLC_CSIB_ADDR_HI                                                                             0x4ca3
9532 #define mmRLC_CSIB_ADDR_HI_BASE_IDX                                                                    1
9533 #define mmRLC_CSIB_LENGTH                                                                              0x4ca4
9534 #define mmRLC_CSIB_LENGTH_BASE_IDX                                                                     1
9535 #define mmRLC_PACE_INT_STAT                                                                            0x4ca5
9536 #define mmRLC_PACE_INT_STAT_BASE_IDX                                                                   1
9537 #define mmRLC_SMU_COMMAND                                                                              0x4ca9
9538 #define mmRLC_SMU_COMMAND_BASE_IDX                                                                     1
9539 #define mmRLC_CP_SCHEDULERS                                                                            0x4caa
9540 #define mmRLC_CP_SCHEDULERS_BASE_IDX                                                                   1
9541 #define mmRLC_SMU_ARGUMENT_1                                                                           0x4cab
9542 #define mmRLC_SMU_ARGUMENT_1_BASE_IDX                                                                  1
9543 #define mmRLC_SMU_ARGUMENT_2                                                                           0x4cac
9544 #define mmRLC_SMU_ARGUMENT_2_BASE_IDX                                                                  1
9545 #define mmRLC_GPM_GENERAL_8                                                                            0x4cad
9546 #define mmRLC_GPM_GENERAL_8_BASE_IDX                                                                   1
9547 #define mmRLC_GPM_GENERAL_9                                                                            0x4cae
9548 #define mmRLC_GPM_GENERAL_9_BASE_IDX                                                                   1
9549 #define mmRLC_GPM_GENERAL_10                                                                           0x4caf
9550 #define mmRLC_GPM_GENERAL_10_BASE_IDX                                                                  1
9551 #define mmRLC_GPM_GENERAL_11                                                                           0x4cb0
9552 #define mmRLC_GPM_GENERAL_11_BASE_IDX                                                                  1
9553 #define mmRLC_GPM_GENERAL_12                                                                           0x4cb1
9554 #define mmRLC_GPM_GENERAL_12_BASE_IDX                                                                  1
9555 #define mmRLC_GPM_UTCL1_CNTL_0                                                                         0x4cb2
9556 #define mmRLC_GPM_UTCL1_CNTL_0_BASE_IDX                                                                1
9557 #define mmRLC_GPM_UTCL1_CNTL_1                                                                         0x4cb3
9558 #define mmRLC_GPM_UTCL1_CNTL_1_BASE_IDX                                                                1
9559 #define mmRLC_GPM_UTCL1_CNTL_2                                                                         0x4cb4
9560 #define mmRLC_GPM_UTCL1_CNTL_2_BASE_IDX                                                                1
9561 #define mmRLC_SPM_UTCL1_CNTL                                                                           0x4cb5
9562 #define mmRLC_SPM_UTCL1_CNTL_BASE_IDX                                                                  1
9563 #define mmRLC_UTCL1_STATUS_2                                                                           0x4cb6
9564 #define mmRLC_UTCL1_STATUS_2_BASE_IDX                                                                  1
9565 #define mmRLC_LB_CONFIG_2                                                                              0x4cb8
9566 #define mmRLC_LB_CONFIG_2_BASE_IDX                                                                     1
9567 #define mmRLC_LB_CONFIG_3                                                                              0x4cb9
9568 #define mmRLC_LB_CONFIG_3_BASE_IDX                                                                     1
9569 #define mmRLC_LB_CONFIG_4                                                                              0x4cba
9570 #define mmRLC_LB_CONFIG_4_BASE_IDX                                                                     1
9571 #define mmRLC_SPM_UTCL1_ERROR_1                                                                        0x4cbc
9572 #define mmRLC_SPM_UTCL1_ERROR_1_BASE_IDX                                                               1
9573 #define mmRLC_SPM_UTCL1_ERROR_2                                                                        0x4cbd
9574 #define mmRLC_SPM_UTCL1_ERROR_2_BASE_IDX                                                               1
9575 #define mmRLC_GPM_UTCL1_TH0_ERROR_1                                                                    0x4cbe
9576 #define mmRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX                                                           1
9577 #define mmRLC_LB_CONFIG_1                                                                              0x4cbf
9578 #define mmRLC_LB_CONFIG_1_BASE_IDX                                                                     1
9579 #define mmRLC_GPM_UTCL1_TH0_ERROR_2                                                                    0x4cc0
9580 #define mmRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX                                                           1
9581 #define mmRLC_GPM_UTCL1_TH1_ERROR_1                                                                    0x4cc1
9582 #define mmRLC_GPM_UTCL1_TH1_ERROR_1_BASE_IDX                                                           1
9583 #define mmRLC_GPM_UTCL1_TH1_ERROR_2                                                                    0x4cc2
9584 #define mmRLC_GPM_UTCL1_TH1_ERROR_2_BASE_IDX                                                           1
9585 #define mmRLC_GPM_UTCL1_TH2_ERROR_1                                                                    0x4cc3
9586 #define mmRLC_GPM_UTCL1_TH2_ERROR_1_BASE_IDX                                                           1
9587 #define mmRLC_GPM_UTCL1_TH2_ERROR_2                                                                    0x4cc4
9588 #define mmRLC_GPM_UTCL1_TH2_ERROR_2_BASE_IDX                                                           1
9589 #define mmRLC_CGCG_CGLS_CTRL_3D                                                                        0x4cc5
9590 #define mmRLC_CGCG_CGLS_CTRL_3D_BASE_IDX                                                               1
9591 #define mmRLC_CGCG_RAMP_CTRL_3D                                                                        0x4cc6
9592 #define mmRLC_CGCG_RAMP_CTRL_3D_BASE_IDX                                                               1
9593 #define mmRLC_SEMAPHORE_0                                                                              0x4cc7
9594 #define mmRLC_SEMAPHORE_0_BASE_IDX                                                                     1
9595 #define mmRLC_SEMAPHORE_1                                                                              0x4cc8
9596 #define mmRLC_SEMAPHORE_1_BASE_IDX                                                                     1
9597 #define mmRLC_CP_EOF_INT                                                                               0x4cca
9598 #define mmRLC_CP_EOF_INT_BASE_IDX                                                                      1
9599 #define mmRLC_CP_EOF_INT_CNT                                                                           0x4ccb
9600 #define mmRLC_CP_EOF_INT_CNT_BASE_IDX                                                                  1
9601 #define mmRLC_SPARE_INT                                                                                0x4ccc
9602 #define mmRLC_SPARE_INT_BASE_IDX                                                                       1
9603 #define mmRLC_PREWALKER_UTCL1_CNTL                                                                     0x4ccd
9604 #define mmRLC_PREWALKER_UTCL1_CNTL_BASE_IDX                                                            1
9605 #define mmRLC_PREWALKER_UTCL1_TRIG                                                                     0x4cce
9606 #define mmRLC_PREWALKER_UTCL1_TRIG_BASE_IDX                                                            1
9607 #define mmRLC_PREWALKER_UTCL1_ADDR_LSB                                                                 0x4ccf
9608 #define mmRLC_PREWALKER_UTCL1_ADDR_LSB_BASE_IDX                                                        1
9609 #define mmRLC_PREWALKER_UTCL1_ADDR_MSB                                                                 0x4cd0
9610 #define mmRLC_PREWALKER_UTCL1_ADDR_MSB_BASE_IDX                                                        1
9611 #define mmRLC_PREWALKER_UTCL1_SIZE_LSB                                                                 0x4cd1
9612 #define mmRLC_PREWALKER_UTCL1_SIZE_LSB_BASE_IDX                                                        1
9613 #define mmRLC_PREWALKER_UTCL1_SIZE_MSB                                                                 0x4cd2
9614 #define mmRLC_PREWALKER_UTCL1_SIZE_MSB_BASE_IDX                                                        1
9615 #define mmRLC_UTCL1_STATUS                                                                             0x4cd4
9616 #define mmRLC_UTCL1_STATUS_BASE_IDX                                                                    1
9617 #define mmRLC_R2I_CNTL_0                                                                               0x4cd5
9618 #define mmRLC_R2I_CNTL_0_BASE_IDX                                                                      1
9619 #define mmRLC_R2I_CNTL_1                                                                               0x4cd6
9620 #define mmRLC_R2I_CNTL_1_BASE_IDX                                                                      1
9621 #define mmRLC_R2I_CNTL_2                                                                               0x4cd7
9622 #define mmRLC_R2I_CNTL_2_BASE_IDX                                                                      1
9623 #define mmRLC_R2I_CNTL_3                                                                               0x4cd8
9624 #define mmRLC_R2I_CNTL_3_BASE_IDX                                                                      1
9625 #define mmRLC_LB_WGP_STAT                                                                              0x4cda
9626 #define mmRLC_LB_WGP_STAT_BASE_IDX                                                                     1
9627 #define mmRLC_GPM_INT_STAT_TH0                                                                         0x4cdc
9628 #define mmRLC_GPM_INT_STAT_TH0_BASE_IDX                                                                1
9629 #define mmRLC_GPM_GENERAL_13                                                                           0x4cdd
9630 #define mmRLC_GPM_GENERAL_13_BASE_IDX                                                                  1
9631 #define mmRLC_GPM_GENERAL_14                                                                           0x4cde
9632 #define mmRLC_GPM_GENERAL_14_BASE_IDX                                                                  1
9633 #define mmRLC_GPM_GENERAL_15                                                                           0x4cdf
9634 #define mmRLC_GPM_GENERAL_15_BASE_IDX                                                                  1
9635 #define mmRLC_SPARE_INT_1                                                                              0x4ce0
9636 #define mmRLC_SPARE_INT_1_BASE_IDX                                                                     1
9637 #define mmRLC_RLCV_SPARE_INT_1                                                                         0x4ce1
9638 #define mmRLC_RLCV_SPARE_INT_1_BASE_IDX                                                                1
9639 #define mmRLC_PACE_SPARE_INT_1                                                                         0x4ce2
9640 #define mmRLC_PACE_SPARE_INT_1_BASE_IDX                                                                1
9641 #define mmRLC_SEMAPHORE_2                                                                              0x4ce3
9642 #define mmRLC_SEMAPHORE_2_BASE_IDX                                                                     1
9643 #define mmRLC_SEMAPHORE_3                                                                              0x4ce4
9644 #define mmRLC_SEMAPHORE_3_BASE_IDX                                                                     1
9645 #define mmRLC_SMU_ARGUMENT_3                                                                           0x4ce5
9646 #define mmRLC_SMU_ARGUMENT_3_BASE_IDX                                                                  1
9647 #define mmRLC_SMU_ARGUMENT_4                                                                           0x4ce6
9648 #define mmRLC_SMU_ARGUMENT_4_BASE_IDX                                                                  1
9649 #define mmRLC_GPU_CLOCK_COUNT_LSB_1                                                                    0x4ce8
9650 #define mmRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX                                                           1
9651 #define mmRLC_GPU_CLOCK_COUNT_MSB_1                                                                    0x4ce9
9652 #define mmRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX                                                           1
9653 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1                                                                0x4cea
9654 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX                                                       1
9655 #define mmRLC_GPU_CLOCK_COUNT_LSB_2                                                                    0x4ceb
9656 #define mmRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX                                                           1
9657 #define mmRLC_GPU_CLOCK_COUNT_MSB_2                                                                    0x4cec
9658 #define mmRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX                                                           1
9659 #define mmRLC_PACE_INT_DISABLE                                                                         0x4ced
9660 #define mmRLC_PACE_INT_DISABLE_BASE_IDX                                                                1
9661 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2                                                                0x4cef
9662 #define mmRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX                                                       1
9663 #define mmRLC_RLCV_SPARE_INT                                                                           0x4d00
9664 #define mmRLC_RLCV_SPARE_INT_BASE_IDX                                                                  1
9665 #define mmRLC_PACE_TIMER_INT_0                                                                         0x4d04
9666 #define mmRLC_PACE_TIMER_INT_0_BASE_IDX                                                                1
9667 #define mmRLC_PACE_TIMER_CTRL                                                                          0x4d05
9668 #define mmRLC_PACE_TIMER_CTRL_BASE_IDX                                                                 1
9669 #define mmRLC_PACE_TIMER_INT_1                                                                         0x4d06
9670 #define mmRLC_PACE_TIMER_INT_1_BASE_IDX                                                                1
9671 #define mmRLC_PACE_SPARE_INT                                                                           0x4d07
9672 #define mmRLC_PACE_SPARE_INT_BASE_IDX                                                                  1
9673 #define mmRLC_SMU_CLK_REQ                                                                              0x4d08
9674 #define mmRLC_SMU_CLK_REQ_BASE_IDX                                                                     1
9675 #define mmRLC_CP_STAT_INVAL_STAT                                                                       0x4d09
9676 #define mmRLC_CP_STAT_INVAL_STAT_BASE_IDX                                                              1
9677 #define mmRLC_CP_STAT_INVAL_CTRL                                                                       0x4d0a
9678 #define mmRLC_CP_STAT_INVAL_CTRL_BASE_IDX                                                              1
9679 #define mmRLC_SPP_CTRL                                                                                 0x4d0c
9680 #define mmRLC_SPP_CTRL_BASE_IDX                                                                        1
9681 #define mmRLC_SPP_SHADER_PROFILE_EN                                                                    0x4d0d
9682 #define mmRLC_SPP_SHADER_PROFILE_EN_BASE_IDX                                                           1
9683 #define mmRLC_SPP_SSF_CAPTURE_EN                                                                       0x4d0e
9684 #define mmRLC_SPP_SSF_CAPTURE_EN_BASE_IDX                                                              1
9685 #define mmRLC_SPP_SSF_THRESHOLD_0                                                                      0x4d0f
9686 #define mmRLC_SPP_SSF_THRESHOLD_0_BASE_IDX                                                             1
9687 #define mmRLC_SPP_SSF_THRESHOLD_1                                                                      0x4d10
9688 #define mmRLC_SPP_SSF_THRESHOLD_1_BASE_IDX                                                             1
9689 #define mmRLC_SPP_SSF_THRESHOLD_2                                                                      0x4d11
9690 #define mmRLC_SPP_SSF_THRESHOLD_2_BASE_IDX                                                             1
9691 #define mmRLC_SPP_INFLIGHT_RD_ADDR                                                                     0x4d12
9692 #define mmRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX                                                            1
9693 #define mmRLC_SPP_INFLIGHT_RD_DATA                                                                     0x4d13
9694 #define mmRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX                                                            1
9695 #define mmRLC_SPP_PROF_INFO_1                                                                          0x4d18
9696 #define mmRLC_SPP_PROF_INFO_1_BASE_IDX                                                                 1
9697 #define mmRLC_SPP_PROF_INFO_2                                                                          0x4d19
9698 #define mmRLC_SPP_PROF_INFO_2_BASE_IDX                                                                 1
9699 #define mmRLC_SPP_GLOBAL_SH_ID                                                                         0x4d1a
9700 #define mmRLC_SPP_GLOBAL_SH_ID_BASE_IDX                                                                1
9701 #define mmRLC_SPP_GLOBAL_SH_ID_VALID                                                                   0x4d1b
9702 #define mmRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX                                                          1
9703 #define mmRLC_SPP_STATUS                                                                               0x4d1c
9704 #define mmRLC_SPP_STATUS_BASE_IDX                                                                      1
9705 #define mmRLC_SPP_PVT_STAT_0                                                                           0x4d1d
9706 #define mmRLC_SPP_PVT_STAT_0_BASE_IDX                                                                  1
9707 #define mmRLC_SPP_PVT_STAT_1                                                                           0x4d1e
9708 #define mmRLC_SPP_PVT_STAT_1_BASE_IDX                                                                  1
9709 #define mmRLC_SPP_PVT_STAT_2                                                                           0x4d1f
9710 #define mmRLC_SPP_PVT_STAT_2_BASE_IDX                                                                  1
9711 #define mmRLC_SPP_PVT_STAT_3                                                                           0x4d20
9712 #define mmRLC_SPP_PVT_STAT_3_BASE_IDX                                                                  1
9713 #define mmRLC_SPP_PVT_LEVEL_MAX                                                                        0x4d21
9714 #define mmRLC_SPP_PVT_LEVEL_MAX_BASE_IDX                                                               1
9715 #define mmRLC_SPP_STALL_STATE_UPDATE                                                                   0x4d22
9716 #define mmRLC_SPP_STALL_STATE_UPDATE_BASE_IDX                                                          1
9717 #define mmRLC_SPP_PBB_INFO                                                                             0x4d23
9718 #define mmRLC_SPP_PBB_INFO_BASE_IDX                                                                    1
9719 #define mmRLC_SPP_RESET                                                                                0x4d24
9720 #define mmRLC_SPP_RESET_BASE_IDX                                                                       1
9721 #define mmRLC_SPM_SAMPLE_CNT                                                                           0x4d25
9722 #define mmRLC_SPM_SAMPLE_CNT_BASE_IDX                                                                  1
9723 #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL                                                              0x4d44
9724 #define mmRLC_PCC_STRETCH_HYSTERESIS_CNTL_BASE_IDX                                                     1
9725 #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB                                                                  0x4de4
9726 #define mmRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX                                                         1
9727 #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB                                                                  0x4de5
9728 #define mmRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX                                                         1
9729 #define mmRLC_SPM_THREAD_TRACE_CTRL                                                                    0x4de6
9730 #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX                                                           1
9731 #define mmRLC_LB_CNTR_2                                                                                0x4de7
9732 #define mmRLC_LB_CNTR_2_BASE_IDX                                                                       1
9733 #define mmRLC_LX6_CORE_PDEBUG_INST                                                                     0x4deb
9734 #define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX                                                            1
9735 #define mmRLC_CPAXI_DOORBELL_MON_CTRL                                                                  0x4df1
9736 #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX                                                         1
9737 #define mmRLC_CPAXI_DOORBELL_MON_STAT                                                                  0x4df2
9738 #define mmRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX                                                         1
9739 #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB                                                              0x4df3
9740 #define mmRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX                                                     1
9741 #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB                                                              0x4df4
9742 #define mmRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX                                                     1
9743 
9744 
9745 // addressBlock: gc_rlcrdec
9746 // base address: 0x3b800
9747 #define mmRLC_SPP_CAM_ADDR                                                                             0x4e00
9748 #define mmRLC_SPP_CAM_ADDR_BASE_IDX                                                                    1
9749 #define mmRLC_SPP_CAM_DATA                                                                             0x4e01
9750 #define mmRLC_SPP_CAM_DATA_BASE_IDX                                                                    1
9751 #define mmRLC_SPP_CAM_EXT_ADDR                                                                         0x4e02
9752 #define mmRLC_SPP_CAM_EXT_ADDR_BASE_IDX                                                                1
9753 #define mmRLC_SPP_CAM_EXT_DATA                                                                         0x4e03
9754 #define mmRLC_SPP_CAM_EXT_DATA_BASE_IDX                                                                1
9755 #define mmRLC_PACE_SCRATCH_ADDR                                                                        0x4e04
9756 #define mmRLC_PACE_SCRATCH_ADDR_BASE_IDX                                                               1
9757 #define mmRLC_PACE_SCRATCH_DATA                                                                        0x4e05
9758 #define mmRLC_PACE_SCRATCH_DATA_BASE_IDX                                                               1
9759 
9760 
9761 // addressBlock: gc_rlcsdec
9762 // base address: 0x3b980
9763 #define mmRLC_RLCS_DEC_START                                                                           0x4e60
9764 #define mmRLC_RLCS_DEC_START_BASE_IDX                                                                  1
9765 #define mmRLC_RLCS_DEC_DUMP_ADDR                                                                       0x4e61
9766 #define mmRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX                                                              1
9767 #define mmRLC_RLCS_EXCEPTION_REG_1                                                                     0x4e62
9768 #define mmRLC_RLCS_EXCEPTION_REG_1_BASE_IDX                                                            1
9769 #define mmRLC_RLCS_EXCEPTION_REG_2                                                                     0x4e63
9770 #define mmRLC_RLCS_EXCEPTION_REG_2_BASE_IDX                                                            1
9771 #define mmRLC_RLCS_EXCEPTION_REG_3                                                                     0x4e64
9772 #define mmRLC_RLCS_EXCEPTION_REG_3_BASE_IDX                                                            1
9773 #define mmRLC_RLCS_EXCEPTION_REG_4                                                                     0x4e65
9774 #define mmRLC_RLCS_EXCEPTION_REG_4_BASE_IDX                                                            1
9775 #define mmRLC_RLCS_GENERAL_6                                                                           0x4e66
9776 #define mmRLC_RLCS_GENERAL_6_BASE_IDX                                                                  1
9777 #define mmRLC_RLCS_GENERAL_7                                                                           0x4e67
9778 #define mmRLC_RLCS_GENERAL_7_BASE_IDX                                                                  1
9779 #define mmRLC_RLCS_CGCG_REQUEST                                                                        0x4e68
9780 #define mmRLC_RLCS_CGCG_REQUEST_BASE_IDX                                                               1
9781 #define mmRLC_RLCS_CGCG_STATUS                                                                         0x4e69
9782 #define mmRLC_RLCS_CGCG_STATUS_BASE_IDX                                                                1
9783 #define mmRLC_RLCS_SMU_GFXCLK_STATUS                                                                   0x4e6a
9784 #define mmRLC_RLCS_SMU_GFXCLK_STATUS_BASE_IDX                                                          1
9785 #define mmRLC_RLCS_SMU_GFXCLK_CONTROL                                                                  0x4e6b
9786 #define mmRLC_RLCS_SMU_GFXCLK_CONTROL_BASE_IDX                                                         1
9787 #define mmRLC_RLCS_SOC_DS_CNTL                                                                         0x4e6c
9788 #define mmRLC_RLCS_SOC_DS_CNTL_BASE_IDX                                                                1
9789 #define mmRLC_RLCS_GFX_DS_CNTL                                                                         0x4e6d
9790 #define mmRLC_RLCS_GFX_DS_CNTL_BASE_IDX                                                                1
9791 #define mmRLC_GPM_STAT                                                                                 0x4e6e
9792 #define mmRLC_GPM_STAT_BASE_IDX                                                                        1
9793 #define mmRLC_RLCS_GPM_STAT                                                                            0x4e6e
9794 #define mmRLC_RLCS_GPM_STAT_BASE_IDX                                                                   1
9795 #define mmRLC_RLCS_ABORTED_PD_SEQUENCE                                                                 0x4e6f
9796 #define mmRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX                                                        1
9797 #define mmRLC_RLCS_DIDT_FORCE_STALL                                                                    0x4e70
9798 #define mmRLC_RLCS_DIDT_FORCE_STALL_BASE_IDX                                                           1
9799 #define mmRLC_RLCS_IOV_CMD_STATUS                                                                      0x4e71
9800 #define mmRLC_RLCS_IOV_CMD_STATUS_BASE_IDX                                                             1
9801 #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE                                                                   0x4e72
9802 #define mmRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX                                                          1
9803 #define mmRLC_RLCS_IOV_SCH_BLOCK                                                                       0x4e73
9804 #define mmRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX                                                              1
9805 #define mmRLC_RLCS_IOV_VM_BUSY_STATUS                                                                  0x4e74
9806 #define mmRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX                                                         1
9807 #define mmRLC_RLCS_GPM_STAT_2                                                                          0x4e75
9808 #define mmRLC_RLCS_GPM_STAT_2_BASE_IDX                                                                 1
9809 #define mmRLC_RLCS_GRBM_SOFT_RESET                                                                     0x4e76
9810 #define mmRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX                                                            1
9811 #define mmRLC_RLCS_PG_CHANGE_STATUS                                                                    0x4e77
9812 #define mmRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX                                                           1
9813 #define mmRLC_RLCS_PG_CHANGE_READ                                                                      0x4e78
9814 #define mmRLC_RLCS_PG_CHANGE_READ_BASE_IDX                                                             1
9815 #define mmRLC_RLCS_LB_STATUS                                                                           0x4e79
9816 #define mmRLC_RLCS_LB_STATUS_BASE_IDX                                                                  1
9817 #define mmRLC_RLCS_LB_READ                                                                             0x4e7a
9818 #define mmRLC_RLCS_LB_READ_BASE_IDX                                                                    1
9819 #define mmRLC_RLCS_LB_CONTROL                                                                          0x4e7b
9820 #define mmRLC_RLCS_LB_CONTROL_BASE_IDX                                                                 1
9821 #define mmRLC_RLCS_IH_SEMAPHORE                                                                        0x4e7c
9822 #define mmRLC_RLCS_IH_SEMAPHORE_BASE_IDX                                                               1
9823 #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE                                                                 0x4e7d
9824 #define mmRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX                                                        1
9825 #define mmRLC_RLCS_IH_CTRL_1                                                                           0x4e7e
9826 #define mmRLC_RLCS_IH_CTRL_1_BASE_IDX                                                                  1
9827 #define mmRLC_RLCS_IH_CTRL_2                                                                           0x4e7f
9828 #define mmRLC_RLCS_IH_CTRL_2_BASE_IDX                                                                  1
9829 #define mmRLC_RLCS_IH_CTRL_3                                                                           0x4e80
9830 #define mmRLC_RLCS_IH_CTRL_3_BASE_IDX                                                                  1
9831 #define mmRLC_RLCS_IH_STATUS                                                                           0x4e81
9832 #define mmRLC_RLCS_IH_STATUS_BASE_IDX                                                                  1
9833 #define mmRLC_RLCS_WGP_STATUS                                                                          0x4e82
9834 #define mmRLC_RLCS_WGP_STATUS_BASE_IDX                                                                 1
9835 #define mmRLC_RLCS_WGP_READ                                                                            0x4e83
9836 #define mmRLC_RLCS_WGP_READ_BASE_IDX                                                                   1
9837 #define mmRLC_RLCS_CP_INT_CTRL_1                                                                       0x4e84
9838 #define mmRLC_RLCS_CP_INT_CTRL_1_BASE_IDX                                                              1
9839 #define mmRLC_RLCS_CP_INT_CTRL_2                                                                       0x4e85
9840 #define mmRLC_RLCS_CP_INT_CTRL_2_BASE_IDX                                                              1
9841 #define mmRLC_RLCS_CP_INT_INFO_1                                                                       0x4e86
9842 #define mmRLC_RLCS_CP_INT_INFO_1_BASE_IDX                                                              1
9843 #define mmRLC_RLCS_CP_INT_INFO_2                                                                       0x4e87
9844 #define mmRLC_RLCS_CP_INT_INFO_2_BASE_IDX                                                              1
9845 #define mmRLC_RLCS_SPM_INT_CTRL                                                                        0x4e88
9846 #define mmRLC_RLCS_SPM_INT_CTRL_BASE_IDX                                                               1
9847 #define mmRLC_RLCS_SPM_INT_INFO_1                                                                      0x4e89
9848 #define mmRLC_RLCS_SPM_INT_INFO_1_BASE_IDX                                                             1
9849 #define mmRLC_RLCS_SPM_INT_INFO_2                                                                      0x4e8a
9850 #define mmRLC_RLCS_SPM_INT_INFO_2_BASE_IDX                                                             1
9851 #define mmRLC_RLCS_DSM_TRIG                                                                            0x4e8b
9852 #define mmRLC_RLCS_DSM_TRIG_BASE_IDX                                                                   1
9853 #define mmRLC_RLCS_GE_FAST_CLOCK                                                                       0x4e8c
9854 #define mmRLC_RLCS_GE_FAST_CLOCK_BASE_IDX                                                              1
9855 #define mmRLC_RLCS_BOOTLOAD_STATUS                                                                     0x4e8d
9856 #define mmRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX                                                            1
9857 #define mmRLC_RLCS_POWER_BRAKE_CNTL                                                                    0x4e8e
9858 #define mmRLC_RLCS_POWER_BRAKE_CNTL_BASE_IDX                                                           1
9859 #define mmRLC_RLCS_GENERAL_0                                                                           0x4e8f
9860 #define mmRLC_RLCS_GENERAL_0_BASE_IDX                                                                  1
9861 #define mmRLC_RLCS_GENERAL_1                                                                           0x4e90
9862 #define mmRLC_RLCS_GENERAL_1_BASE_IDX                                                                  1
9863 #define mmRLC_RLCS_GENERAL_2                                                                           0x4e91
9864 #define mmRLC_RLCS_GENERAL_2_BASE_IDX                                                                  1
9865 #define mmRLC_RLCS_GENERAL_3                                                                           0x4e92
9866 #define mmRLC_RLCS_GENERAL_3_BASE_IDX                                                                  1
9867 #define mmRLC_RLCS_GENERAL_4                                                                           0x4e93
9868 #define mmRLC_RLCS_GENERAL_4_BASE_IDX                                                                  1
9869 #define mmRLC_RLCS_GENERAL_5                                                                           0x4e94
9870 #define mmRLC_RLCS_GENERAL_5_BASE_IDX                                                                  1
9871 #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT                                                                 0x4ec1
9872 #define mmRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX                                                        1
9873 #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL                                                             0x4ec2
9874 #define mmRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX                                                    1
9875 #define mmRLC_RLCS_CMP_IDLE_CNTL                                                                       0x4ec3
9876 #define mmRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX                                                              1
9877 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1                                                                0x4ec4
9878 #define mmRLC_RLCS_POWER_BRAKE_CNTL_TH1_BASE_IDX                                                       1
9879 #define mmRLC_RLCS_AUXILIARY_REG_1                                                                     0x4ec5
9880 #define mmRLC_RLCS_AUXILIARY_REG_1_BASE_IDX                                                            1
9881 #define mmRLC_RLCS_AUXILIARY_REG_2                                                                     0x4ec6
9882 #define mmRLC_RLCS_AUXILIARY_REG_2_BASE_IDX                                                            1
9883 #define mmRLC_RLCS_AUXILIARY_REG_3                                                                     0x4ec7
9884 #define mmRLC_RLCS_AUXILIARY_REG_3_BASE_IDX                                                            1
9885 #define mmRLC_RLCS_AUXILIARY_REG_4                                                                     0x4ec8
9886 #define mmRLC_RLCS_AUXILIARY_REG_4_BASE_IDX                                                            1
9887 #define mmRLC_RLCS_SPM_SQTT_MODE                                                                       0x4ee0
9888 #define mmRLC_RLCS_SPM_SQTT_MODE_BASE_IDX                                                              1
9889 #define mmRLC_RLCS_CP_DMA_SRCID_OVER                                                                   0x4ee4
9890 #define mmRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX                                                          1
9891 #define mmRLC_RLCS_UTCL2_CNTL                                                                          0x4ee6
9892 #define mmRLC_RLCS_UTCL2_CNTL_BASE_IDX                                                                 1
9893 #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL                                                               0x4ee8
9894 #define mmRLC_RLCS_MP1_RLC_DOORBELL_CTRL_BASE_IDX                                                      1
9895 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1                                                                 0x4eec
9896 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX                                                        1
9897 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2                                                                 0x4eed
9898 #define mmRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX                                                        1
9899 #define mmRLC_RLCS_EDC_INT_CNTL                                                                        0x4eef
9900 #define mmRLC_RLCS_EDC_INT_CNTL_BASE_IDX                                                               1
9901 #define mmRLC_RLCS_DEC_END                                                                             0x4fff
9902 #define mmRLC_RLCS_DEC_END_BASE_IDX                                                                    1
9903 
9904 
9905 // addressBlock: gc_pwrdec
9906 // base address: 0x3c000
9907 #define mmCGTS_SA0_QUAD0_SM_CTRL_REG                                                                   0x5000
9908 #define mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX                                                          1
9909 #define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG                                                         0x5001
9910 #define mmCGTS_SA0_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX                                                1
9911 #define mmCGTS_SA0_QUAD1_SM_CTRL_REG                                                                   0x5002
9912 #define mmCGTS_SA0_QUAD1_SM_CTRL_REG_BASE_IDX                                                          1
9913 #define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG                                                         0x5003
9914 #define mmCGTS_SA0_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX                                                1
9915 #define mmCGTS_SA1_QUAD0_SM_CTRL_REG                                                                   0x5004
9916 #define mmCGTS_SA1_QUAD0_SM_CTRL_REG_BASE_IDX                                                          1
9917 #define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG                                                         0x5005
9918 #define mmCGTS_SA1_QUAD0_CLK_MONITOR_DELAY_REG_BASE_IDX                                                1
9919 #define mmCGTS_SA1_QUAD1_SM_CTRL_REG                                                                   0x5006
9920 #define mmCGTS_SA1_QUAD1_SM_CTRL_REG_BASE_IDX                                                          1
9921 #define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG                                                         0x5007
9922 #define mmCGTS_SA1_QUAD1_CLK_MONITOR_DELAY_REG_BASE_IDX                                                1
9923 #define mmCGTS_RD_CTRL_REG                                                                             0x5008
9924 #define mmCGTS_RD_CTRL_REG_BASE_IDX                                                                    1
9925 #define mmCGTS_RD_REG                                                                                  0x5009
9926 #define mmCGTS_RD_REG_BASE_IDX                                                                         1
9927 #define mmCGTS_TCC_DISABLE                                                                             0x500a
9928 #define mmCGTS_TCC_DISABLE_BASE_IDX                                                                    1
9929 #define mmCGTS_USER_TCC_DISABLE                                                                        0x500b
9930 #define mmCGTS_USER_TCC_DISABLE_BASE_IDX                                                               1
9931 #define mmCGTS_STATUS_REG                                                                              0x500c
9932 #define mmCGTS_STATUS_REG_BASE_IDX                                                                     1
9933 #define mmCGTT_SPI_CGTSSM_CLK_CTRL                                                                     0x500d
9934 #define mmCGTT_SPI_CGTSSM_CLK_CTRL_BASE_IDX                                                            1
9935 #define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG                                                            0x5010
9936 #define mmCGTS_SA0_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
9937 #define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG                                                            0x5011
9938 #define mmCGTS_SA0_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
9939 #define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG                                                             0x5012
9940 #define mmCGTS_SA0_WGP00_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
9941 #define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG                                                              0x5013
9942 #define mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
9943 #define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG                                                            0x5014
9944 #define mmCGTS_SA0_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
9945 #define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG                                                            0x5015
9946 #define mmCGTS_SA0_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
9947 #define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG                                                             0x5016
9948 #define mmCGTS_SA0_WGP00_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
9949 #define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG                                                              0x5017
9950 #define mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
9951 #define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG                                                            0x5018
9952 #define mmCGTS_SA0_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
9953 #define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG                                                            0x5019
9954 #define mmCGTS_SA0_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
9955 #define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG                                                             0x501a
9956 #define mmCGTS_SA0_WGP01_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
9957 #define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG                                                              0x501b
9958 #define mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
9959 #define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG                                                            0x501c
9960 #define mmCGTS_SA0_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
9961 #define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG                                                            0x501d
9962 #define mmCGTS_SA0_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
9963 #define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG                                                             0x501e
9964 #define mmCGTS_SA0_WGP01_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
9965 #define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG                                                              0x501f
9966 #define mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
9967 #define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG                                                            0x5020
9968 #define mmCGTS_SA0_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
9969 #define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG                                                            0x5021
9970 #define mmCGTS_SA0_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
9971 #define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG                                                             0x5022
9972 #define mmCGTS_SA0_WGP02_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
9973 #define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG                                                              0x5023
9974 #define mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
9975 #define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG                                                            0x5024
9976 #define mmCGTS_SA0_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
9977 #define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG                                                            0x5025
9978 #define mmCGTS_SA0_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
9979 #define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG                                                             0x5026
9980 #define mmCGTS_SA0_WGP02_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
9981 #define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG                                                              0x5027
9982 #define mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
9983 #define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG                                                            0x5028
9984 #define mmCGTS_SA0_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
9985 #define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG                                                            0x5029
9986 #define mmCGTS_SA0_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
9987 #define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG                                                             0x502a
9988 #define mmCGTS_SA0_WGP10_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
9989 #define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG                                                              0x502b
9990 #define mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
9991 #define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG                                                            0x502c
9992 #define mmCGTS_SA0_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
9993 #define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG                                                            0x502d
9994 #define mmCGTS_SA0_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
9995 #define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG                                                             0x502e
9996 #define mmCGTS_SA0_WGP10_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
9997 #define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG                                                              0x502f
9998 #define mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
9999 #define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG                                                            0x5030
10000 #define mmCGTS_SA0_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10001 #define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG                                                            0x5031
10002 #define mmCGTS_SA0_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10003 #define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG                                                             0x5032
10004 #define mmCGTS_SA0_WGP11_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10005 #define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG                                                              0x5033
10006 #define mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10007 #define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG                                                            0x5034
10008 #define mmCGTS_SA0_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10009 #define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG                                                            0x5035
10010 #define mmCGTS_SA0_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10011 #define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG                                                             0x5036
10012 #define mmCGTS_SA0_WGP11_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10013 #define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG                                                              0x5037
10014 #define mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10015 #define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG                                                            0x5038
10016 #define mmCGTS_SA1_WGP00_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10017 #define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG                                                            0x5039
10018 #define mmCGTS_SA1_WGP00_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10019 #define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG                                                             0x503a
10020 #define mmCGTS_SA1_WGP00_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10021 #define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG                                                              0x503b
10022 #define mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10023 #define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG                                                            0x503c
10024 #define mmCGTS_SA1_WGP00_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10025 #define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG                                                            0x503d
10026 #define mmCGTS_SA1_WGP00_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10027 #define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG                                                             0x503e
10028 #define mmCGTS_SA1_WGP00_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10029 #define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG                                                              0x503f
10030 #define mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10031 #define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG                                                            0x5040
10032 #define mmCGTS_SA1_WGP01_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10033 #define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG                                                            0x5041
10034 #define mmCGTS_SA1_WGP01_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10035 #define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG                                                             0x5042
10036 #define mmCGTS_SA1_WGP01_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10037 #define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG                                                              0x5043
10038 #define mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10039 #define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG                                                            0x5044
10040 #define mmCGTS_SA1_WGP01_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10041 #define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG                                                            0x5045
10042 #define mmCGTS_SA1_WGP01_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10043 #define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG                                                             0x5046
10044 #define mmCGTS_SA1_WGP01_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10045 #define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG                                                              0x5047
10046 #define mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10047 #define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG                                                            0x5048
10048 #define mmCGTS_SA1_WGP02_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10049 #define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG                                                            0x5049
10050 #define mmCGTS_SA1_WGP02_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10051 #define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG                                                             0x504a
10052 #define mmCGTS_SA1_WGP02_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10053 #define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG                                                              0x504b
10054 #define mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10055 #define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG                                                            0x504c
10056 #define mmCGTS_SA1_WGP02_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10057 #define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG                                                            0x504d
10058 #define mmCGTS_SA1_WGP02_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10059 #define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG                                                             0x504e
10060 #define mmCGTS_SA1_WGP02_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10061 #define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG                                                              0x504f
10062 #define mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10063 #define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG                                                            0x5050
10064 #define mmCGTS_SA1_WGP10_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10065 #define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG                                                            0x5051
10066 #define mmCGTS_SA1_WGP10_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10067 #define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG                                                             0x5052
10068 #define mmCGTS_SA1_WGP10_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10069 #define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG                                                              0x5053
10070 #define mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10071 #define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG                                                            0x5054
10072 #define mmCGTS_SA1_WGP10_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10073 #define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG                                                            0x5055
10074 #define mmCGTS_SA1_WGP10_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10075 #define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG                                                             0x5056
10076 #define mmCGTS_SA1_WGP10_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10077 #define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG                                                              0x5057
10078 #define mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10079 #define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG                                                            0x5058
10080 #define mmCGTS_SA1_WGP11_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10081 #define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG                                                            0x5059
10082 #define mmCGTS_SA1_WGP11_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10083 #define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG                                                             0x505a
10084 #define mmCGTS_SA1_WGP11_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10085 #define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG                                                              0x505b
10086 #define mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10087 #define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG                                                            0x505c
10088 #define mmCGTS_SA1_WGP11_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10089 #define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG                                                            0x505d
10090 #define mmCGTS_SA1_WGP11_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10091 #define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG                                                             0x505e
10092 #define mmCGTS_SA1_WGP11_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10093 #define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG                                                              0x505f
10094 #define mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10095 #define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG                                                            0x5060
10096 #define mmCGTS_SA0_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10097 #define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG                                                            0x5061
10098 #define mmCGTS_SA0_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10099 #define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG                                                             0x5062
10100 #define mmCGTS_SA0_WGP12_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10101 #define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG                                                              0x5063
10102 #define mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10103 #define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG                                                            0x5064
10104 #define mmCGTS_SA0_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10105 #define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG                                                            0x5065
10106 #define mmCGTS_SA0_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10107 #define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG                                                             0x5066
10108 #define mmCGTS_SA0_WGP12_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10109 #define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG                                                              0x5067
10110 #define mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10111 #define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG                                                            0x5068
10112 #define mmCGTS_SA1_WGP12_CU0_SIMD0_CTRL_REG_BASE_IDX                                                   1
10113 #define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG                                                            0x5069
10114 #define mmCGTS_SA1_WGP12_CU0_SIMD1_CTRL_REG_BASE_IDX                                                   1
10115 #define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG                                                             0x506a
10116 #define mmCGTS_SA1_WGP12_CU0_TATD_CTRL_REG_BASE_IDX                                                    1
10117 #define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG                                                              0x506b
10118 #define mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG_BASE_IDX                                                     1
10119 #define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG                                                            0x506c
10120 #define mmCGTS_SA1_WGP12_CU1_SIMD0_CTRL_REG_BASE_IDX                                                   1
10121 #define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG                                                            0x506d
10122 #define mmCGTS_SA1_WGP12_CU1_SIMD1_CTRL_REG_BASE_IDX                                                   1
10123 #define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG                                                             0x506e
10124 #define mmCGTS_SA1_WGP12_CU1_TATD_CTRL_REG_BASE_IDX                                                    1
10125 #define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG                                                              0x506f
10126 #define mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG_BASE_IDX                                                     1
10127 #define mmCGTT_SPI_PS_CLK_CTRL                                                                         0x507d
10128 #define mmCGTT_SPI_PS_CLK_CTRL_BASE_IDX                                                                1
10129 #define mmCGTT_SPIS_CLK_CTRL                                                                           0x507e
10130 #define mmCGTT_SPIS_CLK_CTRL_BASE_IDX                                                                  1
10131 #define mmCGTT_SPI_CLK_CTRL                                                                            0x5080
10132 #define mmCGTT_SPI_CLK_CTRL_BASE_IDX                                                                   1
10133 #define mmCGTT_PC_CLK_CTRL                                                                             0x5081
10134 #define mmCGTT_PC_CLK_CTRL_BASE_IDX                                                                    1
10135 #define mmCGTT_BCI_CLK_CTRL                                                                            0x5082
10136 #define mmCGTT_BCI_CLK_CTRL_BASE_IDX                                                                   1
10137 #define mmCGTT_VGT_CLK_CTRL                                                                            0x5084
10138 #define mmCGTT_VGT_CLK_CTRL_BASE_IDX                                                                   1
10139 #define mmCGTT_IA_CLK_CTRL                                                                             0x5085
10140 #define mmCGTT_IA_CLK_CTRL_BASE_IDX                                                                    1
10141 #define mmCGTT_WD_CLK_CTRL                                                                             0x5086
10142 #define mmCGTT_WD_CLK_CTRL_BASE_IDX                                                                    1
10143 #define mmCGTT_GS_NGG_CLK_CTRL                                                                         0x5087
10144 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX                                                                1
10145 #define mmCGTT_PA_CLK_CTRL                                                                             0x5088
10146 #define mmCGTT_PA_CLK_CTRL_BASE_IDX                                                                    1
10147 #define mmCGTT_SC_CLK_CTRL0                                                                            0x5089
10148 #define mmCGTT_SC_CLK_CTRL0_BASE_IDX                                                                   1
10149 #define mmCGTT_SC_CLK_CTRL1                                                                            0x508a
10150 #define mmCGTT_SC_CLK_CTRL1_BASE_IDX                                                                   1
10151 #define mmCGTT_SC_CLK_CTRL2                                                                            0x508b
10152 #define mmCGTT_SC_CLK_CTRL2_BASE_IDX                                                                   1
10153 #define mmCGTT_SQ_CLK_CTRL                                                                             0x508c
10154 #define mmCGTT_SQ_CLK_CTRL_BASE_IDX                                                                    1
10155 #define mmCGTT_SQG_CLK_CTRL                                                                            0x508d
10156 #define mmCGTT_SQG_CLK_CTRL_BASE_IDX                                                                   1
10157 #define mmSQ_ALU_CLK_CTRL                                                                              0x508e
10158 #define mmSQ_ALU_CLK_CTRL_BASE_IDX                                                                     1
10159 #define mmSQ_TEX_CLK_CTRL                                                                              0x508f
10160 #define mmSQ_TEX_CLK_CTRL_BASE_IDX                                                                     1
10161 #define mmSQ_LDS_CLK_CTRL                                                                              0x5090
10162 #define mmSQ_LDS_CLK_CTRL_BASE_IDX                                                                     1
10163 #define mmCGTT_SX_CLK_CTRL0                                                                            0x5094
10164 #define mmCGTT_SX_CLK_CTRL0_BASE_IDX                                                                   1
10165 #define mmCGTT_SX_CLK_CTRL1                                                                            0x5095
10166 #define mmCGTT_SX_CLK_CTRL1_BASE_IDX                                                                   1
10167 #define mmCGTT_SX_CLK_CTRL2                                                                            0x5096
10168 #define mmCGTT_SX_CLK_CTRL2_BASE_IDX                                                                   1
10169 #define mmCGTT_SX_CLK_CTRL3                                                                            0x5097
10170 #define mmCGTT_SX_CLK_CTRL3_BASE_IDX                                                                   1
10171 #define mmCGTT_SX_CLK_CTRL4                                                                            0x5098
10172 #define mmCGTT_SX_CLK_CTRL4_BASE_IDX                                                                   1
10173 #define mmTD_CGTT_CTRL                                                                                 0x509c
10174 #define mmTD_CGTT_CTRL_BASE_IDX                                                                        1
10175 #define mmTA_CGTT_CTRL                                                                                 0x509d
10176 #define mmTA_CGTT_CTRL_BASE_IDX                                                                        1
10177 #define mmCGTT_TCPI_CLK_CTRL                                                                           0x509e
10178 #define mmCGTT_TCPI_CLK_CTRL_BASE_IDX                                                                  1
10179 #define mmCGTT_TCI_CLK_CTRL                                                                            0x509f
10180 #define mmCGTT_TCI_CLK_CTRL_BASE_IDX                                                                   1
10181 #define mmCGTT_GDS_CLK_CTRL                                                                            0x50a0
10182 #define mmCGTT_GDS_CLK_CTRL_BASE_IDX                                                                   1
10183 #define mmDB_CGTT_CLK_CTRL_0                                                                           0x50a4
10184 #define mmDB_CGTT_CLK_CTRL_0_BASE_IDX                                                                  1
10185 #define mmCB_CGTT_SCLK_CTRL                                                                            0x50a8
10186 #define mmCB_CGTT_SCLK_CTRL_BASE_IDX                                                                   1
10187 #define mmGL2C_CGTT_SCLK_CTRL                                                                          0x50ac
10188 #define mmGL2C_CGTT_SCLK_CTRL_BASE_IDX                                                                 1
10189 #define mmGL2A_CGTT_SCLK_CTRL                                                                          0x50ad
10190 #define mmGL2A_CGTT_SCLK_CTRL_BASE_IDX                                                                 1
10191 #define mmGL2A_CGTT_SCLK_CTRL_1                                                                        0x50ae
10192 #define mmGL2A_CGTT_SCLK_CTRL_1_BASE_IDX                                                               1
10193 #define mmCGTT_CP_CLK_CTRL                                                                             0x50b0
10194 #define mmCGTT_CP_CLK_CTRL_BASE_IDX                                                                    1
10195 #define mmCGTT_CPF_CLK_CTRL                                                                            0x50b1
10196 #define mmCGTT_CPF_CLK_CTRL_BASE_IDX                                                                   1
10197 #define mmCGTT_CPC_CLK_CTRL                                                                            0x50b2
10198 #define mmCGTT_CPC_CLK_CTRL_BASE_IDX                                                                   1
10199 #define mmCGTT_RLC_CLK_CTRL                                                                            0x50b5
10200 #define mmCGTT_RLC_CLK_CTRL_BASE_IDX                                                                   1
10201 #define mmRLC_GFX_RM_CNTL                                                                              0x50b6
10202 #define mmRLC_GFX_RM_CNTL_BASE_IDX                                                                     1
10203 #define mmRMI_CGTT_SCLK_CTRL                                                                           0x50c0
10204 #define mmRMI_CGTT_SCLK_CTRL_BASE_IDX                                                                  1
10205 #define mmCGTT_TCPF_CLK_CTRL                                                                           0x50c1
10206 #define mmCGTT_TCPF_CLK_CTRL_BASE_IDX                                                                  1
10207 #define mmGCR_CGTT_SCLK_CTRL                                                                           0x50c2
10208 #define mmGCR_CGTT_SCLK_CTRL_BASE_IDX                                                                  1
10209 #define mmUTCL1_CGTT_CLK_CTRL                                                                          0x50c3
10210 #define mmUTCL1_CGTT_CLK_CTRL_BASE_IDX                                                                 1
10211 #define mmGCEA_CGTT_CLK_CTRL                                                                           0x50c4
10212 #define mmGCEA_CGTT_CLK_CTRL_BASE_IDX                                                                  1
10213 #define mmSE_CAC_CGTT_CLK_CTRL                                                                         0x50d0
10214 #define mmSE_CAC_CGTT_CLK_CTRL_BASE_IDX                                                                1
10215 #define mmGC_CAC_CGTT_CLK_CTRL                                                                         0x50d8
10216 #define mmGC_CAC_CGTT_CLK_CTRL_BASE_IDX                                                                1
10217 #define mmGRBM_CGTT_CLK_CNTL                                                                           0x50e0
10218 #define mmGRBM_CGTT_CLK_CNTL_BASE_IDX                                                                  1
10219 #define mmCGTT_GL1C_CLK_CTRL                                                                           0x50ec
10220 #define mmCGTT_GL1C_CLK_CTRL_BASE_IDX                                                                  1
10221 #define mmCGTT_CHC_CLK_CTRL                                                                            0x50ee
10222 #define mmCGTT_CHC_CLK_CTRL_BASE_IDX                                                                   1
10223 #define mmCGTT_CHCG_CLK_CTRL                                                                           0x50ef
10224 #define mmCGTT_CHCG_CLK_CTRL_BASE_IDX                                                                  1
10225 #define mmCGTT_GL1A_CLK_CTRL                                                                           0x50f0
10226 #define mmCGTT_GL1A_CLK_CTRL_BASE_IDX                                                                  1
10227 #define mmCGTT_CHA_CLK_CTRL                                                                            0x50f1
10228 #define mmCGTT_CHA_CLK_CTRL_BASE_IDX                                                                   1
10229 #define mmGUS_CGTT_CLK_CTRL                                                                            0x50f4
10230 #define mmGUS_CGTT_CLK_CTRL_BASE_IDX                                                                   1
10231 #define mmCGTT_PH_CLK_CTRL0                                                                            0x50f8
10232 #define mmCGTT_PH_CLK_CTRL0_BASE_IDX                                                                   1
10233 #define mmCGTT_PH_CLK_CTRL1                                                                            0x50f9
10234 #define mmCGTT_PH_CLK_CTRL1_BASE_IDX                                                                   1
10235 #define mmCGTT_PH_CLK_CTRL2                                                                            0x50fa
10236 #define mmCGTT_PH_CLK_CTRL2_BASE_IDX                                                                   1
10237 #define mmCGTT_PH_CLK_CTRL3                                                                            0x50fb
10238 #define mmCGTT_PH_CLK_CTRL3_BASE_IDX                                                                   1
10239 
10240 
10241 // addressBlock: gc_hypdec
10242 // base address: 0x3e000
10243 #define mmCP_PFP_UCODE_ADDR                                                                            0x5814
10244 #define mmCP_PFP_UCODE_ADDR_BASE_IDX                                                                   1
10245 #define mmCP_PFP_UCODE_DATA                                                                            0x5815
10246 #define mmCP_PFP_UCODE_DATA_BASE_IDX                                                                   1
10247 #define mmCP_ME_RAM_RADDR                                                                              0x5816
10248 #define mmCP_ME_RAM_RADDR_BASE_IDX                                                                     1
10249 #define mmCP_ME_RAM_WADDR                                                                              0x5816
10250 #define mmCP_ME_RAM_WADDR_BASE_IDX                                                                     1
10251 #define mmCP_ME_RAM_DATA                                                                               0x5817
10252 #define mmCP_ME_RAM_DATA_BASE_IDX                                                                      1
10253 #define mmCP_CE_UCODE_ADDR                                                                             0x5818
10254 #define mmCP_CE_UCODE_ADDR_BASE_IDX                                                                    1
10255 #define mmCP_CE_UCODE_DATA                                                                             0x5819
10256 #define mmCP_CE_UCODE_DATA_BASE_IDX                                                                    1
10257 #define mmCP_MEC_ME1_UCODE_ADDR                                                                        0x581a
10258 #define mmCP_MEC_ME1_UCODE_ADDR_BASE_IDX                                                               1
10259 #define mmCP_MEC_ME1_UCODE_DATA                                                                        0x581b
10260 #define mmCP_MEC_ME1_UCODE_DATA_BASE_IDX                                                               1
10261 #define mmCP_MEC_ME2_UCODE_ADDR                                                                        0x581c
10262 #define mmCP_MEC_ME2_UCODE_ADDR_BASE_IDX                                                               1
10263 #define mmCP_MEC_ME2_UCODE_DATA                                                                        0x581d
10264 #define mmCP_MEC_ME2_UCODE_DATA_BASE_IDX                                                               1
10265 #define mmCP_PFP_IC_BASE_LO                                                                            0x5840
10266 #define mmCP_PFP_IC_BASE_LO_BASE_IDX                                                                   1
10267 #define mmCP_PFP_IC_BASE_HI                                                                            0x5841
10268 #define mmCP_PFP_IC_BASE_HI_BASE_IDX                                                                   1
10269 #define mmCP_PFP_IC_BASE_CNTL                                                                          0x5842
10270 #define mmCP_PFP_IC_BASE_CNTL_BASE_IDX                                                                 1
10271 #define mmCP_PFP_IC_OP_CNTL                                                                            0x5843
10272 #define mmCP_PFP_IC_OP_CNTL_BASE_IDX                                                                   1
10273 #define mmCP_ME_IC_BASE_LO                                                                             0x5844
10274 #define mmCP_ME_IC_BASE_LO_BASE_IDX                                                                    1
10275 #define mmCP_ME_IC_BASE_HI                                                                             0x5845
10276 #define mmCP_ME_IC_BASE_HI_BASE_IDX                                                                    1
10277 #define mmCP_ME_IC_BASE_CNTL                                                                           0x5846
10278 #define mmCP_ME_IC_BASE_CNTL_BASE_IDX                                                                  1
10279 #define mmCP_ME_IC_OP_CNTL                                                                             0x5847
10280 #define mmCP_ME_IC_OP_CNTL_BASE_IDX                                                                    1
10281 #define mmCP_CE_IC_BASE_LO                                                                             0x5848
10282 #define mmCP_CE_IC_BASE_LO_BASE_IDX                                                                    1
10283 #define mmCP_CE_IC_BASE_HI                                                                             0x5849
10284 #define mmCP_CE_IC_BASE_HI_BASE_IDX                                                                    1
10285 #define mmCP_CE_IC_BASE_CNTL                                                                           0x584a
10286 #define mmCP_CE_IC_BASE_CNTL_BASE_IDX                                                                  1
10287 #define mmCP_CE_IC_OP_CNTL                                                                             0x584b
10288 #define mmCP_CE_IC_OP_CNTL_BASE_IDX                                                                    1
10289 #define mmCP_CPC_IC_BASE_LO                                                                            0x584c
10290 #define mmCP_CPC_IC_BASE_LO_BASE_IDX                                                                   1
10291 #define mmCP_CPC_IC_BASE_HI                                                                            0x584d
10292 #define mmCP_CPC_IC_BASE_HI_BASE_IDX                                                                   1
10293 #define mmCP_CPC_IC_BASE_CNTL                                                                          0x584e
10294 #define mmCP_CPC_IC_BASE_CNTL_BASE_IDX                                                                 1
10295 #define mmCP_CPC_IC_OP_CNTL                                                                            0x584f
10296 #define mmCP_CPC_IC_OP_CNTL_BASE_IDX                                                                   1
10297 #define mmCP_MES_IC_BASE_LO                                                                            0x5850
10298 #define mmCP_MES_IC_BASE_LO_BASE_IDX                                                                   1
10299 #define mmCP_MES_MIBASE_LO                                                                             0x5850
10300 #define mmCP_MES_MIBASE_LO_BASE_IDX                                                                    1
10301 #define mmCP_MES_IC_BASE_HI                                                                            0x5851
10302 #define mmCP_MES_IC_BASE_HI_BASE_IDX                                                                   1
10303 #define mmCP_MES_MIBASE_HI                                                                             0x5851
10304 #define mmCP_MES_MIBASE_HI_BASE_IDX                                                                    1
10305 #define mmCP_MES_IC_BASE_CNTL                                                                          0x5852
10306 #define mmCP_MES_IC_BASE_CNTL_BASE_IDX                                                                 1
10307 #define mmCP_MES_IC_OP_CNTL                                                                            0x5853
10308 #define mmCP_MES_IC_OP_CNTL_BASE_IDX                                                                   1
10309 #define mmCP_MES_DC_BASE_LO                                                                            0x5854
10310 #define mmCP_MES_DC_BASE_LO_BASE_IDX                                                                   1
10311 #define mmCP_MES_MDBASE_LO                                                                             0x5854
10312 #define mmCP_MES_MDBASE_LO_BASE_IDX                                                                    1
10313 #define mmCP_MES_DC_BASE_HI                                                                            0x5855
10314 #define mmCP_MES_DC_BASE_HI_BASE_IDX                                                                   1
10315 #define mmCP_MES_MDBASE_HI                                                                             0x5855
10316 #define mmCP_MES_MDBASE_HI_BASE_IDX                                                                    1
10317 #define mmCP_MES_LOCAL_BASE0_LO                                                                        0x5856
10318 #define mmCP_MES_LOCAL_BASE0_LO_BASE_IDX                                                               1
10319 #define mmCP_MES_LOCAL_BASE0_HI                                                                        0x5857
10320 #define mmCP_MES_LOCAL_BASE0_HI_BASE_IDX                                                               1
10321 #define mmCP_MES_LOCAL_MASK0_LO                                                                        0x5858
10322 #define mmCP_MES_LOCAL_MASK0_LO_BASE_IDX                                                               1
10323 #define mmCP_MES_LOCAL_MASK0_HI                                                                        0x5859
10324 #define mmCP_MES_LOCAL_MASK0_HI_BASE_IDX                                                               1
10325 #define mmCP_MES_LOCAL_APERTURE                                                                        0x585a
10326 #define mmCP_MES_LOCAL_APERTURE_BASE_IDX                                                               1
10327 #define mmCP_MES_MIBOUND_LO                                                                            0x585b
10328 #define mmCP_MES_MIBOUND_LO_BASE_IDX                                                                   1
10329 #define mmCP_MES_MIBOUND_HI                                                                            0x585c
10330 #define mmCP_MES_MIBOUND_HI_BASE_IDX                                                                   1
10331 #define mmCP_MES_MDBOUND_LO                                                                            0x585d
10332 #define mmCP_MES_MDBOUND_LO_BASE_IDX                                                                   1
10333 #define mmCP_MES_MDBOUND_HI                                                                            0x585e
10334 #define mmCP_MES_MDBOUND_HI_BASE_IDX                                                                   1
10335 #define mmGFX_PIPE_PRIORITY                                                                            0x587f
10336 #define mmGFX_PIPE_PRIORITY_BASE_IDX                                                                   1
10337 #define mmGRBM_GFX_INDEX_SR_SELECT                                                                     0x5a00
10338 #define mmGRBM_GFX_INDEX_SR_SELECT_BASE_IDX                                                            1
10339 #define mmGRBM_GFX_INDEX_SR_DATA                                                                       0x5a01
10340 #define mmGRBM_GFX_INDEX_SR_DATA_BASE_IDX                                                              1
10341 #define mmGRBM_GFX_CNTL_SR_SELECT                                                                      0x5a02
10342 #define mmGRBM_GFX_CNTL_SR_SELECT_BASE_IDX                                                             1
10343 #define mmGRBM_GFX_CNTL_SR_DATA                                                                        0x5a03
10344 #define mmGRBM_GFX_CNTL_SR_DATA_BASE_IDX                                                               1
10345 #define mmGRBM_CAM_INDEX                                                                               0x5a04
10346 #define mmGRBM_CAM_INDEX_BASE_IDX                                                                      1
10347 #define mmGRBM_HYP_CAM_INDEX                                                                           0x5a04
10348 #define mmGRBM_HYP_CAM_INDEX_BASE_IDX                                                                  1
10349 #define mmGRBM_CAM_DATA                                                                                0x5a05
10350 #define mmGRBM_CAM_DATA_BASE_IDX                                                                       1
10351 #define mmGRBM_HYP_CAM_DATA                                                                            0x5a05
10352 #define mmGRBM_HYP_CAM_DATA_BASE_IDX                                                                   1
10353 #define mmGRBM_CAM_DATA_UPPER                                                                          0x5a06
10354 #define mmGRBM_CAM_DATA_UPPER_BASE_IDX                                                                 1
10355 #define mmGRBM_HYP_CAM_DATA_UPPER                                                                      0x5a06
10356 #define mmGRBM_HYP_CAM_DATA_UPPER_BASE_IDX                                                             1
10357 #define mmGC_IH_COOKIE_0_PTR                                                                           0x5a07
10358 #define mmGC_IH_COOKIE_0_PTR_BASE_IDX                                                                  1
10359 #define mmRLC_GPU_IOV_VF_ENABLE                                                                        0x5b00
10360 #define mmRLC_GPU_IOV_VF_ENABLE_BASE_IDX                                                               1
10361 #define mmRLC_GPU_IOV_CFG_REG6                                                                         0x5b06
10362 #define mmRLC_GPU_IOV_CFG_REG6_BASE_IDX                                                                1
10363 #define mmRLC_GPU_IOV_CFG_REG8                                                                         0x5b20
10364 #define mmRLC_GPU_IOV_CFG_REG8_BASE_IDX                                                                1
10365 #define mmRLC_RLCV_TIMER_INT_0                                                                         0x5b25
10366 #define mmRLC_RLCV_TIMER_INT_0_BASE_IDX                                                                1
10367 #define mmRLC_RLCV_TIMER_CTRL                                                                          0x5b26
10368 #define mmRLC_RLCV_TIMER_CTRL_BASE_IDX                                                                 1
10369 #define mmRLC_RLCV_TIMER_STAT                                                                          0x5b27
10370 #define mmRLC_RLCV_TIMER_STAT_BASE_IDX                                                                 1
10371 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS                                                               0x5b2a
10372 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX                                                      1
10373 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET                                                           0x5b2b
10374 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX                                                  1
10375 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR                                                           0x5b2c
10376 #define mmRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX                                                  1
10377 #define mmRLC_GPU_IOV_VF_MASK                                                                          0x5b2d
10378 #define mmRLC_GPU_IOV_VF_MASK_BASE_IDX                                                                 1
10379 #define mmRLC_HYP_SEMAPHORE_0                                                                          0x5b2e
10380 #define mmRLC_HYP_SEMAPHORE_0_BASE_IDX                                                                 1
10381 #define mmRLC_HYP_SEMAPHORE_1                                                                          0x5b2f
10382 #define mmRLC_HYP_SEMAPHORE_1_BASE_IDX                                                                 1
10383 #define mmRLC_BUSY_CLK_CNTL                                                                            0x5b30
10384 #define mmRLC_BUSY_CLK_CNTL_BASE_IDX                                                                   1
10385 #define mmRLC_CLK_CNTL                                                                                 0x5b31
10386 #define mmRLC_CLK_CNTL_BASE_IDX                                                                        1
10387 #define mmRLC_PACE_TIMER_STAT                                                                          0x5b33
10388 #define mmRLC_PACE_TIMER_STAT_BASE_IDX                                                                 1
10389 #define mmRLC_GPU_IOV_SCH_BLOCK                                                                        0x5b34
10390 #define mmRLC_GPU_IOV_SCH_BLOCK_BASE_IDX                                                               1
10391 #define mmRLC_GPU_IOV_CFG_REG1                                                                         0x5b35
10392 #define mmRLC_GPU_IOV_CFG_REG1_BASE_IDX                                                                1
10393 #define mmRLC_GPU_IOV_CFG_REG2                                                                         0x5b36
10394 #define mmRLC_GPU_IOV_CFG_REG2_BASE_IDX                                                                1
10395 #define mmRLC_GPU_IOV_VM_BUSY_STATUS                                                                   0x5b37
10396 #define mmRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX                                                          1
10397 #define mmRLC_GPU_IOV_SCH_0                                                                            0x5b38
10398 #define mmRLC_GPU_IOV_SCH_0_BASE_IDX                                                                   1
10399 #define mmRLC_GPU_IOV_ACTIVE_FCN_ID                                                                    0x5b39
10400 #define mmRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX                                                           1
10401 #define mmRLC_GPU_IOV_SCH_3                                                                            0x5b3a
10402 #define mmRLC_GPU_IOV_SCH_3_BASE_IDX                                                                   1
10403 #define mmRLC_GPU_IOV_SCH_1                                                                            0x5b3b
10404 #define mmRLC_GPU_IOV_SCH_1_BASE_IDX                                                                   1
10405 #define mmRLC_GPU_IOV_SCH_2                                                                            0x5b3c
10406 #define mmRLC_GPU_IOV_SCH_2_BASE_IDX                                                                   1
10407 #define mmRLC_PACE_INT_FORCE                                                                           0x5b3d
10408 #define mmRLC_PACE_INT_FORCE_BASE_IDX                                                                  1
10409 #define mmRLC_GPU_IOV_INT_STAT                                                                         0x5b3f
10410 #define mmRLC_GPU_IOV_INT_STAT_BASE_IDX                                                                1
10411 #define mmRLC_RLCV_TIMER_INT_1                                                                         0x5b40
10412 #define mmRLC_RLCV_TIMER_INT_1_BASE_IDX                                                                1
10413 #define mmRLC_IH_COOKIE                                                                                0x5b41
10414 #define mmRLC_IH_COOKIE_BASE_IDX                                                                       1
10415 #define mmRLC_IH_COOKIE_CNTL                                                                           0x5b42
10416 #define mmRLC_IH_COOKIE_CNTL_BASE_IDX                                                                  1
10417 #define mmRLC_HYP_RLCG_UCODE_CHKSUM                                                                    0x5b43
10418 #define mmRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX                                                           1
10419 #define mmRLC_HYP_RLCP_UCODE_CHKSUM                                                                    0x5b44
10420 #define mmRLC_HYP_RLCP_UCODE_CHKSUM_BASE_IDX                                                           1
10421 #define mmRLC_HYP_RLCV_UCODE_CHKSUM                                                                    0x5b45
10422 #define mmRLC_HYP_RLCV_UCODE_CHKSUM_BASE_IDX                                                           1
10423 #define mmRLC_GPU_IOV_F32_CNTL                                                                         0x5b46
10424 #define mmRLC_GPU_IOV_F32_CNTL_BASE_IDX                                                                1
10425 #define mmRLC_GPU_IOV_F32_RESET                                                                        0x5b47
10426 #define mmRLC_GPU_IOV_F32_RESET_BASE_IDX                                                               1
10427 #define mmRLC_GPU_IOV_SDMA0_STATUS                                                                     0x5b48
10428 #define mmRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX                                                            1
10429 #define mmRLC_GPU_IOV_SDMA1_STATUS                                                                     0x5b49
10430 #define mmRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX                                                            1
10431 #define mmRLC_GPU_IOV_SMU_RESPONSE                                                                     0x5b4a
10432 #define mmRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX                                                            1
10433 #define mmRLC_GPU_IOV_VIRT_RESET_REQ                                                                   0x5b4c
10434 #define mmRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX                                                          1
10435 #define mmRLC_GPU_IOV_RLC_RESPONSE                                                                     0x5b4d
10436 #define mmRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX                                                            1
10437 #define mmRLC_GPU_IOV_INT_DISABLE                                                                      0x5b4e
10438 #define mmRLC_GPU_IOV_INT_DISABLE_BASE_IDX                                                             1
10439 #define mmRLC_GPU_IOV_INT_FORCE                                                                        0x5b4f
10440 #define mmRLC_GPU_IOV_INT_FORCE_BASE_IDX                                                               1
10441 #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS                                                                0x5b50
10442 #define mmRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX                                                       1
10443 #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS                                                                0x5b51
10444 #define mmRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX                                                       1
10445 #define mmRLC_HYP_SEMAPHORE_2                                                                          0x5b52
10446 #define mmRLC_HYP_SEMAPHORE_2_BASE_IDX                                                                 1
10447 #define mmRLC_HYP_SEMAPHORE_3                                                                          0x5b53
10448 #define mmRLC_HYP_SEMAPHORE_3_BASE_IDX                                                                 1
10449 #define mmRLC_HYP_RESET_VECTOR                                                                         0x5b54
10450 #define mmRLC_HYP_RESET_VECTOR_BASE_IDX                                                                1
10451 #define mmRLC_HYP_BOOTLOAD_SIZE                                                                        0x5b5c
10452 #define mmRLC_HYP_BOOTLOAD_SIZE_BASE_IDX                                                               1
10453 #define mmRLC_HYP_BOOTLOAD_ADDR_LO                                                                     0x5b5d
10454 #define mmRLC_HYP_BOOTLOAD_ADDR_LO_BASE_IDX                                                            1
10455 #define mmRLC_HYP_BOOTLOAD_ADDR_HI                                                                     0x5b5e
10456 #define mmRLC_HYP_BOOTLOAD_ADDR_HI_BASE_IDX                                                            1
10457 #define mmRLC_GPM_IRAM_ADDR                                                                            0x5b5f
10458 #define mmRLC_GPM_IRAM_ADDR_BASE_IDX                                                                   1
10459 #define mmRLC_GPM_IRAM_DATA                                                                            0x5b60
10460 #define mmRLC_GPM_IRAM_DATA_BASE_IDX                                                                   1
10461 #define mmRLC_GPM_UCODE_ADDR                                                                           0x5b61
10462 #define mmRLC_GPM_UCODE_ADDR_BASE_IDX                                                                  1
10463 #define mmRLC_GPM_UCODE_DATA                                                                           0x5b62
10464 #define mmRLC_GPM_UCODE_DATA_BASE_IDX                                                                  1
10465 #define mmRLC_PACE_UCODE_ADDR                                                                          0x5b63
10466 #define mmRLC_PACE_UCODE_ADDR_BASE_IDX                                                                 1
10467 #define mmRLC_PACE_UCODE_DATA                                                                          0x5b64
10468 #define mmRLC_PACE_UCODE_DATA_BASE_IDX                                                                 1
10469 #define mmRLC_GPU_IOV_UCODE_ADDR                                                                       0x5b65
10470 #define mmRLC_GPU_IOV_UCODE_ADDR_BASE_IDX                                                              1
10471 #define mmRLC_GPU_IOV_UCODE_DATA                                                                       0x5b66
10472 #define mmRLC_GPU_IOV_UCODE_DATA_BASE_IDX                                                              1
10473 #define mmRLC_GPU_IOV_SCRATCH_ADDR                                                                     0x5b67
10474 #define mmRLC_GPU_IOV_SCRATCH_ADDR_BASE_IDX                                                            1
10475 #define mmRLC_GPU_IOV_SCRATCH_DATA                                                                     0x5b68
10476 #define mmRLC_GPU_IOV_SCRATCH_DATA_BASE_IDX                                                            1
10477 #define mmRLC_RLCV_IRAM_ADDR                                                                           0x5b69
10478 #define mmRLC_RLCV_IRAM_ADDR_BASE_IDX                                                                  1
10479 #define mmRLC_RLCV_IRAM_DATA                                                                           0x5b6a
10480 #define mmRLC_RLCV_IRAM_DATA_BASE_IDX                                                                  1
10481 #define mmRLC_RLCP_IRAM_ADDR                                                                           0x5b6b
10482 #define mmRLC_RLCP_IRAM_ADDR_BASE_IDX                                                                  1
10483 #define mmRLC_RLCP_IRAM_DATA                                                                           0x5b6c
10484 #define mmRLC_RLCP_IRAM_DATA_BASE_IDX                                                                  1
10485 #define mmRLC_SRM_DRAM_ADDR                                                                            0x5b71
10486 #define mmRLC_SRM_DRAM_ADDR_BASE_IDX                                                                   1
10487 #define mmRLC_SRM_DRAM_DATA                                                                            0x5b72
10488 #define mmRLC_SRM_DRAM_DATA_BASE_IDX                                                                   1
10489 #define mmRLC_SRM_ARAM_ADDR                                                                            0x5b73
10490 #define mmRLC_SRM_ARAM_ADDR_BASE_IDX                                                                   1
10491 #define mmRLC_SRM_ARAM_DATA                                                                            0x5b74
10492 #define mmRLC_SRM_ARAM_DATA_BASE_IDX                                                                   1
10493 #define mmRLC_GPM_SCRATCH_ADDR                                                                         0x5b75
10494 #define mmRLC_GPM_SCRATCH_ADDR_BASE_IDX                                                                1
10495 #define mmRLC_GPM_SCRATCH_DATA                                                                         0x5b76
10496 #define mmRLC_GPM_SCRATCH_DATA_BASE_IDX                                                                1
10497 #define mmRLC_GTS_OFFSET_LSB                                                                           0x5b79
10498 #define mmRLC_GTS_OFFSET_LSB_BASE_IDX                                                                  1
10499 #define mmRLC_GTS_OFFSET_MSB                                                                           0x5b7a
10500 #define mmRLC_GTS_OFFSET_MSB_BASE_IDX                                                                  1
10501 
10502 
10503 // addressBlock: gc_sdma0_sdma0hypdec
10504 // base address: 0x3e200
10505 #define mmSDMA0_UCODE_ADDR                                                                             0x5880
10506 #define mmSDMA0_UCODE_ADDR_BASE_IDX                                                                    1
10507 #define mmSDMA0_UCODE_DATA                                                                             0x5881
10508 #define mmSDMA0_UCODE_DATA_BASE_IDX                                                                    1
10509 #define mmSDMA0_VM_CTX_LO                                                                              0x5882
10510 #define mmSDMA0_VM_CTX_LO_BASE_IDX                                                                     1
10511 #define mmSDMA0_VM_CTX_HI                                                                              0x5883
10512 #define mmSDMA0_VM_CTX_HI_BASE_IDX                                                                     1
10513 #define mmSDMA0_ACTIVE_FCN_ID                                                                          0x5884
10514 #define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10515 #define mmSDMA0_VM_CTX_CNTL                                                                            0x5885
10516 #define mmSDMA0_VM_CTX_CNTL_BASE_IDX                                                                   1
10517 #define mmSDMA0_VIRT_RESET_REQ                                                                         0x5886
10518 #define mmSDMA0_VIRT_RESET_REQ_BASE_IDX                                                                1
10519 #define mmSDMA0_VF_ENABLE                                                                              0x5887
10520 #define mmSDMA0_VF_ENABLE_BASE_IDX                                                                     1
10521 #define mmSDMA0_CONTEXT_REG_TYPE0                                                                      0x5888
10522 #define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10523 #define mmSDMA0_CONTEXT_REG_TYPE1                                                                      0x5889
10524 #define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10525 #define mmSDMA0_CONTEXT_REG_TYPE2                                                                      0x588a
10526 #define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10527 #define mmSDMA0_CONTEXT_REG_TYPE3                                                                      0x588b
10528 #define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10529 #define mmSDMA0_VM_CNTL                                                                                0x5893
10530 #define mmSDMA0_VM_CNTL_BASE_IDX                                                                       1
10531 
10532 
10533 // addressBlock: gc_sdma1_sdma1hypdec
10534 // base address: 0x3e280
10535 #define mmSDMA1_UCODE_ADDR                                                                             0x58a0
10536 #define mmSDMA1_UCODE_ADDR_BASE_IDX                                                                    1
10537 #define mmSDMA1_UCODE_DATA                                                                             0x58a1
10538 #define mmSDMA1_UCODE_DATA_BASE_IDX                                                                    1
10539 #define mmSDMA1_VM_CTX_LO                                                                              0x58a2
10540 #define mmSDMA1_VM_CTX_LO_BASE_IDX                                                                     1
10541 #define mmSDMA1_VM_CTX_HI                                                                              0x58a3
10542 #define mmSDMA1_VM_CTX_HI_BASE_IDX                                                                     1
10543 #define mmSDMA1_ACTIVE_FCN_ID                                                                          0x58a4
10544 #define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX                                                                 1
10545 #define mmSDMA1_VM_CTX_CNTL                                                                            0x58a5
10546 #define mmSDMA1_VM_CTX_CNTL_BASE_IDX                                                                   1
10547 #define mmSDMA1_VIRT_RESET_REQ                                                                         0x58a6
10548 #define mmSDMA1_VIRT_RESET_REQ_BASE_IDX                                                                1
10549 #define mmSDMA1_VF_ENABLE                                                                              0x58a7
10550 #define mmSDMA1_VF_ENABLE_BASE_IDX                                                                     1
10551 #define mmSDMA1_CONTEXT_REG_TYPE0                                                                      0x58a8
10552 #define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX                                                             1
10553 #define mmSDMA1_CONTEXT_REG_TYPE1                                                                      0x58a9
10554 #define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX                                                             1
10555 #define mmSDMA1_CONTEXT_REG_TYPE2                                                                      0x58aa
10556 #define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX                                                             1
10557 #define mmSDMA1_CONTEXT_REG_TYPE3                                                                      0x58ab
10558 #define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX                                                             1
10559 #define mmSDMA1_VM_CNTL                                                                                0x58b3
10560 #define mmSDMA1_VM_CNTL_BASE_IDX                                                                       1
10561 
10562 
10563 // addressBlock: gc_gcvmsharedhvdec
10564 // base address: 0x3ea00
10565 #define mmGCMC_VM_FB_SIZE_OFFSET_VF0                                                                   0x5a80
10566 #define mmGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX                                                          1
10567 #define mmGCMC_VM_FB_SIZE_OFFSET_VF1                                                                   0x5a81
10568 #define mmGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX                                                          1
10569 #define mmGCMC_VM_FB_SIZE_OFFSET_VF2                                                                   0x5a82
10570 #define mmGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX                                                          1
10571 #define mmGCMC_VM_FB_SIZE_OFFSET_VF3                                                                   0x5a83
10572 #define mmGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX                                                          1
10573 #define mmGCMC_VM_FB_SIZE_OFFSET_VF4                                                                   0x5a84
10574 #define mmGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX                                                          1
10575 #define mmGCMC_VM_FB_SIZE_OFFSET_VF5                                                                   0x5a85
10576 #define mmGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX                                                          1
10577 #define mmGCMC_VM_FB_SIZE_OFFSET_VF6                                                                   0x5a86
10578 #define mmGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX                                                          1
10579 #define mmGCMC_VM_FB_SIZE_OFFSET_VF7                                                                   0x5a87
10580 #define mmGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX                                                          1
10581 #define mmGCMC_VM_FB_SIZE_OFFSET_VF8                                                                   0x5a88
10582 #define mmGCMC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX                                                          1
10583 #define mmGCMC_VM_FB_SIZE_OFFSET_VF9                                                                   0x5a89
10584 #define mmGCMC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX                                                          1
10585 #define mmGCMC_VM_FB_SIZE_OFFSET_VF10                                                                  0x5a8a
10586 #define mmGCMC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX                                                         1
10587 #define mmGCMC_VM_FB_SIZE_OFFSET_VF11                                                                  0x5a8b
10588 #define mmGCMC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX                                                         1
10589 #define mmGCMC_VM_FB_SIZE_OFFSET_VF12                                                                  0x5a8c
10590 #define mmGCMC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX                                                         1
10591 #define mmGCMC_VM_FB_SIZE_OFFSET_VF13                                                                  0x5a8d
10592 #define mmGCMC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX                                                         1
10593 #define mmGCMC_VM_FB_SIZE_OFFSET_VF14                                                                  0x5a8e
10594 #define mmGCMC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX                                                         1
10595 #define mmGCMC_VM_FB_SIZE_OFFSET_VF15                                                                  0x5a8f
10596 #define mmGCMC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX                                                         1
10597 #define mmGCMC_VM_FB_SIZE_OFFSET_VF16                                                                  0x5a90
10598 #define mmGCMC_VM_FB_SIZE_OFFSET_VF16_BASE_IDX                                                         1
10599 #define mmGCMC_VM_FB_SIZE_OFFSET_VF17                                                                  0x5a91
10600 #define mmGCMC_VM_FB_SIZE_OFFSET_VF17_BASE_IDX                                                         1
10601 #define mmGCMC_VM_FB_SIZE_OFFSET_VF18                                                                  0x5a92
10602 #define mmGCMC_VM_FB_SIZE_OFFSET_VF18_BASE_IDX                                                         1
10603 #define mmGCMC_VM_FB_SIZE_OFFSET_VF19                                                                  0x5a93
10604 #define mmGCMC_VM_FB_SIZE_OFFSET_VF19_BASE_IDX                                                         1
10605 #define mmGCMC_VM_FB_SIZE_OFFSET_VF20                                                                  0x5a94
10606 #define mmGCMC_VM_FB_SIZE_OFFSET_VF20_BASE_IDX                                                         1
10607 #define mmGCMC_VM_FB_SIZE_OFFSET_VF21                                                                  0x5a95
10608 #define mmGCMC_VM_FB_SIZE_OFFSET_VF21_BASE_IDX                                                         1
10609 #define mmGCMC_VM_FB_SIZE_OFFSET_VF22                                                                  0x5a96
10610 #define mmGCMC_VM_FB_SIZE_OFFSET_VF22_BASE_IDX                                                         1
10611 #define mmGCMC_VM_FB_SIZE_OFFSET_VF23                                                                  0x5a97
10612 #define mmGCMC_VM_FB_SIZE_OFFSET_VF23_BASE_IDX                                                         1
10613 #define mmGCMC_VM_FB_SIZE_OFFSET_VF24                                                                  0x5a98
10614 #define mmGCMC_VM_FB_SIZE_OFFSET_VF24_BASE_IDX                                                         1
10615 #define mmGCMC_VM_FB_SIZE_OFFSET_VF25                                                                  0x5a99
10616 #define mmGCMC_VM_FB_SIZE_OFFSET_VF25_BASE_IDX                                                         1
10617 #define mmGCMC_VM_FB_SIZE_OFFSET_VF26                                                                  0x5a9a
10618 #define mmGCMC_VM_FB_SIZE_OFFSET_VF26_BASE_IDX                                                         1
10619 #define mmGCMC_VM_FB_SIZE_OFFSET_VF27                                                                  0x5a9b
10620 #define mmGCMC_VM_FB_SIZE_OFFSET_VF27_BASE_IDX                                                         1
10621 #define mmGCMC_VM_FB_SIZE_OFFSET_VF28                                                                  0x5a9c
10622 #define mmGCMC_VM_FB_SIZE_OFFSET_VF28_BASE_IDX                                                         1
10623 #define mmGCMC_VM_FB_SIZE_OFFSET_VF29                                                                  0x5a9d
10624 #define mmGCMC_VM_FB_SIZE_OFFSET_VF29_BASE_IDX                                                         1
10625 #define mmGCMC_VM_FB_SIZE_OFFSET_VF30                                                                  0x5a9e
10626 #define mmGCMC_VM_FB_SIZE_OFFSET_VF30_BASE_IDX                                                         1
10627 #define mmGCMC_VM_FB_SIZE_OFFSET_VF31                                                                  0x5a9f
10628 #define mmGCMC_VM_FB_SIZE_OFFSET_VF31_BASE_IDX                                                         1
10629 #define mmGCVM_IOMMU_MMIO_CNTRL_1                                                                      0x5aa0
10630 #define mmGCVM_IOMMU_MMIO_CNTRL_1_BASE_IDX                                                             1
10631 #define mmGCMC_VM_MARC_BASE_LO_0                                                                       0x5aa1
10632 #define mmGCMC_VM_MARC_BASE_LO_0_BASE_IDX                                                              1
10633 #define mmGCMC_VM_MARC_BASE_LO_1                                                                       0x5aa2
10634 #define mmGCMC_VM_MARC_BASE_LO_1_BASE_IDX                                                              1
10635 #define mmGCMC_VM_MARC_BASE_LO_2                                                                       0x5aa3
10636 #define mmGCMC_VM_MARC_BASE_LO_2_BASE_IDX                                                              1
10637 #define mmGCMC_VM_MARC_BASE_LO_3                                                                       0x5aa4
10638 #define mmGCMC_VM_MARC_BASE_LO_3_BASE_IDX                                                              1
10639 #define mmGCMC_VM_MARC_BASE_HI_0                                                                       0x5aa5
10640 #define mmGCMC_VM_MARC_BASE_HI_0_BASE_IDX                                                              1
10641 #define mmGCMC_VM_MARC_BASE_HI_1                                                                       0x5aa6
10642 #define mmGCMC_VM_MARC_BASE_HI_1_BASE_IDX                                                              1
10643 #define mmGCMC_VM_MARC_BASE_HI_2                                                                       0x5aa7
10644 #define mmGCMC_VM_MARC_BASE_HI_2_BASE_IDX                                                              1
10645 #define mmGCMC_VM_MARC_BASE_HI_3                                                                       0x5aa8
10646 #define mmGCMC_VM_MARC_BASE_HI_3_BASE_IDX                                                              1
10647 #define mmGCMC_VM_MARC_RELOC_LO_0                                                                      0x5aa9
10648 #define mmGCMC_VM_MARC_RELOC_LO_0_BASE_IDX                                                             1
10649 #define mmGCMC_VM_MARC_RELOC_LO_1                                                                      0x5aaa
10650 #define mmGCMC_VM_MARC_RELOC_LO_1_BASE_IDX                                                             1
10651 #define mmGCMC_VM_MARC_RELOC_LO_2                                                                      0x5aab
10652 #define mmGCMC_VM_MARC_RELOC_LO_2_BASE_IDX                                                             1
10653 #define mmGCMC_VM_MARC_RELOC_LO_3                                                                      0x5aac
10654 #define mmGCMC_VM_MARC_RELOC_LO_3_BASE_IDX                                                             1
10655 #define mmGCMC_VM_MARC_RELOC_HI_0                                                                      0x5aad
10656 #define mmGCMC_VM_MARC_RELOC_HI_0_BASE_IDX                                                             1
10657 #define mmGCMC_VM_MARC_RELOC_HI_1                                                                      0x5aae
10658 #define mmGCMC_VM_MARC_RELOC_HI_1_BASE_IDX                                                             1
10659 #define mmGCMC_VM_MARC_RELOC_HI_2                                                                      0x5aaf
10660 #define mmGCMC_VM_MARC_RELOC_HI_2_BASE_IDX                                                             1
10661 #define mmGCMC_VM_MARC_RELOC_HI_3                                                                      0x5ab0
10662 #define mmGCMC_VM_MARC_RELOC_HI_3_BASE_IDX                                                             1
10663 #define mmGCMC_VM_MARC_LEN_LO_0                                                                        0x5ab1
10664 #define mmGCMC_VM_MARC_LEN_LO_0_BASE_IDX                                                               1
10665 #define mmGCMC_VM_MARC_LEN_LO_1                                                                        0x5ab2
10666 #define mmGCMC_VM_MARC_LEN_LO_1_BASE_IDX                                                               1
10667 #define mmGCMC_VM_MARC_LEN_LO_2                                                                        0x5ab3
10668 #define mmGCMC_VM_MARC_LEN_LO_2_BASE_IDX                                                               1
10669 #define mmGCMC_VM_MARC_LEN_LO_3                                                                        0x5ab4
10670 #define mmGCMC_VM_MARC_LEN_LO_3_BASE_IDX                                                               1
10671 #define mmGCMC_VM_MARC_LEN_HI_0                                                                        0x5ab5
10672 #define mmGCMC_VM_MARC_LEN_HI_0_BASE_IDX                                                               1
10673 #define mmGCMC_VM_MARC_LEN_HI_1                                                                        0x5ab6
10674 #define mmGCMC_VM_MARC_LEN_HI_1_BASE_IDX                                                               1
10675 #define mmGCMC_VM_MARC_LEN_HI_2                                                                        0x5ab7
10676 #define mmGCMC_VM_MARC_LEN_HI_2_BASE_IDX                                                               1
10677 #define mmGCMC_VM_MARC_LEN_HI_3                                                                        0x5ab8
10678 #define mmGCMC_VM_MARC_LEN_HI_3_BASE_IDX                                                               1
10679 #define mmGCVM_IOMMU_CONTROL_REGISTER                                                                  0x5ab9
10680 #define mmGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX                                                         1
10681 #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER                                         0x5aba
10682 #define mmGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX                                1
10683 #define mmGCVM_PCIE_ATS_CNTL                                                                           0x5abb
10684 #define mmGCVM_PCIE_ATS_CNTL_BASE_IDX                                                                  1
10685 #define mmGCVM_PCIE_ATS_CNTL_VF_0                                                                      0x5abc
10686 #define mmGCVM_PCIE_ATS_CNTL_VF_0_BASE_IDX                                                             1
10687 #define mmGCVM_PCIE_ATS_CNTL_VF_1                                                                      0x5abd
10688 #define mmGCVM_PCIE_ATS_CNTL_VF_1_BASE_IDX                                                             1
10689 #define mmGCVM_PCIE_ATS_CNTL_VF_2                                                                      0x5abe
10690 #define mmGCVM_PCIE_ATS_CNTL_VF_2_BASE_IDX                                                             1
10691 #define mmGCVM_PCIE_ATS_CNTL_VF_3                                                                      0x5abf
10692 #define mmGCVM_PCIE_ATS_CNTL_VF_3_BASE_IDX                                                             1
10693 #define mmGCVM_PCIE_ATS_CNTL_VF_4                                                                      0x5ac0
10694 #define mmGCVM_PCIE_ATS_CNTL_VF_4_BASE_IDX                                                             1
10695 #define mmGCVM_PCIE_ATS_CNTL_VF_5                                                                      0x5ac1
10696 #define mmGCVM_PCIE_ATS_CNTL_VF_5_BASE_IDX                                                             1
10697 #define mmGCVM_PCIE_ATS_CNTL_VF_6                                                                      0x5ac2
10698 #define mmGCVM_PCIE_ATS_CNTL_VF_6_BASE_IDX                                                             1
10699 #define mmGCVM_PCIE_ATS_CNTL_VF_7                                                                      0x5ac3
10700 #define mmGCVM_PCIE_ATS_CNTL_VF_7_BASE_IDX                                                             1
10701 #define mmGCVM_PCIE_ATS_CNTL_VF_8                                                                      0x5ac4
10702 #define mmGCVM_PCIE_ATS_CNTL_VF_8_BASE_IDX                                                             1
10703 #define mmGCVM_PCIE_ATS_CNTL_VF_9                                                                      0x5ac5
10704 #define mmGCVM_PCIE_ATS_CNTL_VF_9_BASE_IDX                                                             1
10705 #define mmGCVM_PCIE_ATS_CNTL_VF_10                                                                     0x5ac6
10706 #define mmGCVM_PCIE_ATS_CNTL_VF_10_BASE_IDX                                                            1
10707 #define mmGCVM_PCIE_ATS_CNTL_VF_11                                                                     0x5ac7
10708 #define mmGCVM_PCIE_ATS_CNTL_VF_11_BASE_IDX                                                            1
10709 #define mmGCVM_PCIE_ATS_CNTL_VF_12                                                                     0x5ac8
10710 #define mmGCVM_PCIE_ATS_CNTL_VF_12_BASE_IDX                                                            1
10711 #define mmGCVM_PCIE_ATS_CNTL_VF_13                                                                     0x5ac9
10712 #define mmGCVM_PCIE_ATS_CNTL_VF_13_BASE_IDX                                                            1
10713 #define mmGCVM_PCIE_ATS_CNTL_VF_14                                                                     0x5aca
10714 #define mmGCVM_PCIE_ATS_CNTL_VF_14_BASE_IDX                                                            1
10715 #define mmGCVM_PCIE_ATS_CNTL_VF_15                                                                     0x5acb
10716 #define mmGCVM_PCIE_ATS_CNTL_VF_15_BASE_IDX                                                            1
10717 #define mmGCVM_PCIE_ATS_CNTL_VF_16                                                                     0x5acc
10718 #define mmGCVM_PCIE_ATS_CNTL_VF_16_BASE_IDX                                                            1
10719 #define mmGCVM_PCIE_ATS_CNTL_VF_17                                                                     0x5acd
10720 #define mmGCVM_PCIE_ATS_CNTL_VF_17_BASE_IDX                                                            1
10721 #define mmGCVM_PCIE_ATS_CNTL_VF_18                                                                     0x5ace
10722 #define mmGCVM_PCIE_ATS_CNTL_VF_18_BASE_IDX                                                            1
10723 #define mmGCVM_PCIE_ATS_CNTL_VF_19                                                                     0x5acf
10724 #define mmGCVM_PCIE_ATS_CNTL_VF_19_BASE_IDX                                                            1
10725 #define mmGCVM_PCIE_ATS_CNTL_VF_20                                                                     0x5ad0
10726 #define mmGCVM_PCIE_ATS_CNTL_VF_20_BASE_IDX                                                            1
10727 #define mmGCVM_PCIE_ATS_CNTL_VF_21                                                                     0x5ad1
10728 #define mmGCVM_PCIE_ATS_CNTL_VF_21_BASE_IDX                                                            1
10729 #define mmGCVM_PCIE_ATS_CNTL_VF_22                                                                     0x5ad2
10730 #define mmGCVM_PCIE_ATS_CNTL_VF_22_BASE_IDX                                                            1
10731 #define mmGCVM_PCIE_ATS_CNTL_VF_23                                                                     0x5ad3
10732 #define mmGCVM_PCIE_ATS_CNTL_VF_23_BASE_IDX                                                            1
10733 #define mmGCVM_PCIE_ATS_CNTL_VF_24                                                                     0x5ad4
10734 #define mmGCVM_PCIE_ATS_CNTL_VF_24_BASE_IDX                                                            1
10735 #define mmGCVM_PCIE_ATS_CNTL_VF_25                                                                     0x5ad5
10736 #define mmGCVM_PCIE_ATS_CNTL_VF_25_BASE_IDX                                                            1
10737 #define mmGCVM_PCIE_ATS_CNTL_VF_26                                                                     0x5ad6
10738 #define mmGCVM_PCIE_ATS_CNTL_VF_26_BASE_IDX                                                            1
10739 #define mmGCVM_PCIE_ATS_CNTL_VF_27                                                                     0x5ad7
10740 #define mmGCVM_PCIE_ATS_CNTL_VF_27_BASE_IDX                                                            1
10741 #define mmGCVM_PCIE_ATS_CNTL_VF_28                                                                     0x5ad8
10742 #define mmGCVM_PCIE_ATS_CNTL_VF_28_BASE_IDX                                                            1
10743 #define mmGCVM_PCIE_ATS_CNTL_VF_29                                                                     0x5ad9
10744 #define mmGCVM_PCIE_ATS_CNTL_VF_29_BASE_IDX                                                            1
10745 #define mmGCVM_PCIE_ATS_CNTL_VF_30                                                                     0x5ada
10746 #define mmGCVM_PCIE_ATS_CNTL_VF_30_BASE_IDX                                                            1
10747 #define mmGCVM_PCIE_ATS_CNTL_VF_31                                                                     0x5adb
10748 #define mmGCVM_PCIE_ATS_CNTL_VF_31_BASE_IDX                                                            1
10749 #define mmGCUTCL2_CGTT_CLK_CTRL                                                                        0x5adc
10750 #define mmGCUTCL2_CGTT_CLK_CTRL_BASE_IDX                                                               1
10751 #define mmGCMC_SHARED_ACTIVE_FCN_ID                                                                    0x5add
10752 #define mmGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX                                                           1
10753 
10754 
10755 // addressBlock: gccacind
10756 // base address: 0x0
10757 #define ixPCC_STALL_PATTERN_CTRL                                                                       0x0000
10758 #define ixPWRBRK_STALL_PATTERN_CTRL                                                                    0x0001
10759 #define ixPCC_STALL_PATTERN_1_2                                                                        0x0006
10760 #define ixPCC_STALL_PATTERN_3_4                                                                        0x0007
10761 #define ixPCC_STALL_PATTERN_5_6                                                                        0x0008
10762 #define ixPCC_STALL_PATTERN_7                                                                          0x0009
10763 #define ixPWRBRK_STALL_PATTERN_1_2                                                                     0x000a
10764 #define ixPWRBRK_STALL_PATTERN_3_4                                                                     0x000b
10765 #define ixPWRBRK_STALL_PATTERN_5_6                                                                     0x000c
10766 #define ixPWRBRK_STALL_PATTERN_7                                                                       0x000d
10767 #define ixGC_CAC_ID                                                                                    0x0010
10768 #define ixGC_CAC_CNTL                                                                                  0x0011
10769 #define ixGC_CAC_OVR_SEL                                                                               0x0012
10770 #define ixGC_CAC_OVR_VAL                                                                               0x0013
10771 #define ixGC_CAC_WEIGHT_BCI_0                                                                          0x0014
10772 #define ixGC_CAC_WEIGHT_CB_0                                                                           0x0015
10773 #define ixGC_CAC_WEIGHT_CB_1                                                                           0x0016
10774 #define ixGC_CAC_WEIGHT_CBR_0                                                                          0x0017
10775 #define ixGC_CAC_WEIGHT_CBR_1                                                                          0x0018
10776 #define ixGC_CAC_WEIGHT_CP_0                                                                           0x0019
10777 #define ixGC_CAC_WEIGHT_CP_1                                                                           0x001a
10778 #define ixGC_CAC_WEIGHT_DB_0                                                                           0x001b
10779 #define ixGC_CAC_WEIGHT_DB_1                                                                           0x001c
10780 #define ixGC_CAC_WEIGHT_DBR_0                                                                          0x001d
10781 #define ixGC_CAC_WEIGHT_DBR_1                                                                          0x001e
10782 #define ixGC_CAC_WEIGHT_GDS_0                                                                          0x001f
10783 #define ixGC_CAC_WEIGHT_GDS_1                                                                          0x0020
10784 #define ixGC_CAC_WEIGHT_LDS_0                                                                          0x0021
10785 #define ixGC_CAC_WEIGHT_LDS_1                                                                          0x0022
10786 #define ixGC_CAC_WEIGHT_PA_0                                                                           0x0023
10787 #define ixGC_CAC_WEIGHT_PC_0                                                                           0x0024
10788 #define ixGC_CAC_WEIGHT_SC_0                                                                           0x0025
10789 #define ixGC_CAC_WEIGHT_SPI_0                                                                          0x0026
10790 #define ixGC_CAC_WEIGHT_SPI_1                                                                          0x0027
10791 #define ixGC_CAC_WEIGHT_SPI_2                                                                          0x0028
10792 #define ixGC_CAC_WEIGHT_SQ_0                                                                           0x0029
10793 #define ixGC_CAC_WEIGHT_SQ_1                                                                           0x002a
10794 #define ixGC_CAC_WEIGHT_SQ_2                                                                           0x002b
10795 #define ixGC_CAC_WEIGHT_SX_0                                                                           0x002e
10796 #define ixGC_CAC_WEIGHT_SXRB_0                                                                         0x002f
10797 #define ixGC_CAC_WEIGHT_TA_0                                                                           0x0030
10798 #define ixGC_CAC_WEIGHT_TCP_0                                                                          0x0031
10799 #define ixGC_CAC_WEIGHT_TCP_1                                                                          0x0032
10800 #define ixGC_CAC_WEIGHT_TCP_2                                                                          0x0033
10801 #define ixGC_CAC_WEIGHT_TD_0                                                                           0x0034
10802 #define ixGC_CAC_WEIGHT_TD_1                                                                           0x0035
10803 #define ixGC_CAC_WEIGHT_TD_2                                                                           0x0036
10804 #define ixGC_CAC_WEIGHT_TD_3                                                                           0x0037
10805 #define ixGC_CAC_WEIGHT_TD_4                                                                           0x0038
10806 #define ixGC_CAC_WEIGHT_RMI_0                                                                          0x0039
10807 #define ixGC_CAC_WEIGHT_EA_0                                                                           0x003a
10808 #define ixGC_CAC_WEIGHT_EA_1                                                                           0x003b
10809 #define ixGC_CAC_WEIGHT_EA_2                                                                           0x003c
10810 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_0                                                                  0x003d
10811 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_1                                                                  0x003e
10812 #define ixGC_CAC_WEIGHT_UTCL2_ATCL2_2                                                                  0x003f
10813 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_0                                                                 0x0040
10814 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_1                                                                 0x0041
10815 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_2                                                                 0x0042
10816 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_3                                                                 0x0043
10817 #define ixGC_CAC_WEIGHT_UTCL2_ROUTER_4                                                                 0x0044
10818 #define ixGC_CAC_WEIGHT_UTCL2_VML2_0                                                                   0x0045
10819 #define ixGC_CAC_WEIGHT_UTCL2_VML2_1                                                                   0x0046
10820 #define ixGC_CAC_WEIGHT_UTCL2_VML2_2                                                                   0x0047
10821 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_0                                                                 0x0048
10822 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_1                                                                 0x0049
10823 #define ixGC_CAC_WEIGHT_UTCL2_WALKER_2                                                                 0x004a
10824 #define ixGC_CAC_WEIGHT_CU_0                                                                           0x004b
10825 #define ixGC_CAC_WEIGHT_UTCL1_0                                                                        0x004d
10826 #define ixGC_CAC_WEIGHT_GE_0                                                                           0x004f
10827 #define ixGC_CAC_WEIGHT_PMM_0                                                                          0x0050
10828 #define ixGC_CAC_WEIGHT_GL2C_0                                                                         0x0051
10829 #define ixGC_CAC_WEIGHT_GL2C_1                                                                         0x0052
10830 #define ixGC_CAC_WEIGHT_GL2C_2                                                                         0x0053
10831 #define ixGC_CAC_WEIGHT_GUS_0                                                                          0x0054
10832 #define ixGC_CAC_WEIGHT_GUS_1                                                                          0x0055
10833 #define ixGC_CAC_WEIGHT_PH_0                                                                           0x0056
10834 #define ixGC_CAC_ACC_BCI0                                                                              0x0070
10835 #define ixGC_CAC_ACC_BCI1                                                                              0x0071
10836 #define ixGC_CAC_ACC_CB0                                                                               0x0072
10837 #define ixGC_CAC_ACC_CB1                                                                               0x0073
10838 #define ixGC_CAC_ACC_CB2                                                                               0x0074
10839 #define ixGC_CAC_ACC_CB3                                                                               0x0075
10840 #define ixGC_CAC_ACC_CBR0                                                                              0x0076
10841 #define ixGC_CAC_ACC_CBR1                                                                              0x0077
10842 #define ixGC_CAC_ACC_CBR2                                                                              0x0078
10843 #define ixGC_CAC_ACC_CBR3                                                                              0x0079
10844 #define ixGC_CAC_ACC_CP0                                                                               0x007a
10845 #define ixGC_CAC_ACC_CP1                                                                               0x007b
10846 #define ixGC_CAC_ACC_CP2                                                                               0x007c
10847 #define ixGC_CAC_ACC_DB0                                                                               0x007d
10848 #define ixGC_CAC_ACC_DB1                                                                               0x007e
10849 #define ixGC_CAC_ACC_DB2                                                                               0x007f
10850 #define ixGC_CAC_ACC_DB3                                                                               0x0080
10851 #define ixGC_CAC_ACC_DBR0                                                                              0x0081
10852 #define ixGC_CAC_ACC_DBR1                                                                              0x0082
10853 #define ixGC_CAC_ACC_DBR2                                                                              0x0083
10854 #define ixGC_CAC_ACC_DBR3                                                                              0x0084
10855 #define ixGC_CAC_ACC_GDS0                                                                              0x0085
10856 #define ixGC_CAC_ACC_GDS1                                                                              0x0086
10857 #define ixGC_CAC_ACC_GDS2                                                                              0x0087
10858 #define ixGC_CAC_ACC_GDS3                                                                              0x0088
10859 #define ixGC_CAC_ACC_LDS0                                                                              0x0089
10860 #define ixGC_CAC_ACC_LDS1                                                                              0x008a
10861 #define ixGC_CAC_ACC_LDS2                                                                              0x008b
10862 #define ixGC_CAC_ACC_LDS3                                                                              0x008c
10863 #define ixGC_CAC_ACC_PA0                                                                               0x008d
10864 #define ixGC_CAC_ACC_PA1                                                                               0x008e
10865 #define ixGC_CAC_ACC_PC0                                                                               0x008f
10866 #define ixGC_CAC_ACC_SC0                                                                               0x0090
10867 #define ixGC_CAC_ACC_SPI0                                                                              0x0091
10868 #define ixGC_CAC_ACC_SPI1                                                                              0x0092
10869 #define ixGC_CAC_ACC_SPI2                                                                              0x0093
10870 #define ixGC_CAC_ACC_SPI3                                                                              0x0094
10871 #define ixGC_CAC_ACC_SPI4                                                                              0x0095
10872 #define ixGC_CAC_ACC_SPI5                                                                              0x0096
10873 #define ixGC_CAC_ACC_SQ0_LOWER                                                                         0x0097
10874 #define ixGC_CAC_ACC_SQ0_UPPER                                                                         0x0098
10875 #define ixGC_CAC_ACC_SQ1_LOWER                                                                         0x0099
10876 #define ixGC_CAC_ACC_SQ1_UPPER                                                                         0x009a
10877 #define ixGC_CAC_ACC_SQ2_LOWER                                                                         0x009b
10878 #define ixGC_CAC_ACC_SQ2_UPPER                                                                         0x009c
10879 #define ixGC_CAC_ACC_SQ3_LOWER                                                                         0x009d
10880 #define ixGC_CAC_ACC_SQ3_UPPER                                                                         0x009e
10881 #define ixGC_CAC_ACC_SQ4_LOWER                                                                         0x009f
10882 #define ixGC_CAC_ACC_SQ4_UPPER                                                                         0x00a0
10883 #define ixGC_CAC_ACC_SQ5_LOWER                                                                         0x00a1
10884 #define ixGC_CAC_ACC_SQ5_UPPER                                                                         0x00a2
10885 #define ixGC_CAC_ACC_SQ6_LOWER                                                                         0x00a3
10886 #define ixGC_CAC_ACC_SQ6_UPPER                                                                         0x00a4
10887 #define ixGC_CAC_ACC_SQ7_LOWER                                                                         0x00a5
10888 #define ixGC_CAC_ACC_SQ7_UPPER                                                                         0x00a6
10889 #define ixGC_CAC_ACC_SQ8_LOWER                                                                         0x00a7
10890 #define ixGC_CAC_ACC_SQ8_UPPER                                                                         0x00a8
10891 #define ixGC_CAC_ACC_SX0                                                                               0x00a9
10892 #define ixGC_CAC_ACC_SXRB0                                                                             0x00aa
10893 #define ixGC_CAC_ACC_TA0                                                                               0x00ab
10894 #define ixGC_CAC_ACC_TCP0                                                                              0x00ac
10895 #define ixGC_CAC_ACC_TCP1                                                                              0x00ad
10896 #define ixGC_CAC_ACC_TCP2                                                                              0x00ae
10897 #define ixGC_CAC_ACC_TCP3                                                                              0x00af
10898 #define ixGC_CAC_ACC_TCP4                                                                              0x00b0
10899 #define ixGC_CAC_ACC_TD0                                                                               0x00b1
10900 #define ixGC_CAC_ACC_TD1                                                                               0x00b2
10901 #define ixGC_CAC_ACC_TD2                                                                               0x00b3
10902 #define ixGC_CAC_ACC_TD3                                                                               0x00b4
10903 #define ixGC_CAC_ACC_TD4                                                                               0x00b5
10904 #define ixGC_CAC_ACC_TD5                                                                               0x00b6
10905 #define ixGC_CAC_ACC_TD6                                                                               0x00b7
10906 #define ixGC_CAC_ACC_TD7                                                                               0x00b8
10907 #define ixGC_CAC_ACC_TD8                                                                               0x00b9
10908 #define ixGC_CAC_ACC_TD9                                                                               0x00ba
10909 #define ixGC_CAC_ACC_RMI0                                                                              0x00bb
10910 #define ixGC_CAC_ACC_EA0                                                                               0x00bc
10911 #define ixGC_CAC_ACC_EA1                                                                               0x00bd
10912 #define ixGC_CAC_ACC_EA2                                                                               0x00be
10913 #define ixGC_CAC_ACC_EA3                                                                               0x00bf
10914 #define ixGC_CAC_ACC_EA4                                                                               0x00c0
10915 #define ixGC_CAC_ACC_EA5                                                                               0x00c1
10916 #define ixGC_CAC_ACC_UTCL2_ATCL20                                                                      0x00c2
10917 #define ixGC_CAC_ACC_UTCL2_ATCL21                                                                      0x00c3
10918 #define ixGC_CAC_ACC_UTCL2_ATCL22                                                                      0x00c4
10919 #define ixGC_CAC_ACC_UTCL2_ATCL23                                                                      0x00c5
10920 #define ixGC_CAC_ACC_UTCL2_ATCL24                                                                      0x00c6
10921 #define ixGC_CAC_ACC_UTCL2_ROUTER0                                                                     0x00c7
10922 #define ixGC_CAC_ACC_UTCL2_ROUTER1                                                                     0x00c8
10923 #define ixGC_CAC_ACC_UTCL2_ROUTER2                                                                     0x00c9
10924 #define ixGC_CAC_ACC_UTCL2_ROUTER3                                                                     0x00ca
10925 #define ixGC_CAC_ACC_UTCL2_ROUTER4                                                                     0x00cb
10926 #define ixGC_CAC_ACC_UTCL2_ROUTER5                                                                     0x00cc
10927 #define ixGC_CAC_ACC_UTCL2_ROUTER6                                                                     0x00cd
10928 #define ixGC_CAC_ACC_UTCL2_ROUTER7                                                                     0x00ce
10929 #define ixGC_CAC_ACC_UTCL2_ROUTER8                                                                     0x00cf
10930 #define ixGC_CAC_ACC_UTCL2_ROUTER9                                                                     0x00d0
10931 #define ixGC_CAC_ACC_UTCL2_VML20                                                                       0x00d1
10932 #define ixGC_CAC_ACC_UTCL2_VML21                                                                       0x00d2
10933 #define ixGC_CAC_ACC_UTCL2_VML22                                                                       0x00d3
10934 #define ixGC_CAC_ACC_UTCL2_VML23                                                                       0x00d4
10935 #define ixGC_CAC_ACC_UTCL2_VML24                                                                       0x00d5
10936 #define ixGC_CAC_ACC_UTCL2_WALKER0                                                                     0x00d6
10937 #define ixGC_CAC_ACC_UTCL2_WALKER1                                                                     0x00d7
10938 #define ixGC_CAC_ACC_UTCL2_WALKER2                                                                     0x00d8
10939 #define ixGC_CAC_ACC_UTCL2_WALKER3                                                                     0x00d9
10940 #define ixGC_CAC_ACC_UTCL2_WALKER4                                                                     0x00da
10941 #define ixGC_CAC_ACC_CU0                                                                               0x00db
10942 #define ixGC_CAC_ACC_UTCL10                                                                            0x00dd
10943 #define ixGC_CAC_ACC_CH0                                                                               0x00de
10944 #define ixGC_CAC_ACC_GE0                                                                               0x00df
10945 #define ixGC_CAC_ACC_PMM0                                                                              0x00e0
10946 #define ixGC_CAC_ACC_GL2C0                                                                             0x00e1
10947 #define ixGC_CAC_ACC_GL2C1                                                                             0x00e2
10948 #define ixGC_CAC_ACC_GL2C2                                                                             0x00e3
10949 #define ixGC_CAC_ACC_GL2C3                                                                             0x00e4
10950 #define ixGC_CAC_ACC_GL2C4                                                                             0x00e5
10951 #define ixGC_CAC_ACC_GUS0                                                                              0x00e6
10952 #define ixGC_CAC_ACC_GUS1                                                                              0x00e7
10953 #define ixGC_CAC_ACC_GUS2                                                                              0x00e8
10954 #define ixGC_CAC_ACC_PH0                                                                               0x00e9
10955 #define ixGC_CAC_OVRD_BCI                                                                              0x0130
10956 #define ixGC_CAC_OVRD_CB                                                                               0x0131
10957 #define ixGC_CAC_OVRD_CBR                                                                              0x0132
10958 #define ixGC_CAC_OVRD_CP                                                                               0x0133
10959 #define ixGC_CAC_OVRD_DB                                                                               0x0134
10960 #define ixGC_CAC_OVRD_DBR                                                                              0x0135
10961 #define ixGC_CAC_OVRD_GDS                                                                              0x0136
10962 #define ixGC_CAC_OVRD_LDS                                                                              0x0137
10963 #define ixGC_CAC_OVRD_PA                                                                               0x0138
10964 #define ixGC_CAC_OVRD_PC                                                                               0x0139
10965 #define ixGC_CAC_OVRD_SC                                                                               0x013a
10966 #define ixGC_CAC_OVRD_SPI                                                                              0x013b
10967 #define ixGC_CAC_OVRD_CU                                                                               0x013c
10968 #define ixGC_CAC_OVRD_SQ                                                                               0x013d
10969 #define ixGC_CAC_OVRD_SX                                                                               0x013e
10970 #define ixGC_CAC_OVRD_SXRB                                                                             0x013f
10971 #define ixGC_CAC_OVRD_TA                                                                               0x0140
10972 #define ixGC_CAC_OVRD_TCP                                                                              0x0141
10973 #define ixGC_CAC_OVRD_TD                                                                               0x0142
10974 #define ixGC_CAC_OVRD_RMI                                                                              0x0143
10975 #define ixGC_CAC_OVRD_EA                                                                               0x0144
10976 #define ixGC_CAC_OVRD_UTCL2_ATCL2                                                                      0x0145
10977 #define ixGC_CAC_OVRD_UTCL2_ROUTER                                                                     0x0146
10978 #define ixGC_CAC_OVRD_UTCL2_VML2                                                                       0x0147
10979 #define ixGC_CAC_OVRD_UTCL2_WALKER                                                                     0x0148
10980 #define ixGC_CAC_OVRD_UTCL1                                                                            0x014a
10981 #define ixGC_CAC_OVRD_GE                                                                               0x014c
10982 #define ixGC_CAC_OVRD_PMM                                                                              0x014d
10983 #define ixGC_CAC_OVRD_GL2C                                                                             0x014e
10984 #define ixGC_CAC_OVRD_GUS                                                                              0x014f
10985 #define ixGC_CAC_OVRD_PH                                                                               0x0153
10986 #define ixRELEASE_TO_STALL_LUT_1_8                                                                     0x0154
10987 #define ixRELEASE_TO_STALL_LUT_9_16                                                                    0x0155
10988 #define ixRELEASE_TO_STALL_LUT_17_20                                                                   0x0156
10989 #define ixSTALL_TO_RELEASE_LUT_1_4                                                                     0x0157
10990 #define ixSTALL_TO_RELEASE_LUT_5_7                                                                     0x0158
10991 #define ixSTALL_TO_PWRBRK_LUT_1_4                                                                      0x0159
10992 #define ixSTALL_TO_PWRBRK_LUT_5_7                                                                      0x015a
10993 #define ixPWRBRK_STALL_TO_RELEASE_LUT_1_4                                                              0x015b
10994 #define ixPWRBRK_STALL_TO_RELEASE_LUT_5_7                                                              0x015c
10995 #define ixPWRBRK_RELEASE_TO_STALL_LUT_1_8                                                              0x015d
10996 #define ixPWRBRK_RELEASE_TO_STALL_LUT_9_16                                                             0x015e
10997 #define ixPWRBRK_RELEASE_TO_STALL_LUT_17_20                                                            0x015f
10998 #define ixFIXED_PATTERN_PERF_COUNTER_1                                                                 0x0160
10999 #define ixFIXED_PATTERN_PERF_COUNTER_2                                                                 0x0161
11000 #define ixFIXED_PATTERN_PERF_COUNTER_3                                                                 0x0162
11001 #define ixFIXED_PATTERN_PERF_COUNTER_4                                                                 0x0163
11002 #define ixFIXED_PATTERN_PERF_COUNTER_5                                                                 0x0164
11003 #define ixFIXED_PATTERN_PERF_COUNTER_6                                                                 0x0165
11004 #define ixFIXED_PATTERN_PERF_COUNTER_7                                                                 0x0166
11005 #define ixFIXED_PATTERN_PERF_COUNTER_8                                                                 0x0167
11006 #define ixFIXED_PATTERN_PERF_COUNTER_9                                                                 0x0168
11007 #define ixFIXED_PATTERN_PERF_COUNTER_10                                                                0x0169
11008 #define ixHW_LUT_UPDATE_STATUS                                                                         0x016a
11009 
11010 
11011 // addressBlock: secacind
11012 // base address: 0x0
11013 #define ixSE_CAC_ID                                                                                    0x0000
11014 #define ixSE_CAC_CNTL                                                                                  0x0001
11015 #define ixSE_CAC_OVR_SEL                                                                               0x0002
11016 #define ixSE_CAC_OVR_VAL                                                                               0x0003
11017 
11018 
11019 // addressBlock: spmglbind
11020 // base address: 0x0
11021 #define ixGLB_CPG_SAMPLEDELAY                                                                          0x0000
11022 #define ixGLB_CPC_SAMPLEDELAY                                                                          0x0001
11023 #define ixGLB_CPF_SAMPLEDELAY                                                                          0x0002
11024 #define ixGLB_GDS_SAMPLEDELAY                                                                          0x0003
11025 #define ixGLB_GCR_SAMPLEDELAY                                                                          0x0004
11026 #define ixGLB_PH_SAMPLEDELAY                                                                           0x0005
11027 #define ixGLB_GE_SAMPLEDELAY                                                                           0x0006
11028 #define ixGLB_GUS_SAMPLEDELAY                                                                          0x0007
11029 #define ixGLB_CHA_SAMPLEDELAY                                                                          0x0008
11030 #define ixGLB_CHCG_SAMPLEDELAY                                                                         0x0009
11031 #define ixGLB_ATCL2_SAMPLEDELAY                                                                        0x000a
11032 #define ixGLB_VML2_SAMPLEDELAY                                                                         0x000b
11033 #define ixGLB_SDMA0_SAMPLEDELAY                                                                        0x000c
11034 #define ixGLB_SDMA1_SAMPLEDELAY                                                                        0x000d
11035 #define ixGLB_GL2A0_SAMPLEDELAY                                                                        0x000e
11036 #define ixGLB_GL2A1_SAMPLEDELAY                                                                        0x000f
11037 #define ixGLB_GL2A2_SAMPLEDELAY                                                                        0x0010
11038 #define ixGLB_GL2A3_SAMPLEDELAY                                                                        0x0011
11039 #define ixGLB_GL2C0_SAMPLEDELAY                                                                        0x0012
11040 #define ixGLB_GL2C1_SAMPLEDELAY                                                                        0x0013
11041 #define ixGLB_GL2C2_SAMPLEDELAY                                                                        0x0014
11042 #define ixGLB_GL2C3_SAMPLEDELAY                                                                        0x0015
11043 #define ixGLB_GL2C4_SAMPLEDELAY                                                                        0x0016
11044 #define ixGLB_GL2C5_SAMPLEDELAY                                                                        0x0017
11045 #define ixGLB_GL2C6_SAMPLEDELAY                                                                        0x0018
11046 #define ixGLB_GL2C7_SAMPLEDELAY                                                                        0x0019
11047 #define ixGLB_GL2C8_SAMPLEDELAY                                                                        0x001a
11048 #define ixGLB_GL2C9_SAMPLEDELAY                                                                        0x001b
11049 #define ixGLB_GL2C10_SAMPLEDELAY                                                                       0x001c
11050 #define ixGLB_GL2C11_SAMPLEDELAY                                                                       0x001d
11051 #define ixGLB_GL2C12_SAMPLEDELAY                                                                       0x001e
11052 #define ixGLB_GL2C13_SAMPLEDELAY                                                                       0x001f
11053 #define ixGLB_GL2C14_SAMPLEDELAY                                                                       0x0020
11054 #define ixGLB_GL2C15_SAMPLEDELAY                                                                       0x0021
11055 #define ixGLB_EA0_SAMPLEDELAY                                                                          0x0022
11056 #define ixGLB_EA1_SAMPLEDELAY                                                                          0x0023
11057 #define ixGLB_EA2_SAMPLEDELAY                                                                          0x0024
11058 #define ixGLB_EA3_SAMPLEDELAY                                                                          0x0025
11059 #define ixGLB_EA4_SAMPLEDELAY                                                                          0x0026
11060 #define ixGLB_EA5_SAMPLEDELAY                                                                          0x0027
11061 #define ixGLB_EA6_SAMPLEDELAY                                                                          0x0028
11062 #define ixGLB_EA7_SAMPLEDELAY                                                                          0x0029
11063 #define ixGLB_EA8_SAMPLEDELAY                                                                          0x002a
11064 #define ixGLB_EA9_SAMPLEDELAY                                                                          0x002b
11065 #define ixGLB_EA10_SAMPLEDELAY                                                                         0x002c
11066 #define ixGLB_EA11_SAMPLEDELAY                                                                         0x002d
11067 #define ixGLB_EA12_SAMPLEDELAY                                                                         0x002e
11068 #define ixGLB_EA13_SAMPLEDELAY                                                                         0x002f
11069 #define ixGLB_EA14_SAMPLEDELAY                                                                         0x0030
11070 #define ixGLB_EA15_SAMPLEDELAY                                                                         0x0031
11071 #define ixGLB_CHC0_SAMPLEDELAY                                                                         0x0032
11072 #define ixGLB_CHC1_SAMPLEDELAY                                                                         0x0033
11073 #define ixGLB_CHC2_SAMPLEDELAY                                                                         0x0034
11074 #define ixGLB_CHC3_SAMPLEDELAY                                                                         0x0035
11075 
11076 
11077 // addressBlock: spmind
11078 // base address: 0x0
11079 #define ixSE_SPI_SAMPLEDELAY                                                                           0x0000
11080 #define ixSE_SQG_SAMPLEDELAY                                                                           0x0001
11081 #define ixSE_CBR_SAMPLEDELAY                                                                           0x0002
11082 #define ixSE_DBR_SAMPLEDELAY                                                                           0x0003
11083 #define ixSE_SA0SX_SAMPLEDELAY                                                                         0x0004
11084 #define ixSE_SA0PA_SAMPLEDELAY                                                                         0x0005
11085 #define ixSE_SA0GL1A_SAMPLEDELAY                                                                       0x0006
11086 #define ixSE_SA0GL1CG_SAMPLEDELAY                                                                      0x0007
11087 #define ixSE_SA0CB0_SAMPLEDELAY                                                                        0x0008
11088 #define ixSE_SA0CB1_SAMPLEDELAY                                                                        0x0009
11089 #define ixSE_SA0CB2_SAMPLEDELAY                                                                        0x000a
11090 #define ixSE_SA0CB3_SAMPLEDELAY                                                                        0x000b
11091 #define ixSE_SA0DB0_SAMPLEDELAY                                                                        0x000c
11092 #define ixSE_SA0DB1_SAMPLEDELAY                                                                        0x000d
11093 #define ixSE_SA0DB2_SAMPLEDELAY                                                                        0x000e
11094 #define ixSE_SA0DB3_SAMPLEDELAY                                                                        0x000f
11095 #define ixSE_SA0SC0_SAMPLEDELAY                                                                        0x0010
11096 #define ixSE_SA0SC1_SAMPLEDELAY                                                                        0x0011
11097 #define ixSE_SA0RMI0_SAMPLEDELAY                                                                       0x0012
11098 #define ixSE_SA0RMI1_SAMPLEDELAY                                                                       0x0013
11099 #define ixSE_SA0GL1C0_SAMPLEDELAY                                                                      0x0014
11100 #define ixSE_SA0GL1C1_SAMPLEDELAY                                                                      0x0015
11101 #define ixSE_SA0GL1C2_SAMPLEDELAY                                                                      0x0016
11102 #define ixSE_SA0GL1C3_SAMPLEDELAY                                                                      0x0017
11103 #define ixSE_SA0WGP00TA0_SAMPLEDELAY                                                                   0x0018
11104 #define ixSE_SA0WGP00TA1_SAMPLEDELAY                                                                   0x0019
11105 #define ixSE_SA0WGP00TD0_SAMPLEDELAY                                                                   0x001a
11106 #define ixSE_SA0WGP00TD1_SAMPLEDELAY                                                                   0x001b
11107 #define ixSE_SA0WGP00TCP0_SAMPLEDELAY                                                                  0x001c
11108 #define ixSE_SA0WGP00TCP1_SAMPLEDELAY                                                                  0x001d
11109 #define ixSE_SA0WGP01TA0_SAMPLEDELAY                                                                   0x001e
11110 #define ixSE_SA0WGP01TA1_SAMPLEDELAY                                                                   0x001f
11111 #define ixSE_SA0WGP01TD0_SAMPLEDELAY                                                                   0x0020
11112 #define ixSE_SA0WGP01TD1_SAMPLEDELAY                                                                   0x0021
11113 #define ixSE_SA0WGP01TCP0_SAMPLEDELAY                                                                  0x0022
11114 #define ixSE_SA0WGP01TCP1_SAMPLEDELAY                                                                  0x0023
11115 #define ixSE_SA0WGP02TA0_SAMPLEDELAY                                                                   0x0024
11116 #define ixSE_SA0WGP02TA1_SAMPLEDELAY                                                                   0x0025
11117 #define ixSE_SA0WGP02TD0_SAMPLEDELAY                                                                   0x0026
11118 #define ixSE_SA0WGP02TD1_SAMPLEDELAY                                                                   0x0027
11119 #define ixSE_SA0WGP02TCP0_SAMPLEDELAY                                                                  0x0028
11120 #define ixSE_SA0WGP02TCP1_SAMPLEDELAY                                                                  0x0029
11121 #define ixSE_SA0WGP10TA0_SAMPLEDELAY                                                                   0x002a
11122 #define ixSE_SA0WGP10TA1_SAMPLEDELAY                                                                   0x002b
11123 #define ixSE_SA0WGP10TD0_SAMPLEDELAY                                                                   0x002c
11124 #define ixSE_SA0WGP10TD1_SAMPLEDELAY                                                                   0x002d
11125 #define ixSE_SA0WGP10TCP0_SAMPLEDELAY                                                                  0x002e
11126 #define ixSE_SA0WGP10TCP1_SAMPLEDELAY                                                                  0x002f
11127 #define ixSE_SA0WGP11TA0_SAMPLEDELAY                                                                   0x0030
11128 #define ixSE_SA0WGP11TA1_SAMPLEDELAY                                                                   0x0031
11129 #define ixSE_SA0WGP11TD0_SAMPLEDELAY                                                                   0x0032
11130 #define ixSE_SA0WGP11TD1_SAMPLEDELAY                                                                   0x0033
11131 #define ixSE_SA0WGP11TCP0_SAMPLEDELAY                                                                  0x0034
11132 #define ixSE_SA0WGP11TCP1_SAMPLEDELAY                                                                  0x0035
11133 #define ixSE_SA1SX_SAMPLEDELAY                                                                         0x0036
11134 #define ixSE_SA1PA_SAMPLEDELAY                                                                         0x0037
11135 #define ixSE_SA1GL1A_SAMPLEDELAY                                                                       0x0038
11136 #define ixSE_SA1GL1CG_SAMPLEDELAY                                                                      0x0039
11137 #define ixSE_SA1CB0_SAMPLEDELAY                                                                        0x003a
11138 #define ixSE_SA1CB1_SAMPLEDELAY                                                                        0x003b
11139 #define ixSE_SA1CB2_SAMPLEDELAY                                                                        0x003c
11140 #define ixSE_SA1CB3_SAMPLEDELAY                                                                        0x003d
11141 #define ixSE_SA1DB0_SAMPLEDELAY                                                                        0x003e
11142 #define ixSE_SA1DB1_SAMPLEDELAY                                                                        0x003f
11143 #define ixSE_SA1DB2_SAMPLEDELAY                                                                        0x0040
11144 #define ixSE_SA1DB3_SAMPLEDELAY                                                                        0x0041
11145 #define ixSE_SA1SC0_SAMPLEDELAY                                                                        0x0042
11146 #define ixSE_SA1SC1_SAMPLEDELAY                                                                        0x0043
11147 #define ixSE_SA1RMI0_SAMPLEDELAY                                                                       0x0044
11148 #define ixSE_SA1RMI1_SAMPLEDELAY                                                                       0x0045
11149 #define ixSE_SA1GL1C0_SAMPLEDELAY                                                                      0x0046
11150 #define ixSE_SA1GL1C1_SAMPLEDELAY                                                                      0x0047
11151 #define ixSE_SA1GL1C2_SAMPLEDELAY                                                                      0x0048
11152 #define ixSE_SA1GL1C3_SAMPLEDELAY                                                                      0x0049
11153 #define ixSE_SA1WGP00TA0_SAMPLEDELAY                                                                   0x004a
11154 #define ixSE_SA1WGP00TA1_SAMPLEDELAY                                                                   0x004b
11155 #define ixSE_SA1WGP00TD0_SAMPLEDELAY                                                                   0x004c
11156 #define ixSE_SA1WGP00TD1_SAMPLEDELAY                                                                   0x004d
11157 #define ixSE_SA1WGP00TCP0_SAMPLEDELAY                                                                  0x004e
11158 #define ixSE_SA1WGP00TCP1_SAMPLEDELAY                                                                  0x004f
11159 #define ixSE_SA1WGP01TA0_SAMPLEDELAY                                                                   0x0050
11160 #define ixSE_SA1WGP01TA1_SAMPLEDELAY                                                                   0x0051
11161 #define ixSE_SA1WGP01TD0_SAMPLEDELAY                                                                   0x0052
11162 #define ixSE_SA1WGP01TD1_SAMPLEDELAY                                                                   0x0053
11163 #define ixSE_SA1WGP01TCP0_SAMPLEDELAY                                                                  0x0054
11164 #define ixSE_SA1WGP01TCP1_SAMPLEDELAY                                                                  0x0055
11165 #define ixSE_SA1WGP02TA0_SAMPLEDELAY                                                                   0x0056
11166 #define ixSE_SA1WGP02TA1_SAMPLEDELAY                                                                   0x0057
11167 #define ixSE_SA1WGP02TD0_SAMPLEDELAY                                                                   0x0058
11168 #define ixSE_SA1WGP02TD1_SAMPLEDELAY                                                                   0x0059
11169 #define ixSE_SA1WGP02TCP0_SAMPLEDELAY                                                                  0x005a
11170 #define ixSE_SA1WGP02TCP1_SAMPLEDELAY                                                                  0x005b
11171 #define ixSE_SA1WGP10TA0_SAMPLEDELAY                                                                   0x005c
11172 #define ixSE_SA1WGP10TA1_SAMPLEDELAY                                                                   0x005d
11173 #define ixSE_SA1WGP10TD0_SAMPLEDELAY                                                                   0x005e
11174 #define ixSE_SA1WGP10TD1_SAMPLEDELAY                                                                   0x005f
11175 #define ixSE_SA1WGP10TCP0_SAMPLEDELAY                                                                  0x0060
11176 #define ixSE_SA1WGP10TCP1_SAMPLEDELAY                                                                  0x0061
11177 #define ixSE_SA1WGP11TA0_SAMPLEDELAY                                                                   0x0062
11178 #define ixSE_SA1WGP11TA1_SAMPLEDELAY                                                                   0x0063
11179 #define ixSE_SA1WGP11TD0_SAMPLEDELAY                                                                   0x0064
11180 #define ixSE_SA1WGP11TD1_SAMPLEDELAY                                                                   0x0065
11181 #define ixSE_SA1WGP11TCP0_SAMPLEDELAY                                                                  0x0066
11182 #define ixSE_SA1WGP11TCP1_SAMPLEDELAY                                                                  0x0067
11183 
11184 
11185 // addressBlock: sqind
11186 // base address: 0x0
11187 #define ixSQ_DEBUG_STS_LOCAL                                                                           0x0008
11188 #define ixSQ_WAVE_MODE                                                                                 0x0101
11189 #define ixSQ_WAVE_STATUS                                                                               0x0102
11190 #define ixSQ_WAVE_TRAPSTS                                                                              0x0103
11191 #define ixSQ_WAVE_HW_ID_LEGACY                                                                         0x0104
11192 #define ixSQ_WAVE_GPR_ALLOC                                                                            0x0105
11193 #define ixSQ_WAVE_LDS_ALLOC                                                                            0x0106
11194 #define ixSQ_WAVE_IB_STS                                                                               0x0107
11195 #define ixSQ_WAVE_PC_LO                                                                                0x0108
11196 #define ixSQ_WAVE_PC_HI                                                                                0x0109
11197 #define ixSQ_WAVE_INST_DW0                                                                             0x010a
11198 #define ixSQ_WAVE_IB_DBG1                                                                              0x010d
11199 #define ixSQ_WAVE_FLUSH_IB                                                                             0x010e
11200 #define ixSQ_WAVE_HW_ID1                                                                               0x0117
11201 #define ixSQ_WAVE_HW_ID2                                                                               0x0118
11202 #define ixSQ_WAVE_POPS_PACKER                                                                          0x0119
11203 #define ixSQ_WAVE_SCHED_MODE                                                                           0x011a
11204 #define ixSQ_WAVE_VGPR_OFFSET                                                                          0x011b
11205 #define ixSQ_WAVE_IB_STS2                                                                              0x011c
11206 #define ixSQ_WAVE_TTMP0                                                                                0x026c
11207 #define ixSQ_WAVE_TTMP1                                                                                0x026d
11208 #define ixSQ_WAVE_TTMP2                                                                                0x026e
11209 #define ixSQ_WAVE_TTMP3                                                                                0x026f
11210 #define ixSQ_WAVE_TTMP4                                                                                0x0270
11211 #define ixSQ_WAVE_TTMP5                                                                                0x0271
11212 #define ixSQ_WAVE_TTMP6                                                                                0x0272
11213 #define ixSQ_WAVE_TTMP7                                                                                0x0273
11214 #define ixSQ_WAVE_TTMP8                                                                                0x0274
11215 #define ixSQ_WAVE_TTMP9                                                                                0x0275
11216 #define ixSQ_WAVE_TTMP10                                                                               0x0276
11217 #define ixSQ_WAVE_TTMP11                                                                               0x0277
11218 #define ixSQ_WAVE_TTMP12                                                                               0x0278
11219 #define ixSQ_WAVE_TTMP13                                                                               0x0279
11220 #define ixSQ_WAVE_TTMP14                                                                               0x027a
11221 #define ixSQ_WAVE_TTMP15                                                                               0x027b
11222 #define ixSQ_WAVE_M0                                                                                   0x027c
11223 #define ixSQ_WAVE_EXEC_LO                                                                              0x027e
11224 #define ixSQ_WAVE_EXEC_HI                                                                              0x027f
11225 #define ixSQ_WAVE_FLAT_SCRATCH_LO                                                                      0x0280
11226 #define ixSQ_WAVE_FLAT_SCRATCH_HI                                                                      0x0281
11227 #define ixSQ_WAVE_FLAT_XNACK_MASK                                                                      0x0282
11228 #define ixSQ_INTERRUPT_WORD_AUTO                                                                       0x20c0
11229 #define ixSQ_INTERRUPT_WORD_ERROR                                                                      0x20c0
11230 #define ixSQ_INTERRUPT_WORD_WAVE                                                                       0x20c0
11231 
11232 
11233 // addressBlock: didtind
11234 // base address: 0x0
11235 #define ixDIDT_SQ_CTRL0                                                                                0x0000
11236 #define ixDIDT_SQ_CTRL1                                                                                0x0001
11237 #define ixDIDT_SQ_CTRL2                                                                                0x0002
11238 #define ixDIDT_SQ_CTRL_OCP                                                                             0x0003
11239 #define ixDIDT_SQ_STALL_CTRL                                                                           0x0004
11240 #define ixDIDT_SQ_TUNING_CTRL                                                                          0x0005
11241 #define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL                                                              0x0006
11242 #define ixDIDT_SQ_CTRL3                                                                                0x0007
11243 #define ixDIDT_SQ_STALL_PATTERN_1_2                                                                    0x0008
11244 #define ixDIDT_SQ_STALL_PATTERN_3_4                                                                    0x0009
11245 #define ixDIDT_SQ_STALL_PATTERN_5_6                                                                    0x000a
11246 #define ixDIDT_SQ_STALL_PATTERN_7                                                                      0x000b
11247 #define ixDIDT_SQ_MPD_SCALE_FACTOR                                                                     0x000c
11248 #define ixDIDT_SQ_STALL_RELEASE_CNTL0                                                                  0x000d
11249 #define ixDIDT_SQ_STALL_RELEASE_CNTL1                                                                  0x000e
11250 #define ixDIDT_SQ_STALL_RELEASE_CNTL_STATUS                                                            0x000f
11251 #define ixDIDT_SQ_WEIGHT0_3                                                                            0x0010
11252 #define ixDIDT_SQ_WEIGHT4_7                                                                            0x0011
11253 #define ixDIDT_SQ_WEIGHT8_11                                                                           0x0012
11254 #define ixDIDT_SQ_EDC_CTRL                                                                             0x0013
11255 #define ixDIDT_SQ_EDC_THRESHOLD                                                                        0x0014
11256 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2                                                                0x0015
11257 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4                                                                0x0016
11258 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6                                                                0x0017
11259 #define ixDIDT_SQ_EDC_STALL_PATTERN_7                                                                  0x0018
11260 #define ixDIDT_SQ_EDC_TIMER_PERIOD                                                                     0x0019
11261 #define ixDIDT_SQ_THROTTLE_CTRL                                                                        0x001a
11262 #define ixDIDT_SQ_EDC_STALL_DELAY_1                                                                    0x001b
11263 #define ixDIDT_SQ_EDC_STALL_DELAY_2                                                                    0x001c
11264 #define ixDIDT_SQ_EDC_STALL_DELAY_3                                                                    0x001d
11265 #define ixDIDT_SQ_EDC_STATUS                                                                           0x001f
11266 #define ixDIDT_SQ_EDC_OVERFLOW                                                                         0x0020
11267 #define ixDIDT_SQ_EDC_ROLLING_POWER_DELTA                                                              0x0021
11268 #define ixDIDT_SQ_EDC_PCC_PERF_COUNTER                                                                 0x0022
11269 #define ixDIDT_DB_CTRL0                                                                                0x0030
11270 #define ixDIDT_DB_CTRL1                                                                                0x0031
11271 #define ixDIDT_DB_CTRL2                                                                                0x0032
11272 #define ixDIDT_DB_CTRL_OCP                                                                             0x0033
11273 #define ixDIDT_DB_STALL_CTRL                                                                           0x0034
11274 #define ixDIDT_DB_TUNING_CTRL                                                                          0x0035
11275 #define ixDIDT_DB_STALL_AUTO_RELEASE_CTRL                                                              0x0036
11276 #define ixDIDT_DB_CTRL3                                                                                0x0037
11277 #define ixDIDT_DB_STALL_PATTERN_1_2                                                                    0x0038
11278 #define ixDIDT_DB_STALL_PATTERN_3_4                                                                    0x0039
11279 #define ixDIDT_DB_STALL_PATTERN_5_6                                                                    0x003a
11280 #define ixDIDT_DB_STALL_PATTERN_7                                                                      0x003b
11281 #define ixDIDT_DB_MPD_SCALE_FACTOR                                                                     0x003c
11282 #define ixDIDT_DB_STALL_RELEASE_CNTL0                                                                  0x003d
11283 #define ixDIDT_DB_STALL_RELEASE_CNTL1                                                                  0x003e
11284 #define ixDIDT_DB_STALL_RELEASE_CNTL_STATUS                                                            0x003f
11285 #define ixDIDT_DB_WEIGHT0_3                                                                            0x0040
11286 #define ixDIDT_DB_WEIGHT4_7                                                                            0x0041
11287 #define ixDIDT_DB_WEIGHT8_11                                                                           0x0042
11288 #define ixDIDT_DB_EDC_CTRL                                                                             0x0043
11289 #define ixDIDT_DB_EDC_THRESHOLD                                                                        0x0044
11290 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2                                                                0x0045
11291 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4                                                                0x0046
11292 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6                                                                0x0047
11293 #define ixDIDT_DB_EDC_STALL_PATTERN_7                                                                  0x0048
11294 #define ixDIDT_DB_EDC_TIMER_PERIOD                                                                     0x0049
11295 #define ixDIDT_DB_THROTTLE_CTRL                                                                        0x004a
11296 #define ixDIDT_DB_EDC_STALL_DELAY_1                                                                    0x004b
11297 #define ixDIDT_DB_EDC_STATUS                                                                           0x004f
11298 #define ixDIDT_DB_EDC_OVERFLOW                                                                         0x0050
11299 #define ixDIDT_DB_EDC_ROLLING_POWER_DELTA                                                              0x0051
11300 #define ixDIDT_DB_EDC_PCC_PERF_COUNTER                                                                 0x0052
11301 #define ixDIDT_TD_CTRL0                                                                                0x0060
11302 #define ixDIDT_TD_CTRL1                                                                                0x0061
11303 #define ixDIDT_TD_CTRL2                                                                                0x0062
11304 #define ixDIDT_TD_CTRL_OCP                                                                             0x0063
11305 #define ixDIDT_TD_STALL_CTRL                                                                           0x0064
11306 #define ixDIDT_TD_TUNING_CTRL                                                                          0x0065
11307 #define ixDIDT_TD_STALL_AUTO_RELEASE_CTRL                                                              0x0066
11308 #define ixDIDT_TD_CTRL3                                                                                0x0067
11309 #define ixDIDT_TD_STALL_PATTERN_1_2                                                                    0x0068
11310 #define ixDIDT_TD_STALL_PATTERN_3_4                                                                    0x0069
11311 #define ixDIDT_TD_STALL_PATTERN_5_6                                                                    0x006a
11312 #define ixDIDT_TD_STALL_PATTERN_7                                                                      0x006b
11313 #define ixDIDT_TD_MPD_SCALE_FACTOR                                                                     0x006c
11314 #define ixDIDT_TD_STALL_RELEASE_CNTL0                                                                  0x006d
11315 #define ixDIDT_TD_STALL_RELEASE_CNTL1                                                                  0x006e
11316 #define ixDIDT_TD_STALL_RELEASE_CNTL_STATUS                                                            0x006f
11317 #define ixDIDT_TD_WEIGHT0_3                                                                            0x0070
11318 #define ixDIDT_TD_WEIGHT4_7                                                                            0x0071
11319 #define ixDIDT_TD_WEIGHT8_11                                                                           0x0072
11320 #define ixDIDT_TD_EDC_CTRL                                                                             0x0073
11321 #define ixDIDT_TD_EDC_THRESHOLD                                                                        0x0074
11322 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2                                                                0x0075
11323 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4                                                                0x0076
11324 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6                                                                0x0077
11325 #define ixDIDT_TD_EDC_STALL_PATTERN_7                                                                  0x0078
11326 #define ixDIDT_TD_EDC_TIMER_PERIOD                                                                     0x0079
11327 #define ixDIDT_TD_THROTTLE_CTRL                                                                        0x007a
11328 #define ixDIDT_TD_EDC_STALL_DELAY_1                                                                    0x007b
11329 #define ixDIDT_TD_EDC_STALL_DELAY_2                                                                    0x007c
11330 #define ixDIDT_TD_EDC_STALL_DELAY_3                                                                    0x007d
11331 #define ixDIDT_TD_EDC_STATUS                                                                           0x007f
11332 #define ixDIDT_TD_EDC_OVERFLOW                                                                         0x0080
11333 #define ixDIDT_TD_EDC_ROLLING_POWER_DELTA                                                              0x0081
11334 #define ixDIDT_TD_EDC_PCC_PERF_COUNTER                                                                 0x0082
11335 #define ixDIDT_TCP_CTRL0                                                                               0x0090
11336 #define ixDIDT_TCP_CTRL1                                                                               0x0091
11337 #define ixDIDT_TCP_CTRL2                                                                               0x0092
11338 #define ixDIDT_TCP_CTRL_OCP                                                                            0x0093
11339 #define ixDIDT_TCP_STALL_CTRL                                                                          0x0094
11340 #define ixDIDT_TCP_TUNING_CTRL                                                                         0x0095
11341 #define ixDIDT_TCP_STALL_AUTO_RELEASE_CTRL                                                             0x0096
11342 #define ixDIDT_TCP_CTRL3                                                                               0x0097
11343 #define ixDIDT_TCP_STALL_PATTERN_1_2                                                                   0x0098
11344 #define ixDIDT_TCP_STALL_PATTERN_3_4                                                                   0x0099
11345 #define ixDIDT_TCP_STALL_PATTERN_5_6                                                                   0x009a
11346 #define ixDIDT_TCP_STALL_PATTERN_7                                                                     0x009b
11347 #define ixDIDT_TCP_MPD_SCALE_FACTOR                                                                    0x009c
11348 #define ixDIDT_TCP_STALL_RELEASE_CNTL0                                                                 0x009d
11349 #define ixDIDT_TCP_STALL_RELEASE_CNTL1                                                                 0x009e
11350 #define ixDIDT_TCP_STALL_RELEASE_CNTL_STATUS                                                           0x009f
11351 #define ixDIDT_TCP_WEIGHT0_3                                                                           0x00a0
11352 #define ixDIDT_TCP_WEIGHT4_7                                                                           0x00a1
11353 #define ixDIDT_TCP_WEIGHT8_11                                                                          0x00a2
11354 #define ixDIDT_TCP_EDC_CTRL                                                                            0x00a3
11355 #define ixDIDT_TCP_EDC_THRESHOLD                                                                       0x00a4
11356 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2                                                               0x00a5
11357 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4                                                               0x00a6
11358 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6                                                               0x00a7
11359 #define ixDIDT_TCP_EDC_STALL_PATTERN_7                                                                 0x00a8
11360 #define ixDIDT_TCP_EDC_TIMER_PERIOD                                                                    0x00a9
11361 #define ixDIDT_TCP_THROTTLE_CTRL                                                                       0x00aa
11362 #define ixDIDT_TCP_EDC_STALL_DELAY_1                                                                   0x00ab
11363 #define ixDIDT_TCP_EDC_STALL_DELAY_2                                                                   0x00ac
11364 #define ixDIDT_TCP_EDC_STALL_DELAY_3                                                                   0x00ad
11365 #define ixDIDT_TCP_EDC_STATUS                                                                          0x00af
11366 #define ixDIDT_TCP_EDC_OVERFLOW                                                                        0x00b0
11367 #define ixDIDT_TCP_EDC_ROLLING_POWER_DELTA                                                             0x00b1
11368 #define ixDIDT_TCP_EDC_PCC_PERF_COUNTER                                                                0x00b2
11369 #define ixDIDT_SQ_STALL_EVENT_COUNTER                                                                  0x00c0
11370 #define ixDIDT_DB_STALL_EVENT_COUNTER                                                                  0x00c1
11371 #define ixDIDT_TD_STALL_EVENT_COUNTER                                                                  0x00c2
11372 #define ixDIDT_TCP_STALL_EVENT_COUNTER                                                                 0x00c3
11373 
11374 
11375 #endif
11376