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Searched refs:mmDP5_DP_DPHY_BS_SR_SWAP_CNTL (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c92 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC macro
/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c98 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h4562 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc macro
H A Ddce_11_2_d.h5794 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4fdc macro
H A Ddce_12_0_offset.h11718 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9997 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_2_offset.h11359 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_2_0_0_offset.h12684 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … macro
H A Ddcn_3_0_0_offset.h12511 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL … macro