1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DMA0_CORE_REGS_H_ 14 #define ASIC_REG_DMA0_CORE_REGS_H_ 15 16 /* 17 ***************************************** 18 * DMA0_CORE (Prototype: DMA_CORE) 19 ***************************************** 20 */ 21 22 #define mmDMA0_CORE_CFG_0 0x500000 23 24 #define mmDMA0_CORE_CFG_1 0x500004 25 26 #define mmDMA0_CORE_LBW_MAX_OUTSTAND 0x500008 27 28 #define mmDMA0_CORE_SRC_BASE_LO 0x500014 29 30 #define mmDMA0_CORE_SRC_BASE_HI 0x500018 31 32 #define mmDMA0_CORE_DST_BASE_LO 0x50001C 33 34 #define mmDMA0_CORE_DST_BASE_HI 0x500020 35 36 #define mmDMA0_CORE_SRC_TSIZE_1 0x50002C 37 38 #define mmDMA0_CORE_SRC_STRIDE_1 0x500030 39 40 #define mmDMA0_CORE_SRC_TSIZE_2 0x500034 41 42 #define mmDMA0_CORE_SRC_STRIDE_2 0x500038 43 44 #define mmDMA0_CORE_SRC_TSIZE_3 0x50003C 45 46 #define mmDMA0_CORE_SRC_STRIDE_3 0x500040 47 48 #define mmDMA0_CORE_SRC_TSIZE_4 0x500044 49 50 #define mmDMA0_CORE_SRC_STRIDE_4 0x500048 51 52 #define mmDMA0_CORE_SRC_TSIZE_0 0x50004C 53 54 #define mmDMA0_CORE_DST_TSIZE_1 0x500054 55 56 #define mmDMA0_CORE_DST_STRIDE_1 0x500058 57 58 #define mmDMA0_CORE_DST_TSIZE_2 0x50005C 59 60 #define mmDMA0_CORE_DST_STRIDE_2 0x500060 61 62 #define mmDMA0_CORE_DST_TSIZE_3 0x500064 63 64 #define mmDMA0_CORE_DST_STRIDE_3 0x500068 65 66 #define mmDMA0_CORE_DST_TSIZE_4 0x50006C 67 68 #define mmDMA0_CORE_DST_STRIDE_4 0x500070 69 70 #define mmDMA0_CORE_DST_TSIZE_0 0x500074 71 72 #define mmDMA0_CORE_COMMIT 0x500078 73 74 #define mmDMA0_CORE_WR_COMP_WDATA 0x50007C 75 76 #define mmDMA0_CORE_WR_COMP_ADDR_LO 0x500080 77 78 #define mmDMA0_CORE_WR_COMP_ADDR_HI 0x500084 79 80 #define mmDMA0_CORE_WR_COMP_AWUSER_31_11 0x500088 81 82 #define mmDMA0_CORE_TE_NUMROWS 0x500094 83 84 #define mmDMA0_CORE_PROT 0x5000B8 85 86 #define mmDMA0_CORE_SECURE_PROPS 0x5000F0 87 88 #define mmDMA0_CORE_NON_SECURE_PROPS 0x5000F4 89 90 #define mmDMA0_CORE_RD_MAX_OUTSTAND 0x500100 91 92 #define mmDMA0_CORE_RD_MAX_SIZE 0x500104 93 94 #define mmDMA0_CORE_RD_ARCACHE 0x500108 95 96 #define mmDMA0_CORE_RD_ARUSER_31_11 0x500110 97 98 #define mmDMA0_CORE_RD_INFLIGHTS 0x500114 99 100 #define mmDMA0_CORE_WR_MAX_OUTSTAND 0x500120 101 102 #define mmDMA0_CORE_WR_MAX_AWID 0x500124 103 104 #define mmDMA0_CORE_WR_AWCACHE 0x500128 105 106 #define mmDMA0_CORE_WR_AWUSER_31_11 0x500130 107 108 #define mmDMA0_CORE_WR_INFLIGHTS 0x500134 109 110 #define mmDMA0_CORE_RD_RATE_LIM_CFG_0 0x500150 111 112 #define mmDMA0_CORE_RD_RATE_LIM_CFG_1 0x500154 113 114 #define mmDMA0_CORE_WR_RATE_LIM_CFG_0 0x500158 115 116 #define mmDMA0_CORE_WR_RATE_LIM_CFG_1 0x50015C 117 118 #define mmDMA0_CORE_ERR_CFG 0x500160 119 120 #define mmDMA0_CORE_ERR_CAUSE 0x500164 121 122 #define mmDMA0_CORE_ERRMSG_ADDR_LO 0x500170 123 124 #define mmDMA0_CORE_ERRMSG_ADDR_HI 0x500174 125 126 #define mmDMA0_CORE_ERRMSG_WDATA 0x500178 127 128 #define mmDMA0_CORE_STS0 0x500190 129 130 #define mmDMA0_CORE_STS1 0x500194 131 132 #define mmDMA0_CORE_RD_DBGMEM_ADD 0x500200 133 134 #define mmDMA0_CORE_RD_DBGMEM_DATA_WR 0x500204 135 136 #define mmDMA0_CORE_RD_DBGMEM_DATA_RD 0x500208 137 138 #define mmDMA0_CORE_RD_DBGMEM_CTRL 0x50020C 139 140 #define mmDMA0_CORE_RD_DBGMEM_RC 0x500210 141 142 #define mmDMA0_CORE_DBG_HBW_AXI_AR_CNT 0x500220 143 144 #define mmDMA0_CORE_DBG_HBW_AXI_AW_CNT 0x500224 145 146 #define mmDMA0_CORE_DBG_LBW_AXI_AW_CNT 0x500228 147 148 #define mmDMA0_CORE_DBG_DESC_CNT 0x50022C 149 150 #define mmDMA0_CORE_DBG_STS 0x500230 151 152 #define mmDMA0_CORE_DBG_RD_DESC_ID 0x500234 153 154 #define mmDMA0_CORE_DBG_WR_DESC_ID 0x500238 155 156 #endif /* ASIC_REG_DMA0_CORE_REGS_H_ */ 157