dcore1_sync_mngr_glbl_regs.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) - OpenGrok cross reference for /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore1_sync_mngr_glbl_regs.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2020 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

/************************************
 ** This is an auto-generated file **
 **       DO NOT EDIT BELOW        **
 ************************************/

#ifndef ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_
#define ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_

/*
 *****************************************
 *   DCORE1_SYNC_MNGR_GLBL
 *   (Prototype: SOB_GLBL)
 *****************************************
 */

#define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_MASK 0x431E000

#define mmDCORE1_SYNC_MNGR_GLBL_SM_SEI_CAUSE 0x431E004

#define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_L 0x431E008

#define mmDCORE1_SYNC_MNGR_GLBL_L2H_CPMR_H 0x431E00C

#define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_L 0x431E020

#define mmDCORE1_SYNC_MNGR_GLBL_L2H_MASK_H 0x431E024

#define mmDCORE1_SYNC_MNGR_GLBL_ASID_SEC 0x431E030

#define mmDCORE1_SYNC_MNGR_GLBL_ASID_PRIV_ONLY 0x431E034

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DELAY 0x431E038

#define mmDCORE1_SYNC_MNGR_GLBL_PI_SIZE 0x431E03C

#define mmDCORE1_SYNC_MNGR_GLBL_SOB_ONLY 0x431E040

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INTR 0x431E044

#define mmDCORE1_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV 0x431E048

#define mmDCORE1_SYNC_MNGR_GLBL_PI_INC_MODE_SIZE 0x431E04C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0 0x431E050

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1 0x431E054

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_2 0x431E058

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_3 0x431E05C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_4 0x431E060

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_5 0x431E064

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_6 0x431E068

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_7 0x431E06C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_8 0x431E070

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_9 0x431E074

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_10 0x431E078

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_11 0x431E07C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_12 0x431E080

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_13 0x431E084

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_14 0x431E088

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_15 0x431E08C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_16 0x431E090

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_17 0x431E094

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_18 0x431E098

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_19 0x431E09C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_20 0x431E0A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_21 0x431E0A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_22 0x431E0A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_23 0x431E0AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_24 0x431E0B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_25 0x431E0B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_26 0x431E0B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_27 0x431E0BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_28 0x431E0C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_29 0x431E0C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_30 0x431E0C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_31 0x431E0CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_32 0x431E0D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_33 0x431E0D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_34 0x431E0D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_35 0x431E0DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_36 0x431E0E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_37 0x431E0E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_38 0x431E0E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_39 0x431E0EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_40 0x431E0F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_41 0x431E0F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_42 0x431E0F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_43 0x431E0FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_44 0x431E100

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_45 0x431E104

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_46 0x431E108

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_47 0x431E10C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_48 0x431E110

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_49 0x431E114

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_50 0x431E118

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_51 0x431E11C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_52 0x431E120

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_53 0x431E124

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_54 0x431E128

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_55 0x431E12C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_56 0x431E130

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_57 0x431E134

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_58 0x431E138

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_59 0x431E13C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_60 0x431E140

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_61 0x431E144

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_62 0x431E148

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63 0x431E14C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0 0x431E150

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1 0x431E154

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_2 0x431E158

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_3 0x431E15C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_4 0x431E160

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_5 0x431E164

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_6 0x431E168

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_7 0x431E16C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_8 0x431E170

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_9 0x431E174

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_10 0x431E178

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_11 0x431E17C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_12 0x431E180

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_13 0x431E184

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_14 0x431E188

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_15 0x431E18C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_16 0x431E190

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_17 0x431E194

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_18 0x431E198

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_19 0x431E19C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_20 0x431E1A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_21 0x431E1A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_22 0x431E1A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_23 0x431E1AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_24 0x431E1B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_25 0x431E1B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_26 0x431E1B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_27 0x431E1BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_28 0x431E1C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_29 0x431E1C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_30 0x431E1C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_31 0x431E1CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_32 0x431E1D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_33 0x431E1D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_34 0x431E1D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_35 0x431E1DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_36 0x431E1E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_37 0x431E1E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_38 0x431E1E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_39 0x431E1EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_40 0x431E1F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_41 0x431E1F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_42 0x431E1F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_43 0x431E1FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_44 0x431E200

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_45 0x431E204

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_46 0x431E208

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_47 0x431E20C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_48 0x431E210

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_49 0x431E214

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_50 0x431E218

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_51 0x431E21C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_52 0x431E220

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_53 0x431E224

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_54 0x431E228

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_55 0x431E22C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_56 0x431E230

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_57 0x431E234

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_58 0x431E238

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_59 0x431E23C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_60 0x431E240

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_61 0x431E244

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_62 0x431E248

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63 0x431E24C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0 0x431E250

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1 0x431E254

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_2 0x431E258

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_3 0x431E25C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_4 0x431E260

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_5 0x431E264

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_6 0x431E268

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_7 0x431E26C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_8 0x431E270

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_9 0x431E274

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_10 0x431E278

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_11 0x431E27C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_12 0x431E280

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_13 0x431E284

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_14 0x431E288

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_15 0x431E28C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_16 0x431E290

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_17 0x431E294

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_18 0x431E298

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_19 0x431E29C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_20 0x431E2A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_21 0x431E2A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_22 0x431E2A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_23 0x431E2AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_24 0x431E2B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_25 0x431E2B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_26 0x431E2B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_27 0x431E2BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_28 0x431E2C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_29 0x431E2C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_30 0x431E2C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_31 0x431E2CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_32 0x431E2D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_33 0x431E2D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_34 0x431E2D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_35 0x431E2DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_36 0x431E2E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_37 0x431E2E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_38 0x431E2E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_39 0x431E2EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_40 0x431E2F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_41 0x431E2F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_42 0x431E2F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_43 0x431E2FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_44 0x431E300

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_45 0x431E304

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_46 0x431E308

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_47 0x431E30C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_48 0x431E310

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_49 0x431E314

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_50 0x431E318

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_51 0x431E31C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_52 0x431E320

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_53 0x431E324

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_54 0x431E328

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_55 0x431E32C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_56 0x431E330

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_57 0x431E334

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_58 0x431E338

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_59 0x431E33C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_60 0x431E340

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_61 0x431E344

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_62 0x431E348

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63 0x431E34C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0 0x431E350

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_1 0x431E354

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_2 0x431E358

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_3 0x431E35C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_4 0x431E360

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_5 0x431E364

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_6 0x431E368

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_7 0x431E36C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_8 0x431E370

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_9 0x431E374

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_10 0x431E378

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_11 0x431E37C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_12 0x431E380

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_13 0x431E384

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_14 0x431E388

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_15 0x431E38C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_16 0x431E390

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_17 0x431E394

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_18 0x431E398

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_19 0x431E39C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_20 0x431E3A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_21 0x431E3A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_22 0x431E3A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_23 0x431E3AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_24 0x431E3B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_25 0x431E3B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_26 0x431E3B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_27 0x431E3BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_28 0x431E3C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_29 0x431E3C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_30 0x431E3C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_31 0x431E3CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_32 0x431E3D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_33 0x431E3D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_34 0x431E3D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_35 0x431E3DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_36 0x431E3E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_37 0x431E3E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_38 0x431E3E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_39 0x431E3EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_40 0x431E3F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_41 0x431E3F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_42 0x431E3F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_43 0x431E3FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_44 0x431E400

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_45 0x431E404

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_46 0x431E408

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_47 0x431E40C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_48 0x431E410

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_49 0x431E414

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_50 0x431E418

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_51 0x431E41C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_52 0x431E420

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_53 0x431E424

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_54 0x431E428

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_55 0x431E42C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_56 0x431E430

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_57 0x431E434

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_58 0x431E438

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_59 0x431E43C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_60 0x431E440

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_61 0x431E444

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_62 0x431E448

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63 0x431E44C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_0 0x431E450

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_1 0x431E454

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_2 0x431E458

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_3 0x431E45C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_4 0x431E460

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_5 0x431E464

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_6 0x431E468

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_7 0x431E46C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_8 0x431E470

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_9 0x431E474

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_10 0x431E478

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_11 0x431E47C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_12 0x431E480

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_13 0x431E484

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_14 0x431E488

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_15 0x431E48C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_16 0x431E490

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_17 0x431E494

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_18 0x431E498

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_19 0x431E49C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_20 0x431E4A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_21 0x431E4A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_22 0x431E4A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_23 0x431E4AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_24 0x431E4B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_25 0x431E4B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_26 0x431E4B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_27 0x431E4BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_28 0x431E4C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_29 0x431E4C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_30 0x431E4C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_31 0x431E4CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_32 0x431E4D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_33 0x431E4D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_34 0x431E4D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_35 0x431E4DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_36 0x431E4E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_37 0x431E4E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_38 0x431E4E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_39 0x431E4EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_40 0x431E4F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_41 0x431E4F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_42 0x431E4F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_43 0x431E4FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_44 0x431E500

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_45 0x431E504

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_46 0x431E508

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_47 0x431E50C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_48 0x431E510

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_49 0x431E514

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_50 0x431E518

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_51 0x431E51C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_52 0x431E520

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_53 0x431E524

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_54 0x431E528

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_55 0x431E52C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_56 0x431E530

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_57 0x431E534

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_58 0x431E538

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_59 0x431E53C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_60 0x431E540

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_61 0x431E544

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_62 0x431E548

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_SEC_63 0x431E54C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0 0x431E550

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_1 0x431E554

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_2 0x431E558

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_3 0x431E55C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_4 0x431E560

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_5 0x431E564

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_6 0x431E568

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_7 0x431E56C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_8 0x431E570

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_9 0x431E574

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_10 0x431E578

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_11 0x431E57C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_12 0x431E580

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_13 0x431E584

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_14 0x431E588

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_15 0x431E58C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_16 0x431E590

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_17 0x431E594

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_18 0x431E598

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_19 0x431E59C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_20 0x431E5A0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_21 0x431E5A4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_22 0x431E5A8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_23 0x431E5AC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_24 0x431E5B0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_25 0x431E5B4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_26 0x431E5B8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_27 0x431E5BC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_28 0x431E5C0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_29 0x431E5C4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_30 0x431E5C8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_31 0x431E5CC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_32 0x431E5D0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_33 0x431E5D4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_34 0x431E5D8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_35 0x431E5DC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_36 0x431E5E0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_37 0x431E5E4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_38 0x431E5E8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_39 0x431E5EC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_40 0x431E5F0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_41 0x431E5F4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_42 0x431E5F8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_43 0x431E5FC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_44 0x431E600

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_45 0x431E604

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_46 0x431E608

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_47 0x431E60C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_48 0x431E610

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_49 0x431E614

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_50 0x431E618

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_51 0x431E61C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_52 0x431E620

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_53 0x431E624

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_54 0x431E628

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_55 0x431E62C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_56 0x431E630

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_57 0x431E634

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_58 0x431E638

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_59 0x431E63C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_60 0x431E640

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_61 0x431E644

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_62 0x431E648

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63 0x431E64C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0 0x431E650

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_1 0x431E654

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_2 0x431E658

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_3 0x431E65C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_4 0x431E660

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_5 0x431E664

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_6 0x431E668

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_7 0x431E66C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_8 0x431E670

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_9 0x431E674

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_10 0x431E678

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_11 0x431E67C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_12 0x431E680

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_13 0x431E684

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_14 0x431E688

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_15 0x431E68C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_16 0x431E690

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_17 0x431E694

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_18 0x431E698

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_19 0x431E69C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_20 0x431E6A0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_21 0x431E6A4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_22 0x431E6A8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_23 0x431E6AC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_24 0x431E6B0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_25 0x431E6B4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_26 0x431E6B8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_27 0x431E6BC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_28 0x431E6C0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_29 0x431E6C4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_30 0x431E6C8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_31 0x431E6CC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_32 0x431E6D0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_33 0x431E6D4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_34 0x431E6D8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_35 0x431E6DC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_36 0x431E6E0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_37 0x431E6E4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_38 0x431E6E8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_39 0x431E6EC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_40 0x431E6F0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_41 0x431E6F4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_42 0x431E6F8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_43 0x431E6FC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_44 0x431E700

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_45 0x431E704

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_46 0x431E708

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_47 0x431E70C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_48 0x431E710

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_49 0x431E714

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_50 0x431E718

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_51 0x431E71C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_52 0x431E720

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_53 0x431E724

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_54 0x431E728

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_55 0x431E72C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_56 0x431E730

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_57 0x431E734

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_58 0x431E738

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_59 0x431E73C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_60 0x431E740

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_61 0x431E744

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_62 0x431E748

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63 0x431E74C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0 0x431E750

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_1 0x431E754

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_2 0x431E758

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_3 0x431E75C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_4 0x431E760

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_5 0x431E764

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_6 0x431E768

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_7 0x431E76C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_8 0x431E770

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_9 0x431E774

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_10 0x431E778

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_11 0x431E77C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_12 0x431E780

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_13 0x431E784

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_14 0x431E788

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_15 0x431E78C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_16 0x431E790

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_17 0x431E794

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_18 0x431E798

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_19 0x431E79C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_20 0x431E7A0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_21 0x431E7A4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_22 0x431E7A8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_23 0x431E7AC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_24 0x431E7B0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_25 0x431E7B4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_26 0x431E7B8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_27 0x431E7BC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_28 0x431E7C0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_29 0x431E7C4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_30 0x431E7C8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_31 0x431E7CC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_32 0x431E7D0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_33 0x431E7D4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_34 0x431E7D8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_35 0x431E7DC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_36 0x431E7E0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_37 0x431E7E4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_38 0x431E7E8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_39 0x431E7EC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_40 0x431E7F0

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_41 0x431E7F4

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_42 0x431E7F8

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_43 0x431E7FC

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_44 0x431E800

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_45 0x431E804

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_46 0x431E808

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_47 0x431E80C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_48 0x431E810

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_49 0x431E814

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_50 0x431E818

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_51 0x431E81C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_52 0x431E820

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_53 0x431E824

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_54 0x431E828

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_55 0x431E82C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_56 0x431E830

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_57 0x431E834

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_58 0x431E838

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_59 0x431E83C

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_60 0x431E840

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_61 0x431E844

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_62 0x431E848

#define mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63 0x431E84C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0 0x431E850

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_1 0x431E854

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_2 0x431E858

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_3 0x431E85C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_4 0x431E860

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_5 0x431E864

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_6 0x431E868

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_7 0x431E86C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_8 0x431E870

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_9 0x431E874

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_10 0x431E878

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_11 0x431E87C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_12 0x431E880

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_13 0x431E884

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_14 0x431E888

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_15 0x431E88C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_16 0x431E890

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_17 0x431E894

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_18 0x431E898

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_19 0x431E89C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_20 0x431E8A0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_21 0x431E8A4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_22 0x431E8A8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_23 0x431E8AC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_24 0x431E8B0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_25 0x431E8B4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_26 0x431E8B8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_27 0x431E8BC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_28 0x431E8C0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_29 0x431E8C4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_30 0x431E8C8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_31 0x431E8CC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_32 0x431E8D0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_33 0x431E8D4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_34 0x431E8D8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_35 0x431E8DC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_36 0x431E8E0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_37 0x431E8E4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_38 0x431E8E8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_39 0x431E8EC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_40 0x431E8F0

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_41 0x431E8F4

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_42 0x431E8F8

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_43 0x431E8FC

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_44 0x431E900

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_45 0x431E904

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_46 0x431E908

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_47 0x431E90C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_48 0x431E910

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_49 0x431E914

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_50 0x431E918

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_51 0x431E91C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_52 0x431E920

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_53 0x431E924

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_54 0x431E928

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_55 0x431E92C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_56 0x431E930

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_57 0x431E934

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_58 0x431E938

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_59 0x431E93C

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_60 0x431E940

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_61 0x431E944

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_62 0x431E948

#define mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63 0x431E94C

#endif /* ASIC_REG_DCORE1_SYNC_MNGR_GLBL_REGS_H_ */