1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_TPC0_QM_REGS_H_ 14 #define ASIC_REG_DCORE0_TPC0_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_TPC0_QM 19 * (Prototype: QMAN) 20 ***************************************** 21 */ 22 23 #define mmDCORE0_TPC0_QM_GLBL_CFG0 0x400A000 24 25 #define mmDCORE0_TPC0_QM_GLBL_CFG1 0x400A004 26 27 #define mmDCORE0_TPC0_QM_GLBL_CFG2 0x400A008 28 29 #define mmDCORE0_TPC0_QM_GLBL_ERR_CFG 0x400A00C 30 31 #define mmDCORE0_TPC0_QM_GLBL_ERR_CFG1 0x400A010 32 33 #define mmDCORE0_TPC0_QM_GLBL_ERR_ARC_HALT_EN 0x400A014 34 35 #define mmDCORE0_TPC0_QM_GLBL_AXCACHE 0x400A018 36 37 #define mmDCORE0_TPC0_QM_GLBL_STS0 0x400A01C 38 39 #define mmDCORE0_TPC0_QM_GLBL_STS1 0x400A020 40 41 #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_0 0x400A024 42 43 #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_1 0x400A028 44 45 #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_2 0x400A02C 46 47 #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_3 0x400A030 48 49 #define mmDCORE0_TPC0_QM_GLBL_ERR_STS_4 0x400A034 50 51 #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_0 0x400A038 52 53 #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_1 0x400A03C 54 55 #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_2 0x400A040 56 57 #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_3 0x400A044 58 59 #define mmDCORE0_TPC0_QM_GLBL_ERR_MSG_EN_4 0x400A048 60 61 #define mmDCORE0_TPC0_QM_GLBL_PROT 0x400A04C 62 63 #define mmDCORE0_TPC0_QM_PQ_BASE_LO_0 0x400A050 64 65 #define mmDCORE0_TPC0_QM_PQ_BASE_LO_1 0x400A054 66 67 #define mmDCORE0_TPC0_QM_PQ_BASE_LO_2 0x400A058 68 69 #define mmDCORE0_TPC0_QM_PQ_BASE_LO_3 0x400A05C 70 71 #define mmDCORE0_TPC0_QM_PQ_BASE_HI_0 0x400A060 72 73 #define mmDCORE0_TPC0_QM_PQ_BASE_HI_1 0x400A064 74 75 #define mmDCORE0_TPC0_QM_PQ_BASE_HI_2 0x400A068 76 77 #define mmDCORE0_TPC0_QM_PQ_BASE_HI_3 0x400A06C 78 79 #define mmDCORE0_TPC0_QM_PQ_SIZE_0 0x400A070 80 81 #define mmDCORE0_TPC0_QM_PQ_SIZE_1 0x400A074 82 83 #define mmDCORE0_TPC0_QM_PQ_SIZE_2 0x400A078 84 85 #define mmDCORE0_TPC0_QM_PQ_SIZE_3 0x400A07C 86 87 #define mmDCORE0_TPC0_QM_PQ_PI_0 0x400A080 88 89 #define mmDCORE0_TPC0_QM_PQ_PI_1 0x400A084 90 91 #define mmDCORE0_TPC0_QM_PQ_PI_2 0x400A088 92 93 #define mmDCORE0_TPC0_QM_PQ_PI_3 0x400A08C 94 95 #define mmDCORE0_TPC0_QM_PQ_CI_0 0x400A090 96 97 #define mmDCORE0_TPC0_QM_PQ_CI_1 0x400A094 98 99 #define mmDCORE0_TPC0_QM_PQ_CI_2 0x400A098 100 101 #define mmDCORE0_TPC0_QM_PQ_CI_3 0x400A09C 102 103 #define mmDCORE0_TPC0_QM_PQ_CFG0_0 0x400A0A0 104 105 #define mmDCORE0_TPC0_QM_PQ_CFG0_1 0x400A0A4 106 107 #define mmDCORE0_TPC0_QM_PQ_CFG0_2 0x400A0A8 108 109 #define mmDCORE0_TPC0_QM_PQ_CFG0_3 0x400A0AC 110 111 #define mmDCORE0_TPC0_QM_PQ_CFG1_0 0x400A0B0 112 113 #define mmDCORE0_TPC0_QM_PQ_CFG1_1 0x400A0B4 114 115 #define mmDCORE0_TPC0_QM_PQ_CFG1_2 0x400A0B8 116 117 #define mmDCORE0_TPC0_QM_PQ_CFG1_3 0x400A0BC 118 119 #define mmDCORE0_TPC0_QM_PQ_STS0_0 0x400A0C0 120 121 #define mmDCORE0_TPC0_QM_PQ_STS0_1 0x400A0C4 122 123 #define mmDCORE0_TPC0_QM_PQ_STS0_2 0x400A0C8 124 125 #define mmDCORE0_TPC0_QM_PQ_STS0_3 0x400A0CC 126 127 #define mmDCORE0_TPC0_QM_PQ_STS1_0 0x400A0D0 128 129 #define mmDCORE0_TPC0_QM_PQ_STS1_1 0x400A0D4 130 131 #define mmDCORE0_TPC0_QM_PQ_STS1_2 0x400A0D8 132 133 #define mmDCORE0_TPC0_QM_PQ_STS1_3 0x400A0DC 134 135 #define mmDCORE0_TPC0_QM_CQ_CFG0_0 0x400A0E0 136 137 #define mmDCORE0_TPC0_QM_CQ_CFG0_1 0x400A0E4 138 139 #define mmDCORE0_TPC0_QM_CQ_CFG0_2 0x400A0E8 140 141 #define mmDCORE0_TPC0_QM_CQ_CFG0_3 0x400A0EC 142 143 #define mmDCORE0_TPC0_QM_CQ_CFG0_4 0x400A0F0 144 145 #define mmDCORE0_TPC0_QM_CQ_STS0_0 0x400A0F4 146 147 #define mmDCORE0_TPC0_QM_CQ_STS0_1 0x400A0F8 148 149 #define mmDCORE0_TPC0_QM_CQ_STS0_2 0x400A0FC 150 151 #define mmDCORE0_TPC0_QM_CQ_STS0_3 0x400A100 152 153 #define mmDCORE0_TPC0_QM_CQ_STS0_4 0x400A104 154 155 #define mmDCORE0_TPC0_QM_CQ_CFG1_0 0x400A108 156 157 #define mmDCORE0_TPC0_QM_CQ_CFG1_1 0x400A10C 158 159 #define mmDCORE0_TPC0_QM_CQ_CFG1_2 0x400A110 160 161 #define mmDCORE0_TPC0_QM_CQ_CFG1_3 0x400A114 162 163 #define mmDCORE0_TPC0_QM_CQ_CFG1_4 0x400A118 164 165 #define mmDCORE0_TPC0_QM_CQ_STS1_0 0x400A11C 166 167 #define mmDCORE0_TPC0_QM_CQ_STS1_1 0x400A120 168 169 #define mmDCORE0_TPC0_QM_CQ_STS1_2 0x400A124 170 171 #define mmDCORE0_TPC0_QM_CQ_STS1_3 0x400A128 172 173 #define mmDCORE0_TPC0_QM_CQ_STS1_4 0x400A12C 174 175 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_0 0x400A150 176 177 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_0 0x400A154 178 179 #define mmDCORE0_TPC0_QM_CQ_TSIZE_0 0x400A158 180 181 #define mmDCORE0_TPC0_QM_CQ_CTL_0 0x400A15C 182 183 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_1 0x400A160 184 185 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_1 0x400A164 186 187 #define mmDCORE0_TPC0_QM_CQ_TSIZE_1 0x400A168 188 189 #define mmDCORE0_TPC0_QM_CQ_CTL_1 0x400A16C 190 191 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_2 0x400A170 192 193 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_2 0x400A174 194 195 #define mmDCORE0_TPC0_QM_CQ_TSIZE_2 0x400A178 196 197 #define mmDCORE0_TPC0_QM_CQ_CTL_2 0x400A17C 198 199 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_3 0x400A180 200 201 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_3 0x400A184 202 203 #define mmDCORE0_TPC0_QM_CQ_TSIZE_3 0x400A188 204 205 #define mmDCORE0_TPC0_QM_CQ_CTL_3 0x400A18C 206 207 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_4 0x400A190 208 209 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_4 0x400A194 210 211 #define mmDCORE0_TPC0_QM_CQ_TSIZE_4 0x400A198 212 213 #define mmDCORE0_TPC0_QM_CQ_CTL_4 0x400A19C 214 215 #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_0 0x400A1A0 216 217 #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_1 0x400A1A4 218 219 #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_2 0x400A1A8 220 221 #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_3 0x400A1AC 222 223 #define mmDCORE0_TPC0_QM_CQ_TSIZE_STS_4 0x400A1B0 224 225 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_0 0x400A1B4 226 227 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_1 0x400A1B8 228 229 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_2 0x400A1BC 230 231 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_3 0x400A1C0 232 233 #define mmDCORE0_TPC0_QM_CQ_PTR_LO_STS_4 0x400A1C4 234 235 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_0 0x400A1C8 236 237 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_1 0x400A1CC 238 239 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_2 0x400A1D0 240 241 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_3 0x400A1D4 242 243 #define mmDCORE0_TPC0_QM_CQ_PTR_HI_STS_4 0x400A1D8 244 245 #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_0 0x400A1DC 246 247 #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_1 0x400A1E0 248 249 #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_2 0x400A1E4 250 251 #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_3 0x400A1E8 252 253 #define mmDCORE0_TPC0_QM_CQ_IFIFO_STS_4 0x400A1EC 254 255 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0 0x400A1F0 256 257 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1 0x400A1F4 258 259 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2 0x400A1F8 260 261 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3 0x400A1FC 262 263 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4 0x400A200 264 265 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0 0x400A204 266 267 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1 0x400A208 268 269 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2 0x400A20C 270 271 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3 0x400A210 272 273 #define mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4 0x400A214 274 275 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0 0x400A218 276 277 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1 0x400A21C 278 279 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2 0x400A220 280 281 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3 0x400A224 282 283 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4 0x400A228 284 285 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0 0x400A22C 286 287 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1 0x400A230 288 289 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2 0x400A234 290 291 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3 0x400A238 292 293 #define mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4 0x400A23C 294 295 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0 0x400A240 296 297 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1 0x400A244 298 299 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2 0x400A248 300 301 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3 0x400A24C 302 303 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4 0x400A250 304 305 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0 0x400A254 306 307 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1 0x400A258 308 309 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2 0x400A25C 310 311 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3 0x400A260 312 313 #define mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4 0x400A264 314 315 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0 0x400A268 316 317 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1 0x400A26C 318 319 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2 0x400A270 320 321 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3 0x400A274 322 323 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4 0x400A278 324 325 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0 0x400A27C 326 327 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1 0x400A280 328 329 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2 0x400A284 330 331 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3 0x400A288 332 333 #define mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4 0x400A28C 334 335 #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0 0x400A290 336 337 #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1 0x400A294 338 339 #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2 0x400A298 340 341 #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3 0x400A29C 342 343 #define mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4 0x400A2A0 344 345 #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0 0x400A2A4 346 347 #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1 0x400A2A8 348 349 #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2 0x400A2AC 350 351 #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3 0x400A2B0 352 353 #define mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4 0x400A2B4 354 355 #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0 0x400A2B8 356 357 #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1 0x400A2BC 358 359 #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2 0x400A2C0 360 361 #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3 0x400A2C4 362 363 #define mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4 0x400A2C8 364 365 #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0 0x400A2CC 366 367 #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1 0x400A2D0 368 369 #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2 0x400A2D4 370 371 #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3 0x400A2D8 372 373 #define mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4 0x400A2DC 374 375 #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0 0x400A2E0 376 377 #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1 0x400A2E4 378 379 #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2 0x400A2E8 380 381 #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3 0x400A2EC 382 383 #define mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4 0x400A2F0 384 385 #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0 0x400A2F4 386 387 #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1 0x400A2F8 388 389 #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2 0x400A2FC 390 391 #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3 0x400A300 392 393 #define mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4 0x400A304 394 395 #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0 0x400A308 396 397 #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1 0x400A30C 398 399 #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2 0x400A310 400 401 #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3 0x400A314 402 403 #define mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4 0x400A318 404 405 #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0 0x400A31C 406 407 #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1 0x400A320 408 409 #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2 0x400A324 410 411 #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3 0x400A328 412 413 #define mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4 0x400A32C 414 415 #define mmDCORE0_TPC0_QM_CP_BARRIER_CFG 0x400A330 416 417 #define mmDCORE0_TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x400A334 418 419 #define mmDCORE0_TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x400A338 420 421 #define mmDCORE0_TPC0_QM_CP_LDMA_TSIZE_OFFSET 0x400A33C 422 423 #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_0 0x400A340 424 425 #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_1 0x400A344 426 427 #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_2 0x400A348 428 429 #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_3 0x400A34C 430 431 #define mmDCORE0_TPC0_QM_CP_CQ_PTR_LO_OFFSET_4 0x400A350 432 433 #define mmDCORE0_TPC0_QM_CP_STS_0 0x400A368 434 435 #define mmDCORE0_TPC0_QM_CP_STS_1 0x400A36C 436 437 #define mmDCORE0_TPC0_QM_CP_STS_2 0x400A370 438 439 #define mmDCORE0_TPC0_QM_CP_STS_3 0x400A374 440 441 #define mmDCORE0_TPC0_QM_CP_STS_4 0x400A378 442 443 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_0 0x400A37C 444 445 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_1 0x400A380 446 447 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_2 0x400A384 448 449 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_3 0x400A388 450 451 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_LO_4 0x400A38C 452 453 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_0 0x400A390 454 455 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_1 0x400A394 456 457 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_2 0x400A398 458 459 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_3 0x400A39C 460 461 #define mmDCORE0_TPC0_QM_CP_CURRENT_INST_HI_4 0x400A3A0 462 463 #define mmDCORE0_TPC0_QM_CP_PRED_0 0x400A3A4 464 465 #define mmDCORE0_TPC0_QM_CP_PRED_1 0x400A3A8 466 467 #define mmDCORE0_TPC0_QM_CP_PRED_2 0x400A3AC 468 469 #define mmDCORE0_TPC0_QM_CP_PRED_3 0x400A3B0 470 471 #define mmDCORE0_TPC0_QM_CP_PRED_4 0x400A3B4 472 473 #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_0 0x400A3B8 474 475 #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_1 0x400A3BC 476 477 #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_2 0x400A3C0 478 479 #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_3 0x400A3C4 480 481 #define mmDCORE0_TPC0_QM_CP_PRED_UPEN_4 0x400A3C8 482 483 #define mmDCORE0_TPC0_QM_CP_DBG_0_0 0x400A3CC 484 485 #define mmDCORE0_TPC0_QM_CP_DBG_0_1 0x400A3D0 486 487 #define mmDCORE0_TPC0_QM_CP_DBG_0_2 0x400A3D4 488 489 #define mmDCORE0_TPC0_QM_CP_DBG_0_3 0x400A3D8 490 491 #define mmDCORE0_TPC0_QM_CP_DBG_0_4 0x400A3DC 492 493 #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_0 0x400A3E0 494 495 #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_1 0x400A3E4 496 497 #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_2 0x400A3E8 498 499 #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_3 0x400A3EC 500 501 #define mmDCORE0_TPC0_QM_CP_CPDMA_UP_CRED_4 0x400A3F0 502 503 #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_0 0x400A3F4 504 505 #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_1 0x400A3F8 506 507 #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_2 0x400A3FC 508 509 #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_3 0x400A400 510 511 #define mmDCORE0_TPC0_QM_CP_IN_DATA_LO_4 0x400A404 512 513 #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_0 0x400A408 514 515 #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_1 0x400A40C 516 517 #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_2 0x400A410 518 519 #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_3 0x400A414 520 521 #define mmDCORE0_TPC0_QM_CP_IN_DATA_HI_4 0x400A418 522 523 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_0 0x400A41C 524 525 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_1 0x400A420 526 527 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_2 0x400A424 528 529 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_LO_3 0x400A428 530 531 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_0 0x400A42C 532 533 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_1 0x400A430 534 535 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_2 0x400A434 536 537 #define mmDCORE0_TPC0_QM_PQC_HBW_BASE_HI_3 0x400A438 538 539 #define mmDCORE0_TPC0_QM_PQC_SIZE_0 0x400A43C 540 541 #define mmDCORE0_TPC0_QM_PQC_SIZE_1 0x400A440 542 543 #define mmDCORE0_TPC0_QM_PQC_SIZE_2 0x400A444 544 545 #define mmDCORE0_TPC0_QM_PQC_SIZE_3 0x400A448 546 547 #define mmDCORE0_TPC0_QM_PQC_PI_0 0x400A44C 548 549 #define mmDCORE0_TPC0_QM_PQC_PI_1 0x400A450 550 551 #define mmDCORE0_TPC0_QM_PQC_PI_2 0x400A454 552 553 #define mmDCORE0_TPC0_QM_PQC_PI_3 0x400A458 554 555 #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_0 0x400A45C 556 557 #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_1 0x400A460 558 559 #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_2 0x400A464 560 561 #define mmDCORE0_TPC0_QM_PQC_LBW_WDATA_3 0x400A468 562 563 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_0 0x400A46C 564 565 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_1 0x400A470 566 567 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_2 0x400A474 568 569 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_LO_3 0x400A478 570 571 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_0 0x400A47C 572 573 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_1 0x400A480 574 575 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_2 0x400A484 576 577 #define mmDCORE0_TPC0_QM_PQC_LBW_BASE_HI_3 0x400A488 578 579 #define mmDCORE0_TPC0_QM_PQC_CFG 0x400A48C 580 581 #define mmDCORE0_TPC0_QM_PQC_SECURE_PUSH_IND 0x400A490 582 583 #define mmDCORE0_TPC0_QM_ARB_MASK 0x400A4A0 584 585 #define mmDCORE0_TPC0_QM_ARB_CFG_0 0x400A4A4 586 587 #define mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH 0x400A4A8 588 589 #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0 0x400A4AC 590 591 #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1 0x400A4B0 592 593 #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2 0x400A4B4 594 595 #define mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3 0x400A4B8 596 597 #define mmDCORE0_TPC0_QM_ARB_CFG_1 0x400A4BC 598 599 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_0 0x400A4C0 600 601 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_1 0x400A4C4 602 603 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_2 0x400A4C8 604 605 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_3 0x400A4CC 606 607 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_4 0x400A4D0 608 609 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_5 0x400A4D4 610 611 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_6 0x400A4D8 612 613 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_7 0x400A4DC 614 615 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_8 0x400A4E0 616 617 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_9 0x400A4E4 618 619 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_10 0x400A4E8 620 621 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_11 0x400A4EC 622 623 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_12 0x400A4F0 624 625 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_13 0x400A4F4 626 627 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_14 0x400A4F8 628 629 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_15 0x400A4FC 630 631 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_16 0x400A500 632 633 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_17 0x400A504 634 635 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_18 0x400A508 636 637 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_19 0x400A50C 638 639 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_20 0x400A510 640 641 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_21 0x400A514 642 643 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_22 0x400A518 644 645 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_23 0x400A51C 646 647 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_24 0x400A520 648 649 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_25 0x400A524 650 651 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_26 0x400A528 652 653 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_27 0x400A52C 654 655 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_28 0x400A530 656 657 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_29 0x400A534 658 659 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_30 0x400A538 660 661 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_31 0x400A53C 662 663 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_32 0x400A540 664 665 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_33 0x400A544 666 667 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_34 0x400A548 668 669 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_35 0x400A54C 670 671 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_36 0x400A550 672 673 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_37 0x400A554 674 675 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_38 0x400A558 676 677 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_39 0x400A55C 678 679 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_40 0x400A560 680 681 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_41 0x400A564 682 683 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_42 0x400A568 684 685 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_43 0x400A56C 686 687 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_44 0x400A570 688 689 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_45 0x400A574 690 691 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_46 0x400A578 692 693 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_47 0x400A57C 694 695 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_48 0x400A580 696 697 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_49 0x400A584 698 699 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_50 0x400A588 700 701 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_51 0x400A58C 702 703 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_52 0x400A590 704 705 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_53 0x400A594 706 707 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_54 0x400A598 708 709 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_55 0x400A59C 710 711 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_56 0x400A5A0 712 713 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_57 0x400A5A4 714 715 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_58 0x400A5A8 716 717 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_59 0x400A5AC 718 719 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_60 0x400A5B0 720 721 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_61 0x400A5B4 722 723 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_62 0x400A5B8 724 725 #define mmDCORE0_TPC0_QM_ARB_MST_AVAIL_CRED_63 0x400A5BC 726 727 #define mmDCORE0_TPC0_QM_ARB_MST_CRED_INC 0x400A5E0 728 729 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x400A5E4 730 731 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x400A5E8 732 733 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x400A5EC 734 735 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x400A5F0 736 737 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x400A5F4 738 739 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x400A5F8 740 741 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x400A5FC 742 743 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x400A600 744 745 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x400A604 746 747 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x400A608 748 749 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x400A60C 750 751 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x400A610 752 753 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x400A614 754 755 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x400A618 756 757 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x400A61C 758 759 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x400A620 760 761 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x400A624 762 763 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x400A628 764 765 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x400A62C 766 767 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x400A630 768 769 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x400A634 770 771 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x400A638 772 773 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x400A63C 774 775 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x400A640 776 777 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x400A644 778 779 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x400A648 780 781 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x400A64C 782 783 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x400A650 784 785 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x400A654 786 787 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x400A658 788 789 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x400A65C 790 791 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x400A660 792 793 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x400A664 794 795 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x400A668 796 797 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x400A66C 798 799 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x400A670 800 801 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x400A674 802 803 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x400A678 804 805 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x400A67C 806 807 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x400A680 808 809 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x400A684 810 811 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x400A688 812 813 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x400A68C 814 815 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x400A690 816 817 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x400A694 818 819 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x400A698 820 821 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x400A69C 822 823 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x400A6A0 824 825 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x400A6A4 826 827 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x400A6A8 828 829 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x400A6AC 830 831 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x400A6B0 832 833 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x400A6B4 834 835 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x400A6B8 836 837 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x400A6BC 838 839 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x400A6C0 840 841 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x400A6C4 842 843 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x400A6C8 844 845 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x400A6CC 846 847 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x400A6D0 848 849 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x400A6D4 850 851 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x400A6D8 852 853 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x400A6DC 854 855 #define mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x400A6E0 856 857 #define mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x400A704 858 859 #define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN 0x400A708 860 861 #define mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1 0x400A70C 862 863 #define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_WDT 0x400A710 864 865 #define mmDCORE0_TPC0_QM_ARB_SLV_ID 0x400A714 866 867 #define mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER 0x400A718 868 869 #define mmDCORE0_TPC0_QM_ARB_MSG_MAX_INFLIGHT 0x400A744 870 871 #define mmDCORE0_TPC0_QM_ARB_BASE_LO 0x400A754 872 873 #define mmDCORE0_TPC0_QM_ARB_BASE_HI 0x400A758 874 875 #define mmDCORE0_TPC0_QM_ARB_STATE_STS 0x400A780 876 877 #define mmDCORE0_TPC0_QM_ARB_CHOICE_FULLNESS_STS 0x400A784 878 879 #define mmDCORE0_TPC0_QM_ARB_MSG_STS 0x400A788 880 881 #define mmDCORE0_TPC0_QM_ARB_SLV_CHOICE_Q_HEAD 0x400A78C 882 883 #define mmDCORE0_TPC0_QM_ARB_ERR_CAUSE 0x400A79C 884 885 #define mmDCORE0_TPC0_QM_ARB_ERR_MSG_EN 0x400A7A0 886 887 #define mmDCORE0_TPC0_QM_ARB_ERR_STS_DRP 0x400A7A8 888 889 #define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS 0x400A7B0 890 891 #define mmDCORE0_TPC0_QM_ARB_MST_CRED_STS_1 0x400A7B4 892 893 #define mmDCORE0_TPC0_QM_CSMR_STRICT_PRIO_CFG 0x400A7FC 894 895 #define mmDCORE0_TPC0_QM_ARC_CQ_CFG0 0x400A800 896 897 #define mmDCORE0_TPC0_QM_ARC_CQ_CFG1 0x400A804 898 899 #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO 0x400A808 900 901 #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI 0x400A80C 902 903 #define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE 0x400A810 904 905 #define mmDCORE0_TPC0_QM_ARC_CQ_CTL 0x400A814 906 907 #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_STS 0x400A81C 908 909 #define mmDCORE0_TPC0_QM_ARC_CQ_STS0 0x400A820 910 911 #define mmDCORE0_TPC0_QM_ARC_CQ_STS1 0x400A824 912 913 #define mmDCORE0_TPC0_QM_ARC_CQ_TSIZE_STS 0x400A828 914 915 #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS 0x400A82C 916 917 #define mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS 0x400A830 918 919 #define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_HI 0x400A834 920 921 #define mmDCORE0_TPC0_QM_CP_WR_ARC_ADDR_LO 0x400A838 922 923 #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x400A83C 924 925 #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x400A840 926 927 #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_HI 0x400A844 928 929 #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO 0x400A848 930 931 #define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_HI 0x400A84C 932 933 #define mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO 0x400A850 934 935 #define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_HI 0x400A854 936 937 #define mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO 0x400A858 938 939 #define mmDCORE0_TPC0_QM_ADDR_OVRD 0x400A85C 940 941 #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0 0x400A860 942 943 #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1 0x400A864 944 945 #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2 0x400A868 946 947 #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3 0x400A86C 948 949 #define mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4 0x400A870 950 951 #define mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI 0x400A874 952 953 #define mmDCORE0_TPC0_QM_CQ_CTL_CI_0 0x400A878 954 955 #define mmDCORE0_TPC0_QM_CQ_CTL_CI_1 0x400A87C 956 957 #define mmDCORE0_TPC0_QM_CQ_CTL_CI_2 0x400A880 958 959 #define mmDCORE0_TPC0_QM_CQ_CTL_CI_3 0x400A884 960 961 #define mmDCORE0_TPC0_QM_CQ_CTL_CI_4 0x400A888 962 963 #define mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI 0x400A88C 964 965 #define mmDCORE0_TPC0_QM_CP_CFG 0x400A890 966 967 #define mmDCORE0_TPC0_QM_CP_EXT_SWITCH 0x400A894 968 969 #define mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET 0x400A898 970 971 #define mmDCORE0_TPC0_QM_CP_SWITCH_WD 0x400A89C 972 973 #define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_LO 0x400A8A4 974 975 #define mmDCORE0_TPC0_QM_ARC_LB_ADDR_BASE_HI 0x400A8A8 976 977 #define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_HI 0x400A8AC 978 979 #define mmDCORE0_TPC0_QM_ENGINE_BASE_ADDR_LO 0x400A8B0 980 981 #define mmDCORE0_TPC0_QM_ENGINE_ADDR_RANGE_SIZE 0x400A8B4 982 983 #define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_HI 0x400A8B8 984 985 #define mmDCORE0_TPC0_QM_QM_ARC_AUX_BASE_ADDR_LO 0x400A8BC 986 987 #define mmDCORE0_TPC0_QM_QM_BASE_ADDR_HI 0x400A8C0 988 989 #define mmDCORE0_TPC0_QM_QM_BASE_ADDR_LO 0x400A8C4 990 991 #define mmDCORE0_TPC0_QM_ARC_PQC_SECURE_PUSH_IND 0x400A8C8 992 993 #define mmDCORE0_TPC0_QM_PQC_STS_0_0 0x400A8D0 994 995 #define mmDCORE0_TPC0_QM_PQC_STS_0_1 0x400A8D4 996 997 #define mmDCORE0_TPC0_QM_PQC_STS_0_2 0x400A8D8 998 999 #define mmDCORE0_TPC0_QM_PQC_STS_0_3 0x400A8DC 1000 1001 #define mmDCORE0_TPC0_QM_PQC_STS_1_0 0x400A8E0 1002 1003 #define mmDCORE0_TPC0_QM_PQC_STS_1_1 0x400A8E4 1004 1005 #define mmDCORE0_TPC0_QM_PQC_STS_1_2 0x400A8E8 1006 1007 #define mmDCORE0_TPC0_QM_PQC_STS_1_3 0x400A8EC 1008 1009 #define mmDCORE0_TPC0_QM_SEI_STATUS 0x400A8F0 1010 1011 #define mmDCORE0_TPC0_QM_SEI_MASK 0x400A8F4 1012 1013 #define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_LO 0x400AD00 1014 1015 #define mmDCORE0_TPC0_QM_GLBL_ERR_ADDR_HI 0x400AD04 1016 1017 #define mmDCORE0_TPC0_QM_GLBL_ERR_WDATA 0x400AD08 1018 1019 #define mmDCORE0_TPC0_QM_L2H_MASK_LO 0x400AD14 1020 1021 #define mmDCORE0_TPC0_QM_L2H_MASK_HI 0x400AD18 1022 1023 #define mmDCORE0_TPC0_QM_L2H_CMPR_LO 0x400AD1C 1024 1025 #define mmDCORE0_TPC0_QM_L2H_CMPR_HI 0x400AD20 1026 1027 #define mmDCORE0_TPC0_QM_LOCAL_RANGE_BASE 0x400AD24 1028 1029 #define mmDCORE0_TPC0_QM_LOCAL_RANGE_SIZE 0x400AD28 1030 1031 #define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_1 0x400AD30 1032 1033 #define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_0 0x400AD34 1034 1035 #define mmDCORE0_TPC0_QM_LBW_WR_RATE_LIM_CFG_1 0x400AD38 1036 1037 #define mmDCORE0_TPC0_QM_HBW_RD_RATE_LIM_CFG_0 0x400AD3C 1038 1039 #define mmDCORE0_TPC0_QM_IND_GW_APB_CFG 0x400AD40 1040 1041 #define mmDCORE0_TPC0_QM_IND_GW_APB_WDATA 0x400AD44 1042 1043 #define mmDCORE0_TPC0_QM_IND_GW_APB_RDATA 0x400AD48 1044 1045 #define mmDCORE0_TPC0_QM_IND_GW_APB_STATUS 0x400AD4C 1046 1047 #define mmDCORE0_TPC0_QM_PERF_CNT_FREE_LO 0x400AD60 1048 1049 #define mmDCORE0_TPC0_QM_PERF_CNT_FREE_HI 0x400AD64 1050 1051 #define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_LO 0x400AD68 1052 1053 #define mmDCORE0_TPC0_QM_PERF_CNT_IDLE_HI 0x400AD6C 1054 1055 #define mmDCORE0_TPC0_QM_PERF_CNT_CFG 0x400AD70 1056 1057 #endif /* ASIC_REG_DCORE0_TPC0_QM_REGS_H_ */ 1058