1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_MME_QM_REGS_H_ 14 #define ASIC_REG_DCORE0_MME_QM_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_MME_QM 19 * (Prototype: QMAN) 20 ***************************************** 21 */ 22 23 #define mmDCORE0_MME_QM_GLBL_CFG0 0x40CA000 24 25 #define mmDCORE0_MME_QM_GLBL_CFG1 0x40CA004 26 27 #define mmDCORE0_MME_QM_GLBL_CFG2 0x40CA008 28 29 #define mmDCORE0_MME_QM_GLBL_ERR_CFG 0x40CA00C 30 31 #define mmDCORE0_MME_QM_GLBL_ERR_CFG1 0x40CA010 32 33 #define mmDCORE0_MME_QM_GLBL_ERR_ARC_HALT_EN 0x40CA014 34 35 #define mmDCORE0_MME_QM_GLBL_AXCACHE 0x40CA018 36 37 #define mmDCORE0_MME_QM_GLBL_STS0 0x40CA01C 38 39 #define mmDCORE0_MME_QM_GLBL_STS1 0x40CA020 40 41 #define mmDCORE0_MME_QM_GLBL_ERR_STS_0 0x40CA024 42 43 #define mmDCORE0_MME_QM_GLBL_ERR_STS_1 0x40CA028 44 45 #define mmDCORE0_MME_QM_GLBL_ERR_STS_2 0x40CA02C 46 47 #define mmDCORE0_MME_QM_GLBL_ERR_STS_3 0x40CA030 48 49 #define mmDCORE0_MME_QM_GLBL_ERR_STS_4 0x40CA034 50 51 #define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_0 0x40CA038 52 53 #define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_1 0x40CA03C 54 55 #define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_2 0x40CA040 56 57 #define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_3 0x40CA044 58 59 #define mmDCORE0_MME_QM_GLBL_ERR_MSG_EN_4 0x40CA048 60 61 #define mmDCORE0_MME_QM_GLBL_PROT 0x40CA04C 62 63 #define mmDCORE0_MME_QM_PQ_BASE_LO_0 0x40CA050 64 65 #define mmDCORE0_MME_QM_PQ_BASE_LO_1 0x40CA054 66 67 #define mmDCORE0_MME_QM_PQ_BASE_LO_2 0x40CA058 68 69 #define mmDCORE0_MME_QM_PQ_BASE_LO_3 0x40CA05C 70 71 #define mmDCORE0_MME_QM_PQ_BASE_HI_0 0x40CA060 72 73 #define mmDCORE0_MME_QM_PQ_BASE_HI_1 0x40CA064 74 75 #define mmDCORE0_MME_QM_PQ_BASE_HI_2 0x40CA068 76 77 #define mmDCORE0_MME_QM_PQ_BASE_HI_3 0x40CA06C 78 79 #define mmDCORE0_MME_QM_PQ_SIZE_0 0x40CA070 80 81 #define mmDCORE0_MME_QM_PQ_SIZE_1 0x40CA074 82 83 #define mmDCORE0_MME_QM_PQ_SIZE_2 0x40CA078 84 85 #define mmDCORE0_MME_QM_PQ_SIZE_3 0x40CA07C 86 87 #define mmDCORE0_MME_QM_PQ_PI_0 0x40CA080 88 89 #define mmDCORE0_MME_QM_PQ_PI_1 0x40CA084 90 91 #define mmDCORE0_MME_QM_PQ_PI_2 0x40CA088 92 93 #define mmDCORE0_MME_QM_PQ_PI_3 0x40CA08C 94 95 #define mmDCORE0_MME_QM_PQ_CI_0 0x40CA090 96 97 #define mmDCORE0_MME_QM_PQ_CI_1 0x40CA094 98 99 #define mmDCORE0_MME_QM_PQ_CI_2 0x40CA098 100 101 #define mmDCORE0_MME_QM_PQ_CI_3 0x40CA09C 102 103 #define mmDCORE0_MME_QM_PQ_CFG0_0 0x40CA0A0 104 105 #define mmDCORE0_MME_QM_PQ_CFG0_1 0x40CA0A4 106 107 #define mmDCORE0_MME_QM_PQ_CFG0_2 0x40CA0A8 108 109 #define mmDCORE0_MME_QM_PQ_CFG0_3 0x40CA0AC 110 111 #define mmDCORE0_MME_QM_PQ_CFG1_0 0x40CA0B0 112 113 #define mmDCORE0_MME_QM_PQ_CFG1_1 0x40CA0B4 114 115 #define mmDCORE0_MME_QM_PQ_CFG1_2 0x40CA0B8 116 117 #define mmDCORE0_MME_QM_PQ_CFG1_3 0x40CA0BC 118 119 #define mmDCORE0_MME_QM_PQ_STS0_0 0x40CA0C0 120 121 #define mmDCORE0_MME_QM_PQ_STS0_1 0x40CA0C4 122 123 #define mmDCORE0_MME_QM_PQ_STS0_2 0x40CA0C8 124 125 #define mmDCORE0_MME_QM_PQ_STS0_3 0x40CA0CC 126 127 #define mmDCORE0_MME_QM_PQ_STS1_0 0x40CA0D0 128 129 #define mmDCORE0_MME_QM_PQ_STS1_1 0x40CA0D4 130 131 #define mmDCORE0_MME_QM_PQ_STS1_2 0x40CA0D8 132 133 #define mmDCORE0_MME_QM_PQ_STS1_3 0x40CA0DC 134 135 #define mmDCORE0_MME_QM_CQ_CFG0_0 0x40CA0E0 136 137 #define mmDCORE0_MME_QM_CQ_CFG0_1 0x40CA0E4 138 139 #define mmDCORE0_MME_QM_CQ_CFG0_2 0x40CA0E8 140 141 #define mmDCORE0_MME_QM_CQ_CFG0_3 0x40CA0EC 142 143 #define mmDCORE0_MME_QM_CQ_CFG0_4 0x40CA0F0 144 145 #define mmDCORE0_MME_QM_CQ_STS0_0 0x40CA0F4 146 147 #define mmDCORE0_MME_QM_CQ_STS0_1 0x40CA0F8 148 149 #define mmDCORE0_MME_QM_CQ_STS0_2 0x40CA0FC 150 151 #define mmDCORE0_MME_QM_CQ_STS0_3 0x40CA100 152 153 #define mmDCORE0_MME_QM_CQ_STS0_4 0x40CA104 154 155 #define mmDCORE0_MME_QM_CQ_CFG1_0 0x40CA108 156 157 #define mmDCORE0_MME_QM_CQ_CFG1_1 0x40CA10C 158 159 #define mmDCORE0_MME_QM_CQ_CFG1_2 0x40CA110 160 161 #define mmDCORE0_MME_QM_CQ_CFG1_3 0x40CA114 162 163 #define mmDCORE0_MME_QM_CQ_CFG1_4 0x40CA118 164 165 #define mmDCORE0_MME_QM_CQ_STS1_0 0x40CA11C 166 167 #define mmDCORE0_MME_QM_CQ_STS1_1 0x40CA120 168 169 #define mmDCORE0_MME_QM_CQ_STS1_2 0x40CA124 170 171 #define mmDCORE0_MME_QM_CQ_STS1_3 0x40CA128 172 173 #define mmDCORE0_MME_QM_CQ_STS1_4 0x40CA12C 174 175 #define mmDCORE0_MME_QM_CQ_PTR_LO_0 0x40CA150 176 177 #define mmDCORE0_MME_QM_CQ_PTR_HI_0 0x40CA154 178 179 #define mmDCORE0_MME_QM_CQ_TSIZE_0 0x40CA158 180 181 #define mmDCORE0_MME_QM_CQ_CTL_0 0x40CA15C 182 183 #define mmDCORE0_MME_QM_CQ_PTR_LO_1 0x40CA160 184 185 #define mmDCORE0_MME_QM_CQ_PTR_HI_1 0x40CA164 186 187 #define mmDCORE0_MME_QM_CQ_TSIZE_1 0x40CA168 188 189 #define mmDCORE0_MME_QM_CQ_CTL_1 0x40CA16C 190 191 #define mmDCORE0_MME_QM_CQ_PTR_LO_2 0x40CA170 192 193 #define mmDCORE0_MME_QM_CQ_PTR_HI_2 0x40CA174 194 195 #define mmDCORE0_MME_QM_CQ_TSIZE_2 0x40CA178 196 197 #define mmDCORE0_MME_QM_CQ_CTL_2 0x40CA17C 198 199 #define mmDCORE0_MME_QM_CQ_PTR_LO_3 0x40CA180 200 201 #define mmDCORE0_MME_QM_CQ_PTR_HI_3 0x40CA184 202 203 #define mmDCORE0_MME_QM_CQ_TSIZE_3 0x40CA188 204 205 #define mmDCORE0_MME_QM_CQ_CTL_3 0x40CA18C 206 207 #define mmDCORE0_MME_QM_CQ_PTR_LO_4 0x40CA190 208 209 #define mmDCORE0_MME_QM_CQ_PTR_HI_4 0x40CA194 210 211 #define mmDCORE0_MME_QM_CQ_TSIZE_4 0x40CA198 212 213 #define mmDCORE0_MME_QM_CQ_CTL_4 0x40CA19C 214 215 #define mmDCORE0_MME_QM_CQ_TSIZE_STS_0 0x40CA1A0 216 217 #define mmDCORE0_MME_QM_CQ_TSIZE_STS_1 0x40CA1A4 218 219 #define mmDCORE0_MME_QM_CQ_TSIZE_STS_2 0x40CA1A8 220 221 #define mmDCORE0_MME_QM_CQ_TSIZE_STS_3 0x40CA1AC 222 223 #define mmDCORE0_MME_QM_CQ_TSIZE_STS_4 0x40CA1B0 224 225 #define mmDCORE0_MME_QM_CQ_PTR_LO_STS_0 0x40CA1B4 226 227 #define mmDCORE0_MME_QM_CQ_PTR_LO_STS_1 0x40CA1B8 228 229 #define mmDCORE0_MME_QM_CQ_PTR_LO_STS_2 0x40CA1BC 230 231 #define mmDCORE0_MME_QM_CQ_PTR_LO_STS_3 0x40CA1C0 232 233 #define mmDCORE0_MME_QM_CQ_PTR_LO_STS_4 0x40CA1C4 234 235 #define mmDCORE0_MME_QM_CQ_PTR_HI_STS_0 0x40CA1C8 236 237 #define mmDCORE0_MME_QM_CQ_PTR_HI_STS_1 0x40CA1CC 238 239 #define mmDCORE0_MME_QM_CQ_PTR_HI_STS_2 0x40CA1D0 240 241 #define mmDCORE0_MME_QM_CQ_PTR_HI_STS_3 0x40CA1D4 242 243 #define mmDCORE0_MME_QM_CQ_PTR_HI_STS_4 0x40CA1D8 244 245 #define mmDCORE0_MME_QM_CQ_IFIFO_STS_0 0x40CA1DC 246 247 #define mmDCORE0_MME_QM_CQ_IFIFO_STS_1 0x40CA1E0 248 249 #define mmDCORE0_MME_QM_CQ_IFIFO_STS_2 0x40CA1E4 250 251 #define mmDCORE0_MME_QM_CQ_IFIFO_STS_3 0x40CA1E8 252 253 #define mmDCORE0_MME_QM_CQ_IFIFO_STS_4 0x40CA1EC 254 255 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0 0x40CA1F0 256 257 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1 0x40CA1F4 258 259 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2 0x40CA1F8 260 261 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3 0x40CA1FC 262 263 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4 0x40CA200 264 265 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0 0x40CA204 266 267 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1 0x40CA208 268 269 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2 0x40CA20C 270 271 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3 0x40CA210 272 273 #define mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4 0x40CA214 274 275 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0 0x40CA218 276 277 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1 0x40CA21C 278 279 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2 0x40CA220 280 281 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3 0x40CA224 282 283 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4 0x40CA228 284 285 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0 0x40CA22C 286 287 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1 0x40CA230 288 289 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2 0x40CA234 290 291 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3 0x40CA238 292 293 #define mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4 0x40CA23C 294 295 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0 0x40CA240 296 297 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1 0x40CA244 298 299 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2 0x40CA248 300 301 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3 0x40CA24C 302 303 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4 0x40CA250 304 305 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0 0x40CA254 306 307 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1 0x40CA258 308 309 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2 0x40CA25C 310 311 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3 0x40CA260 312 313 #define mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4 0x40CA264 314 315 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0 0x40CA268 316 317 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1 0x40CA26C 318 319 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2 0x40CA270 320 321 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3 0x40CA274 322 323 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4 0x40CA278 324 325 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0 0x40CA27C 326 327 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1 0x40CA280 328 329 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2 0x40CA284 330 331 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3 0x40CA288 332 333 #define mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4 0x40CA28C 334 335 #define mmDCORE0_MME_QM_CP_FENCE0_RDATA_0 0x40CA290 336 337 #define mmDCORE0_MME_QM_CP_FENCE0_RDATA_1 0x40CA294 338 339 #define mmDCORE0_MME_QM_CP_FENCE0_RDATA_2 0x40CA298 340 341 #define mmDCORE0_MME_QM_CP_FENCE0_RDATA_3 0x40CA29C 342 343 #define mmDCORE0_MME_QM_CP_FENCE0_RDATA_4 0x40CA2A0 344 345 #define mmDCORE0_MME_QM_CP_FENCE1_RDATA_0 0x40CA2A4 346 347 #define mmDCORE0_MME_QM_CP_FENCE1_RDATA_1 0x40CA2A8 348 349 #define mmDCORE0_MME_QM_CP_FENCE1_RDATA_2 0x40CA2AC 350 351 #define mmDCORE0_MME_QM_CP_FENCE1_RDATA_3 0x40CA2B0 352 353 #define mmDCORE0_MME_QM_CP_FENCE1_RDATA_4 0x40CA2B4 354 355 #define mmDCORE0_MME_QM_CP_FENCE2_RDATA_0 0x40CA2B8 356 357 #define mmDCORE0_MME_QM_CP_FENCE2_RDATA_1 0x40CA2BC 358 359 #define mmDCORE0_MME_QM_CP_FENCE2_RDATA_2 0x40CA2C0 360 361 #define mmDCORE0_MME_QM_CP_FENCE2_RDATA_3 0x40CA2C4 362 363 #define mmDCORE0_MME_QM_CP_FENCE2_RDATA_4 0x40CA2C8 364 365 #define mmDCORE0_MME_QM_CP_FENCE3_RDATA_0 0x40CA2CC 366 367 #define mmDCORE0_MME_QM_CP_FENCE3_RDATA_1 0x40CA2D0 368 369 #define mmDCORE0_MME_QM_CP_FENCE3_RDATA_2 0x40CA2D4 370 371 #define mmDCORE0_MME_QM_CP_FENCE3_RDATA_3 0x40CA2D8 372 373 #define mmDCORE0_MME_QM_CP_FENCE3_RDATA_4 0x40CA2DC 374 375 #define mmDCORE0_MME_QM_CP_FENCE0_CNT_0 0x40CA2E0 376 377 #define mmDCORE0_MME_QM_CP_FENCE0_CNT_1 0x40CA2E4 378 379 #define mmDCORE0_MME_QM_CP_FENCE0_CNT_2 0x40CA2E8 380 381 #define mmDCORE0_MME_QM_CP_FENCE0_CNT_3 0x40CA2EC 382 383 #define mmDCORE0_MME_QM_CP_FENCE0_CNT_4 0x40CA2F0 384 385 #define mmDCORE0_MME_QM_CP_FENCE1_CNT_0 0x40CA2F4 386 387 #define mmDCORE0_MME_QM_CP_FENCE1_CNT_1 0x40CA2F8 388 389 #define mmDCORE0_MME_QM_CP_FENCE1_CNT_2 0x40CA2FC 390 391 #define mmDCORE0_MME_QM_CP_FENCE1_CNT_3 0x40CA300 392 393 #define mmDCORE0_MME_QM_CP_FENCE1_CNT_4 0x40CA304 394 395 #define mmDCORE0_MME_QM_CP_FENCE2_CNT_0 0x40CA308 396 397 #define mmDCORE0_MME_QM_CP_FENCE2_CNT_1 0x40CA30C 398 399 #define mmDCORE0_MME_QM_CP_FENCE2_CNT_2 0x40CA310 400 401 #define mmDCORE0_MME_QM_CP_FENCE2_CNT_3 0x40CA314 402 403 #define mmDCORE0_MME_QM_CP_FENCE2_CNT_4 0x40CA318 404 405 #define mmDCORE0_MME_QM_CP_FENCE3_CNT_0 0x40CA31C 406 407 #define mmDCORE0_MME_QM_CP_FENCE3_CNT_1 0x40CA320 408 409 #define mmDCORE0_MME_QM_CP_FENCE3_CNT_2 0x40CA324 410 411 #define mmDCORE0_MME_QM_CP_FENCE3_CNT_3 0x40CA328 412 413 #define mmDCORE0_MME_QM_CP_FENCE3_CNT_4 0x40CA32C 414 415 #define mmDCORE0_MME_QM_CP_BARRIER_CFG 0x40CA330 416 417 #define mmDCORE0_MME_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0x40CA334 418 419 #define mmDCORE0_MME_QM_CP_LDMA_DST_BASE_LO_OFFSET 0x40CA338 420 421 #define mmDCORE0_MME_QM_CP_LDMA_TSIZE_OFFSET 0x40CA33C 422 423 #define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_0 0x40CA340 424 425 #define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_1 0x40CA344 426 427 #define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_2 0x40CA348 428 429 #define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_3 0x40CA34C 430 431 #define mmDCORE0_MME_QM_CP_CQ_PTR_LO_OFFSET_4 0x40CA350 432 433 #define mmDCORE0_MME_QM_CP_STS_0 0x40CA368 434 435 #define mmDCORE0_MME_QM_CP_STS_1 0x40CA36C 436 437 #define mmDCORE0_MME_QM_CP_STS_2 0x40CA370 438 439 #define mmDCORE0_MME_QM_CP_STS_3 0x40CA374 440 441 #define mmDCORE0_MME_QM_CP_STS_4 0x40CA378 442 443 #define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_0 0x40CA37C 444 445 #define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_1 0x40CA380 446 447 #define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_2 0x40CA384 448 449 #define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_3 0x40CA388 450 451 #define mmDCORE0_MME_QM_CP_CURRENT_INST_LO_4 0x40CA38C 452 453 #define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_0 0x40CA390 454 455 #define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_1 0x40CA394 456 457 #define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_2 0x40CA398 458 459 #define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_3 0x40CA39C 460 461 #define mmDCORE0_MME_QM_CP_CURRENT_INST_HI_4 0x40CA3A0 462 463 #define mmDCORE0_MME_QM_CP_PRED_0 0x40CA3A4 464 465 #define mmDCORE0_MME_QM_CP_PRED_1 0x40CA3A8 466 467 #define mmDCORE0_MME_QM_CP_PRED_2 0x40CA3AC 468 469 #define mmDCORE0_MME_QM_CP_PRED_3 0x40CA3B0 470 471 #define mmDCORE0_MME_QM_CP_PRED_4 0x40CA3B4 472 473 #define mmDCORE0_MME_QM_CP_PRED_UPEN_0 0x40CA3B8 474 475 #define mmDCORE0_MME_QM_CP_PRED_UPEN_1 0x40CA3BC 476 477 #define mmDCORE0_MME_QM_CP_PRED_UPEN_2 0x40CA3C0 478 479 #define mmDCORE0_MME_QM_CP_PRED_UPEN_3 0x40CA3C4 480 481 #define mmDCORE0_MME_QM_CP_PRED_UPEN_4 0x40CA3C8 482 483 #define mmDCORE0_MME_QM_CP_DBG_0_0 0x40CA3CC 484 485 #define mmDCORE0_MME_QM_CP_DBG_0_1 0x40CA3D0 486 487 #define mmDCORE0_MME_QM_CP_DBG_0_2 0x40CA3D4 488 489 #define mmDCORE0_MME_QM_CP_DBG_0_3 0x40CA3D8 490 491 #define mmDCORE0_MME_QM_CP_DBG_0_4 0x40CA3DC 492 493 #define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_0 0x40CA3E0 494 495 #define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_1 0x40CA3E4 496 497 #define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_2 0x40CA3E8 498 499 #define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_3 0x40CA3EC 500 501 #define mmDCORE0_MME_QM_CP_CPDMA_UP_CRED_4 0x40CA3F0 502 503 #define mmDCORE0_MME_QM_CP_IN_DATA_LO_0 0x40CA3F4 504 505 #define mmDCORE0_MME_QM_CP_IN_DATA_LO_1 0x40CA3F8 506 507 #define mmDCORE0_MME_QM_CP_IN_DATA_LO_2 0x40CA3FC 508 509 #define mmDCORE0_MME_QM_CP_IN_DATA_LO_3 0x40CA400 510 511 #define mmDCORE0_MME_QM_CP_IN_DATA_LO_4 0x40CA404 512 513 #define mmDCORE0_MME_QM_CP_IN_DATA_HI_0 0x40CA408 514 515 #define mmDCORE0_MME_QM_CP_IN_DATA_HI_1 0x40CA40C 516 517 #define mmDCORE0_MME_QM_CP_IN_DATA_HI_2 0x40CA410 518 519 #define mmDCORE0_MME_QM_CP_IN_DATA_HI_3 0x40CA414 520 521 #define mmDCORE0_MME_QM_CP_IN_DATA_HI_4 0x40CA418 522 523 #define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_0 0x40CA41C 524 525 #define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_1 0x40CA420 526 527 #define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_2 0x40CA424 528 529 #define mmDCORE0_MME_QM_PQC_HBW_BASE_LO_3 0x40CA428 530 531 #define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_0 0x40CA42C 532 533 #define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_1 0x40CA430 534 535 #define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_2 0x40CA434 536 537 #define mmDCORE0_MME_QM_PQC_HBW_BASE_HI_3 0x40CA438 538 539 #define mmDCORE0_MME_QM_PQC_SIZE_0 0x40CA43C 540 541 #define mmDCORE0_MME_QM_PQC_SIZE_1 0x40CA440 542 543 #define mmDCORE0_MME_QM_PQC_SIZE_2 0x40CA444 544 545 #define mmDCORE0_MME_QM_PQC_SIZE_3 0x40CA448 546 547 #define mmDCORE0_MME_QM_PQC_PI_0 0x40CA44C 548 549 #define mmDCORE0_MME_QM_PQC_PI_1 0x40CA450 550 551 #define mmDCORE0_MME_QM_PQC_PI_2 0x40CA454 552 553 #define mmDCORE0_MME_QM_PQC_PI_3 0x40CA458 554 555 #define mmDCORE0_MME_QM_PQC_LBW_WDATA_0 0x40CA45C 556 557 #define mmDCORE0_MME_QM_PQC_LBW_WDATA_1 0x40CA460 558 559 #define mmDCORE0_MME_QM_PQC_LBW_WDATA_2 0x40CA464 560 561 #define mmDCORE0_MME_QM_PQC_LBW_WDATA_3 0x40CA468 562 563 #define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_0 0x40CA46C 564 565 #define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_1 0x40CA470 566 567 #define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_2 0x40CA474 568 569 #define mmDCORE0_MME_QM_PQC_LBW_BASE_LO_3 0x40CA478 570 571 #define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_0 0x40CA47C 572 573 #define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_1 0x40CA480 574 575 #define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_2 0x40CA484 576 577 #define mmDCORE0_MME_QM_PQC_LBW_BASE_HI_3 0x40CA488 578 579 #define mmDCORE0_MME_QM_PQC_CFG 0x40CA48C 580 581 #define mmDCORE0_MME_QM_PQC_SECURE_PUSH_IND 0x40CA490 582 583 #define mmDCORE0_MME_QM_ARB_MASK 0x40CA4A0 584 585 #define mmDCORE0_MME_QM_ARB_CFG_0 0x40CA4A4 586 587 #define mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH 0x40CA4A8 588 589 #define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0 0x40CA4AC 590 591 #define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1 0x40CA4B0 592 593 #define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2 0x40CA4B4 594 595 #define mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3 0x40CA4B8 596 597 #define mmDCORE0_MME_QM_ARB_CFG_1 0x40CA4BC 598 599 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_0 0x40CA4C0 600 601 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_1 0x40CA4C4 602 603 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_2 0x40CA4C8 604 605 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_3 0x40CA4CC 606 607 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_4 0x40CA4D0 608 609 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_5 0x40CA4D4 610 611 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_6 0x40CA4D8 612 613 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_7 0x40CA4DC 614 615 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_8 0x40CA4E0 616 617 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_9 0x40CA4E4 618 619 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_10 0x40CA4E8 620 621 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_11 0x40CA4EC 622 623 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_12 0x40CA4F0 624 625 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_13 0x40CA4F4 626 627 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_14 0x40CA4F8 628 629 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_15 0x40CA4FC 630 631 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_16 0x40CA500 632 633 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_17 0x40CA504 634 635 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_18 0x40CA508 636 637 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_19 0x40CA50C 638 639 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_20 0x40CA510 640 641 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_21 0x40CA514 642 643 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_22 0x40CA518 644 645 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_23 0x40CA51C 646 647 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_24 0x40CA520 648 649 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_25 0x40CA524 650 651 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_26 0x40CA528 652 653 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_27 0x40CA52C 654 655 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_28 0x40CA530 656 657 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_29 0x40CA534 658 659 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_30 0x40CA538 660 661 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_31 0x40CA53C 662 663 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_32 0x40CA540 664 665 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_33 0x40CA544 666 667 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_34 0x40CA548 668 669 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_35 0x40CA54C 670 671 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_36 0x40CA550 672 673 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_37 0x40CA554 674 675 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_38 0x40CA558 676 677 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_39 0x40CA55C 678 679 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_40 0x40CA560 680 681 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_41 0x40CA564 682 683 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_42 0x40CA568 684 685 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_43 0x40CA56C 686 687 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_44 0x40CA570 688 689 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_45 0x40CA574 690 691 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_46 0x40CA578 692 693 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_47 0x40CA57C 694 695 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_48 0x40CA580 696 697 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_49 0x40CA584 698 699 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_50 0x40CA588 700 701 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_51 0x40CA58C 702 703 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_52 0x40CA590 704 705 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_53 0x40CA594 706 707 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_54 0x40CA598 708 709 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_55 0x40CA59C 710 711 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_56 0x40CA5A0 712 713 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_57 0x40CA5A4 714 715 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_58 0x40CA5A8 716 717 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_59 0x40CA5AC 718 719 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_60 0x40CA5B0 720 721 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_61 0x40CA5B4 722 723 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_62 0x40CA5B8 724 725 #define mmDCORE0_MME_QM_ARB_MST_AVAIL_CRED_63 0x40CA5BC 726 727 #define mmDCORE0_MME_QM_ARB_MST_CRED_INC 0x40CA5E0 728 729 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0 0x40CA5E4 730 731 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1 0x40CA5E8 732 733 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2 0x40CA5EC 734 735 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3 0x40CA5F0 736 737 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4 0x40CA5F4 738 739 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5 0x40CA5F8 740 741 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6 0x40CA5FC 742 743 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7 0x40CA600 744 745 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8 0x40CA604 746 747 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9 0x40CA608 748 749 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10 0x40CA60C 750 751 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11 0x40CA610 752 753 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12 0x40CA614 754 755 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13 0x40CA618 756 757 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14 0x40CA61C 758 759 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15 0x40CA620 760 761 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16 0x40CA624 762 763 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17 0x40CA628 764 765 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18 0x40CA62C 766 767 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19 0x40CA630 768 769 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20 0x40CA634 770 771 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21 0x40CA638 772 773 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22 0x40CA63C 774 775 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23 0x40CA640 776 777 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24 0x40CA644 778 779 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25 0x40CA648 780 781 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26 0x40CA64C 782 783 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27 0x40CA650 784 785 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28 0x40CA654 786 787 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29 0x40CA658 788 789 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30 0x40CA65C 790 791 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31 0x40CA660 792 793 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32 0x40CA664 794 795 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33 0x40CA668 796 797 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34 0x40CA66C 798 799 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35 0x40CA670 800 801 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36 0x40CA674 802 803 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37 0x40CA678 804 805 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38 0x40CA67C 806 807 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39 0x40CA680 808 809 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40 0x40CA684 810 811 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41 0x40CA688 812 813 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42 0x40CA68C 814 815 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43 0x40CA690 816 817 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44 0x40CA694 818 819 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45 0x40CA698 820 821 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46 0x40CA69C 822 823 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47 0x40CA6A0 824 825 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48 0x40CA6A4 826 827 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49 0x40CA6A8 828 829 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50 0x40CA6AC 830 831 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51 0x40CA6B0 832 833 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52 0x40CA6B4 834 835 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53 0x40CA6B8 836 837 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54 0x40CA6BC 838 839 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55 0x40CA6C0 840 841 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56 0x40CA6C4 842 843 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57 0x40CA6C8 844 845 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58 0x40CA6CC 846 847 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59 0x40CA6D0 848 849 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60 0x40CA6D4 850 851 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61 0x40CA6D8 852 853 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62 0x40CA6DC 854 855 #define mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63 0x40CA6E0 856 857 #define mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x40CA704 858 859 #define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN 0x40CA708 860 861 #define mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1 0x40CA70C 862 863 #define mmDCORE0_MME_QM_ARB_SLV_CHOICE_WDT 0x40CA710 864 865 #define mmDCORE0_MME_QM_ARB_SLV_ID 0x40CA714 866 867 #define mmDCORE0_MME_QM_ARB_MST_QUIET_PER 0x40CA718 868 869 #define mmDCORE0_MME_QM_ARB_MSG_MAX_INFLIGHT 0x40CA744 870 871 #define mmDCORE0_MME_QM_ARB_BASE_LO 0x40CA754 872 873 #define mmDCORE0_MME_QM_ARB_BASE_HI 0x40CA758 874 875 #define mmDCORE0_MME_QM_ARB_STATE_STS 0x40CA780 876 877 #define mmDCORE0_MME_QM_ARB_CHOICE_FULLNESS_STS 0x40CA784 878 879 #define mmDCORE0_MME_QM_ARB_MSG_STS 0x40CA788 880 881 #define mmDCORE0_MME_QM_ARB_SLV_CHOICE_Q_HEAD 0x40CA78C 882 883 #define mmDCORE0_MME_QM_ARB_ERR_CAUSE 0x40CA79C 884 885 #define mmDCORE0_MME_QM_ARB_ERR_MSG_EN 0x40CA7A0 886 887 #define mmDCORE0_MME_QM_ARB_ERR_STS_DRP 0x40CA7A8 888 889 #define mmDCORE0_MME_QM_ARB_MST_CRED_STS 0x40CA7B0 890 891 #define mmDCORE0_MME_QM_ARB_MST_CRED_STS_1 0x40CA7B4 892 893 #define mmDCORE0_MME_QM_CSMR_STRICT_PRIO_CFG 0x40CA7FC 894 895 #define mmDCORE0_MME_QM_ARC_CQ_CFG0 0x40CA800 896 897 #define mmDCORE0_MME_QM_ARC_CQ_CFG1 0x40CA804 898 899 #define mmDCORE0_MME_QM_ARC_CQ_PTR_LO 0x40CA808 900 901 #define mmDCORE0_MME_QM_ARC_CQ_PTR_HI 0x40CA80C 902 903 #define mmDCORE0_MME_QM_ARC_CQ_TSIZE 0x40CA810 904 905 #define mmDCORE0_MME_QM_ARC_CQ_CTL 0x40CA814 906 907 #define mmDCORE0_MME_QM_ARC_CQ_IFIFO_STS 0x40CA81C 908 909 #define mmDCORE0_MME_QM_ARC_CQ_STS0 0x40CA820 910 911 #define mmDCORE0_MME_QM_ARC_CQ_STS1 0x40CA824 912 913 #define mmDCORE0_MME_QM_ARC_CQ_TSIZE_STS 0x40CA828 914 915 #define mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS 0x40CA82C 916 917 #define mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS 0x40CA830 918 919 #define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_HI 0x40CA834 920 921 #define mmDCORE0_MME_QM_CP_WR_ARC_ADDR_LO 0x40CA838 922 923 #define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_HI 0x40CA83C 924 925 #define mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO 0x40CA840 926 927 #define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_HI 0x40CA844 928 929 #define mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO 0x40CA848 930 931 #define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_HI 0x40CA84C 932 933 #define mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO 0x40CA850 934 935 #define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_HI 0x40CA854 936 937 #define mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 0x40CA858 938 939 #define mmDCORE0_MME_QM_ADDR_OVRD 0x40CA85C 940 941 #define mmDCORE0_MME_QM_CQ_IFIFO_CI_0 0x40CA860 942 943 #define mmDCORE0_MME_QM_CQ_IFIFO_CI_1 0x40CA864 944 945 #define mmDCORE0_MME_QM_CQ_IFIFO_CI_2 0x40CA868 946 947 #define mmDCORE0_MME_QM_CQ_IFIFO_CI_3 0x40CA86C 948 949 #define mmDCORE0_MME_QM_CQ_IFIFO_CI_4 0x40CA870 950 951 #define mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI 0x40CA874 952 953 #define mmDCORE0_MME_QM_CQ_CTL_CI_0 0x40CA878 954 955 #define mmDCORE0_MME_QM_CQ_CTL_CI_1 0x40CA87C 956 957 #define mmDCORE0_MME_QM_CQ_CTL_CI_2 0x40CA880 958 959 #define mmDCORE0_MME_QM_CQ_CTL_CI_3 0x40CA884 960 961 #define mmDCORE0_MME_QM_CQ_CTL_CI_4 0x40CA888 962 963 #define mmDCORE0_MME_QM_ARC_CQ_CTL_CI 0x40CA88C 964 965 #define mmDCORE0_MME_QM_CP_CFG 0x40CA890 966 967 #define mmDCORE0_MME_QM_CP_EXT_SWITCH 0x40CA894 968 969 #define mmDCORE0_MME_QM_CP_SWITCH_WD_SET 0x40CA898 970 971 #define mmDCORE0_MME_QM_CP_SWITCH_WD 0x40CA89C 972 973 #define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_LO 0x40CA8A4 974 975 #define mmDCORE0_MME_QM_ARC_LB_ADDR_BASE_HI 0x40CA8A8 976 977 #define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_HI 0x40CA8AC 978 979 #define mmDCORE0_MME_QM_ENGINE_BASE_ADDR_LO 0x40CA8B0 980 981 #define mmDCORE0_MME_QM_ENGINE_ADDR_RANGE_SIZE 0x40CA8B4 982 983 #define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_HI 0x40CA8B8 984 985 #define mmDCORE0_MME_QM_QM_ARC_AUX_BASE_ADDR_LO 0x40CA8BC 986 987 #define mmDCORE0_MME_QM_QM_BASE_ADDR_HI 0x40CA8C0 988 989 #define mmDCORE0_MME_QM_QM_BASE_ADDR_LO 0x40CA8C4 990 991 #define mmDCORE0_MME_QM_ARC_PQC_SECURE_PUSH_IND 0x40CA8C8 992 993 #define mmDCORE0_MME_QM_PQC_STS_0_0 0x40CA8D0 994 995 #define mmDCORE0_MME_QM_PQC_STS_0_1 0x40CA8D4 996 997 #define mmDCORE0_MME_QM_PQC_STS_0_2 0x40CA8D8 998 999 #define mmDCORE0_MME_QM_PQC_STS_0_3 0x40CA8DC 1000 1001 #define mmDCORE0_MME_QM_PQC_STS_1_0 0x40CA8E0 1002 1003 #define mmDCORE0_MME_QM_PQC_STS_1_1 0x40CA8E4 1004 1005 #define mmDCORE0_MME_QM_PQC_STS_1_2 0x40CA8E8 1006 1007 #define mmDCORE0_MME_QM_PQC_STS_1_3 0x40CA8EC 1008 1009 #define mmDCORE0_MME_QM_SEI_STATUS 0x40CA8F0 1010 1011 #define mmDCORE0_MME_QM_SEI_MASK 0x40CA8F4 1012 1013 #define mmDCORE0_MME_QM_GLBL_ERR_ADDR_LO 0x40CAD00 1014 1015 #define mmDCORE0_MME_QM_GLBL_ERR_ADDR_HI 0x40CAD04 1016 1017 #define mmDCORE0_MME_QM_GLBL_ERR_WDATA 0x40CAD08 1018 1019 #define mmDCORE0_MME_QM_L2H_MASK_LO 0x40CAD14 1020 1021 #define mmDCORE0_MME_QM_L2H_MASK_HI 0x40CAD18 1022 1023 #define mmDCORE0_MME_QM_L2H_CMPR_LO 0x40CAD1C 1024 1025 #define mmDCORE0_MME_QM_L2H_CMPR_HI 0x40CAD20 1026 1027 #define mmDCORE0_MME_QM_LOCAL_RANGE_BASE 0x40CAD24 1028 1029 #define mmDCORE0_MME_QM_LOCAL_RANGE_SIZE 0x40CAD28 1030 1031 #define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_1 0x40CAD30 1032 1033 #define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_0 0x40CAD34 1034 1035 #define mmDCORE0_MME_QM_LBW_WR_RATE_LIM_CFG_1 0x40CAD38 1036 1037 #define mmDCORE0_MME_QM_HBW_RD_RATE_LIM_CFG_0 0x40CAD3C 1038 1039 #define mmDCORE0_MME_QM_IND_GW_APB_CFG 0x40CAD40 1040 1041 #define mmDCORE0_MME_QM_IND_GW_APB_WDATA 0x40CAD44 1042 1043 #define mmDCORE0_MME_QM_IND_GW_APB_RDATA 0x40CAD48 1044 1045 #define mmDCORE0_MME_QM_IND_GW_APB_STATUS 0x40CAD4C 1046 1047 #define mmDCORE0_MME_QM_PERF_CNT_FREE_LO 0x40CAD60 1048 1049 #define mmDCORE0_MME_QM_PERF_CNT_FREE_HI 0x40CAD64 1050 1051 #define mmDCORE0_MME_QM_PERF_CNT_IDLE_LO 0x40CAD68 1052 1053 #define mmDCORE0_MME_QM_PERF_CNT_IDLE_HI 0x40CAD6C 1054 1055 #define mmDCORE0_MME_QM_PERF_CNT_CFG 0x40CAD70 1056 1057 #endif /* ASIC_REG_DCORE0_MME_QM_REGS_H_ */ 1058