1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ 14 #define ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ 15 16 /* 17 ***************************************** 18 * DCORE0_MME_CTRL_LO 19 * (Prototype: MME_CTRL_LO) 20 ***************************************** 21 */ 22 23 #define mmDCORE0_MME_CTRL_LO_ARCH_STATUS 0x40CB000 24 25 #define mmDCORE0_MME_CTRL_LO_CMD 0x40CB004 26 27 #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x40CB148 28 29 #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x40CB14C 30 31 #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x40CB150 32 33 #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x40CB154 34 35 #define mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x40CB158 36 37 #define mmDCORE0_MME_CTRL_LO_ARCH_A_SS 0x40CB224 38 39 #define mmDCORE0_MME_CTRL_LO_ARCH_B_SS 0x40CB228 40 41 #define mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS 0x40CB27C 42 43 #define mmDCORE0_MME_CTRL_LO_QM_STALL 0x40CB400 44 45 #define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_LO 0x40CB404 46 47 #define mmDCORE0_MME_CTRL_LO_LOG_SHADOW_HI 0x40CB408 48 49 #define mmDCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x40CB40C 50 51 #define mmDCORE0_MME_CTRL_LO_REDUN 0x40CB410 52 53 #define mmDCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x40CB414 54 55 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x40CB418 56 57 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x40CB41C 58 59 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x40CB420 60 61 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x40CB424 62 63 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x40CB428 64 65 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x40CB42C 66 67 #define mmDCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x40CB430 68 69 #define mmDCORE0_MME_CTRL_LO_PCU_RL_DESC0 0x40CB434 70 71 #define mmDCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x40CB438 72 73 #define mmDCORE0_MME_CTRL_LO_PCU_RL_TH 0x40CB43C 74 75 #define mmDCORE0_MME_CTRL_LO_PCU_RL_MIN 0x40CB440 76 77 #define mmDCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN 0x40CB444 78 79 #define mmDCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x40CB448 80 81 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x40CB44C 82 83 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x40CB450 84 85 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x40CB454 86 87 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x40CB458 88 89 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_F8 0x40CB45C 90 91 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x40CB460 92 93 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x40CB464 94 95 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x40CB468 96 97 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x40CB46C 98 99 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x40CB470 100 101 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x40CB474 102 103 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x40CB478 104 105 #define mmDCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x40CB47C 106 107 #define mmDCORE0_MME_CTRL_LO_PROT 0x40CB480 108 109 #define mmDCORE0_MME_CTRL_LO_EU 0x40CB484 110 111 #define mmDCORE0_MME_CTRL_LO_SBTE 0x40CB488 112 113 #define mmDCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x40CB48C 114 115 #define mmDCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x40CB490 116 117 #define mmDCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC 0x40CB494 118 119 #define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x40CB498 120 121 #define mmDCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x40CB49C 122 123 #define mmDCORE0_MME_CTRL_LO_EU_ISOLATION_DIS 0x40CB4A0 124 125 #define mmDCORE0_MME_CTRL_LO_QM_SLV_CLK_EN 0x40CB4A4 126 127 #define mmDCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x40CB4A8 128 129 #define mmDCORE0_MME_CTRL_LO_AGU 0x40CB4AC 130 131 #define mmDCORE0_MME_CTRL_LO_QM 0x40CB4B0 132 133 #define mmDCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x40CB4B4 134 135 #define mmDCORE0_MME_CTRL_LO_INTR_CAUSE 0x40CB4B8 136 137 #define mmDCORE0_MME_CTRL_LO_INTR_MASK 0x40CB4BC 138 139 #define mmDCORE0_MME_CTRL_LO_INTR_CLEAR 0x40CB4C0 140 141 #define mmDCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x40CB4C4 142 143 #define mmDCORE0_MME_CTRL_LO_BIST 0x40CB4C8 144 145 #define mmDCORE0_MME_CTRL_LO_EU_RL_ENABLE 0x40CB4CC 146 147 #define mmDCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x40CB4D0 148 149 #define mmDCORE0_MME_CTRL_LO_EU_RL_CFG 0x40CB4D4 150 151 #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW0 0x40CB4D8 152 153 #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW1 0x40CB4DC 154 155 #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW2 0x40CB4E0 156 157 #define mmDCORE0_MME_CTRL_LO_PCU_DBG_DW3 0x40CB4E4 158 159 #define mmDCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID 0x40CB4E8 160 161 #define mmDCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x40CB4EC 162 163 #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_REGS_H_ */ 164