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Searched refs:mmCP_ME_IC_BASE_CNTL (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h10277 #define mmCP_ME_IC_BASE_CNTL … macro
H A Dgc_10_3_0_offset.h9987 #define mmCP_ME_IC_BASE_CNTL … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c6181 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); in gfx_v10_0_cp_gfx_load_me_microcode()