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Searched refs:mmCP_GFX_HQD_HQ_CONTROL0 (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h5055 #define mmCP_GFX_HQD_HQ_CONTROL0 … macro
H A Dgc_10_3_0_offset.h4712 #define mmCP_GFX_HQD_HQ_CONTROL0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c441 SOC15_REG_ENTRY_STR(GC, 0, mmCP_GFX_HQD_HQ_CONTROL0),