1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/pci-tph.h>
40 #include <linux/irq.h>
41 #include <linux/spinlock_types.h>
42 #include <linux/semaphore.h>
43 #include <linux/slab.h>
44 #include <linux/vmalloc.h>
45 #include <linux/xarray.h>
46 #include <linux/workqueue.h>
47 #include <linux/mempool.h>
48 #include <linux/interrupt.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52 #include <linux/mutex.h>
53
54 #include <linux/mlx5/device.h>
55 #include <linux/mlx5/doorbell.h>
56 #include <linux/mlx5/eq.h>
57 #include <linux/timecounter.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 8,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_SBPR = 0xb001,
104 MLX5_REG_SBCM = 0xb002,
105 MLX5_REG_QPTS = 0x4002,
106 MLX5_REG_QETCR = 0x4005,
107 MLX5_REG_QTCT = 0x400a,
108 MLX5_REG_QPDPM = 0x4013,
109 MLX5_REG_QCAM = 0x4019,
110 MLX5_REG_DCBX_PARAM = 0x4020,
111 MLX5_REG_DCBX_APP = 0x4021,
112 MLX5_REG_FPGA_CAP = 0x4022,
113 MLX5_REG_FPGA_CTRL = 0x4023,
114 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
115 MLX5_REG_CORE_DUMP = 0x402e,
116 MLX5_REG_PCAP = 0x5001,
117 MLX5_REG_PMTU = 0x5003,
118 MLX5_REG_PTYS = 0x5004,
119 MLX5_REG_PAOS = 0x5006,
120 MLX5_REG_PFCC = 0x5007,
121 MLX5_REG_PPCNT = 0x5008,
122 MLX5_REG_PPTB = 0x500b,
123 MLX5_REG_PBMC = 0x500c,
124 MLX5_REG_PMAOS = 0x5012,
125 MLX5_REG_PUDE = 0x5009,
126 MLX5_REG_PMPE = 0x5010,
127 MLX5_REG_PELC = 0x500e,
128 MLX5_REG_PVLC = 0x500f,
129 MLX5_REG_PCMR = 0x5041,
130 MLX5_REG_PDDR = 0x5031,
131 MLX5_REG_PMLP = 0x5002,
132 MLX5_REG_PPLM = 0x5023,
133 MLX5_REG_PPHCR = 0x503E,
134 MLX5_REG_PCAM = 0x507f,
135 MLX5_REG_NODE_DESC = 0x6001,
136 MLX5_REG_HOST_ENDIANNESS = 0x7004,
137 MLX5_REG_MTCAP = 0x9009,
138 MLX5_REG_MTMP = 0x900A,
139 MLX5_REG_MCIA = 0x9014,
140 MLX5_REG_MNVDA = 0x9024,
141 MLX5_REG_MFRL = 0x9028,
142 MLX5_REG_MLCR = 0x902b,
143 MLX5_REG_MRTC = 0x902d,
144 MLX5_REG_MTRC_CAP = 0x9040,
145 MLX5_REG_MTRC_CONF = 0x9041,
146 MLX5_REG_MTRC_STDB = 0x9042,
147 MLX5_REG_MTRC_CTRL = 0x9043,
148 MLX5_REG_MPEIN = 0x9050,
149 MLX5_REG_MPCNT = 0x9051,
150 MLX5_REG_MTPPS = 0x9053,
151 MLX5_REG_MTPPSE = 0x9054,
152 MLX5_REG_MTUTC = 0x9055,
153 MLX5_REG_MPEGC = 0x9056,
154 MLX5_REG_MPIR = 0x9059,
155 MLX5_REG_MCQS = 0x9060,
156 MLX5_REG_MCQI = 0x9061,
157 MLX5_REG_MCC = 0x9062,
158 MLX5_REG_MCDA = 0x9063,
159 MLX5_REG_MCAM = 0x907f,
160 MLX5_REG_MSECQ = 0x9155,
161 MLX5_REG_MSEES = 0x9156,
162 MLX5_REG_MIRC = 0x9162,
163 MLX5_REG_MTPTM = 0x9180,
164 MLX5_REG_MTCTR = 0x9181,
165 MLX5_REG_MRTCQ = 0x9182,
166 MLX5_REG_SBCAM = 0xB01F,
167 MLX5_REG_RESOURCE_DUMP = 0xC000,
168 MLX5_REG_NIC_CAP = 0xC00D,
169 MLX5_REG_DTOR = 0xC00E,
170 MLX5_REG_VHCA_ICM_CTRL = 0xC010,
171 };
172
173 enum mlx5_qpts_trust_state {
174 MLX5_QPTS_TRUST_PCP = 1,
175 MLX5_QPTS_TRUST_DSCP = 2,
176 };
177
178 enum mlx5_dcbx_oper_mode {
179 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
180 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
181 };
182
183 enum {
184 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
185 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
186 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
187 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
188 };
189
190 enum mlx5_page_fault_resume_flags {
191 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
192 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
193 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
194 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
195 };
196
197 enum dbg_rsc_type {
198 MLX5_DBG_RSC_QP,
199 MLX5_DBG_RSC_EQ,
200 MLX5_DBG_RSC_CQ,
201 };
202
203 enum port_state_policy {
204 MLX5_POLICY_DOWN = 0,
205 MLX5_POLICY_UP = 1,
206 MLX5_POLICY_FOLLOW = 2,
207 MLX5_POLICY_INVALID = 0xffffffff
208 };
209
210 enum mlx5_coredev_type {
211 MLX5_COREDEV_PF,
212 MLX5_COREDEV_VF,
213 MLX5_COREDEV_SF,
214 };
215
216 struct mlx5_field_desc {
217 int i;
218 };
219
220 struct mlx5_rsc_debug {
221 struct mlx5_core_dev *dev;
222 void *object;
223 enum dbg_rsc_type type;
224 struct dentry *root;
225 struct mlx5_field_desc fields[];
226 };
227
228 enum mlx5_dev_event {
229 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
230 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
231 MLX5_DEV_EVENT_MULTIPORT_ESW = 130,
232 };
233
234 enum mlx5_port_status {
235 MLX5_PORT_UP = 1,
236 MLX5_PORT_DOWN = 2,
237 };
238
239 enum mlx5_cmdif_state {
240 MLX5_CMDIF_STATE_UNINITIALIZED,
241 MLX5_CMDIF_STATE_UP,
242 MLX5_CMDIF_STATE_DOWN,
243 };
244
245 struct mlx5_cmd_first {
246 __be32 data[4];
247 };
248
249 struct mlx5_cmd_msg {
250 struct list_head list;
251 struct cmd_msg_cache *parent;
252 u32 len;
253 struct mlx5_cmd_first first;
254 struct mlx5_cmd_mailbox *next;
255 };
256
257 struct mlx5_cmd_debug {
258 struct dentry *dbg_root;
259 void *in_msg;
260 void *out_msg;
261 u8 status;
262 u16 inlen;
263 u16 outlen;
264 };
265
266 struct cmd_msg_cache {
267 /* protect block chain allocations
268 */
269 spinlock_t lock;
270 struct list_head head;
271 unsigned int max_inbox_size;
272 unsigned int num_ent;
273 };
274
275 enum {
276 MLX5_NUM_COMMAND_CACHES = 5,
277 };
278
279 struct mlx5_cmd_stats {
280 u64 sum;
281 u64 n;
282 /* number of times command failed */
283 u64 failed;
284 /* number of times command failed on bad status returned by FW */
285 u64 failed_mbox_status;
286 /* last command failed returned errno */
287 u32 last_failed_errno;
288 /* last bad status returned by FW */
289 u8 last_failed_mbox_status;
290 /* last command failed syndrome returned by FW */
291 u32 last_failed_syndrome;
292 struct dentry *root;
293 /* protect command average calculations */
294 spinlock_t lock;
295 };
296
297 struct mlx5_cmd {
298 struct mlx5_nb nb;
299
300 /* members which needs to be queried or reinitialized each reload */
301 struct {
302 u16 cmdif_rev;
303 u8 log_sz;
304 u8 log_stride;
305 int max_reg_cmds;
306 unsigned long bitmask;
307 struct semaphore sem;
308 struct semaphore pages_sem;
309 struct semaphore throttle_sem;
310 struct semaphore unprivileged_sem;
311 struct xarray privileged_uids;
312 } vars;
313 enum mlx5_cmdif_state state;
314 void *cmd_alloc_buf;
315 dma_addr_t alloc_dma;
316 int alloc_size;
317 void *cmd_buf;
318 dma_addr_t dma;
319
320 /* protect command queue allocations
321 */
322 spinlock_t alloc_lock;
323
324 /* protect token allocations
325 */
326 spinlock_t token_lock;
327 u8 token;
328 char wq_name[MLX5_CMD_WQ_MAX_NAME];
329 struct workqueue_struct *wq;
330 int mode;
331 u16 allowed_opcode;
332 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
333 struct dma_pool *pool;
334 struct mlx5_cmd_debug dbg;
335 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
336 int checksum_disabled;
337 struct xarray stats;
338 };
339
340 struct mlx5_cmd_mailbox {
341 void *buf;
342 dma_addr_t dma;
343 struct mlx5_cmd_mailbox *next;
344 };
345
346 struct mlx5_dma_pool_page;
347 struct mlx5_buf_list {
348 void *buf;
349 dma_addr_t map;
350 struct mlx5_dma_pool_page *frag_page;
351 };
352
353 struct mlx5_frag_buf {
354 struct mlx5_buf_list *frags;
355 int npages;
356 int size;
357 u8 page_shift;
358 };
359
360 struct mlx5_frag_buf_ctrl {
361 struct mlx5_buf_list *frags;
362 u32 sz_m1;
363 u16 frag_sz_m1;
364 u16 strides_offset;
365 u8 log_sz;
366 u8 log_stride;
367 u8 log_frag_strides;
368 };
369
370 struct mlx5_core_psv {
371 u32 psv_idx;
372 struct psv_layout {
373 u32 pd;
374 u16 syndrome;
375 u16 reserved;
376 u16 bg;
377 u16 app_tag;
378 u32 ref_tag;
379 } psv;
380 };
381
382 struct mlx5_core_sig_ctx {
383 struct mlx5_core_psv psv_memory;
384 struct mlx5_core_psv psv_wire;
385 struct ib_sig_err err_item;
386 bool sig_status_checked;
387 bool sig_err_exists;
388 u32 sigerr_count;
389 };
390
391 #define MLX5_24BIT_MASK ((1 << 24) - 1)
392
393 enum mlx5_res_type {
394 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
395 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
396 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
397 MLX5_RES_SRQ = 3,
398 MLX5_RES_XSRQ = 4,
399 MLX5_RES_XRQ = 5,
400 };
401
402 struct mlx5_core_rsc_common {
403 enum mlx5_res_type res;
404 refcount_t refcount;
405 struct completion free;
406 bool invalid;
407 };
408
409 struct mlx5_uars_page {
410 void __iomem *map;
411 bool wc;
412 u32 index;
413 struct list_head list;
414 unsigned int bfregs;
415 unsigned long *reg_bitmap; /* for non fast path bf regs */
416 unsigned long *fp_bitmap;
417 unsigned int reg_avail;
418 unsigned int fp_avail;
419 struct kref ref_count;
420 struct mlx5_core_dev *mdev;
421 };
422
423 struct mlx5_bfreg_head {
424 /* protect blue flame registers allocations */
425 struct mutex lock;
426 struct list_head list;
427 };
428
429 struct mlx5_bfreg_data {
430 struct mlx5_bfreg_head reg_head;
431 struct mlx5_bfreg_head wc_head;
432 };
433
434 struct mlx5_sq_bfreg {
435 void __iomem *map;
436 struct mlx5_uars_page *up;
437 bool wc;
438 u32 index;
439 };
440
441 struct mlx5_core_health {
442 struct health_buffer __iomem *health;
443 __be32 __iomem *health_counter;
444 struct timer_list timer;
445 u32 prev;
446 int miss_counter;
447 u8 synd;
448 u32 fatal_error;
449 u32 crdump_size;
450 struct workqueue_struct *wq;
451 unsigned long flags;
452 struct work_struct fatal_report_work;
453 struct work_struct report_work;
454 struct devlink_health_reporter *fw_reporter;
455 struct devlink_health_reporter *fw_fatal_reporter;
456 struct devlink_health_reporter *vnic_reporter;
457 struct delayed_work update_fw_log_ts_work;
458 };
459
460 enum {
461 MLX5_PF_NOTIFY_DISABLE_VF,
462 MLX5_PF_NOTIFY_ENABLE_VF,
463 };
464
465 struct mlx5_vf_context {
466 int enabled;
467 u64 port_guid;
468 u64 node_guid;
469 /* Valid bits are used to validate administrative guid only.
470 * Enabled after ndo_set_vf_guid
471 */
472 u8 port_guid_valid:1;
473 u8 node_guid_valid:1;
474 enum port_state_policy policy;
475 struct blocking_notifier_head notifier;
476 };
477
478 struct mlx5_core_sriov {
479 struct mlx5_vf_context *vfs_ctx;
480 int num_vfs;
481 u16 max_vfs;
482 u16 max_ec_vfs;
483 };
484
485 struct mlx5_events;
486 struct mlx5_mpfs;
487 struct mlx5_eswitch;
488 struct mlx5_lag;
489 struct mlx5_devcom_dev;
490 struct mlx5_fw_reset;
491 struct mlx5_eq_table;
492 struct mlx5_irq_table;
493 struct mlx5_sf_dev_table;
494 struct mlx5_sf_hw_table;
495 struct mlx5_sf_table;
496 struct mlx5_crypto_dek_priv;
497
498 struct mlx5_rate_limit {
499 u32 rate;
500 u32 max_burst_sz;
501 u16 typical_pkt_sz;
502 };
503
504 struct mlx5_rl_entry {
505 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
506 u64 refcount;
507 u16 index;
508 u16 uid;
509 u8 dedicated : 1;
510 };
511
512 struct mlx5_rl_table {
513 /* protect rate limit table */
514 struct mutex rl_lock;
515 u16 max_size;
516 u32 max_rate;
517 u32 min_rate;
518 struct mlx5_rl_entry *rl_entry;
519 u64 refcount;
520 };
521
522 struct mlx5_core_roce {
523 struct mlx5_flow_table *ft;
524 struct mlx5_flow_group *fg;
525 struct mlx5_flow_handle *allow_rule;
526 };
527
528 enum {
529 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
530 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
531 /* Set during device detach to block any further devices
532 * creation/deletion on drivers rescan. Unset during device attach.
533 */
534 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
535 MLX5_PRIV_FLAGS_SWITCH_LEGACY = 1 << 3,
536 };
537
538 struct mlx5_adev {
539 struct auxiliary_device adev;
540 struct mlx5_core_dev *mdev;
541 int idx;
542 };
543
544 struct mlx5_debugfs_entries {
545 struct dentry *dbg_root;
546 struct dentry *qp_debugfs;
547 struct dentry *eq_debugfs;
548 struct dentry *cq_debugfs;
549 struct dentry *cmdif_debugfs;
550 struct dentry *frag_buf_dma_pools_debugfs;
551 struct dentry *db_dma_pools_debugfs;
552 struct dentry *pages_debugfs;
553 struct dentry *lag_debugfs;
554 };
555
556 enum mlx5_func_type {
557 MLX5_SELF,
558 MLX5_VF,
559 MLX5_SF,
560 MLX5_HOST_PF,
561 MLX5_SPF,
562 MLX5_EC_VF,
563 MLX5_FUNC_TYPE_NUM,
564 MLX5_FUNC_TYPE_NONE = MLX5_FUNC_TYPE_NUM,
565 };
566
567 enum mlx5_page_mgt_mode {
568 MLX5_PAGE_MGT_MODE_FUNC_ID,
569 MLX5_PAGE_MGT_MODE_VHCA_ID,
570 };
571
572 struct mlx5_frag_buf_node_pools;
573 struct mlx5_dma_pool;
574 struct mlx5_ft_pool;
575 struct mlx5_priv {
576 /* IRQ table valid only for real pci devices PF or VF */
577 struct mlx5_irq_table *irq_table;
578 struct mlx5_eq_table *eq_table;
579
580 /* pages stuff */
581 struct mlx5_nb pg_nb;
582 struct workqueue_struct *pg_wq;
583 struct xarray page_root_xa;
584 atomic_t reg_pages;
585 struct list_head free_list;
586 u32 fw_pages;
587 u32 page_counters[MLX5_FUNC_TYPE_NUM];
588 u32 fw_pages_alloc_failed;
589 u32 give_pages_dropped;
590 u32 reclaim_pages_discard;
591 enum mlx5_page_mgt_mode page_mgt_mode;
592
593 struct mlx5_core_health health;
594 struct list_head traps;
595
596 struct mlx5_debugfs_entries dbg;
597
598 /* start: alloc stuff */
599 /* protect buffer allocation according to numa node */
600 struct mutex alloc_mutex;
601 int numa_node;
602
603 struct mlx5_frag_buf_node_pools **frag_buf_node_pools;
604 struct mlx5_dma_pool **db_node_pools;
605 /* end: alloc stuff */
606
607 struct mlx5_adev **adev;
608 int adev_idx;
609 int sw_vhca_id;
610 struct mlx5_events *events;
611 struct mlx5_vhca_events *vhca_events;
612
613 struct mlx5_flow_steering *steering;
614 struct mlx5_mpfs *mpfs;
615 struct blocking_notifier_head esw_n_head;
616 struct mlx5_eswitch *eswitch;
617 struct mlx5_core_sriov sriov;
618 struct mlx5_lag *lag;
619 u32 flags;
620 struct mlx5_devcom_dev *devc;
621 struct mlx5_devcom_comp_dev *hca_devcom_comp;
622 struct mlx5_fw_reset *fw_reset;
623 struct mlx5_core_roce roce;
624 struct mlx5_fc_stats *fc_stats;
625 struct mlx5_rl_table rl_table;
626 struct mlx5_ft_pool *ft_pool;
627
628 struct mlx5_bfreg_data bfregs;
629 struct mlx5_sq_bfreg bfreg;
630 #ifdef CONFIG_MLX5_SF
631 struct mlx5_nb vhca_state_nb;
632 struct blocking_notifier_head vhca_state_n_head;
633 struct notifier_block sf_dev_nb;
634 struct mlx5_sf_dev_table *sf_dev_table;
635 struct mlx5_core_dev *parent_mdev;
636 #endif
637 #ifdef CONFIG_MLX5_SF_MANAGER
638 struct notifier_block sf_hw_table_vhca_nb;
639 struct mlx5_sf_hw_table *sf_hw_table;
640 struct notifier_block sf_table_esw_nb;
641 struct notifier_block sf_table_vhca_nb;
642 struct notifier_block sf_table_mdev_nb;
643 struct mlx5_sf_table *sf_table;
644 #endif
645 struct blocking_notifier_head lag_nh;
646 };
647
648 enum mlx5_device_state {
649 MLX5_DEVICE_STATE_UP = 1,
650 MLX5_DEVICE_STATE_INTERNAL_ERROR,
651 };
652
653 enum mlx5_interface_state {
654 MLX5_INTERFACE_STATE_UP = BIT(0),
655 MLX5_BREAK_FW_WAIT = BIT(1),
656 };
657
658 enum mlx5_pci_status {
659 MLX5_PCI_STATUS_DISABLED,
660 MLX5_PCI_STATUS_ENABLED,
661 };
662
663 enum mlx5_pagefault_type_flags {
664 MLX5_PFAULT_REQUESTOR = 1 << 0,
665 MLX5_PFAULT_WRITE = 1 << 1,
666 MLX5_PFAULT_RDMA = 1 << 2,
667 };
668
669 struct mlx5_td {
670 /* protects tirs list changes while tirs refresh */
671 struct mutex list_lock;
672 struct list_head tirs_list;
673 u32 tdn;
674 };
675
676 struct mlx5e_resources {
677 struct mlx5e_hw_objs {
678 u32 pdn;
679 struct mlx5_td td;
680 u32 mkey;
681 struct mlx5_sq_bfreg *bfregs;
682 unsigned int num_bfregs;
683 #define MLX5_MAX_NUM_TC 8
684 u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC];
685 bool tisn_valid;
686 } hw_objs;
687 struct net_device *uplink_netdev;
688 netdevice_tracker tracker;
689 struct mutex uplink_netdev_lock;
690 struct mlx5_crypto_dek_priv *dek_priv;
691 };
692
693 enum mlx5_sw_icm_type {
694 MLX5_SW_ICM_TYPE_STEERING,
695 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
696 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
697 MLX5_SW_ICM_TYPE_SW_ENCAP,
698 };
699
700 #define MLX5_MAX_RESERVED_GIDS 8
701
702 struct mlx5_rsvd_gids {
703 unsigned int start;
704 unsigned int count;
705 struct ida ida;
706 };
707
708 struct mlx5_clock;
709 struct mlx5_clock_dev_state;
710 struct mlx5_dm;
711 struct mlx5_fw_tracer;
712 struct mlx5_vxlan;
713 struct mlx5_geneve;
714 struct mlx5_hv_vhca;
715 struct mlx5_st;
716
717 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
718 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
719
720 enum {
721 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
722 };
723
724 struct mlx5_profile {
725 u64 mask;
726 u8 log_max_qp;
727 u8 num_cmd_caches;
728 };
729
730 struct mlx5_hca_cap {
731 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
732 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
733 };
734
735 enum mlx5_wc_state {
736 MLX5_WC_STATE_UNINITIALIZED,
737 MLX5_WC_STATE_UNSUPPORTED,
738 MLX5_WC_STATE_SUPPORTED,
739 };
740
741 struct mlx5_core_dev {
742 struct device *device;
743 enum mlx5_coredev_type coredev_type;
744 struct pci_dev *pdev;
745 /* sync pci state */
746 struct mutex pci_status_mutex;
747 enum mlx5_pci_status pci_status;
748 u8 rev_id;
749 char board_id[MLX5_BOARD_ID_LEN];
750 struct mlx5_cmd cmd;
751 struct {
752 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
753 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
754 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
755 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
756 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
757 u8 embedded_cpu;
758 } caps;
759 struct mlx5_timeouts *timeouts;
760 u64 sys_image_guid;
761 struct mlx5_init_seg __iomem *iseg;
762 phys_addr_t bar_addr;
763 enum mlx5_device_state state;
764 /* sync interface state */
765 struct mutex intf_state_mutex;
766 struct lock_class_key lock_key;
767 unsigned long intf_state;
768 struct mlx5_priv priv;
769 struct mlx5_profile profile;
770 u32 issi;
771 struct mlx5e_resources mlx5e_res;
772 struct mlx5_dm *dm;
773 struct mlx5_st *st;
774 struct mlx5_vxlan *vxlan;
775 struct mlx5_geneve *geneve;
776 struct {
777 struct mlx5_rsvd_gids reserved_gids;
778 u32 roce_en;
779 } roce;
780 #ifdef CONFIG_MLX5_FPGA
781 struct mlx5_fpga_device *fpga;
782 #endif
783 struct mlx5_clock *clock;
784 struct mlx5_clock_dev_state *clock_state;
785 struct mlx5_ib_clock_info *clock_info;
786 struct mlx5_fw_tracer *tracer;
787 struct mlx5_rsc_dump *rsc_dump;
788 u32 vsc_addr;
789 struct mlx5_hv_vhca *hv_vhca;
790 struct mlx5_hwmon *hwmon;
791 u64 num_block_tc;
792 u64 num_block_ipsec;
793 #ifdef CONFIG_MLX5_MACSEC
794 struct mlx5_macsec_fs *macsec_fs;
795 /* MACsec notifier chain to sync MACsec core and IB database */
796 struct blocking_notifier_head macsec_nh;
797 #endif
798 u64 num_ipsec_offloads;
799 struct mlx5_sd *sd;
800 enum mlx5_wc_state wc_state;
801 /* sync write combining state */
802 struct mutex wc_state_lock;
803 struct devlink *shd;
804 };
805
806 struct mlx5_db {
807 __be32 *db;
808 union {
809 struct mlx5_dma_pool_page *pool_page;
810 struct mlx5_ib_user_db_page *user_page;
811 } u;
812 dma_addr_t dma;
813 int index;
814 };
815
816 #define MLX5_DEFAULT_NUM_DOORBELLS 8
817
818 enum {
819 MLX5_COMP_EQ_SIZE = 1024,
820 };
821
822 enum {
823 MLX5_PTYS_IB = 1 << 0,
824 MLX5_PTYS_EN = 1 << 2,
825 };
826
827 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
828
829 enum {
830 MLX5_CMD_ENT_STATE_PENDING_COMP,
831 MLX5_CMD_ENT_STATE_TIMEDOUT,
832 };
833
834 struct mlx5_cmd_work_ent {
835 unsigned long state;
836 struct mlx5_cmd_msg *in;
837 struct mlx5_cmd_msg *out;
838 void *uout;
839 int uout_size;
840 mlx5_cmd_cbk_t callback;
841 struct delayed_work cb_timeout_work;
842 void *context;
843 int idx;
844 struct completion handling;
845 struct completion slotted;
846 struct completion done;
847 struct mlx5_cmd *cmd;
848 struct work_struct work;
849 struct mlx5_cmd_layout *lay;
850 int ret;
851 int page_queue;
852 u8 status;
853 u8 token;
854 u64 ts1;
855 u64 ts2;
856 u16 op;
857 bool polling;
858 /* Track the max comp handlers */
859 refcount_t refcnt;
860 };
861
862 enum phy_port_state {
863 MLX5_AAA_111
864 };
865
866 struct mlx5_hca_vport_context {
867 u32 field_select;
868 bool sm_virt_aware;
869 bool has_smi;
870 bool has_raw;
871 enum port_state_policy policy;
872 enum phy_port_state phys_state;
873 enum ib_port_state vport_state;
874 u8 port_physical_state;
875 u64 sys_image_guid;
876 u64 port_guid;
877 u64 node_guid;
878 u32 cap_mask1;
879 u32 cap_mask1_perm;
880 u16 cap_mask2;
881 u16 cap_mask2_perm;
882 u16 lid;
883 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
884 u8 lmc;
885 u8 subnet_timeout;
886 u16 sm_lid;
887 u8 sm_sl;
888 u16 qkey_violation_counter;
889 u16 pkey_violation_counter;
890 bool grh_required;
891 u8 num_plane;
892 };
893
894 #define STRUCT_FIELD(header, field) \
895 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
896 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
897
898 extern struct dentry *mlx5_debugfs_root;
899
fw_rev_maj(struct mlx5_core_dev * dev)900 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
901 {
902 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
903 }
904
fw_rev_min(struct mlx5_core_dev * dev)905 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
906 {
907 return ioread32be(&dev->iseg->fw_rev) >> 16;
908 }
909
fw_rev_sub(struct mlx5_core_dev * dev)910 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
911 {
912 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
913 }
914
mlx5_base_mkey(const u32 key)915 static inline u32 mlx5_base_mkey(const u32 key)
916 {
917 return key & 0xffffff00u;
918 }
919
wq_get_byte_sz(u8 log_sz,u8 log_stride)920 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
921 {
922 return ((u32)1 << log_sz) << log_stride;
923 }
924
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)925 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
926 u8 log_stride, u8 log_sz,
927 u16 strides_offset,
928 struct mlx5_frag_buf_ctrl *fbc)
929 {
930 fbc->frags = frags;
931 fbc->log_stride = log_stride;
932 fbc->log_sz = log_sz;
933 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
934 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
935 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
936 fbc->strides_offset = strides_offset;
937 }
938
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)939 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
940 u8 log_stride, u8 log_sz,
941 struct mlx5_frag_buf_ctrl *fbc)
942 {
943 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
944 }
945
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)946 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
947 u32 ix)
948 {
949 unsigned int frag;
950
951 ix += fbc->strides_offset;
952 frag = ix >> fbc->log_frag_strides;
953
954 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
955 }
956
957 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)958 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
959 {
960 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
961
962 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
963 }
964
965 enum {
966 CMD_ALLOWED_OPCODE_ALL,
967 };
968
969 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
970 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
971 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
972
973 struct mlx5_async_ctx {
974 struct mlx5_core_dev *dev;
975 atomic_t num_inflight;
976 struct completion inflight_done;
977 };
978
979 struct mlx5_async_work;
980
981 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
982
983 struct mlx5_async_work {
984 struct mlx5_async_ctx *ctx;
985 mlx5_async_cbk_t user_callback;
986 u16 opcode; /* cmd opcode */
987 u16 op_mod; /* cmd op_mod */
988 u8 throttle_locked:1;
989 u8 unpriv_locked:1;
990 void *out; /* pointer to the cmd output buffer */
991 };
992
993 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
994 struct mlx5_async_ctx *ctx);
995 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
996 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
997 void *out, int out_size, mlx5_async_cbk_t callback,
998 struct mlx5_async_work *work);
999 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
1000 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
1001 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
1002 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1003 int out_size);
1004
1005 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1006 ({ \
1007 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1008 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1009 })
1010
1011 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1012 ({ \
1013 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1014 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1015 })
1016
1017 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1018 void *out, int out_size);
1019 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1020 int mlx5_cmd_add_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1021 void mlx5_cmd_remove_privileged_uid(struct mlx5_core_dev *dev, u16 uid);
1022
1023 void mlx5_core_uplink_netdev_set(struct mlx5_core_dev *mdev, struct net_device *netdev);
1024 void mlx5_core_uplink_netdev_event_replay(struct mlx5_core_dev *mdev);
1025
1026 void mlx5_core_mp_event_replay(struct mlx5_core_dev *dev, u32 event, void *data);
1027
1028 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1029 int mlx5_health_init(struct mlx5_core_dev *dev);
1030 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1031 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1032 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1033 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1034 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1035 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1036 struct mlx5_frag_buf *buf, int node);
1037 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1038 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1039 int inlen);
1040 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1041 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1042 int outlen);
1043 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1044 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1045 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1046 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1047 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1048 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1049 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1050 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1051 void mlx5_pages_by_func_type_debugfs_init(struct mlx5_core_dev *dev);
1052 void mlx5_pages_by_func_type_debugfs_cleanup(struct mlx5_core_dev *dev);
1053 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1054 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1055 void mlx5_register_debugfs(void);
1056 void mlx5_unregister_debugfs(void);
1057
1058 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1059 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1060 int mlx5_comp_eqn_get(struct mlx5_core_dev *dev, u16 vecidx, int *eqn);
1061 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1062 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1063
1064 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1065 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1066 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1067 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1068 void *data_out, int size_out, u16 reg_id, int arg,
1069 int write, bool verbose);
1070 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1071 int size_in, void *data_out, int size_out,
1072 u16 reg_num, int arg, int write);
1073
1074 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1075 int node);
1076
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1077 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1078 {
1079 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1080 }
1081
1082 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1083
1084 const char *mlx5_command_str(int command);
1085 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1086 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1087 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1088 int npsvs, u32 *sig_index);
1089 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1090 __be32 mlx5_core_get_terminate_scatter_list_mkey(struct mlx5_core_dev *dev);
1091 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1092
1093 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1094 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1095 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1096 struct mlx5_rate_limit *rl);
1097 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1098 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1099 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1100 bool dedicated_entry, u16 *index);
1101 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1102 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1103 struct mlx5_rate_limit *rl_1);
1104 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1105 bool map_wc, bool fast_path);
1106 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1107
1108 unsigned int mlx5_comp_vectors_max(struct mlx5_core_dev *dev);
1109 int mlx5_comp_vector_get_cpu(struct mlx5_core_dev *dev, int vector);
1110 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1111 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1112 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1113 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1114
mlx5_mkey_to_idx(u32 mkey)1115 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1116 {
1117 return mkey >> 8;
1118 }
1119
mlx5_idx_to_mkey(u32 mkey_idx)1120 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1121 {
1122 return mkey_idx << 8;
1123 }
1124
mlx5_mkey_variant(u32 mkey)1125 static inline u8 mlx5_mkey_variant(u32 mkey)
1126 {
1127 return mkey & 0xff;
1128 }
1129
1130 /* Async-atomic event notifier used by mlx5 core to forward FW
1131 * evetns received from event queue to mlx5 consumers.
1132 * Optimise event queue dipatching.
1133 */
1134 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1135 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1136
1137 /* Async-atomic event notifier used for forwarding
1138 * evetns from the event queue into the to mlx5 events dispatcher,
1139 * eswitch, clock and others.
1140 */
1141 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1142 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1143
1144 /* Blocking event notifier used to forward SW events, used for slow path */
1145 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1146 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1147 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1148 void *data);
1149
1150 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1151
1152 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1153 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1155 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1156 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1157 int mlx5_lag_query_bond_speed(struct mlx5_core_dev *dev, u32 *speed);
1158 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1159 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1160 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1161 bool mlx5_lag_is_mpesw(struct mlx5_core_dev *dev);
1162 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1163 struct net_device *slave);
1164 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1165 u64 *values,
1166 int num_counters,
1167 size_t *offsets);
1168 struct mlx5_core_dev *mlx5_lag_get_next_peer_mdev(struct mlx5_core_dev *dev, int *i);
1169
1170 #define mlx5_lag_for_each_peer_mdev(dev, peer, i) \
1171 for (i = 0, peer = mlx5_lag_get_next_peer_mdev(dev, &i); \
1172 peer; \
1173 peer = mlx5_lag_get_next_peer_mdev(dev, &i))
1174
1175 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1176 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1177 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1178 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1179 u64 length, u32 log_alignment, u16 uid,
1180 phys_addr_t *addr, u32 *obj_id);
1181 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1182 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1183
1184 #ifdef CONFIG_PCIE_TPH
1185 int mlx5_st_alloc_index(struct mlx5_core_dev *dev, enum tph_mem_type mem_type,
1186 unsigned int cpu_uid, u16 *st_index);
1187 int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index);
1188 #else
mlx5_st_alloc_index(struct mlx5_core_dev * dev,enum tph_mem_type mem_type,unsigned int cpu_uid,u16 * st_index)1189 static inline int mlx5_st_alloc_index(struct mlx5_core_dev *dev,
1190 enum tph_mem_type mem_type,
1191 unsigned int cpu_uid, u16 *st_index)
1192 {
1193 return -EOPNOTSUPP;
1194 }
mlx5_st_dealloc_index(struct mlx5_core_dev * dev,u16 st_index)1195 static inline int mlx5_st_dealloc_index(struct mlx5_core_dev *dev, u16 st_index)
1196 {
1197 return -EOPNOTSUPP;
1198 }
1199 #endif
1200
1201 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1202 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1203
1204 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1205 int vf_id,
1206 struct notifier_block *nb);
1207 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1208 int vf_id,
1209 struct notifier_block *nb);
1210 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1211 struct ib_device *device,
1212 struct rdma_netdev_alloc_params *params);
1213
1214 enum {
1215 MLX5_PCI_DEV_IS_VF = 1 << 0,
1216 };
1217
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1218 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1219 {
1220 return dev->coredev_type == MLX5_COREDEV_PF;
1221 }
1222
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1223 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1224 {
1225 return dev->coredev_type == MLX5_COREDEV_VF;
1226 }
1227
mlx5_core_same_coredev_type(const struct mlx5_core_dev * dev1,const struct mlx5_core_dev * dev2)1228 static inline bool mlx5_core_same_coredev_type(const struct mlx5_core_dev *dev1,
1229 const struct mlx5_core_dev *dev2)
1230 {
1231 return dev1->coredev_type == dev2->coredev_type;
1232 }
1233
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1234 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1235 {
1236 return dev->caps.embedded_cpu;
1237 }
1238
1239 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1240 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1241 {
1242 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1243 }
1244
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1245 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1246 {
1247 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1248 }
1249
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1250 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1251 {
1252 return dev->priv.sriov.max_vfs;
1253 }
1254
mlx5_lag_is_lacp_owner(struct mlx5_core_dev * dev)1255 static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
1256 {
1257 /* LACP owner conditions:
1258 * 1) Function is physical.
1259 * 2) LAG is supported by FW.
1260 * 3) LAG is managed by driver (currently the only option).
1261 */
1262 return MLX5_CAP_GEN(dev, vport_group_manager) &&
1263 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
1264 MLX5_CAP_GEN(dev, lag_master);
1265 }
1266
mlx5_core_max_ec_vfs(const struct mlx5_core_dev * dev)1267 static inline u16 mlx5_core_max_ec_vfs(const struct mlx5_core_dev *dev)
1268 {
1269 return dev->priv.sriov.max_ec_vfs;
1270 }
1271
mlx5_get_gid_table_len(u16 param)1272 static inline int mlx5_get_gid_table_len(u16 param)
1273 {
1274 if (param > 4) {
1275 pr_warn("gid table length is zero\n");
1276 return 0;
1277 }
1278
1279 return 8 * (1 << param);
1280 }
1281
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1282 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1283 {
1284 return !!(dev->priv.rl_table.max_size);
1285 }
1286
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1287 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1288 {
1289 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1290 MLX5_CAP_GEN_MAX(dev, num_vhca_ports) <= 1;
1291 }
1292
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1293 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1294 {
1295 return MLX5_CAP_GEN_MAX(dev, num_vhca_ports) > 1;
1296 }
1297
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1298 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1299 {
1300 return mlx5_core_is_mp_slave(dev) ||
1301 mlx5_core_is_mp_master(dev);
1302 }
1303
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1304 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1305 {
1306 if (!mlx5_core_mp_enabled(dev))
1307 return 1;
1308
1309 return MLX5_CAP_GEN(dev, native_port_num);
1310 }
1311
mlx5_get_dev_index(struct mlx5_core_dev * dev)1312 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1313 {
1314 int idx = MLX5_CAP_GEN(dev, native_port_num);
1315
1316 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1317 return idx - 1;
1318 else
1319 return PCI_FUNC(dev->pdev->devfn);
1320 }
1321
1322 enum {
1323 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1324 };
1325
1326 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1327
mlx5_get_roce_state(struct mlx5_core_dev * dev)1328 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1329 {
1330 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1331 return MLX5_CAP_GEN(dev, roce);
1332
1333 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1334 * in order to support RoCE enable/disable feature
1335 */
1336 return mlx5_is_roce_on(dev);
1337 }
1338
1339 #ifdef CONFIG_MLX5_MACSEC
mlx5e_is_macsec_device(const struct mlx5_core_dev * mdev)1340 static inline bool mlx5e_is_macsec_device(const struct mlx5_core_dev *mdev)
1341 {
1342 if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
1343 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD))
1344 return false;
1345
1346 if (!MLX5_CAP_GEN(mdev, log_max_dek))
1347 return false;
1348
1349 if (!MLX5_CAP_MACSEC(mdev, log_max_macsec_offload))
1350 return false;
1351
1352 if (!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, macsec_decrypt) ||
1353 !MLX5_CAP_FLOWTABLE_NIC_RX(mdev, reformat_remove_macsec))
1354 return false;
1355
1356 if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, macsec_encrypt) ||
1357 !MLX5_CAP_FLOWTABLE_NIC_TX(mdev, reformat_add_macsec))
1358 return false;
1359
1360 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_encrypt) &&
1361 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_encrypt))
1362 return false;
1363
1364 if (!MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_128_decrypt) &&
1365 !MLX5_CAP_MACSEC(mdev, macsec_crypto_esp_aes_gcm_256_decrypt))
1366 return false;
1367
1368 return true;
1369 }
1370
1371 #define NIC_RDMA_BOTH_DIRS_CAPS (MLX5_FT_NIC_RX_2_NIC_RX_RDMA | MLX5_FT_NIC_TX_RDMA_2_NIC_TX)
1372
mlx5_is_macsec_roce_supported(struct mlx5_core_dev * mdev)1373 static inline bool mlx5_is_macsec_roce_supported(struct mlx5_core_dev *mdev)
1374 {
1375 if (((MLX5_CAP_GEN_2(mdev, flow_table_type_2_type) &
1376 NIC_RDMA_BOTH_DIRS_CAPS) != NIC_RDMA_BOTH_DIRS_CAPS) ||
1377 !MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, max_modify_header_actions) ||
1378 !mlx5e_is_macsec_device(mdev) || !mdev->macsec_fs)
1379 return false;
1380
1381 return true;
1382 }
1383 #endif
1384
1385 enum {
1386 MLX5_OCTWORD = 16,
1387 };
1388
1389 bool mlx5_wc_support_get(struct mlx5_core_dev *mdev);
1390
mlx5_core_net(struct mlx5_core_dev * dev)1391 static inline struct net *mlx5_core_net(struct mlx5_core_dev *dev)
1392 {
1393 return devlink_net(priv_to_devlink(dev));
1394 }
1395
1396 #define MLX5_SW_IMAGE_GUID_MAX_BYTES 9
1397
1398 #endif /* MLX5_DRIVER_H */
1399