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Searched refs:mdp4_kms (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_kms.c20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_hw_init() local
21 struct drm_device *dev = mdp4_kms->dev; in mdp4_hw_init()
27 if (mdp4_kms->rev > 1) { in mdp4_hw_init()
28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); in mdp4_hw_init()
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); in mdp4_hw_init()
32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); in mdp4_hw_init()
35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); in mdp4_hw_init()
37 clk = clk_get_rate(mdp4_kms->clk); in mdp4_hw_init()
39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { in mdp4_hw_init()
49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); in mdp4_hw_init()
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H A Dmdp4_irq.c23 struct mdp4_kms *mdp4_kms = container_of(irq, struct mdp4_kms, error_handler); in mdp4_irq_error_handler() local
30 struct drm_printer p = drm_info_printer(mdp4_kms->dev->dev); in mdp4_irq_error_handler()
31 drm_state_dump(mdp4_kms->dev, &p); in mdp4_irq_error_handler()
37 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); in mdp4_irq_preinstall() local
38 mdp4_enable(mdp4_kms); in mdp4_irq_preinstall()
39 mdp4_write(mdp4_kms, REG_MDP4_INTR_CLEAR, 0xffffffff); in mdp4_irq_preinstall()
40 mdp4_write(mdp4_kms, REG_MDP4_INTR_ENABLE, 0x00000000); in mdp4_irq_preinstall()
41 mdp4_disable(mdp4_kms); in mdp4_irq_preinstall()
47 struct mdp4_kms *mdp4_kms = to_mdp4_kms(mdp_kms); in mdp4_irq_postinstall() local
48 struct mdp_irq *error_handler = &mdp4_kms->error_handler; in mdp4_irq_postinstall()
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H A Dmdp4_dsi_encoder.c23 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
33 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dsi_encoder_mode_set() local
59 mdp4_write(mdp4_kms, REG_MDP4_DSI_HSYNC_CTRL, in mdp4_dsi_encoder_mode_set()
62 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_PERIOD, vsync_period); in mdp4_dsi_encoder_mode_set()
63 mdp4_write(mdp4_kms, REG_MDP4_DSI_VSYNC_LEN, vsync_len); in mdp4_dsi_encoder_mode_set()
64 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_HCTRL, in mdp4_dsi_encoder_mode_set()
67 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VSTART, display_v_start); in mdp4_dsi_encoder_mode_set()
68 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); in mdp4_dsi_encoder_mode_set()
70 mdp4_write(mdp4_kms, REG_MDP4_DSI_CTRL_POLARITY, ctrl_pol); in mdp4_dsi_encoder_mode_set()
71 mdp4_write(mdp4_kms, REG_MDP4_DSI_UNDERFLOW_CLR, in mdp4_dsi_encoder_mode_set()
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H A Dmdp4_dtv_encoder.c22 static struct mdp4_kms *get_kms(struct drm_encoder *encoder) in get_kms()
33 struct mdp4_kms *mdp4_kms = get_kms(encoder); in mdp4_dtv_encoder_mode_set() local
63 mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL, in mdp4_dtv_encoder_mode_set()
66 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period); in mdp4_dtv_encoder_mode_set()
67 mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len); in mdp4_dtv_encoder_mode_set()
68 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL, in mdp4_dtv_encoder_mode_set()
71 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start); in mdp4_dtv_encoder_mode_set()
72 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
73 mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0); in mdp4_dtv_encoder_mode_set()
74 mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR, in mdp4_dtv_encoder_mode_set()
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/linux/drivers/gpu/drm/msm/
H A DMakefile55 disp/mdp4/mdp4_kms.o \