1 /*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20 #include <linux/numa.h>
21
22 #define EDAC_DEVICE_NAME_LEN 31
23
24 struct device;
25
26 #define EDAC_OPSTATE_INVAL -1
27 #define EDAC_OPSTATE_POLL 0
28 #define EDAC_OPSTATE_NMI 1
29 #define EDAC_OPSTATE_INT 2
30
31 extern int edac_op_state;
32
33 const struct bus_type *edac_get_sysfs_subsys(void);
34
opstate_init(void)35 static inline void opstate_init(void)
36 {
37 switch (edac_op_state) {
38 case EDAC_OPSTATE_POLL:
39 case EDAC_OPSTATE_NMI:
40 break;
41 default:
42 edac_op_state = EDAC_OPSTATE_POLL;
43 }
44 return;
45 }
46
47 /* Max length of a DIMM label*/
48 #define EDAC_MC_LABEL_LEN 31
49
50 /* Maximum size of the location string */
51 #define LOCATION_SIZE 256
52
53 /* Defines the maximum number of labels that can be reported */
54 #define EDAC_MAX_LABELS 8
55
56 /* String used to join two or more labels */
57 #define OTHER_LABEL " or "
58
59 /**
60 * enum dev_type - describe the type of memory DRAM chips used at the stick
61 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
62 * @DEV_X1: 1 bit for data
63 * @DEV_X2: 2 bits for data
64 * @DEV_X4: 4 bits for data
65 * @DEV_X8: 8 bits for data
66 * @DEV_X16: 16 bits for data
67 * @DEV_X32: 32 bits for data
68 * @DEV_X64: 64 bits for data
69 *
70 * Typical values are x4 and x8.
71 */
72 enum dev_type {
73 DEV_UNKNOWN = 0,
74 DEV_X1,
75 DEV_X2,
76 DEV_X4,
77 DEV_X8,
78 DEV_X16,
79 DEV_X32, /* Do these parts exist? */
80 DEV_X64 /* Do these parts exist? */
81 };
82
83 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
84 #define DEV_FLAG_X1 BIT(DEV_X1)
85 #define DEV_FLAG_X2 BIT(DEV_X2)
86 #define DEV_FLAG_X4 BIT(DEV_X4)
87 #define DEV_FLAG_X8 BIT(DEV_X8)
88 #define DEV_FLAG_X16 BIT(DEV_X16)
89 #define DEV_FLAG_X32 BIT(DEV_X32)
90 #define DEV_FLAG_X64 BIT(DEV_X64)
91
92 /**
93 * enum hw_event_mc_err_type - type of the detected error
94 *
95 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
96 * corrected error was detected
97 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
98 * can't be corrected by ECC, but it is not
99 * fatal (maybe it is on an unused memory area,
100 * or the memory controller could recover from
101 * it for example, by re-trying the operation).
102 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
103 * error whose handling is not urgent. This could
104 * be due to hardware data poisoning where the
105 * system can continue operation until the poisoned
106 * data is consumed. Preemptive measures may also
107 * be taken, e.g. offlining pages, etc.
108 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
109 * be recovered.
110 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
111 * type of error: informational logs.
112 */
113 enum hw_event_mc_err_type {
114 HW_EVENT_ERR_CORRECTED,
115 HW_EVENT_ERR_UNCORRECTED,
116 HW_EVENT_ERR_DEFERRED,
117 HW_EVENT_ERR_FATAL,
118 HW_EVENT_ERR_INFO,
119 };
120
mc_event_error_type(const unsigned int err_type)121 static inline char *mc_event_error_type(const unsigned int err_type)
122 {
123 switch (err_type) {
124 case HW_EVENT_ERR_CORRECTED:
125 return "Corrected";
126 case HW_EVENT_ERR_UNCORRECTED:
127 return "Uncorrected";
128 case HW_EVENT_ERR_DEFERRED:
129 return "Deferred";
130 case HW_EVENT_ERR_FATAL:
131 return "Fatal";
132 default:
133 case HW_EVENT_ERR_INFO:
134 return "Info";
135 }
136 }
137
138 /**
139 * enum mem_type - memory types. For a more detailed reference, please see
140 * http://en.wikipedia.org/wiki/DRAM
141 *
142 * @MEM_EMPTY: Empty csrow
143 * @MEM_RESERVED: Reserved csrow type
144 * @MEM_UNKNOWN: Unknown csrow type
145 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
146 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
147 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
148 * @MEM_SDR: SDR - Single data rate SDRAM
149 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
150 * They use 3 pins for chip select: Pins 0 and 2 are
151 * for rank 0; pins 1 and 3 are for rank 1, if the memory
152 * is dual-rank.
153 * @MEM_RDR: Registered SDR SDRAM
154 * @MEM_DDR: Double data rate SDRAM
155 * http://en.wikipedia.org/wiki/DDR_SDRAM
156 * @MEM_RDDR: Registered Double data rate SDRAM
157 * This is a variant of the DDR memories.
158 * A registered memory has a buffer inside it, hiding
159 * part of the memory details to the memory controller.
160 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
161 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
162 * Those memories are labeled as "PC2-" instead of "PC" to
163 * differentiate from DDR.
164 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
165 * and JESD206.
166 * Those memories are accessed per DIMM slot, and not by
167 * a chip select signal.
168 * @MEM_RDDR2: Registered DDR2 RAM
169 * This is a variant of the DDR2 memories.
170 * @MEM_XDR: Rambus XDR
171 * It is an evolution of the original RAMBUS memories,
172 * created to compete with DDR2. Weren't used on any
173 * x86 arch, but cell_edac PPC memory controller uses it.
174 * @MEM_DDR3: DDR3 RAM
175 * @MEM_RDDR3: Registered DDR3 RAM
176 * This is a variant of the DDR3 memories.
177 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
178 * @MEM_LPDDR3: Low-Power DDR3 memory.
179 * @MEM_DDR4: Unbuffered DDR4 RAM
180 * @MEM_RDDR4: Registered DDR4 RAM
181 * This is a variant of the DDR4 memories.
182 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
183 * @MEM_LPDDR4: Low-Power DDR4 memory.
184 * @MEM_DDR5: Unbuffered DDR5 RAM
185 * @MEM_RDDR5: Registered DDR5 RAM
186 * @MEM_LRDDR5: Load-Reduced DDR5 memory.
187 * @MEM_LPDDR5: Low-Power DDR5 memory.
188 * @MEM_NVDIMM: Non-volatile RAM
189 * @MEM_WIO2: Wide I/O 2.
190 * @MEM_HBM2: High bandwidth Memory Gen 2.
191 * @MEM_HBM3: High bandwidth Memory Gen 3.
192 */
193 enum mem_type {
194 MEM_EMPTY = 0,
195 MEM_RESERVED,
196 MEM_UNKNOWN,
197 MEM_FPM,
198 MEM_EDO,
199 MEM_BEDO,
200 MEM_SDR,
201 MEM_RDR,
202 MEM_DDR,
203 MEM_RDDR,
204 MEM_RMBS,
205 MEM_DDR2,
206 MEM_FB_DDR2,
207 MEM_RDDR2,
208 MEM_XDR,
209 MEM_DDR3,
210 MEM_RDDR3,
211 MEM_LRDDR3,
212 MEM_LPDDR3,
213 MEM_DDR4,
214 MEM_RDDR4,
215 MEM_LRDDR4,
216 MEM_LPDDR4,
217 MEM_DDR5,
218 MEM_RDDR5,
219 MEM_LRDDR5,
220 MEM_LPDDR5,
221 MEM_NVDIMM,
222 MEM_WIO2,
223 MEM_HBM2,
224 MEM_HBM3,
225 };
226
227 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
228 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
229 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
230 #define MEM_FLAG_FPM BIT(MEM_FPM)
231 #define MEM_FLAG_EDO BIT(MEM_EDO)
232 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
233 #define MEM_FLAG_SDR BIT(MEM_SDR)
234 #define MEM_FLAG_RDR BIT(MEM_RDR)
235 #define MEM_FLAG_DDR BIT(MEM_DDR)
236 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
237 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
238 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
239 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
240 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
241 #define MEM_FLAG_XDR BIT(MEM_XDR)
242 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
243 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
244 #define MEM_FLAG_LPDDR3 BIT(MEM_LPDDR3)
245 #define MEM_FLAG_DDR4 BIT(MEM_DDR4)
246 #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
247 #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
248 #define MEM_FLAG_LPDDR4 BIT(MEM_LPDDR4)
249 #define MEM_FLAG_DDR5 BIT(MEM_DDR5)
250 #define MEM_FLAG_RDDR5 BIT(MEM_RDDR5)
251 #define MEM_FLAG_LRDDR5 BIT(MEM_LRDDR5)
252 #define MEM_FLAG_LPDDR5 BIT(MEM_LPDDR5)
253 #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
254 #define MEM_FLAG_WIO2 BIT(MEM_WIO2)
255 #define MEM_FLAG_HBM2 BIT(MEM_HBM2)
256 #define MEM_FLAG_HBM3 BIT(MEM_HBM3)
257
258 /**
259 * enum edac_type - Error Detection and Correction capabilities and mode
260 * @EDAC_UNKNOWN: Unknown if ECC is available
261 * @EDAC_NONE: Doesn't support ECC
262 * @EDAC_RESERVED: Reserved ECC type
263 * @EDAC_PARITY: Detects parity errors
264 * @EDAC_EC: Error Checking - no correction
265 * @EDAC_SECDED: Single bit error correction, Double detection
266 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
267 * @EDAC_S4ECD4ED: Chipkill x4 devices
268 * @EDAC_S8ECD8ED: Chipkill x8 devices
269 * @EDAC_S16ECD16ED: Chipkill x16 devices
270 */
271 enum edac_type {
272 EDAC_UNKNOWN = 0,
273 EDAC_NONE,
274 EDAC_RESERVED,
275 EDAC_PARITY,
276 EDAC_EC,
277 EDAC_SECDED,
278 EDAC_S2ECD2ED,
279 EDAC_S4ECD4ED,
280 EDAC_S8ECD8ED,
281 EDAC_S16ECD16ED,
282 };
283
284 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
285 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
286 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
287 #define EDAC_FLAG_EC BIT(EDAC_EC)
288 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
289 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
290 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
291 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
292 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
293
294 /**
295 * enum scrub_type - scrubbing capabilities
296 * @SCRUB_UNKNOWN: Unknown if scrubber is available
297 * @SCRUB_NONE: No scrubber
298 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
299 * @SCRUB_SW_SRC: Software scrub only errors
300 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
301 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
302 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
303 * @SCRUB_HW_SRC: Hardware scrub only errors
304 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
305 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
306 */
307 enum scrub_type {
308 SCRUB_UNKNOWN = 0,
309 SCRUB_NONE,
310 SCRUB_SW_PROG,
311 SCRUB_SW_SRC,
312 SCRUB_SW_PROG_SRC,
313 SCRUB_SW_TUNABLE,
314 SCRUB_HW_PROG,
315 SCRUB_HW_SRC,
316 SCRUB_HW_PROG_SRC,
317 SCRUB_HW_TUNABLE
318 };
319
320 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
321 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
322 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
323 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
324 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
325 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
326 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
327 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
328
329 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
330
331 /* EDAC internal operation states */
332 #define OP_ALLOC 0x100
333 #define OP_RUNNING_POLL 0x201
334 #define OP_RUNNING_INTERRUPT 0x202
335 #define OP_RUNNING_POLL_INTR 0x203
336 #define OP_OFFLINE 0x300
337
338 /**
339 * enum edac_mc_layer_type - memory controller hierarchy layer
340 *
341 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
342 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
343 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
344 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
345 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
346 * as a single memory area. This is used when
347 * retrieving errors from a firmware driven driver.
348 *
349 * This enum is used by the drivers to tell edac_mc_sysfs what name should
350 * be used when describing a memory stick location.
351 */
352 enum edac_mc_layer_type {
353 EDAC_MC_LAYER_BRANCH,
354 EDAC_MC_LAYER_CHANNEL,
355 EDAC_MC_LAYER_SLOT,
356 EDAC_MC_LAYER_CHIP_SELECT,
357 EDAC_MC_LAYER_ALL_MEM,
358 };
359
360 /**
361 * struct edac_mc_layer - describes the memory controller hierarchy
362 * @type: layer type
363 * @size: number of components per layer. For example,
364 * if the channel layer has two channels, size = 2
365 * @is_virt_csrow: This layer is part of the "csrow" when old API
366 * compatibility mode is enabled. Otherwise, it is
367 * a channel
368 */
369 struct edac_mc_layer {
370 enum edac_mc_layer_type type;
371 unsigned size;
372 bool is_virt_csrow;
373 };
374
375 /*
376 * Maximum number of layers used by the memory controller to uniquely
377 * identify a single memory stick.
378 * NOTE: Changing this constant requires not only to change the constant
379 * below, but also to change the existing code at the core, as there are
380 * some code there that are optimized for 3 layers.
381 */
382 #define EDAC_MAX_LAYERS 3
383
384 struct dimm_info {
385 struct device dev;
386
387 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
388
389 /* Memory location data */
390 unsigned int location[EDAC_MAX_LAYERS];
391
392 struct mem_ctl_info *mci; /* the parent */
393 unsigned int idx; /* index within the parent dimm array */
394
395 u32 grain; /* granularity of reported error in bytes */
396 enum dev_type dtype; /* memory device type */
397 enum mem_type mtype; /* memory dimm type */
398 enum edac_type edac_mode; /* EDAC mode for this dimm */
399
400 u32 nr_pages; /* number of pages on this dimm */
401
402 unsigned int csrow, cschannel; /* Points to the old API data */
403
404 u16 smbios_handle; /* Handle for SMBIOS type 17 */
405
406 u32 ce_count;
407 u32 ue_count;
408 };
409
410 /**
411 * struct rank_info - contains the information for one DIMM rank
412 *
413 * @chan_idx: channel number where the rank is (typically, 0 or 1)
414 * @ce_count: number of correctable errors for this rank
415 * @csrow: A pointer to the chip select row structure (the parent
416 * structure). The location of the rank is given by
417 * the (csrow->csrow_idx, chan_idx) vector.
418 * @dimm: A pointer to the DIMM structure, where the DIMM label
419 * information is stored.
420 *
421 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
422 * This is a bad assumption, but it makes this patch easier. Later
423 * patches in this series will fix this issue.
424 */
425 struct rank_info {
426 int chan_idx;
427 struct csrow_info *csrow;
428 struct dimm_info *dimm;
429
430 u32 ce_count; /* Correctable Errors for this csrow */
431 };
432
433 struct csrow_info {
434 struct device dev;
435
436 /* Used only by edac_mc_find_csrow_by_page() */
437 unsigned long first_page; /* first page number in csrow */
438 unsigned long last_page; /* last page number in csrow */
439 unsigned long page_mask; /* used for interleaving -
440 * 0UL for non intlv */
441
442 int csrow_idx; /* the chip-select row */
443
444 u32 ue_count; /* Uncorrectable Errors for this csrow */
445 u32 ce_count; /* Correctable Errors for this csrow */
446
447 struct mem_ctl_info *mci; /* the parent */
448
449 /* channel information for this csrow */
450 u32 nr_channels;
451 struct rank_info **channels;
452 };
453
454 /*
455 * struct errcount_attribute - used to store the several error counts
456 */
457 struct errcount_attribute_data {
458 int n_layers;
459 int pos[EDAC_MAX_LAYERS];
460 int layer0, layer1, layer2;
461 };
462
463 /**
464 * struct edac_raw_error_desc - Raw error report structure
465 * @grain: minimum granularity for an error report, in bytes
466 * @error_count: number of errors of the same type
467 * @type: severity of the error (CE/UE/Fatal)
468 * @top_layer: top layer of the error (layer[0])
469 * @mid_layer: middle layer of the error (layer[1])
470 * @low_layer: low layer of the error (layer[2])
471 * @page_frame_number: page where the error happened
472 * @offset_in_page: page offset
473 * @syndrome: syndrome of the error (or 0 if unknown or if
474 * the syndrome is not applicable)
475 * @msg: error message
476 * @location: location of the error
477 * @label: label of the affected DIMM(s)
478 * @other_detail: other driver-specific detail about the error
479 */
480 struct edac_raw_error_desc {
481 char location[LOCATION_SIZE];
482 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
483 long grain;
484
485 u16 error_count;
486 enum hw_event_mc_err_type type;
487 int top_layer;
488 int mid_layer;
489 int low_layer;
490 unsigned long page_frame_number;
491 unsigned long offset_in_page;
492 unsigned long syndrome;
493 const char *msg;
494 const char *other_detail;
495 };
496
497 /* MEMORY controller information structure
498 */
499 struct mem_ctl_info {
500 struct device dev;
501 const struct bus_type *bus;
502
503 struct list_head link; /* for global list of mem_ctl_info structs */
504
505 struct module *owner; /* Module owner of this control struct */
506
507 unsigned long mtype_cap; /* memory types supported by mc */
508 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
509 unsigned long edac_cap; /* configuration capabilities - this is
510 * closely related to edac_ctl_cap. The
511 * difference is that the controller may be
512 * capable of s4ecd4ed which would be listed
513 * in edac_ctl_cap, but if channels aren't
514 * capable of s4ecd4ed then the edac_cap would
515 * not have that capability.
516 */
517 unsigned long scrub_cap; /* chipset scrub capabilities */
518 enum scrub_type scrub_mode; /* current scrub mode */
519
520 /* Translates sdram memory scrub rate given in bytes/sec to the
521 internal representation and configures whatever else needs
522 to be configured.
523 */
524 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
525
526 /* Get the current sdram memory scrub rate from the internal
527 representation and converts it to the closest matching
528 bandwidth in bytes/sec.
529 */
530 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
531
532
533 /* pointer to edac checking routine */
534 void (*edac_check) (struct mem_ctl_info * mci);
535
536 /*
537 * Remaps memory pages: controller pages to physical pages.
538 * For most MC's, this will be NULL.
539 */
540 /* FIXME - why not send the phys page to begin with? */
541 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
542 unsigned long page);
543 int mc_idx;
544 struct csrow_info **csrows;
545 unsigned int nr_csrows, num_cschannel;
546
547 bool csbased;
548
549 /*
550 * DIMM info. Will eventually remove the entire csrows_info some day
551 */
552 unsigned int tot_dimms;
553 struct dimm_info **dimms;
554
555 /*
556 * FIXME - what about controllers on other busses? - IDs must be
557 * unique. dev pointer should be sufficiently unique, but
558 * BUS:SLOT.FUNC numbers may not be unique.
559 */
560 struct device *pdev;
561 const char *mod_name;
562 const char *ctl_name;
563 const char *dev_name;
564 void *pvt_info;
565 unsigned long start_time; /* mci load start time (in jiffies) */
566
567 /*
568 * drivers shouldn't access those fields directly, as the core
569 * already handles that.
570 */
571 u32 ce_noinfo_count, ue_noinfo_count;
572 u32 ue_mc, ce_mc;
573
574 struct completion complete;
575
576 /* Additional top controller level attributes, but specified
577 * by the low level driver.
578 *
579 * Set by the low level driver to provide attributes at the
580 * controller level.
581 * An array of structures, NULL terminated
582 *
583 * If attributes are desired, then set to array of attributes
584 * If no attributes are desired, leave NULL
585 */
586 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
587
588 /* work struct for this MC */
589 struct delayed_work work;
590
591 /*
592 * Used to report an error - by being at the global struct
593 * makes the memory allocated by the EDAC core
594 */
595 struct edac_raw_error_desc error_desc;
596
597 /* the internal state of this controller instance */
598 int op_state;
599
600 struct dentry *debugfs;
601
602 /*
603 * Memory Controller hierarchy
604 *
605 * There are basically two types of memory controller: the ones that
606 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
607 * All old memory controllers enumerate memories per rank, but most
608 * of the recent drivers enumerate memories per DIMM, instead.
609 * When the memory controller is per rank, csbased is true.
610 */
611 unsigned int n_layers;
612 struct edac_mc_layer layers[] __counted_by(n_layers);
613 };
614
615 #define mci_for_each_dimm(mci, dimm) \
616 for ((dimm) = (mci)->dimms[0]; \
617 (dimm); \
618 (dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \
619 ? (mci)->dimms[(dimm)->idx + 1] \
620 : NULL)
621
622 /**
623 * edac_get_dimm - Get DIMM info from a memory controller given by
624 * [layer0,layer1,layer2] position
625 *
626 * @mci: MC descriptor struct mem_ctl_info
627 * @layer0: layer0 position
628 * @layer1: layer1 position. Unused if n_layers < 2
629 * @layer2: layer2 position. Unused if n_layers < 3
630 *
631 * For 1 layer, this function returns "dimms[layer0]";
632 *
633 * For 2 layers, this function is similar to allocating a two-dimensional
634 * array and returning "dimms[layer0][layer1]";
635 *
636 * For 3 layers, this function is similar to allocating a tri-dimensional
637 * array and returning "dimms[layer0][layer1][layer2]";
638 */
edac_get_dimm(struct mem_ctl_info * mci,int layer0,int layer1,int layer2)639 static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
640 int layer0, int layer1, int layer2)
641 {
642 int index;
643
644 if (layer0 < 0
645 || (mci->n_layers > 1 && layer1 < 0)
646 || (mci->n_layers > 2 && layer2 < 0))
647 return NULL;
648
649 index = layer0;
650
651 if (mci->n_layers > 1)
652 index = index * mci->layers[1].size + layer1;
653
654 if (mci->n_layers > 2)
655 index = index * mci->layers[2].size + layer2;
656
657 if (index < 0 || index >= mci->tot_dimms)
658 return NULL;
659
660 if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
661 return NULL;
662
663 return mci->dimms[index];
664 }
665
666 #define EDAC_FEAT_NAME_LEN 128
667
668 /* RAS feature type */
669 enum edac_dev_feat {
670 RAS_FEAT_SCRUB,
671 RAS_FEAT_ECS,
672 RAS_FEAT_MEM_REPAIR,
673 RAS_FEAT_MAX
674 };
675
676 /**
677 * struct edac_scrub_ops - scrub device operations (all elements optional)
678 * @read_addr: read base address of scrubbing range.
679 * @read_size: read offset of scrubbing range.
680 * @write_addr: set base address of the scrubbing range.
681 * @write_size: set offset of the scrubbing range.
682 * @get_enabled_bg: check if currently performing background scrub.
683 * @set_enabled_bg: start or stop a bg-scrub.
684 * @get_min_cycle: get minimum supported scrub cycle duration in seconds.
685 * @get_max_cycle: get maximum supported scrub cycle duration in seconds.
686 * @get_cycle_duration: get current scrub cycle duration in seconds.
687 * @set_cycle_duration: set current scrub cycle duration in seconds.
688 */
689 struct edac_scrub_ops {
690 int (*read_addr)(struct device *dev, void *drv_data, u64 *base);
691 int (*read_size)(struct device *dev, void *drv_data, u64 *size);
692 int (*write_addr)(struct device *dev, void *drv_data, u64 base);
693 int (*write_size)(struct device *dev, void *drv_data, u64 size);
694 int (*get_enabled_bg)(struct device *dev, void *drv_data, bool *enable);
695 int (*set_enabled_bg)(struct device *dev, void *drv_data, bool enable);
696 int (*get_min_cycle)(struct device *dev, void *drv_data, u32 *min);
697 int (*get_max_cycle)(struct device *dev, void *drv_data, u32 *max);
698 int (*get_cycle_duration)(struct device *dev, void *drv_data, u32 *cycle);
699 int (*set_cycle_duration)(struct device *dev, void *drv_data, u32 cycle);
700 };
701
702 #if IS_ENABLED(CONFIG_EDAC_SCRUB)
703 int edac_scrub_get_desc(struct device *scrub_dev,
704 const struct attribute_group **attr_groups,
705 u8 instance);
706 #else
edac_scrub_get_desc(struct device * scrub_dev,const struct attribute_group ** attr_groups,u8 instance)707 static inline int edac_scrub_get_desc(struct device *scrub_dev,
708 const struct attribute_group **attr_groups,
709 u8 instance)
710 { return -EOPNOTSUPP; }
711 #endif /* CONFIG_EDAC_SCRUB */
712
713 /**
714 * struct edac_ecs_ops - ECS device operations (all elements optional)
715 * @get_log_entry_type: read the log entry type value.
716 * @set_log_entry_type: set the log entry type value.
717 * @get_mode: read the mode value.
718 * @set_mode: set the mode value.
719 * @reset: reset the ECS counter.
720 * @get_threshold: read the threshold count per gigabits of memory cells.
721 * @set_threshold: set the threshold count per gigabits of memory cells.
722 */
723 struct edac_ecs_ops {
724 int (*get_log_entry_type)(struct device *dev, void *drv_data, int fru_id, u32 *val);
725 int (*set_log_entry_type)(struct device *dev, void *drv_data, int fru_id, u32 val);
726 int (*get_mode)(struct device *dev, void *drv_data, int fru_id, u32 *val);
727 int (*set_mode)(struct device *dev, void *drv_data, int fru_id, u32 val);
728 int (*reset)(struct device *dev, void *drv_data, int fru_id, u32 val);
729 int (*get_threshold)(struct device *dev, void *drv_data, int fru_id, u32 *threshold);
730 int (*set_threshold)(struct device *dev, void *drv_data, int fru_id, u32 threshold);
731 };
732
733 struct edac_ecs_ex_info {
734 u16 num_media_frus;
735 };
736
737 #if IS_ENABLED(CONFIG_EDAC_ECS)
738 int edac_ecs_get_desc(struct device *ecs_dev,
739 const struct attribute_group **attr_groups,
740 u16 num_media_frus);
741 #else
edac_ecs_get_desc(struct device * ecs_dev,const struct attribute_group ** attr_groups,u16 num_media_frus)742 static inline int edac_ecs_get_desc(struct device *ecs_dev,
743 const struct attribute_group **attr_groups,
744 u16 num_media_frus)
745 { return -EOPNOTSUPP; }
746 #endif /* CONFIG_EDAC_ECS */
747
748 enum edac_mem_repair_type {
749 EDAC_REPAIR_PPR,
750 EDAC_REPAIR_CACHELINE_SPARING,
751 EDAC_REPAIR_ROW_SPARING,
752 EDAC_REPAIR_BANK_SPARING,
753 EDAC_REPAIR_RANK_SPARING,
754 EDAC_REPAIR_MAX
755 };
756
757 extern const char * const edac_repair_type[];
758
759 enum edac_mem_repair_cmd {
760 EDAC_DO_MEM_REPAIR = 1,
761 };
762
763 /**
764 * struct edac_mem_repair_ops - memory repair operations
765 * (all elements are optional except do_repair, set_hpa/set_dpa)
766 * @get_repair_type: get the memory repair type, listed in
767 * enum edac_mem_repair_function.
768 * @get_persist_mode: get the current persist mode.
769 * false - Soft repair type (temporary repair).
770 * true - Hard memory repair type (permanent repair).
771 * @set_persist_mode: set the persist mode of the memory repair instance.
772 * @get_repair_safe_when_in_use: get whether memory media is accessible and
773 * data is retained during repair operation.
774 * @get_hpa: get current host physical address (HPA) of memory to repair.
775 * @set_hpa: set host physical address (HPA) of memory to repair.
776 * @get_min_hpa: get the minimum supported host physical address (HPA).
777 * @get_max_hpa: get the maximum supported host physical address (HPA).
778 * @get_dpa: get current device physical address (DPA) of memory to repair.
779 * @set_dpa: set device physical address (DPA) of memory to repair.
780 * In some states of system configuration (e.g. before address decoders
781 * have been configured), memory devices (e.g. CXL) may not have an active
782 * mapping in the host physical address map. As such, the memory
783 * to repair must be identified by a device specific physical addressing
784 * scheme using a device physical address(DPA). The DPA and other control
785 * attributes to use for the repair operations will be presented in related
786 * error records.
787 * @get_min_dpa: get the minimum supported device physical address (DPA).
788 * @get_max_dpa: get the maximum supported device physical address (DPA).
789 * @get_nibble_mask: get current nibble mask of memory to repair.
790 * @set_nibble_mask: set nibble mask of memory to repair.
791 * @get_bank_group: get current bank group of memory to repair.
792 * @set_bank_group: set bank group of memory to repair.
793 * @get_bank: get current bank of memory to repair.
794 * @set_bank: set bank of memory to repair.
795 * @get_rank: get current rank of memory to repair.
796 * @set_rank: set rank of memory to repair.
797 * @get_row: get current row of memory to repair.
798 * @set_row: set row of memory to repair.
799 * @get_column: get current column of memory to repair.
800 * @set_column: set column of memory to repair.
801 * @get_channel: get current channel of memory to repair.
802 * @set_channel: set channel of memory to repair.
803 * @get_sub_channel: get current subchannel of memory to repair.
804 * @set_sub_channel: set subchannel of memory to repair.
805 * @do_repair: Issue memory repair operation for the HPA/DPA and
806 * other control attributes set for the memory to repair.
807 *
808 * All elements are optional except do_repair and at least one of set_hpa/set_dpa.
809 */
810 struct edac_mem_repair_ops {
811 int (*get_repair_type)(struct device *dev, void *drv_data, const char **type);
812 int (*get_persist_mode)(struct device *dev, void *drv_data, bool *persist);
813 int (*set_persist_mode)(struct device *dev, void *drv_data, bool persist);
814 int (*get_repair_safe_when_in_use)(struct device *dev, void *drv_data, bool *safe);
815 int (*get_hpa)(struct device *dev, void *drv_data, u64 *hpa);
816 int (*set_hpa)(struct device *dev, void *drv_data, u64 hpa);
817 int (*get_min_hpa)(struct device *dev, void *drv_data, u64 *hpa);
818 int (*get_max_hpa)(struct device *dev, void *drv_data, u64 *hpa);
819 int (*get_dpa)(struct device *dev, void *drv_data, u64 *dpa);
820 int (*set_dpa)(struct device *dev, void *drv_data, u64 dpa);
821 int (*get_min_dpa)(struct device *dev, void *drv_data, u64 *dpa);
822 int (*get_max_dpa)(struct device *dev, void *drv_data, u64 *dpa);
823 int (*get_nibble_mask)(struct device *dev, void *drv_data, u32 *val);
824 int (*set_nibble_mask)(struct device *dev, void *drv_data, u32 val);
825 int (*get_bank_group)(struct device *dev, void *drv_data, u32 *val);
826 int (*set_bank_group)(struct device *dev, void *drv_data, u32 val);
827 int (*get_bank)(struct device *dev, void *drv_data, u32 *val);
828 int (*set_bank)(struct device *dev, void *drv_data, u32 val);
829 int (*get_rank)(struct device *dev, void *drv_data, u32 *val);
830 int (*set_rank)(struct device *dev, void *drv_data, u32 val);
831 int (*get_row)(struct device *dev, void *drv_data, u32 *val);
832 int (*set_row)(struct device *dev, void *drv_data, u32 val);
833 int (*get_column)(struct device *dev, void *drv_data, u32 *val);
834 int (*set_column)(struct device *dev, void *drv_data, u32 val);
835 int (*get_channel)(struct device *dev, void *drv_data, u32 *val);
836 int (*set_channel)(struct device *dev, void *drv_data, u32 val);
837 int (*get_sub_channel)(struct device *dev, void *drv_data, u32 *val);
838 int (*set_sub_channel)(struct device *dev, void *drv_data, u32 val);
839 int (*do_repair)(struct device *dev, void *drv_data, u32 val);
840 };
841
842 #if IS_ENABLED(CONFIG_EDAC_MEM_REPAIR)
843 int edac_mem_repair_get_desc(struct device *dev,
844 const struct attribute_group **attr_groups,
845 u8 instance);
846 #else
edac_mem_repair_get_desc(struct device * dev,const struct attribute_group ** attr_groups,u8 instance)847 static inline int edac_mem_repair_get_desc(struct device *dev,
848 const struct attribute_group **attr_groups,
849 u8 instance)
850 { return -EOPNOTSUPP; }
851 #endif /* CONFIG_EDAC_MEM_REPAIR */
852
853 /* EDAC device feature information structure */
854 struct edac_dev_data {
855 union {
856 const struct edac_scrub_ops *scrub_ops;
857 const struct edac_ecs_ops *ecs_ops;
858 const struct edac_mem_repair_ops *mem_repair_ops;
859 };
860 u8 instance;
861 void *private;
862 };
863
864 struct edac_dev_feat_ctx {
865 struct device dev;
866 void *private;
867 struct edac_dev_data *scrub;
868 struct edac_dev_data ecs;
869 struct edac_dev_data *mem_repair;
870 };
871
872 struct edac_dev_feature {
873 enum edac_dev_feat ft_type;
874 u8 instance;
875 union {
876 const struct edac_scrub_ops *scrub_ops;
877 const struct edac_ecs_ops *ecs_ops;
878 const struct edac_mem_repair_ops *mem_repair_ops;
879 };
880 void *ctx;
881 struct edac_ecs_ex_info ecs_info;
882 };
883
884 int edac_dev_register(struct device *parent, char *dev_name,
885 void *parent_pvt_data, int num_features,
886 const struct edac_dev_feature *ras_features);
887 #endif /* _LINUX_EDAC_H_ */
888