Searched refs:max_supported_dispclk_khz (Results 1 – 8 of 8) sorted by relevance
120 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()123 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispc… in dml21_calculate_rq_and_dlg_params()
81 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
367 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array… in dml2_calculate_rq_and_dlg_params()371 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dml2_calculate_rq_and_dlg_params()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
875 const uint32_t max_pix_clk_khz = max(dc->clk_mgr->clks.max_supported_dispclk_khz, 400000); in dce100_validate_bandwidth()
723 int max_supported_dispclk_khz; member
1219 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn20_calculate_dlg_params()
1745 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel… in dcn32_calculate_dlg_params()