1 /* 2 MaxLinear MXL5005S VSB/QAM/DVBT tuner driver 3 4 Copyright (C) 2008 MaxLinear 5 Copyright (C) 2006 Steven Toth <stoth@linuxtv.org> 6 Functions: 7 mxl5005s_reset() 8 mxl5005s_writereg() 9 mxl5005s_writeregs() 10 mxl5005s_init() 11 mxl5005s_reconfigure() 12 mxl5005s_AssignTunerMode() 13 mxl5005s_set_params() 14 mxl5005s_get_frequency() 15 mxl5005s_get_bandwidth() 16 mxl5005s_release() 17 mxl5005s_attach() 18 19 Copyright (C) 2008 Realtek 20 Copyright (C) 2008 Jan Hoogenraad 21 Functions: 22 mxl5005s_SetRfFreqHz() 23 24 This program is free software; you can redistribute it and/or modify 25 it under the terms of the GNU General Public License as published by 26 the Free Software Foundation; either version 2 of the License, or 27 (at your option) any later version. 28 29 This program is distributed in the hope that it will be useful, 30 but WITHOUT ANY WARRANTY; without even the implied warranty of 31 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 GNU General Public License for more details. 33 34 You should have received a copy of the GNU General Public License 35 along with this program; if not, write to the Free Software 36 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 37 38 */ 39 40 /* 41 History of this driver (Steven Toth): 42 I was given a public release of a linux driver that included 43 support for the MaxLinear MXL5005S silicon tuner. Analysis of 44 the tuner driver showed clearly three things. 45 46 1. The tuner driver didn't support the LinuxTV tuner API 47 so the code Realtek added had to be removed. 48 49 2. A significant amount of the driver is reference driver code 50 from MaxLinear, I felt it was important to identify and 51 preserve this. 52 53 3. New code has to be added to interface correctly with the 54 LinuxTV API, as a regular kernel module. 55 56 Other than the reference driver enum's, I've clearly marked 57 sections of the code and retained the copyright of the 58 respective owners. 59 */ 60 #include <linux/kernel.h> 61 #include <linux/init.h> 62 #include <linux/module.h> 63 #include <linux/string.h> 64 #include <linux/slab.h> 65 #include <linux/delay.h> 66 #include <media/dvb_frontend.h> 67 #include "mxl5005s.h" 68 69 static int debug; 70 71 #define dprintk(level, arg...) do { \ 72 if (level <= debug) \ 73 printk(arg); \ 74 } while (0) 75 76 #define TUNER_REGS_NUM 104 77 #define INITCTRL_NUM 40 78 79 #ifdef _MXL_PRODUCTION 80 #define CHCTRL_NUM 39 81 #else 82 #define CHCTRL_NUM 36 83 #endif 84 85 #define MXLCTRL_NUM 189 86 #define MASTER_CONTROL_ADDR 9 87 88 /* Enumeration of Master Control Register State */ 89 enum master_control_state { 90 MC_LOAD_START = 1, 91 MC_POWER_DOWN, 92 MC_SYNTH_RESET, 93 MC_SEQ_OFF 94 }; 95 96 /* Enumeration of MXL5005 Tuner Modulation Type */ 97 enum { 98 MXL_DEFAULT_MODULATION = 0, 99 MXL_DVBT, 100 MXL_ATSC, 101 MXL_QAM, 102 MXL_ANALOG_CABLE, 103 MXL_ANALOG_OTA 104 }; 105 106 /* MXL5005 Tuner Register Struct */ 107 struct TunerReg { 108 u16 Reg_Num; /* Tuner Register Address */ 109 u16 Reg_Val; /* Current sw programmed value waiting to be written */ 110 }; 111 112 enum { 113 /* Initialization Control Names */ 114 DN_IQTN_AMP_CUT = 1, /* 1 */ 115 BB_MODE, /* 2 */ 116 BB_BUF, /* 3 */ 117 BB_BUF_OA, /* 4 */ 118 BB_ALPF_BANDSELECT, /* 5 */ 119 BB_IQSWAP, /* 6 */ 120 BB_DLPF_BANDSEL, /* 7 */ 121 RFSYN_CHP_GAIN, /* 8 */ 122 RFSYN_EN_CHP_HIGAIN, /* 9 */ 123 AGC_IF, /* 10 */ 124 AGC_RF, /* 11 */ 125 IF_DIVVAL, /* 12 */ 126 IF_VCO_BIAS, /* 13 */ 127 CHCAL_INT_MOD_IF, /* 14 */ 128 CHCAL_FRAC_MOD_IF, /* 15 */ 129 DRV_RES_SEL, /* 16 */ 130 I_DRIVER, /* 17 */ 131 EN_AAF, /* 18 */ 132 EN_3P, /* 19 */ 133 EN_AUX_3P, /* 20 */ 134 SEL_AAF_BAND, /* 21 */ 135 SEQ_ENCLK16_CLK_OUT, /* 22 */ 136 SEQ_SEL4_16B, /* 23 */ 137 XTAL_CAPSELECT, /* 24 */ 138 IF_SEL_DBL, /* 25 */ 139 RFSYN_R_DIV, /* 26 */ 140 SEQ_EXTSYNTHCALIF, /* 27 */ 141 SEQ_EXTDCCAL, /* 28 */ 142 AGC_EN_RSSI, /* 29 */ 143 RFA_ENCLKRFAGC, /* 30 */ 144 RFA_RSSI_REFH, /* 31 */ 145 RFA_RSSI_REF, /* 32 */ 146 RFA_RSSI_REFL, /* 33 */ 147 RFA_FLR, /* 34 */ 148 RFA_CEIL, /* 35 */ 149 SEQ_EXTIQFSMPULSE, /* 36 */ 150 OVERRIDE_1, /* 37 */ 151 BB_INITSTATE_DLPF_TUNE, /* 38 */ 152 TG_R_DIV, /* 39 */ 153 EN_CHP_LIN_B, /* 40 */ 154 155 /* Channel Change Control Names */ 156 DN_POLY = 51, /* 51 */ 157 DN_RFGAIN, /* 52 */ 158 DN_CAP_RFLPF, /* 53 */ 159 DN_EN_VHFUHFBAR, /* 54 */ 160 DN_GAIN_ADJUST, /* 55 */ 161 DN_IQTNBUF_AMP, /* 56 */ 162 DN_IQTNGNBFBIAS_BST, /* 57 */ 163 RFSYN_EN_OUTMUX, /* 58 */ 164 RFSYN_SEL_VCO_OUT, /* 59 */ 165 RFSYN_SEL_VCO_HI, /* 60 */ 166 RFSYN_SEL_DIVM, /* 61 */ 167 RFSYN_RF_DIV_BIAS, /* 62 */ 168 DN_SEL_FREQ, /* 63 */ 169 RFSYN_VCO_BIAS, /* 64 */ 170 CHCAL_INT_MOD_RF, /* 65 */ 171 CHCAL_FRAC_MOD_RF, /* 66 */ 172 RFSYN_LPF_R, /* 67 */ 173 CHCAL_EN_INT_RF, /* 68 */ 174 TG_LO_DIVVAL, /* 69 */ 175 TG_LO_SELVAL, /* 70 */ 176 TG_DIV_VAL, /* 71 */ 177 TG_VCO_BIAS, /* 72 */ 178 SEQ_EXTPOWERUP, /* 73 */ 179 OVERRIDE_2, /* 74 */ 180 OVERRIDE_3, /* 75 */ 181 OVERRIDE_4, /* 76 */ 182 SEQ_FSM_PULSE, /* 77 */ 183 GPIO_4B, /* 78 */ 184 GPIO_3B, /* 79 */ 185 GPIO_4, /* 80 */ 186 GPIO_3, /* 81 */ 187 GPIO_1B, /* 82 */ 188 DAC_A_ENABLE, /* 83 */ 189 DAC_B_ENABLE, /* 84 */ 190 DAC_DIN_A, /* 85 */ 191 DAC_DIN_B, /* 86 */ 192 #ifdef _MXL_PRODUCTION 193 RFSYN_EN_DIV, /* 87 */ 194 RFSYN_DIVM, /* 88 */ 195 DN_BYPASS_AGC_I2C /* 89 */ 196 #endif 197 }; 198 199 /* 200 * The following context is source code provided by MaxLinear. 201 * MaxLinear source code - Common_MXL.h (?) 202 */ 203 204 /* Constants */ 205 #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 206 #define MXL5005S_LATCH_BYTE 0xfe 207 208 /* Register address, MSB, and LSB */ 209 #define MXL5005S_BB_IQSWAP_ADDR 59 210 #define MXL5005S_BB_IQSWAP_MSB 0 211 #define MXL5005S_BB_IQSWAP_LSB 0 212 213 #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 214 #define MXL5005S_BB_DLPF_BANDSEL_MSB 4 215 #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 216 217 /* Standard modes */ 218 enum { 219 MXL5005S_STANDARD_DVBT, 220 MXL5005S_STANDARD_ATSC, 221 }; 222 #define MXL5005S_STANDARD_MODE_NUM 2 223 224 /* Bandwidth modes */ 225 enum { 226 MXL5005S_BANDWIDTH_6MHZ = 6000000, 227 MXL5005S_BANDWIDTH_7MHZ = 7000000, 228 MXL5005S_BANDWIDTH_8MHZ = 8000000, 229 }; 230 #define MXL5005S_BANDWIDTH_MODE_NUM 3 231 232 /* MXL5005 Tuner Control Struct */ 233 struct TunerControl { 234 u16 Ctrl_Num; /* Control Number */ 235 u16 size; /* Number of bits to represent Value */ 236 u16 addr[25]; /* Array of Tuner Register Address for each bit pos */ 237 u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ 238 u16 val[25]; /* Binary representation of Value */ 239 }; 240 241 /* MXL5005 Tuner Struct */ 242 struct mxl5005s_state { 243 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ 244 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ 245 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ 246 u32 IF_OUT; /* Desired IF Out Frequency */ 247 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ 248 u32 RF_IN; /* RF Input Frequency */ 249 u32 Fxtal; /* XTAL Frequency */ 250 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ 251 u16 TOP; /* Value: take over point */ 252 u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */ 253 u8 DIV_OUT; /* 4MHz or 16MHz */ 254 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ 255 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ 256 257 /* Modulation Type; */ 258 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ 259 u8 Mod_Type; 260 261 /* Tracking Filter Type */ 262 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ 263 u8 TF_Type; 264 265 /* Calculated Settings */ 266 u32 RF_LO; /* Synth RF LO Frequency */ 267 u32 IF_LO; /* Synth IF LO Frequency */ 268 u32 TG_LO; /* Synth TG_LO Frequency */ 269 270 /* Pointers to ControlName Arrays */ 271 u16 Init_Ctrl_Num; /* Number of INIT Control Names */ 272 struct TunerControl 273 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ 274 275 u16 CH_Ctrl_Num; /* Number of CH Control Names */ 276 struct TunerControl 277 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ 278 279 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ 280 struct TunerControl 281 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ 282 283 /* Pointer to Tuner Register Array */ 284 u16 TunerRegs_Num; /* Number of Tuner Registers */ 285 struct TunerReg 286 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ 287 288 /* Linux driver framework specific */ 289 struct mxl5005s_config *config; 290 struct dvb_frontend *frontend; 291 struct i2c_adapter *i2c; 292 293 /* Cache values */ 294 u32 current_mode; 295 296 }; 297 298 static u16 MXL_GetMasterControl(u8 *MasterReg, int state); 299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); 300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); 301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, 302 u8 bitVal); 303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, 304 u8 *RegVal, int *count); 305 static u32 MXL_Ceiling(u32 value, u32 resolution); 306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); 307 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, 308 u32 value, u16 controlGroup); 309 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); 310 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, 311 u8 *RegVal, int *count); 312 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); 313 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); 314 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); 315 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, 316 u8 *RegVal, int *count); 317 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, 318 u8 *datatable, u8 len); 319 static u16 MXL_IFSynthInit(struct dvb_frontend *fe); 320 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, 321 u32 bandwidth); 322 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, 323 u32 bandwidth); 324 325 /* ---------------------------------------------------------------- 326 * Begin: Custom code salvaged from the Realtek driver. 327 * Copyright (C) 2008 Realtek 328 * Copyright (C) 2008 Jan Hoogenraad 329 * This code is placed under the terms of the GNU General Public License 330 * 331 * Released by Realtek under GPLv2. 332 * Thanks to Realtek for a lot of support we received ! 333 * 334 * Revision: 080314 - original version 335 */ 336 337 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) 338 { 339 struct mxl5005s_state *state = fe->tuner_priv; 340 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 341 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 342 int TableLen; 343 344 u32 IfDivval = 0; 345 unsigned char MasterControlByte; 346 347 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); 348 349 /* Set MxL5005S tuner RF frequency according to example code. */ 350 351 /* Tuner RF frequency setting stage 0 */ 352 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); 353 AddrTable[0] = MASTER_CONTROL_ADDR; 354 ByteTable[0] |= state->config->AgcMasterByte; 355 356 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); 357 358 /* Tuner RF frequency setting stage 1 */ 359 MXL_TuneRF(fe, RfFreqHz); 360 361 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); 362 363 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); 364 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); 365 MXL_ControlWrite(fe, IF_DIVVAL, 8); 366 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen); 367 368 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); 369 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 370 ByteTable[TableLen] = MasterControlByte | 371 state->config->AgcMasterByte; 372 TableLen += 1; 373 374 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); 375 376 /* Wait 30 ms. */ 377 msleep(150); 378 379 /* Tuner RF frequency setting stage 2 */ 380 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1); 381 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval); 382 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen); 383 384 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); 385 AddrTable[TableLen] = MASTER_CONTROL_ADDR ; 386 ByteTable[TableLen] = MasterControlByte | 387 state->config->AgcMasterByte ; 388 TableLen += 1; 389 390 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); 391 392 msleep(100); 393 394 return 0; 395 } 396 /* End: Custom code taken from the Realtek driver */ 397 398 /* ---------------------------------------------------------------- 399 * Begin: Reference driver code found in the Realtek driver. 400 * Copyright (C) 2008 MaxLinear 401 */ 402 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) 403 { 404 struct mxl5005s_state *state = fe->tuner_priv; 405 state->TunerRegs_Num = TUNER_REGS_NUM ; 406 407 state->TunerRegs[0].Reg_Num = 9 ; 408 state->TunerRegs[0].Reg_Val = 0x40 ; 409 410 state->TunerRegs[1].Reg_Num = 11 ; 411 state->TunerRegs[1].Reg_Val = 0x19 ; 412 413 state->TunerRegs[2].Reg_Num = 12 ; 414 state->TunerRegs[2].Reg_Val = 0x60 ; 415 416 state->TunerRegs[3].Reg_Num = 13 ; 417 state->TunerRegs[3].Reg_Val = 0x00 ; 418 419 state->TunerRegs[4].Reg_Num = 14 ; 420 state->TunerRegs[4].Reg_Val = 0x00 ; 421 422 state->TunerRegs[5].Reg_Num = 15 ; 423 state->TunerRegs[5].Reg_Val = 0xC0 ; 424 425 state->TunerRegs[6].Reg_Num = 16 ; 426 state->TunerRegs[6].Reg_Val = 0x00 ; 427 428 state->TunerRegs[7].Reg_Num = 17 ; 429 state->TunerRegs[7].Reg_Val = 0x00 ; 430 431 state->TunerRegs[8].Reg_Num = 18 ; 432 state->TunerRegs[8].Reg_Val = 0x00 ; 433 434 state->TunerRegs[9].Reg_Num = 19 ; 435 state->TunerRegs[9].Reg_Val = 0x34 ; 436 437 state->TunerRegs[10].Reg_Num = 21 ; 438 state->TunerRegs[10].Reg_Val = 0x00 ; 439 440 state->TunerRegs[11].Reg_Num = 22 ; 441 state->TunerRegs[11].Reg_Val = 0x6B ; 442 443 state->TunerRegs[12].Reg_Num = 23 ; 444 state->TunerRegs[12].Reg_Val = 0x35 ; 445 446 state->TunerRegs[13].Reg_Num = 24 ; 447 state->TunerRegs[13].Reg_Val = 0x70 ; 448 449 state->TunerRegs[14].Reg_Num = 25 ; 450 state->TunerRegs[14].Reg_Val = 0x3E ; 451 452 state->TunerRegs[15].Reg_Num = 26 ; 453 state->TunerRegs[15].Reg_Val = 0x82 ; 454 455 state->TunerRegs[16].Reg_Num = 31 ; 456 state->TunerRegs[16].Reg_Val = 0x00 ; 457 458 state->TunerRegs[17].Reg_Num = 32 ; 459 state->TunerRegs[17].Reg_Val = 0x40 ; 460 461 state->TunerRegs[18].Reg_Num = 33 ; 462 state->TunerRegs[18].Reg_Val = 0x53 ; 463 464 state->TunerRegs[19].Reg_Num = 34 ; 465 state->TunerRegs[19].Reg_Val = 0x81 ; 466 467 state->TunerRegs[20].Reg_Num = 35 ; 468 state->TunerRegs[20].Reg_Val = 0xC9 ; 469 470 state->TunerRegs[21].Reg_Num = 36 ; 471 state->TunerRegs[21].Reg_Val = 0x01 ; 472 473 state->TunerRegs[22].Reg_Num = 37 ; 474 state->TunerRegs[22].Reg_Val = 0x00 ; 475 476 state->TunerRegs[23].Reg_Num = 41 ; 477 state->TunerRegs[23].Reg_Val = 0x00 ; 478 479 state->TunerRegs[24].Reg_Num = 42 ; 480 state->TunerRegs[24].Reg_Val = 0xF8 ; 481 482 state->TunerRegs[25].Reg_Num = 43 ; 483 state->TunerRegs[25].Reg_Val = 0x43 ; 484 485 state->TunerRegs[26].Reg_Num = 44 ; 486 state->TunerRegs[26].Reg_Val = 0x20 ; 487 488 state->TunerRegs[27].Reg_Num = 45 ; 489 state->TunerRegs[27].Reg_Val = 0x80 ; 490 491 state->TunerRegs[28].Reg_Num = 46 ; 492 state->TunerRegs[28].Reg_Val = 0x88 ; 493 494 state->TunerRegs[29].Reg_Num = 47 ; 495 state->TunerRegs[29].Reg_Val = 0x86 ; 496 497 state->TunerRegs[30].Reg_Num = 48 ; 498 state->TunerRegs[30].Reg_Val = 0x00 ; 499 500 state->TunerRegs[31].Reg_Num = 49 ; 501 state->TunerRegs[31].Reg_Val = 0x00 ; 502 503 state->TunerRegs[32].Reg_Num = 53 ; 504 state->TunerRegs[32].Reg_Val = 0x94 ; 505 506 state->TunerRegs[33].Reg_Num = 54 ; 507 state->TunerRegs[33].Reg_Val = 0xFA ; 508 509 state->TunerRegs[34].Reg_Num = 55 ; 510 state->TunerRegs[34].Reg_Val = 0x92 ; 511 512 state->TunerRegs[35].Reg_Num = 56 ; 513 state->TunerRegs[35].Reg_Val = 0x80 ; 514 515 state->TunerRegs[36].Reg_Num = 57 ; 516 state->TunerRegs[36].Reg_Val = 0x41 ; 517 518 state->TunerRegs[37].Reg_Num = 58 ; 519 state->TunerRegs[37].Reg_Val = 0xDB ; 520 521 state->TunerRegs[38].Reg_Num = 59 ; 522 state->TunerRegs[38].Reg_Val = 0x00 ; 523 524 state->TunerRegs[39].Reg_Num = 60 ; 525 state->TunerRegs[39].Reg_Val = 0x00 ; 526 527 state->TunerRegs[40].Reg_Num = 61 ; 528 state->TunerRegs[40].Reg_Val = 0x00 ; 529 530 state->TunerRegs[41].Reg_Num = 62 ; 531 state->TunerRegs[41].Reg_Val = 0x00 ; 532 533 state->TunerRegs[42].Reg_Num = 65 ; 534 state->TunerRegs[42].Reg_Val = 0xF8 ; 535 536 state->TunerRegs[43].Reg_Num = 66 ; 537 state->TunerRegs[43].Reg_Val = 0xE4 ; 538 539 state->TunerRegs[44].Reg_Num = 67 ; 540 state->TunerRegs[44].Reg_Val = 0x90 ; 541 542 state->TunerRegs[45].Reg_Num = 68 ; 543 state->TunerRegs[45].Reg_Val = 0xC0 ; 544 545 state->TunerRegs[46].Reg_Num = 69 ; 546 state->TunerRegs[46].Reg_Val = 0x01 ; 547 548 state->TunerRegs[47].Reg_Num = 70 ; 549 state->TunerRegs[47].Reg_Val = 0x50 ; 550 551 state->TunerRegs[48].Reg_Num = 71 ; 552 state->TunerRegs[48].Reg_Val = 0x06 ; 553 554 state->TunerRegs[49].Reg_Num = 72 ; 555 state->TunerRegs[49].Reg_Val = 0x00 ; 556 557 state->TunerRegs[50].Reg_Num = 73 ; 558 state->TunerRegs[50].Reg_Val = 0x20 ; 559 560 state->TunerRegs[51].Reg_Num = 76 ; 561 state->TunerRegs[51].Reg_Val = 0xBB ; 562 563 state->TunerRegs[52].Reg_Num = 77 ; 564 state->TunerRegs[52].Reg_Val = 0x13 ; 565 566 state->TunerRegs[53].Reg_Num = 81 ; 567 state->TunerRegs[53].Reg_Val = 0x04 ; 568 569 state->TunerRegs[54].Reg_Num = 82 ; 570 state->TunerRegs[54].Reg_Val = 0x75 ; 571 572 state->TunerRegs[55].Reg_Num = 83 ; 573 state->TunerRegs[55].Reg_Val = 0x00 ; 574 575 state->TunerRegs[56].Reg_Num = 84 ; 576 state->TunerRegs[56].Reg_Val = 0x00 ; 577 578 state->TunerRegs[57].Reg_Num = 85 ; 579 state->TunerRegs[57].Reg_Val = 0x00 ; 580 581 state->TunerRegs[58].Reg_Num = 91 ; 582 state->TunerRegs[58].Reg_Val = 0x70 ; 583 584 state->TunerRegs[59].Reg_Num = 92 ; 585 state->TunerRegs[59].Reg_Val = 0x00 ; 586 587 state->TunerRegs[60].Reg_Num = 93 ; 588 state->TunerRegs[60].Reg_Val = 0x00 ; 589 590 state->TunerRegs[61].Reg_Num = 94 ; 591 state->TunerRegs[61].Reg_Val = 0x00 ; 592 593 state->TunerRegs[62].Reg_Num = 95 ; 594 state->TunerRegs[62].Reg_Val = 0x0C ; 595 596 state->TunerRegs[63].Reg_Num = 96 ; 597 state->TunerRegs[63].Reg_Val = 0x00 ; 598 599 state->TunerRegs[64].Reg_Num = 97 ; 600 state->TunerRegs[64].Reg_Val = 0x00 ; 601 602 state->TunerRegs[65].Reg_Num = 98 ; 603 state->TunerRegs[65].Reg_Val = 0xE2 ; 604 605 state->TunerRegs[66].Reg_Num = 99 ; 606 state->TunerRegs[66].Reg_Val = 0x00 ; 607 608 state->TunerRegs[67].Reg_Num = 100 ; 609 state->TunerRegs[67].Reg_Val = 0x00 ; 610 611 state->TunerRegs[68].Reg_Num = 101 ; 612 state->TunerRegs[68].Reg_Val = 0x12 ; 613 614 state->TunerRegs[69].Reg_Num = 102 ; 615 state->TunerRegs[69].Reg_Val = 0x80 ; 616 617 state->TunerRegs[70].Reg_Num = 103 ; 618 state->TunerRegs[70].Reg_Val = 0x32 ; 619 620 state->TunerRegs[71].Reg_Num = 104 ; 621 state->TunerRegs[71].Reg_Val = 0xB4 ; 622 623 state->TunerRegs[72].Reg_Num = 105 ; 624 state->TunerRegs[72].Reg_Val = 0x60 ; 625 626 state->TunerRegs[73].Reg_Num = 106 ; 627 state->TunerRegs[73].Reg_Val = 0x83 ; 628 629 state->TunerRegs[74].Reg_Num = 107 ; 630 state->TunerRegs[74].Reg_Val = 0x84 ; 631 632 state->TunerRegs[75].Reg_Num = 108 ; 633 state->TunerRegs[75].Reg_Val = 0x9C ; 634 635 state->TunerRegs[76].Reg_Num = 109 ; 636 state->TunerRegs[76].Reg_Val = 0x02 ; 637 638 state->TunerRegs[77].Reg_Num = 110 ; 639 state->TunerRegs[77].Reg_Val = 0x81 ; 640 641 state->TunerRegs[78].Reg_Num = 111 ; 642 state->TunerRegs[78].Reg_Val = 0xC0 ; 643 644 state->TunerRegs[79].Reg_Num = 112 ; 645 state->TunerRegs[79].Reg_Val = 0x10 ; 646 647 state->TunerRegs[80].Reg_Num = 131 ; 648 state->TunerRegs[80].Reg_Val = 0x8A ; 649 650 state->TunerRegs[81].Reg_Num = 132 ; 651 state->TunerRegs[81].Reg_Val = 0x10 ; 652 653 state->TunerRegs[82].Reg_Num = 133 ; 654 state->TunerRegs[82].Reg_Val = 0x24 ; 655 656 state->TunerRegs[83].Reg_Num = 134 ; 657 state->TunerRegs[83].Reg_Val = 0x00 ; 658 659 state->TunerRegs[84].Reg_Num = 135 ; 660 state->TunerRegs[84].Reg_Val = 0x00 ; 661 662 state->TunerRegs[85].Reg_Num = 136 ; 663 state->TunerRegs[85].Reg_Val = 0x7E ; 664 665 state->TunerRegs[86].Reg_Num = 137 ; 666 state->TunerRegs[86].Reg_Val = 0x40 ; 667 668 state->TunerRegs[87].Reg_Num = 138 ; 669 state->TunerRegs[87].Reg_Val = 0x38 ; 670 671 state->TunerRegs[88].Reg_Num = 146 ; 672 state->TunerRegs[88].Reg_Val = 0xF6 ; 673 674 state->TunerRegs[89].Reg_Num = 147 ; 675 state->TunerRegs[89].Reg_Val = 0x1A ; 676 677 state->TunerRegs[90].Reg_Num = 148 ; 678 state->TunerRegs[90].Reg_Val = 0x62 ; 679 680 state->TunerRegs[91].Reg_Num = 149 ; 681 state->TunerRegs[91].Reg_Val = 0x33 ; 682 683 state->TunerRegs[92].Reg_Num = 150 ; 684 state->TunerRegs[92].Reg_Val = 0x80 ; 685 686 state->TunerRegs[93].Reg_Num = 156 ; 687 state->TunerRegs[93].Reg_Val = 0x56 ; 688 689 state->TunerRegs[94].Reg_Num = 157 ; 690 state->TunerRegs[94].Reg_Val = 0x17 ; 691 692 state->TunerRegs[95].Reg_Num = 158 ; 693 state->TunerRegs[95].Reg_Val = 0xA9 ; 694 695 state->TunerRegs[96].Reg_Num = 159 ; 696 state->TunerRegs[96].Reg_Val = 0x00 ; 697 698 state->TunerRegs[97].Reg_Num = 160 ; 699 state->TunerRegs[97].Reg_Val = 0x00 ; 700 701 state->TunerRegs[98].Reg_Num = 161 ; 702 state->TunerRegs[98].Reg_Val = 0x00 ; 703 704 state->TunerRegs[99].Reg_Num = 162 ; 705 state->TunerRegs[99].Reg_Val = 0x40 ; 706 707 state->TunerRegs[100].Reg_Num = 166 ; 708 state->TunerRegs[100].Reg_Val = 0xAE ; 709 710 state->TunerRegs[101].Reg_Num = 167 ; 711 state->TunerRegs[101].Reg_Val = 0x1B ; 712 713 state->TunerRegs[102].Reg_Num = 168 ; 714 state->TunerRegs[102].Reg_Val = 0xF2 ; 715 716 state->TunerRegs[103].Reg_Num = 195 ; 717 state->TunerRegs[103].Reg_Val = 0x00 ; 718 719 return 0 ; 720 } 721 722 static u16 MXL5005_ControlInit(struct dvb_frontend *fe) 723 { 724 struct mxl5005s_state *state = fe->tuner_priv; 725 state->Init_Ctrl_Num = INITCTRL_NUM; 726 727 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; 728 state->Init_Ctrl[0].size = 1 ; 729 state->Init_Ctrl[0].addr[0] = 73; 730 state->Init_Ctrl[0].bit[0] = 7; 731 state->Init_Ctrl[0].val[0] = 0; 732 733 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; 734 state->Init_Ctrl[1].size = 1 ; 735 state->Init_Ctrl[1].addr[0] = 53; 736 state->Init_Ctrl[1].bit[0] = 2; 737 state->Init_Ctrl[1].val[0] = 1; 738 739 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; 740 state->Init_Ctrl[2].size = 2 ; 741 state->Init_Ctrl[2].addr[0] = 53; 742 state->Init_Ctrl[2].bit[0] = 1; 743 state->Init_Ctrl[2].val[0] = 0; 744 state->Init_Ctrl[2].addr[1] = 57; 745 state->Init_Ctrl[2].bit[1] = 0; 746 state->Init_Ctrl[2].val[1] = 1; 747 748 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; 749 state->Init_Ctrl[3].size = 1 ; 750 state->Init_Ctrl[3].addr[0] = 53; 751 state->Init_Ctrl[3].bit[0] = 0; 752 state->Init_Ctrl[3].val[0] = 0; 753 754 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; 755 state->Init_Ctrl[4].size = 3 ; 756 state->Init_Ctrl[4].addr[0] = 53; 757 state->Init_Ctrl[4].bit[0] = 5; 758 state->Init_Ctrl[4].val[0] = 0; 759 state->Init_Ctrl[4].addr[1] = 53; 760 state->Init_Ctrl[4].bit[1] = 6; 761 state->Init_Ctrl[4].val[1] = 0; 762 state->Init_Ctrl[4].addr[2] = 53; 763 state->Init_Ctrl[4].bit[2] = 7; 764 state->Init_Ctrl[4].val[2] = 1; 765 766 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; 767 state->Init_Ctrl[5].size = 1 ; 768 state->Init_Ctrl[5].addr[0] = 59; 769 state->Init_Ctrl[5].bit[0] = 0; 770 state->Init_Ctrl[5].val[0] = 0; 771 772 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; 773 state->Init_Ctrl[6].size = 2 ; 774 state->Init_Ctrl[6].addr[0] = 53; 775 state->Init_Ctrl[6].bit[0] = 3; 776 state->Init_Ctrl[6].val[0] = 0; 777 state->Init_Ctrl[6].addr[1] = 53; 778 state->Init_Ctrl[6].bit[1] = 4; 779 state->Init_Ctrl[6].val[1] = 1; 780 781 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; 782 state->Init_Ctrl[7].size = 4 ; 783 state->Init_Ctrl[7].addr[0] = 22; 784 state->Init_Ctrl[7].bit[0] = 4; 785 state->Init_Ctrl[7].val[0] = 0; 786 state->Init_Ctrl[7].addr[1] = 22; 787 state->Init_Ctrl[7].bit[1] = 5; 788 state->Init_Ctrl[7].val[1] = 1; 789 state->Init_Ctrl[7].addr[2] = 22; 790 state->Init_Ctrl[7].bit[2] = 6; 791 state->Init_Ctrl[7].val[2] = 1; 792 state->Init_Ctrl[7].addr[3] = 22; 793 state->Init_Ctrl[7].bit[3] = 7; 794 state->Init_Ctrl[7].val[3] = 0; 795 796 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; 797 state->Init_Ctrl[8].size = 1 ; 798 state->Init_Ctrl[8].addr[0] = 22; 799 state->Init_Ctrl[8].bit[0] = 2; 800 state->Init_Ctrl[8].val[0] = 0; 801 802 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; 803 state->Init_Ctrl[9].size = 4 ; 804 state->Init_Ctrl[9].addr[0] = 76; 805 state->Init_Ctrl[9].bit[0] = 0; 806 state->Init_Ctrl[9].val[0] = 1; 807 state->Init_Ctrl[9].addr[1] = 76; 808 state->Init_Ctrl[9].bit[1] = 1; 809 state->Init_Ctrl[9].val[1] = 1; 810 state->Init_Ctrl[9].addr[2] = 76; 811 state->Init_Ctrl[9].bit[2] = 2; 812 state->Init_Ctrl[9].val[2] = 0; 813 state->Init_Ctrl[9].addr[3] = 76; 814 state->Init_Ctrl[9].bit[3] = 3; 815 state->Init_Ctrl[9].val[3] = 1; 816 817 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; 818 state->Init_Ctrl[10].size = 4 ; 819 state->Init_Ctrl[10].addr[0] = 76; 820 state->Init_Ctrl[10].bit[0] = 4; 821 state->Init_Ctrl[10].val[0] = 1; 822 state->Init_Ctrl[10].addr[1] = 76; 823 state->Init_Ctrl[10].bit[1] = 5; 824 state->Init_Ctrl[10].val[1] = 1; 825 state->Init_Ctrl[10].addr[2] = 76; 826 state->Init_Ctrl[10].bit[2] = 6; 827 state->Init_Ctrl[10].val[2] = 0; 828 state->Init_Ctrl[10].addr[3] = 76; 829 state->Init_Ctrl[10].bit[3] = 7; 830 state->Init_Ctrl[10].val[3] = 1; 831 832 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; 833 state->Init_Ctrl[11].size = 5 ; 834 state->Init_Ctrl[11].addr[0] = 43; 835 state->Init_Ctrl[11].bit[0] = 3; 836 state->Init_Ctrl[11].val[0] = 0; 837 state->Init_Ctrl[11].addr[1] = 43; 838 state->Init_Ctrl[11].bit[1] = 4; 839 state->Init_Ctrl[11].val[1] = 0; 840 state->Init_Ctrl[11].addr[2] = 43; 841 state->Init_Ctrl[11].bit[2] = 5; 842 state->Init_Ctrl[11].val[2] = 0; 843 state->Init_Ctrl[11].addr[3] = 43; 844 state->Init_Ctrl[11].bit[3] = 6; 845 state->Init_Ctrl[11].val[3] = 1; 846 state->Init_Ctrl[11].addr[4] = 43; 847 state->Init_Ctrl[11].bit[4] = 7; 848 state->Init_Ctrl[11].val[4] = 0; 849 850 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; 851 state->Init_Ctrl[12].size = 6 ; 852 state->Init_Ctrl[12].addr[0] = 44; 853 state->Init_Ctrl[12].bit[0] = 2; 854 state->Init_Ctrl[12].val[0] = 0; 855 state->Init_Ctrl[12].addr[1] = 44; 856 state->Init_Ctrl[12].bit[1] = 3; 857 state->Init_Ctrl[12].val[1] = 0; 858 state->Init_Ctrl[12].addr[2] = 44; 859 state->Init_Ctrl[12].bit[2] = 4; 860 state->Init_Ctrl[12].val[2] = 0; 861 state->Init_Ctrl[12].addr[3] = 44; 862 state->Init_Ctrl[12].bit[3] = 5; 863 state->Init_Ctrl[12].val[3] = 1; 864 state->Init_Ctrl[12].addr[4] = 44; 865 state->Init_Ctrl[12].bit[4] = 6; 866 state->Init_Ctrl[12].val[4] = 0; 867 state->Init_Ctrl[12].addr[5] = 44; 868 state->Init_Ctrl[12].bit[5] = 7; 869 state->Init_Ctrl[12].val[5] = 0; 870 871 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; 872 state->Init_Ctrl[13].size = 7 ; 873 state->Init_Ctrl[13].addr[0] = 11; 874 state->Init_Ctrl[13].bit[0] = 0; 875 state->Init_Ctrl[13].val[0] = 1; 876 state->Init_Ctrl[13].addr[1] = 11; 877 state->Init_Ctrl[13].bit[1] = 1; 878 state->Init_Ctrl[13].val[1] = 0; 879 state->Init_Ctrl[13].addr[2] = 11; 880 state->Init_Ctrl[13].bit[2] = 2; 881 state->Init_Ctrl[13].val[2] = 0; 882 state->Init_Ctrl[13].addr[3] = 11; 883 state->Init_Ctrl[13].bit[3] = 3; 884 state->Init_Ctrl[13].val[3] = 1; 885 state->Init_Ctrl[13].addr[4] = 11; 886 state->Init_Ctrl[13].bit[4] = 4; 887 state->Init_Ctrl[13].val[4] = 1; 888 state->Init_Ctrl[13].addr[5] = 11; 889 state->Init_Ctrl[13].bit[5] = 5; 890 state->Init_Ctrl[13].val[5] = 0; 891 state->Init_Ctrl[13].addr[6] = 11; 892 state->Init_Ctrl[13].bit[6] = 6; 893 state->Init_Ctrl[13].val[6] = 0; 894 895 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; 896 state->Init_Ctrl[14].size = 16 ; 897 state->Init_Ctrl[14].addr[0] = 13; 898 state->Init_Ctrl[14].bit[0] = 0; 899 state->Init_Ctrl[14].val[0] = 0; 900 state->Init_Ctrl[14].addr[1] = 13; 901 state->Init_Ctrl[14].bit[1] = 1; 902 state->Init_Ctrl[14].val[1] = 0; 903 state->Init_Ctrl[14].addr[2] = 13; 904 state->Init_Ctrl[14].bit[2] = 2; 905 state->Init_Ctrl[14].val[2] = 0; 906 state->Init_Ctrl[14].addr[3] = 13; 907 state->Init_Ctrl[14].bit[3] = 3; 908 state->Init_Ctrl[14].val[3] = 0; 909 state->Init_Ctrl[14].addr[4] = 13; 910 state->Init_Ctrl[14].bit[4] = 4; 911 state->Init_Ctrl[14].val[4] = 0; 912 state->Init_Ctrl[14].addr[5] = 13; 913 state->Init_Ctrl[14].bit[5] = 5; 914 state->Init_Ctrl[14].val[5] = 0; 915 state->Init_Ctrl[14].addr[6] = 13; 916 state->Init_Ctrl[14].bit[6] = 6; 917 state->Init_Ctrl[14].val[6] = 0; 918 state->Init_Ctrl[14].addr[7] = 13; 919 state->Init_Ctrl[14].bit[7] = 7; 920 state->Init_Ctrl[14].val[7] = 0; 921 state->Init_Ctrl[14].addr[8] = 12; 922 state->Init_Ctrl[14].bit[8] = 0; 923 state->Init_Ctrl[14].val[8] = 0; 924 state->Init_Ctrl[14].addr[9] = 12; 925 state->Init_Ctrl[14].bit[9] = 1; 926 state->Init_Ctrl[14].val[9] = 0; 927 state->Init_Ctrl[14].addr[10] = 12; 928 state->Init_Ctrl[14].bit[10] = 2; 929 state->Init_Ctrl[14].val[10] = 0; 930 state->Init_Ctrl[14].addr[11] = 12; 931 state->Init_Ctrl[14].bit[11] = 3; 932 state->Init_Ctrl[14].val[11] = 0; 933 state->Init_Ctrl[14].addr[12] = 12; 934 state->Init_Ctrl[14].bit[12] = 4; 935 state->Init_Ctrl[14].val[12] = 0; 936 state->Init_Ctrl[14].addr[13] = 12; 937 state->Init_Ctrl[14].bit[13] = 5; 938 state->Init_Ctrl[14].val[13] = 1; 939 state->Init_Ctrl[14].addr[14] = 12; 940 state->Init_Ctrl[14].bit[14] = 6; 941 state->Init_Ctrl[14].val[14] = 1; 942 state->Init_Ctrl[14].addr[15] = 12; 943 state->Init_Ctrl[14].bit[15] = 7; 944 state->Init_Ctrl[14].val[15] = 0; 945 946 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; 947 state->Init_Ctrl[15].size = 3 ; 948 state->Init_Ctrl[15].addr[0] = 147; 949 state->Init_Ctrl[15].bit[0] = 2; 950 state->Init_Ctrl[15].val[0] = 0; 951 state->Init_Ctrl[15].addr[1] = 147; 952 state->Init_Ctrl[15].bit[1] = 3; 953 state->Init_Ctrl[15].val[1] = 1; 954 state->Init_Ctrl[15].addr[2] = 147; 955 state->Init_Ctrl[15].bit[2] = 4; 956 state->Init_Ctrl[15].val[2] = 1; 957 958 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; 959 state->Init_Ctrl[16].size = 2 ; 960 state->Init_Ctrl[16].addr[0] = 147; 961 state->Init_Ctrl[16].bit[0] = 0; 962 state->Init_Ctrl[16].val[0] = 0; 963 state->Init_Ctrl[16].addr[1] = 147; 964 state->Init_Ctrl[16].bit[1] = 1; 965 state->Init_Ctrl[16].val[1] = 1; 966 967 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; 968 state->Init_Ctrl[17].size = 1 ; 969 state->Init_Ctrl[17].addr[0] = 147; 970 state->Init_Ctrl[17].bit[0] = 7; 971 state->Init_Ctrl[17].val[0] = 0; 972 973 state->Init_Ctrl[18].Ctrl_Num = EN_3P ; 974 state->Init_Ctrl[18].size = 1 ; 975 state->Init_Ctrl[18].addr[0] = 147; 976 state->Init_Ctrl[18].bit[0] = 6; 977 state->Init_Ctrl[18].val[0] = 0; 978 979 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; 980 state->Init_Ctrl[19].size = 1 ; 981 state->Init_Ctrl[19].addr[0] = 156; 982 state->Init_Ctrl[19].bit[0] = 0; 983 state->Init_Ctrl[19].val[0] = 0; 984 985 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; 986 state->Init_Ctrl[20].size = 1 ; 987 state->Init_Ctrl[20].addr[0] = 147; 988 state->Init_Ctrl[20].bit[0] = 5; 989 state->Init_Ctrl[20].val[0] = 0; 990 991 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; 992 state->Init_Ctrl[21].size = 1 ; 993 state->Init_Ctrl[21].addr[0] = 137; 994 state->Init_Ctrl[21].bit[0] = 4; 995 state->Init_Ctrl[21].val[0] = 0; 996 997 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; 998 state->Init_Ctrl[22].size = 1 ; 999 state->Init_Ctrl[22].addr[0] = 137; 1000 state->Init_Ctrl[22].bit[0] = 7; 1001 state->Init_Ctrl[22].val[0] = 0; 1002 1003 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; 1004 state->Init_Ctrl[23].size = 1 ; 1005 state->Init_Ctrl[23].addr[0] = 91; 1006 state->Init_Ctrl[23].bit[0] = 5; 1007 state->Init_Ctrl[23].val[0] = 1; 1008 1009 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; 1010 state->Init_Ctrl[24].size = 1 ; 1011 state->Init_Ctrl[24].addr[0] = 43; 1012 state->Init_Ctrl[24].bit[0] = 0; 1013 state->Init_Ctrl[24].val[0] = 1; 1014 1015 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; 1016 state->Init_Ctrl[25].size = 2 ; 1017 state->Init_Ctrl[25].addr[0] = 22; 1018 state->Init_Ctrl[25].bit[0] = 0; 1019 state->Init_Ctrl[25].val[0] = 1; 1020 state->Init_Ctrl[25].addr[1] = 22; 1021 state->Init_Ctrl[25].bit[1] = 1; 1022 state->Init_Ctrl[25].val[1] = 1; 1023 1024 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; 1025 state->Init_Ctrl[26].size = 1 ; 1026 state->Init_Ctrl[26].addr[0] = 134; 1027 state->Init_Ctrl[26].bit[0] = 2; 1028 state->Init_Ctrl[26].val[0] = 0; 1029 1030 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; 1031 state->Init_Ctrl[27].size = 1 ; 1032 state->Init_Ctrl[27].addr[0] = 137; 1033 state->Init_Ctrl[27].bit[0] = 3; 1034 state->Init_Ctrl[27].val[0] = 0; 1035 1036 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; 1037 state->Init_Ctrl[28].size = 1 ; 1038 state->Init_Ctrl[28].addr[0] = 77; 1039 state->Init_Ctrl[28].bit[0] = 7; 1040 state->Init_Ctrl[28].val[0] = 0; 1041 1042 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; 1043 state->Init_Ctrl[29].size = 1 ; 1044 state->Init_Ctrl[29].addr[0] = 166; 1045 state->Init_Ctrl[29].bit[0] = 7; 1046 state->Init_Ctrl[29].val[0] = 1; 1047 1048 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; 1049 state->Init_Ctrl[30].size = 3 ; 1050 state->Init_Ctrl[30].addr[0] = 166; 1051 state->Init_Ctrl[30].bit[0] = 0; 1052 state->Init_Ctrl[30].val[0] = 0; 1053 state->Init_Ctrl[30].addr[1] = 166; 1054 state->Init_Ctrl[30].bit[1] = 1; 1055 state->Init_Ctrl[30].val[1] = 1; 1056 state->Init_Ctrl[30].addr[2] = 166; 1057 state->Init_Ctrl[30].bit[2] = 2; 1058 state->Init_Ctrl[30].val[2] = 1; 1059 1060 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; 1061 state->Init_Ctrl[31].size = 3 ; 1062 state->Init_Ctrl[31].addr[0] = 166; 1063 state->Init_Ctrl[31].bit[0] = 3; 1064 state->Init_Ctrl[31].val[0] = 1; 1065 state->Init_Ctrl[31].addr[1] = 166; 1066 state->Init_Ctrl[31].bit[1] = 4; 1067 state->Init_Ctrl[31].val[1] = 0; 1068 state->Init_Ctrl[31].addr[2] = 166; 1069 state->Init_Ctrl[31].bit[2] = 5; 1070 state->Init_Ctrl[31].val[2] = 1; 1071 1072 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; 1073 state->Init_Ctrl[32].size = 3 ; 1074 state->Init_Ctrl[32].addr[0] = 167; 1075 state->Init_Ctrl[32].bit[0] = 0; 1076 state->Init_Ctrl[32].val[0] = 1; 1077 state->Init_Ctrl[32].addr[1] = 167; 1078 state->Init_Ctrl[32].bit[1] = 1; 1079 state->Init_Ctrl[32].val[1] = 1; 1080 state->Init_Ctrl[32].addr[2] = 167; 1081 state->Init_Ctrl[32].bit[2] = 2; 1082 state->Init_Ctrl[32].val[2] = 0; 1083 1084 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; 1085 state->Init_Ctrl[33].size = 4 ; 1086 state->Init_Ctrl[33].addr[0] = 168; 1087 state->Init_Ctrl[33].bit[0] = 0; 1088 state->Init_Ctrl[33].val[0] = 0; 1089 state->Init_Ctrl[33].addr[1] = 168; 1090 state->Init_Ctrl[33].bit[1] = 1; 1091 state->Init_Ctrl[33].val[1] = 1; 1092 state->Init_Ctrl[33].addr[2] = 168; 1093 state->Init_Ctrl[33].bit[2] = 2; 1094 state->Init_Ctrl[33].val[2] = 0; 1095 state->Init_Ctrl[33].addr[3] = 168; 1096 state->Init_Ctrl[33].bit[3] = 3; 1097 state->Init_Ctrl[33].val[3] = 0; 1098 1099 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; 1100 state->Init_Ctrl[34].size = 4 ; 1101 state->Init_Ctrl[34].addr[0] = 168; 1102 state->Init_Ctrl[34].bit[0] = 4; 1103 state->Init_Ctrl[34].val[0] = 1; 1104 state->Init_Ctrl[34].addr[1] = 168; 1105 state->Init_Ctrl[34].bit[1] = 5; 1106 state->Init_Ctrl[34].val[1] = 1; 1107 state->Init_Ctrl[34].addr[2] = 168; 1108 state->Init_Ctrl[34].bit[2] = 6; 1109 state->Init_Ctrl[34].val[2] = 1; 1110 state->Init_Ctrl[34].addr[3] = 168; 1111 state->Init_Ctrl[34].bit[3] = 7; 1112 state->Init_Ctrl[34].val[3] = 1; 1113 1114 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; 1115 state->Init_Ctrl[35].size = 1 ; 1116 state->Init_Ctrl[35].addr[0] = 135; 1117 state->Init_Ctrl[35].bit[0] = 0; 1118 state->Init_Ctrl[35].val[0] = 0; 1119 1120 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; 1121 state->Init_Ctrl[36].size = 1 ; 1122 state->Init_Ctrl[36].addr[0] = 56; 1123 state->Init_Ctrl[36].bit[0] = 3; 1124 state->Init_Ctrl[36].val[0] = 0; 1125 1126 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; 1127 state->Init_Ctrl[37].size = 7 ; 1128 state->Init_Ctrl[37].addr[0] = 59; 1129 state->Init_Ctrl[37].bit[0] = 1; 1130 state->Init_Ctrl[37].val[0] = 0; 1131 state->Init_Ctrl[37].addr[1] = 59; 1132 state->Init_Ctrl[37].bit[1] = 2; 1133 state->Init_Ctrl[37].val[1] = 0; 1134 state->Init_Ctrl[37].addr[2] = 59; 1135 state->Init_Ctrl[37].bit[2] = 3; 1136 state->Init_Ctrl[37].val[2] = 0; 1137 state->Init_Ctrl[37].addr[3] = 59; 1138 state->Init_Ctrl[37].bit[3] = 4; 1139 state->Init_Ctrl[37].val[3] = 0; 1140 state->Init_Ctrl[37].addr[4] = 59; 1141 state->Init_Ctrl[37].bit[4] = 5; 1142 state->Init_Ctrl[37].val[4] = 0; 1143 state->Init_Ctrl[37].addr[5] = 59; 1144 state->Init_Ctrl[37].bit[5] = 6; 1145 state->Init_Ctrl[37].val[5] = 0; 1146 state->Init_Ctrl[37].addr[6] = 59; 1147 state->Init_Ctrl[37].bit[6] = 7; 1148 state->Init_Ctrl[37].val[6] = 0; 1149 1150 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; 1151 state->Init_Ctrl[38].size = 6 ; 1152 state->Init_Ctrl[38].addr[0] = 32; 1153 state->Init_Ctrl[38].bit[0] = 2; 1154 state->Init_Ctrl[38].val[0] = 0; 1155 state->Init_Ctrl[38].addr[1] = 32; 1156 state->Init_Ctrl[38].bit[1] = 3; 1157 state->Init_Ctrl[38].val[1] = 0; 1158 state->Init_Ctrl[38].addr[2] = 32; 1159 state->Init_Ctrl[38].bit[2] = 4; 1160 state->Init_Ctrl[38].val[2] = 0; 1161 state->Init_Ctrl[38].addr[3] = 32; 1162 state->Init_Ctrl[38].bit[3] = 5; 1163 state->Init_Ctrl[38].val[3] = 0; 1164 state->Init_Ctrl[38].addr[4] = 32; 1165 state->Init_Ctrl[38].bit[4] = 6; 1166 state->Init_Ctrl[38].val[4] = 1; 1167 state->Init_Ctrl[38].addr[5] = 32; 1168 state->Init_Ctrl[38].bit[5] = 7; 1169 state->Init_Ctrl[38].val[5] = 0; 1170 1171 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; 1172 state->Init_Ctrl[39].size = 1 ; 1173 state->Init_Ctrl[39].addr[0] = 25; 1174 state->Init_Ctrl[39].bit[0] = 3; 1175 state->Init_Ctrl[39].val[0] = 1; 1176 1177 return 0; 1178 } 1179 1180 static u16 MXL5005_ControlInitCH(struct dvb_frontend *fe) 1181 { 1182 struct mxl5005s_state *state = fe->tuner_priv; 1183 state->CH_Ctrl_Num = CHCTRL_NUM ; 1184 1185 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; 1186 state->CH_Ctrl[0].size = 2 ; 1187 state->CH_Ctrl[0].addr[0] = 68; 1188 state->CH_Ctrl[0].bit[0] = 6; 1189 state->CH_Ctrl[0].val[0] = 1; 1190 state->CH_Ctrl[0].addr[1] = 68; 1191 state->CH_Ctrl[0].bit[1] = 7; 1192 state->CH_Ctrl[0].val[1] = 1; 1193 1194 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; 1195 state->CH_Ctrl[1].size = 2 ; 1196 state->CH_Ctrl[1].addr[0] = 70; 1197 state->CH_Ctrl[1].bit[0] = 6; 1198 state->CH_Ctrl[1].val[0] = 1; 1199 state->CH_Ctrl[1].addr[1] = 70; 1200 state->CH_Ctrl[1].bit[1] = 7; 1201 state->CH_Ctrl[1].val[1] = 0; 1202 1203 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; 1204 state->CH_Ctrl[2].size = 9 ; 1205 state->CH_Ctrl[2].addr[0] = 69; 1206 state->CH_Ctrl[2].bit[0] = 5; 1207 state->CH_Ctrl[2].val[0] = 0; 1208 state->CH_Ctrl[2].addr[1] = 69; 1209 state->CH_Ctrl[2].bit[1] = 6; 1210 state->CH_Ctrl[2].val[1] = 0; 1211 state->CH_Ctrl[2].addr[2] = 69; 1212 state->CH_Ctrl[2].bit[2] = 7; 1213 state->CH_Ctrl[2].val[2] = 0; 1214 state->CH_Ctrl[2].addr[3] = 68; 1215 state->CH_Ctrl[2].bit[3] = 0; 1216 state->CH_Ctrl[2].val[3] = 0; 1217 state->CH_Ctrl[2].addr[4] = 68; 1218 state->CH_Ctrl[2].bit[4] = 1; 1219 state->CH_Ctrl[2].val[4] = 0; 1220 state->CH_Ctrl[2].addr[5] = 68; 1221 state->CH_Ctrl[2].bit[5] = 2; 1222 state->CH_Ctrl[2].val[5] = 0; 1223 state->CH_Ctrl[2].addr[6] = 68; 1224 state->CH_Ctrl[2].bit[6] = 3; 1225 state->CH_Ctrl[2].val[6] = 0; 1226 state->CH_Ctrl[2].addr[7] = 68; 1227 state->CH_Ctrl[2].bit[7] = 4; 1228 state->CH_Ctrl[2].val[7] = 0; 1229 state->CH_Ctrl[2].addr[8] = 68; 1230 state->CH_Ctrl[2].bit[8] = 5; 1231 state->CH_Ctrl[2].val[8] = 0; 1232 1233 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; 1234 state->CH_Ctrl[3].size = 1 ; 1235 state->CH_Ctrl[3].addr[0] = 70; 1236 state->CH_Ctrl[3].bit[0] = 5; 1237 state->CH_Ctrl[3].val[0] = 0; 1238 1239 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; 1240 state->CH_Ctrl[4].size = 3 ; 1241 state->CH_Ctrl[4].addr[0] = 73; 1242 state->CH_Ctrl[4].bit[0] = 4; 1243 state->CH_Ctrl[4].val[0] = 0; 1244 state->CH_Ctrl[4].addr[1] = 73; 1245 state->CH_Ctrl[4].bit[1] = 5; 1246 state->CH_Ctrl[4].val[1] = 1; 1247 state->CH_Ctrl[4].addr[2] = 73; 1248 state->CH_Ctrl[4].bit[2] = 6; 1249 state->CH_Ctrl[4].val[2] = 0; 1250 1251 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; 1252 state->CH_Ctrl[5].size = 4 ; 1253 state->CH_Ctrl[5].addr[0] = 70; 1254 state->CH_Ctrl[5].bit[0] = 0; 1255 state->CH_Ctrl[5].val[0] = 0; 1256 state->CH_Ctrl[5].addr[1] = 70; 1257 state->CH_Ctrl[5].bit[1] = 1; 1258 state->CH_Ctrl[5].val[1] = 0; 1259 state->CH_Ctrl[5].addr[2] = 70; 1260 state->CH_Ctrl[5].bit[2] = 2; 1261 state->CH_Ctrl[5].val[2] = 0; 1262 state->CH_Ctrl[5].addr[3] = 70; 1263 state->CH_Ctrl[5].bit[3] = 3; 1264 state->CH_Ctrl[5].val[3] = 0; 1265 1266 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; 1267 state->CH_Ctrl[6].size = 1 ; 1268 state->CH_Ctrl[6].addr[0] = 70; 1269 state->CH_Ctrl[6].bit[0] = 4; 1270 state->CH_Ctrl[6].val[0] = 1; 1271 1272 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; 1273 state->CH_Ctrl[7].size = 1 ; 1274 state->CH_Ctrl[7].addr[0] = 111; 1275 state->CH_Ctrl[7].bit[0] = 4; 1276 state->CH_Ctrl[7].val[0] = 0; 1277 1278 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; 1279 state->CH_Ctrl[8].size = 1 ; 1280 state->CH_Ctrl[8].addr[0] = 111; 1281 state->CH_Ctrl[8].bit[0] = 7; 1282 state->CH_Ctrl[8].val[0] = 1; 1283 1284 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; 1285 state->CH_Ctrl[9].size = 1 ; 1286 state->CH_Ctrl[9].addr[0] = 111; 1287 state->CH_Ctrl[9].bit[0] = 6; 1288 state->CH_Ctrl[9].val[0] = 1; 1289 1290 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; 1291 state->CH_Ctrl[10].size = 1 ; 1292 state->CH_Ctrl[10].addr[0] = 111; 1293 state->CH_Ctrl[10].bit[0] = 5; 1294 state->CH_Ctrl[10].val[0] = 0; 1295 1296 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; 1297 state->CH_Ctrl[11].size = 2 ; 1298 state->CH_Ctrl[11].addr[0] = 110; 1299 state->CH_Ctrl[11].bit[0] = 0; 1300 state->CH_Ctrl[11].val[0] = 1; 1301 state->CH_Ctrl[11].addr[1] = 110; 1302 state->CH_Ctrl[11].bit[1] = 1; 1303 state->CH_Ctrl[11].val[1] = 0; 1304 1305 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; 1306 state->CH_Ctrl[12].size = 3 ; 1307 state->CH_Ctrl[12].addr[0] = 69; 1308 state->CH_Ctrl[12].bit[0] = 2; 1309 state->CH_Ctrl[12].val[0] = 0; 1310 state->CH_Ctrl[12].addr[1] = 69; 1311 state->CH_Ctrl[12].bit[1] = 3; 1312 state->CH_Ctrl[12].val[1] = 0; 1313 state->CH_Ctrl[12].addr[2] = 69; 1314 state->CH_Ctrl[12].bit[2] = 4; 1315 state->CH_Ctrl[12].val[2] = 0; 1316 1317 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; 1318 state->CH_Ctrl[13].size = 6 ; 1319 state->CH_Ctrl[13].addr[0] = 110; 1320 state->CH_Ctrl[13].bit[0] = 2; 1321 state->CH_Ctrl[13].val[0] = 0; 1322 state->CH_Ctrl[13].addr[1] = 110; 1323 state->CH_Ctrl[13].bit[1] = 3; 1324 state->CH_Ctrl[13].val[1] = 0; 1325 state->CH_Ctrl[13].addr[2] = 110; 1326 state->CH_Ctrl[13].bit[2] = 4; 1327 state->CH_Ctrl[13].val[2] = 0; 1328 state->CH_Ctrl[13].addr[3] = 110; 1329 state->CH_Ctrl[13].bit[3] = 5; 1330 state->CH_Ctrl[13].val[3] = 0; 1331 state->CH_Ctrl[13].addr[4] = 110; 1332 state->CH_Ctrl[13].bit[4] = 6; 1333 state->CH_Ctrl[13].val[4] = 0; 1334 state->CH_Ctrl[13].addr[5] = 110; 1335 state->CH_Ctrl[13].bit[5] = 7; 1336 state->CH_Ctrl[13].val[5] = 1; 1337 1338 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; 1339 state->CH_Ctrl[14].size = 7 ; 1340 state->CH_Ctrl[14].addr[0] = 14; 1341 state->CH_Ctrl[14].bit[0] = 0; 1342 state->CH_Ctrl[14].val[0] = 0; 1343 state->CH_Ctrl[14].addr[1] = 14; 1344 state->CH_Ctrl[14].bit[1] = 1; 1345 state->CH_Ctrl[14].val[1] = 0; 1346 state->CH_Ctrl[14].addr[2] = 14; 1347 state->CH_Ctrl[14].bit[2] = 2; 1348 state->CH_Ctrl[14].val[2] = 0; 1349 state->CH_Ctrl[14].addr[3] = 14; 1350 state->CH_Ctrl[14].bit[3] = 3; 1351 state->CH_Ctrl[14].val[3] = 0; 1352 state->CH_Ctrl[14].addr[4] = 14; 1353 state->CH_Ctrl[14].bit[4] = 4; 1354 state->CH_Ctrl[14].val[4] = 0; 1355 state->CH_Ctrl[14].addr[5] = 14; 1356 state->CH_Ctrl[14].bit[5] = 5; 1357 state->CH_Ctrl[14].val[5] = 0; 1358 state->CH_Ctrl[14].addr[6] = 14; 1359 state->CH_Ctrl[14].bit[6] = 6; 1360 state->CH_Ctrl[14].val[6] = 0; 1361 1362 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; 1363 state->CH_Ctrl[15].size = 18 ; 1364 state->CH_Ctrl[15].addr[0] = 17; 1365 state->CH_Ctrl[15].bit[0] = 6; 1366 state->CH_Ctrl[15].val[0] = 0; 1367 state->CH_Ctrl[15].addr[1] = 17; 1368 state->CH_Ctrl[15].bit[1] = 7; 1369 state->CH_Ctrl[15].val[1] = 0; 1370 state->CH_Ctrl[15].addr[2] = 16; 1371 state->CH_Ctrl[15].bit[2] = 0; 1372 state->CH_Ctrl[15].val[2] = 0; 1373 state->CH_Ctrl[15].addr[3] = 16; 1374 state->CH_Ctrl[15].bit[3] = 1; 1375 state->CH_Ctrl[15].val[3] = 0; 1376 state->CH_Ctrl[15].addr[4] = 16; 1377 state->CH_Ctrl[15].bit[4] = 2; 1378 state->CH_Ctrl[15].val[4] = 0; 1379 state->CH_Ctrl[15].addr[5] = 16; 1380 state->CH_Ctrl[15].bit[5] = 3; 1381 state->CH_Ctrl[15].val[5] = 0; 1382 state->CH_Ctrl[15].addr[6] = 16; 1383 state->CH_Ctrl[15].bit[6] = 4; 1384 state->CH_Ctrl[15].val[6] = 0; 1385 state->CH_Ctrl[15].addr[7] = 16; 1386 state->CH_Ctrl[15].bit[7] = 5; 1387 state->CH_Ctrl[15].val[7] = 0; 1388 state->CH_Ctrl[15].addr[8] = 16; 1389 state->CH_Ctrl[15].bit[8] = 6; 1390 state->CH_Ctrl[15].val[8] = 0; 1391 state->CH_Ctrl[15].addr[9] = 16; 1392 state->CH_Ctrl[15].bit[9] = 7; 1393 state->CH_Ctrl[15].val[9] = 0; 1394 state->CH_Ctrl[15].addr[10] = 15; 1395 state->CH_Ctrl[15].bit[10] = 0; 1396 state->CH_Ctrl[15].val[10] = 0; 1397 state->CH_Ctrl[15].addr[11] = 15; 1398 state->CH_Ctrl[15].bit[11] = 1; 1399 state->CH_Ctrl[15].val[11] = 0; 1400 state->CH_Ctrl[15].addr[12] = 15; 1401 state->CH_Ctrl[15].bit[12] = 2; 1402 state->CH_Ctrl[15].val[12] = 0; 1403 state->CH_Ctrl[15].addr[13] = 15; 1404 state->CH_Ctrl[15].bit[13] = 3; 1405 state->CH_Ctrl[15].val[13] = 0; 1406 state->CH_Ctrl[15].addr[14] = 15; 1407 state->CH_Ctrl[15].bit[14] = 4; 1408 state->CH_Ctrl[15].val[14] = 0; 1409 state->CH_Ctrl[15].addr[15] = 15; 1410 state->CH_Ctrl[15].bit[15] = 5; 1411 state->CH_Ctrl[15].val[15] = 0; 1412 state->CH_Ctrl[15].addr[16] = 15; 1413 state->CH_Ctrl[15].bit[16] = 6; 1414 state->CH_Ctrl[15].val[16] = 1; 1415 state->CH_Ctrl[15].addr[17] = 15; 1416 state->CH_Ctrl[15].bit[17] = 7; 1417 state->CH_Ctrl[15].val[17] = 1; 1418 1419 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; 1420 state->CH_Ctrl[16].size = 5 ; 1421 state->CH_Ctrl[16].addr[0] = 112; 1422 state->CH_Ctrl[16].bit[0] = 0; 1423 state->CH_Ctrl[16].val[0] = 0; 1424 state->CH_Ctrl[16].addr[1] = 112; 1425 state->CH_Ctrl[16].bit[1] = 1; 1426 state->CH_Ctrl[16].val[1] = 0; 1427 state->CH_Ctrl[16].addr[2] = 112; 1428 state->CH_Ctrl[16].bit[2] = 2; 1429 state->CH_Ctrl[16].val[2] = 0; 1430 state->CH_Ctrl[16].addr[3] = 112; 1431 state->CH_Ctrl[16].bit[3] = 3; 1432 state->CH_Ctrl[16].val[3] = 0; 1433 state->CH_Ctrl[16].addr[4] = 112; 1434 state->CH_Ctrl[16].bit[4] = 4; 1435 state->CH_Ctrl[16].val[4] = 1; 1436 1437 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; 1438 state->CH_Ctrl[17].size = 1 ; 1439 state->CH_Ctrl[17].addr[0] = 14; 1440 state->CH_Ctrl[17].bit[0] = 7; 1441 state->CH_Ctrl[17].val[0] = 0; 1442 1443 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; 1444 state->CH_Ctrl[18].size = 4 ; 1445 state->CH_Ctrl[18].addr[0] = 107; 1446 state->CH_Ctrl[18].bit[0] = 3; 1447 state->CH_Ctrl[18].val[0] = 0; 1448 state->CH_Ctrl[18].addr[1] = 107; 1449 state->CH_Ctrl[18].bit[1] = 4; 1450 state->CH_Ctrl[18].val[1] = 0; 1451 state->CH_Ctrl[18].addr[2] = 107; 1452 state->CH_Ctrl[18].bit[2] = 5; 1453 state->CH_Ctrl[18].val[2] = 0; 1454 state->CH_Ctrl[18].addr[3] = 107; 1455 state->CH_Ctrl[18].bit[3] = 6; 1456 state->CH_Ctrl[18].val[3] = 0; 1457 1458 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; 1459 state->CH_Ctrl[19].size = 3 ; 1460 state->CH_Ctrl[19].addr[0] = 107; 1461 state->CH_Ctrl[19].bit[0] = 7; 1462 state->CH_Ctrl[19].val[0] = 1; 1463 state->CH_Ctrl[19].addr[1] = 106; 1464 state->CH_Ctrl[19].bit[1] = 0; 1465 state->CH_Ctrl[19].val[1] = 1; 1466 state->CH_Ctrl[19].addr[2] = 106; 1467 state->CH_Ctrl[19].bit[2] = 1; 1468 state->CH_Ctrl[19].val[2] = 1; 1469 1470 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; 1471 state->CH_Ctrl[20].size = 11 ; 1472 state->CH_Ctrl[20].addr[0] = 109; 1473 state->CH_Ctrl[20].bit[0] = 2; 1474 state->CH_Ctrl[20].val[0] = 0; 1475 state->CH_Ctrl[20].addr[1] = 109; 1476 state->CH_Ctrl[20].bit[1] = 3; 1477 state->CH_Ctrl[20].val[1] = 0; 1478 state->CH_Ctrl[20].addr[2] = 109; 1479 state->CH_Ctrl[20].bit[2] = 4; 1480 state->CH_Ctrl[20].val[2] = 0; 1481 state->CH_Ctrl[20].addr[3] = 109; 1482 state->CH_Ctrl[20].bit[3] = 5; 1483 state->CH_Ctrl[20].val[3] = 0; 1484 state->CH_Ctrl[20].addr[4] = 109; 1485 state->CH_Ctrl[20].bit[4] = 6; 1486 state->CH_Ctrl[20].val[4] = 0; 1487 state->CH_Ctrl[20].addr[5] = 109; 1488 state->CH_Ctrl[20].bit[5] = 7; 1489 state->CH_Ctrl[20].val[5] = 0; 1490 state->CH_Ctrl[20].addr[6] = 108; 1491 state->CH_Ctrl[20].bit[6] = 0; 1492 state->CH_Ctrl[20].val[6] = 0; 1493 state->CH_Ctrl[20].addr[7] = 108; 1494 state->CH_Ctrl[20].bit[7] = 1; 1495 state->CH_Ctrl[20].val[7] = 0; 1496 state->CH_Ctrl[20].addr[8] = 108; 1497 state->CH_Ctrl[20].bit[8] = 2; 1498 state->CH_Ctrl[20].val[8] = 1; 1499 state->CH_Ctrl[20].addr[9] = 108; 1500 state->CH_Ctrl[20].bit[9] = 3; 1501 state->CH_Ctrl[20].val[9] = 1; 1502 state->CH_Ctrl[20].addr[10] = 108; 1503 state->CH_Ctrl[20].bit[10] = 4; 1504 state->CH_Ctrl[20].val[10] = 1; 1505 1506 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; 1507 state->CH_Ctrl[21].size = 6 ; 1508 state->CH_Ctrl[21].addr[0] = 106; 1509 state->CH_Ctrl[21].bit[0] = 2; 1510 state->CH_Ctrl[21].val[0] = 0; 1511 state->CH_Ctrl[21].addr[1] = 106; 1512 state->CH_Ctrl[21].bit[1] = 3; 1513 state->CH_Ctrl[21].val[1] = 0; 1514 state->CH_Ctrl[21].addr[2] = 106; 1515 state->CH_Ctrl[21].bit[2] = 4; 1516 state->CH_Ctrl[21].val[2] = 0; 1517 state->CH_Ctrl[21].addr[3] = 106; 1518 state->CH_Ctrl[21].bit[3] = 5; 1519 state->CH_Ctrl[21].val[3] = 0; 1520 state->CH_Ctrl[21].addr[4] = 106; 1521 state->CH_Ctrl[21].bit[4] = 6; 1522 state->CH_Ctrl[21].val[4] = 0; 1523 state->CH_Ctrl[21].addr[5] = 106; 1524 state->CH_Ctrl[21].bit[5] = 7; 1525 state->CH_Ctrl[21].val[5] = 1; 1526 1527 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; 1528 state->CH_Ctrl[22].size = 1 ; 1529 state->CH_Ctrl[22].addr[0] = 138; 1530 state->CH_Ctrl[22].bit[0] = 4; 1531 state->CH_Ctrl[22].val[0] = 1; 1532 1533 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; 1534 state->CH_Ctrl[23].size = 1 ; 1535 state->CH_Ctrl[23].addr[0] = 17; 1536 state->CH_Ctrl[23].bit[0] = 5; 1537 state->CH_Ctrl[23].val[0] = 0; 1538 1539 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; 1540 state->CH_Ctrl[24].size = 1 ; 1541 state->CH_Ctrl[24].addr[0] = 111; 1542 state->CH_Ctrl[24].bit[0] = 3; 1543 state->CH_Ctrl[24].val[0] = 0; 1544 1545 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; 1546 state->CH_Ctrl[25].size = 1 ; 1547 state->CH_Ctrl[25].addr[0] = 112; 1548 state->CH_Ctrl[25].bit[0] = 7; 1549 state->CH_Ctrl[25].val[0] = 0; 1550 1551 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; 1552 state->CH_Ctrl[26].size = 1 ; 1553 state->CH_Ctrl[26].addr[0] = 136; 1554 state->CH_Ctrl[26].bit[0] = 7; 1555 state->CH_Ctrl[26].val[0] = 0; 1556 1557 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; 1558 state->CH_Ctrl[27].size = 1 ; 1559 state->CH_Ctrl[27].addr[0] = 149; 1560 state->CH_Ctrl[27].bit[0] = 7; 1561 state->CH_Ctrl[27].val[0] = 0; 1562 1563 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; 1564 state->CH_Ctrl[28].size = 1 ; 1565 state->CH_Ctrl[28].addr[0] = 149; 1566 state->CH_Ctrl[28].bit[0] = 6; 1567 state->CH_Ctrl[28].val[0] = 0; 1568 1569 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; 1570 state->CH_Ctrl[29].size = 1 ; 1571 state->CH_Ctrl[29].addr[0] = 149; 1572 state->CH_Ctrl[29].bit[0] = 5; 1573 state->CH_Ctrl[29].val[0] = 1; 1574 1575 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; 1576 state->CH_Ctrl[30].size = 1 ; 1577 state->CH_Ctrl[30].addr[0] = 149; 1578 state->CH_Ctrl[30].bit[0] = 4; 1579 state->CH_Ctrl[30].val[0] = 1; 1580 1581 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; 1582 state->CH_Ctrl[31].size = 1 ; 1583 state->CH_Ctrl[31].addr[0] = 149; 1584 state->CH_Ctrl[31].bit[0] = 3; 1585 state->CH_Ctrl[31].val[0] = 0; 1586 1587 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; 1588 state->CH_Ctrl[32].size = 1 ; 1589 state->CH_Ctrl[32].addr[0] = 93; 1590 state->CH_Ctrl[32].bit[0] = 1; 1591 state->CH_Ctrl[32].val[0] = 0; 1592 1593 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; 1594 state->CH_Ctrl[33].size = 1 ; 1595 state->CH_Ctrl[33].addr[0] = 93; 1596 state->CH_Ctrl[33].bit[0] = 0; 1597 state->CH_Ctrl[33].val[0] = 0; 1598 1599 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; 1600 state->CH_Ctrl[34].size = 6 ; 1601 state->CH_Ctrl[34].addr[0] = 92; 1602 state->CH_Ctrl[34].bit[0] = 2; 1603 state->CH_Ctrl[34].val[0] = 0; 1604 state->CH_Ctrl[34].addr[1] = 92; 1605 state->CH_Ctrl[34].bit[1] = 3; 1606 state->CH_Ctrl[34].val[1] = 0; 1607 state->CH_Ctrl[34].addr[2] = 92; 1608 state->CH_Ctrl[34].bit[2] = 4; 1609 state->CH_Ctrl[34].val[2] = 0; 1610 state->CH_Ctrl[34].addr[3] = 92; 1611 state->CH_Ctrl[34].bit[3] = 5; 1612 state->CH_Ctrl[34].val[3] = 0; 1613 state->CH_Ctrl[34].addr[4] = 92; 1614 state->CH_Ctrl[34].bit[4] = 6; 1615 state->CH_Ctrl[34].val[4] = 0; 1616 state->CH_Ctrl[34].addr[5] = 92; 1617 state->CH_Ctrl[34].bit[5] = 7; 1618 state->CH_Ctrl[34].val[5] = 0; 1619 1620 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; 1621 state->CH_Ctrl[35].size = 6 ; 1622 state->CH_Ctrl[35].addr[0] = 93; 1623 state->CH_Ctrl[35].bit[0] = 2; 1624 state->CH_Ctrl[35].val[0] = 0; 1625 state->CH_Ctrl[35].addr[1] = 93; 1626 state->CH_Ctrl[35].bit[1] = 3; 1627 state->CH_Ctrl[35].val[1] = 0; 1628 state->CH_Ctrl[35].addr[2] = 93; 1629 state->CH_Ctrl[35].bit[2] = 4; 1630 state->CH_Ctrl[35].val[2] = 0; 1631 state->CH_Ctrl[35].addr[3] = 93; 1632 state->CH_Ctrl[35].bit[3] = 5; 1633 state->CH_Ctrl[35].val[3] = 0; 1634 state->CH_Ctrl[35].addr[4] = 93; 1635 state->CH_Ctrl[35].bit[4] = 6; 1636 state->CH_Ctrl[35].val[4] = 0; 1637 state->CH_Ctrl[35].addr[5] = 93; 1638 state->CH_Ctrl[35].bit[5] = 7; 1639 state->CH_Ctrl[35].val[5] = 0; 1640 1641 #ifdef _MXL_PRODUCTION 1642 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; 1643 state->CH_Ctrl[36].size = 1 ; 1644 state->CH_Ctrl[36].addr[0] = 109; 1645 state->CH_Ctrl[36].bit[0] = 1; 1646 state->CH_Ctrl[36].val[0] = 1; 1647 1648 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; 1649 state->CH_Ctrl[37].size = 2 ; 1650 state->CH_Ctrl[37].addr[0] = 112; 1651 state->CH_Ctrl[37].bit[0] = 5; 1652 state->CH_Ctrl[37].val[0] = 0; 1653 state->CH_Ctrl[37].addr[1] = 112; 1654 state->CH_Ctrl[37].bit[1] = 6; 1655 state->CH_Ctrl[37].val[1] = 0; 1656 1657 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; 1658 state->CH_Ctrl[38].size = 1 ; 1659 state->CH_Ctrl[38].addr[0] = 65; 1660 state->CH_Ctrl[38].bit[0] = 1; 1661 state->CH_Ctrl[38].val[0] = 0; 1662 #endif 1663 1664 return 0 ; 1665 } 1666 1667 static void InitTunerControls(struct dvb_frontend *fe) 1668 { 1669 MXL5005_RegisterInit(fe); 1670 MXL5005_ControlInit(fe); 1671 MXL5005_ControlInitCH(fe); 1672 #ifdef _MXL_INTERNAL 1673 MXL5005_MXLControlInit(fe); 1674 #endif 1675 } 1676 1677 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, 1678 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ 1679 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ 1680 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ 1681 u32 IF_out, /* Desired IF Out Frequency */ 1682 u32 Fxtal, /* XTAL Frequency */ 1683 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ 1684 u16 TOP, /* 0: Dual AGC; Value: take over point */ 1685 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ 1686 u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ 1687 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ 1688 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ 1689 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ 1690 1691 /* Modulation Type; */ 1692 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ 1693 u8 Mod_Type, 1694 1695 /* Tracking Filter */ 1696 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ 1697 u8 TF_Type 1698 ) 1699 { 1700 struct mxl5005s_state *state = fe->tuner_priv; 1701 1702 state->Mode = Mode; 1703 state->IF_Mode = IF_mode; 1704 state->Chan_Bandwidth = Bandwidth; 1705 state->IF_OUT = IF_out; 1706 state->Fxtal = Fxtal; 1707 state->AGC_Mode = AGC_Mode; 1708 state->TOP = TOP; 1709 state->IF_OUT_LOAD = IF_OUT_LOAD; 1710 state->CLOCK_OUT = CLOCK_OUT; 1711 state->DIV_OUT = DIV_OUT; 1712 state->CAPSELECT = CAPSELECT; 1713 state->EN_RSSI = EN_RSSI; 1714 state->Mod_Type = Mod_Type; 1715 state->TF_Type = TF_Type; 1716 1717 /* Initialize all the controls and registers */ 1718 InitTunerControls(fe); 1719 1720 /* Synthesizer LO frequency calculation */ 1721 MXL_SynthIFLO_Calc(fe); 1722 1723 return 0; 1724 } 1725 1726 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) 1727 { 1728 struct mxl5005s_state *state = fe->tuner_priv; 1729 if (state->Mode == 1) /* Digital Mode */ 1730 state->IF_LO = state->IF_OUT; 1731 else /* Analog Mode */ { 1732 if (state->IF_Mode == 0) /* Analog Zero IF mode */ 1733 state->IF_LO = state->IF_OUT + 400000; 1734 else /* Analog Low IF mode */ 1735 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; 1736 } 1737 } 1738 1739 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) 1740 { 1741 struct mxl5005s_state *state = fe->tuner_priv; 1742 1743 if (state->Mode == 1) /* Digital Mode */ { 1744 /* remove 20.48MHz setting for 2.6.10 */ 1745 state->RF_LO = state->RF_IN; 1746 /* change for 2.6.6 */ 1747 state->TG_LO = state->RF_IN - 750000; 1748 } else /* Analog Mode */ { 1749 if (state->IF_Mode == 0) /* Analog Zero IF mode */ { 1750 state->RF_LO = state->RF_IN - 400000; 1751 state->TG_LO = state->RF_IN - 1750000; 1752 } else /* Analog Low IF mode */ { 1753 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; 1754 state->TG_LO = state->RF_IN - 1755 state->Chan_Bandwidth + 500000; 1756 } 1757 } 1758 } 1759 1760 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) 1761 { 1762 u16 status = 0; 1763 1764 status += MXL_ControlWrite(fe, OVERRIDE_1, 1); 1765 status += MXL_ControlWrite(fe, OVERRIDE_2, 1); 1766 status += MXL_ControlWrite(fe, OVERRIDE_3, 1); 1767 status += MXL_ControlWrite(fe, OVERRIDE_4, 1); 1768 1769 return status; 1770 } 1771 1772 static u16 MXL_BlockInit(struct dvb_frontend *fe) 1773 { 1774 struct mxl5005s_state *state = fe->tuner_priv; 1775 u16 status = 0; 1776 1777 status += MXL_OverwriteICDefault(fe); 1778 1779 /* Downconverter Control Dig Ana */ 1780 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); 1781 1782 /* Filter Control Dig Ana */ 1783 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); 1784 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); 1785 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); 1786 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); 1787 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0); 1788 1789 /* Initialize Low-Pass Filter */ 1790 if (state->Mode) { /* Digital Mode */ 1791 switch (state->Chan_Bandwidth) { 1792 case 8000000: 1793 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); 1794 break; 1795 case 7000000: 1796 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); 1797 break; 1798 case 6000000: 1799 status += MXL_ControlWrite(fe, 1800 BB_DLPF_BANDSEL, 3); 1801 break; 1802 } 1803 } else { /* Analog Mode */ 1804 switch (state->Chan_Bandwidth) { 1805 case 8000000: /* Low Zero */ 1806 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, 1807 (state->IF_Mode ? 0 : 3)); 1808 break; 1809 case 7000000: 1810 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, 1811 (state->IF_Mode ? 1 : 4)); 1812 break; 1813 case 6000000: 1814 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, 1815 (state->IF_Mode ? 2 : 5)); 1816 break; 1817 } 1818 } 1819 1820 /* Charge Pump Control Dig Ana */ 1821 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); 1822 status += MXL_ControlWrite(fe, 1823 RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); 1824 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); 1825 1826 /* AGC TOP Control */ 1827 if (state->AGC_Mode == 0) /* Dual AGC */ { 1828 status += MXL_ControlWrite(fe, AGC_IF, 15); 1829 status += MXL_ControlWrite(fe, AGC_RF, 15); 1830 } else /* Single AGC Mode Dig Ana */ 1831 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); 1832 1833 if (state->TOP == 55) /* TOP == 5.5 */ 1834 status += MXL_ControlWrite(fe, AGC_IF, 0x0); 1835 1836 if (state->TOP == 72) /* TOP == 7.2 */ 1837 status += MXL_ControlWrite(fe, AGC_IF, 0x1); 1838 1839 if (state->TOP == 92) /* TOP == 9.2 */ 1840 status += MXL_ControlWrite(fe, AGC_IF, 0x2); 1841 1842 if (state->TOP == 110) /* TOP == 11.0 */ 1843 status += MXL_ControlWrite(fe, AGC_IF, 0x3); 1844 1845 if (state->TOP == 129) /* TOP == 12.9 */ 1846 status += MXL_ControlWrite(fe, AGC_IF, 0x4); 1847 1848 if (state->TOP == 147) /* TOP == 14.7 */ 1849 status += MXL_ControlWrite(fe, AGC_IF, 0x5); 1850 1851 if (state->TOP == 168) /* TOP == 16.8 */ 1852 status += MXL_ControlWrite(fe, AGC_IF, 0x6); 1853 1854 if (state->TOP == 194) /* TOP == 19.4 */ 1855 status += MXL_ControlWrite(fe, AGC_IF, 0x7); 1856 1857 if (state->TOP == 212) /* TOP == 21.2 */ 1858 status += MXL_ControlWrite(fe, AGC_IF, 0x9); 1859 1860 if (state->TOP == 232) /* TOP == 23.2 */ 1861 status += MXL_ControlWrite(fe, AGC_IF, 0xA); 1862 1863 if (state->TOP == 252) /* TOP == 25.2 */ 1864 status += MXL_ControlWrite(fe, AGC_IF, 0xB); 1865 1866 if (state->TOP == 271) /* TOP == 27.1 */ 1867 status += MXL_ControlWrite(fe, AGC_IF, 0xC); 1868 1869 if (state->TOP == 292) /* TOP == 29.2 */ 1870 status += MXL_ControlWrite(fe, AGC_IF, 0xD); 1871 1872 if (state->TOP == 317) /* TOP == 31.7 */ 1873 status += MXL_ControlWrite(fe, AGC_IF, 0xE); 1874 1875 if (state->TOP == 349) /* TOP == 34.9 */ 1876 status += MXL_ControlWrite(fe, AGC_IF, 0xF); 1877 1878 /* IF Synthesizer Control */ 1879 status += MXL_IFSynthInit(fe); 1880 1881 /* IF UpConverter Control */ 1882 if (state->IF_OUT_LOAD == 200) { 1883 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6); 1884 status += MXL_ControlWrite(fe, I_DRIVER, 2); 1885 } 1886 if (state->IF_OUT_LOAD == 300) { 1887 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4); 1888 status += MXL_ControlWrite(fe, I_DRIVER, 1); 1889 } 1890 1891 /* Anti-Alias Filtering Control 1892 * initialise Anti-Aliasing Filter 1893 */ 1894 if (state->Mode) { /* Digital Mode */ 1895 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { 1896 status += MXL_ControlWrite(fe, EN_AAF, 1); 1897 status += MXL_ControlWrite(fe, EN_3P, 1); 1898 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1899 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); 1900 } 1901 if ((state->IF_OUT == 36125000UL) || 1902 (state->IF_OUT == 36150000UL)) { 1903 status += MXL_ControlWrite(fe, EN_AAF, 1); 1904 status += MXL_ControlWrite(fe, EN_3P, 1); 1905 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1906 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); 1907 } 1908 if (state->IF_OUT > 36150000UL) { 1909 status += MXL_ControlWrite(fe, EN_AAF, 0); 1910 status += MXL_ControlWrite(fe, EN_3P, 1); 1911 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1912 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); 1913 } 1914 } else { /* Analog Mode */ 1915 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { 1916 status += MXL_ControlWrite(fe, EN_AAF, 1); 1917 status += MXL_ControlWrite(fe, EN_3P, 1); 1918 status += MXL_ControlWrite(fe, EN_AUX_3P, 1); 1919 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); 1920 } 1921 if (state->IF_OUT > 5000000UL) { 1922 status += MXL_ControlWrite(fe, EN_AAF, 0); 1923 status += MXL_ControlWrite(fe, EN_3P, 0); 1924 status += MXL_ControlWrite(fe, EN_AUX_3P, 0); 1925 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); 1926 } 1927 } 1928 1929 /* Demod Clock Out */ 1930 if (state->CLOCK_OUT) 1931 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1); 1932 else 1933 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0); 1934 1935 if (state->DIV_OUT == 1) 1936 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1); 1937 if (state->DIV_OUT == 0) 1938 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0); 1939 1940 /* Crystal Control */ 1941 if (state->CAPSELECT) 1942 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1); 1943 else 1944 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0); 1945 1946 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) 1947 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1); 1948 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) 1949 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0); 1950 1951 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) 1952 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3); 1953 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) 1954 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); 1955 1956 /* Misc Controls */ 1957 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ 1958 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); 1959 else 1960 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); 1961 1962 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ 1963 1964 /* Set TG_R_DIV */ 1965 status += MXL_ControlWrite(fe, TG_R_DIV, 1966 MXL_Ceiling(state->Fxtal, 1000000)); 1967 1968 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ 1969 1970 /* RSSI Control */ 1971 if (state->EN_RSSI) { 1972 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 1973 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 1974 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 1975 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 1976 1977 /* RSSI reference point */ 1978 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); 1979 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3); 1980 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); 1981 1982 /* TOP point */ 1983 status += MXL_ControlWrite(fe, RFA_FLR, 0); 1984 status += MXL_ControlWrite(fe, RFA_CEIL, 12); 1985 } 1986 1987 /* Modulation type bit settings 1988 * Override the control values preset 1989 */ 1990 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { 1991 state->AGC_Mode = 1; /* Single AGC Mode */ 1992 1993 /* Enable RSSI */ 1994 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 1995 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 1996 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 1997 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 1998 1999 /* RSSI reference point */ 2000 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); 2001 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); 2002 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); 2003 2004 /* TOP point */ 2005 status += MXL_ControlWrite(fe, RFA_FLR, 2); 2006 status += MXL_ControlWrite(fe, RFA_CEIL, 13); 2007 if (state->IF_OUT <= 6280000UL) /* Low IF */ 2008 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2009 else /* High IF */ 2010 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2011 2012 } 2013 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { 2014 state->AGC_Mode = 1; /* Single AGC Mode */ 2015 2016 /* Enable RSSI */ 2017 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2018 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2019 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 2020 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2021 2022 /* RSSI reference point */ 2023 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); 2024 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4); 2025 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); 2026 2027 /* TOP point */ 2028 status += MXL_ControlWrite(fe, RFA_FLR, 2); 2029 status += MXL_ControlWrite(fe, RFA_CEIL, 13); 2030 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); 2031 /* Low Zero */ 2032 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); 2033 2034 if (state->IF_OUT <= 6280000UL) /* Low IF */ 2035 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2036 else /* High IF */ 2037 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2038 } 2039 if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { 2040 state->Mode = MXL_DIGITAL_MODE; 2041 2042 /* state->AGC_Mode = 1; */ /* Single AGC Mode */ 2043 2044 /* Disable RSSI */ /* change here for v2.6.5 */ 2045 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2046 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2047 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2048 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2049 2050 /* RSSI reference point */ 2051 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); 2052 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); 2053 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); 2054 /* change here for v2.6.5 */ 2055 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); 2056 2057 if (state->IF_OUT <= 6280000UL) /* Low IF */ 2058 status += MXL_ControlWrite(fe, BB_IQSWAP, 0); 2059 else /* High IF */ 2060 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2061 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); 2062 2063 } 2064 if (state->Mod_Type == MXL_ANALOG_CABLE) { 2065 /* Analog Cable Mode */ 2066 /* state->Mode = MXL_DIGITAL_MODE; */ 2067 2068 state->AGC_Mode = 1; /* Single AGC Mode */ 2069 2070 /* Disable RSSI */ 2071 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2072 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2073 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2074 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2075 /* change for 2.6.3 */ 2076 status += MXL_ControlWrite(fe, AGC_IF, 1); 2077 status += MXL_ControlWrite(fe, AGC_RF, 15); 2078 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2079 } 2080 2081 if (state->Mod_Type == MXL_ANALOG_OTA) { 2082 /* Analog OTA Terrestrial mode add for 2.6.7 */ 2083 /* state->Mode = MXL_ANALOG_MODE; */ 2084 2085 /* Enable RSSI */ 2086 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2087 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2088 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 2089 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2090 2091 /* RSSI reference point */ 2092 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); 2093 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); 2094 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); 2095 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); 2096 status += MXL_ControlWrite(fe, BB_IQSWAP, 1); 2097 } 2098 2099 /* RSSI disable */ 2100 if (state->EN_RSSI == 0) { 2101 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 2102 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 2103 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 2104 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 2105 } 2106 2107 return status; 2108 } 2109 2110 static u16 MXL_IFSynthInit(struct dvb_frontend *fe) 2111 { 2112 struct mxl5005s_state *state = fe->tuner_priv; 2113 u16 status = 0 ; 2114 u32 Fref = 0 ; 2115 u32 Kdbl, intModVal ; 2116 u32 fracModVal ; 2117 Kdbl = 2 ; 2118 2119 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) 2120 Kdbl = 2 ; 2121 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) 2122 Kdbl = 1 ; 2123 2124 /* IF Synthesizer Control */ 2125 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { 2126 if (state->IF_LO == 41000000UL) { 2127 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2128 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2129 Fref = 328000000UL ; 2130 } 2131 if (state->IF_LO == 47000000UL) { 2132 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2133 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2134 Fref = 376000000UL ; 2135 } 2136 if (state->IF_LO == 54000000UL) { 2137 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); 2138 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2139 Fref = 324000000UL ; 2140 } 2141 if (state->IF_LO == 60000000UL) { 2142 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); 2143 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2144 Fref = 360000000UL ; 2145 } 2146 if (state->IF_LO == 39250000UL) { 2147 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2148 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2149 Fref = 314000000UL ; 2150 } 2151 if (state->IF_LO == 39650000UL) { 2152 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2153 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2154 Fref = 317200000UL ; 2155 } 2156 if (state->IF_LO == 40150000UL) { 2157 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2158 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2159 Fref = 321200000UL ; 2160 } 2161 if (state->IF_LO == 40650000UL) { 2162 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2163 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2164 Fref = 325200000UL ; 2165 } 2166 } 2167 2168 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { 2169 if (state->IF_LO == 57000000UL) { 2170 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); 2171 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2172 Fref = 342000000UL ; 2173 } 2174 if (state->IF_LO == 44000000UL) { 2175 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2176 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2177 Fref = 352000000UL ; 2178 } 2179 if (state->IF_LO == 43750000UL) { 2180 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2181 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2182 Fref = 350000000UL ; 2183 } 2184 if (state->IF_LO == 36650000UL) { 2185 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2186 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2187 Fref = 366500000UL ; 2188 } 2189 if (state->IF_LO == 36150000UL) { 2190 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2191 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2192 Fref = 361500000UL ; 2193 } 2194 if (state->IF_LO == 36000000UL) { 2195 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2196 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2197 Fref = 360000000UL ; 2198 } 2199 if (state->IF_LO == 35250000UL) { 2200 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2201 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2202 Fref = 352500000UL ; 2203 } 2204 if (state->IF_LO == 34750000UL) { 2205 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2206 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2207 Fref = 347500000UL ; 2208 } 2209 if (state->IF_LO == 6280000UL) { 2210 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); 2211 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2212 Fref = 376800000UL ; 2213 } 2214 if (state->IF_LO == 5000000UL) { 2215 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); 2216 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2217 Fref = 360000000UL ; 2218 } 2219 if (state->IF_LO == 4500000UL) { 2220 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); 2221 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2222 Fref = 360000000UL ; 2223 } 2224 if (state->IF_LO == 4570000UL) { 2225 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); 2226 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2227 Fref = 365600000UL ; 2228 } 2229 if (state->IF_LO == 4000000UL) { 2230 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); 2231 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2232 Fref = 360000000UL ; 2233 } 2234 if (state->IF_LO == 57400000UL) { 2235 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); 2236 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2237 Fref = 344400000UL ; 2238 } 2239 if (state->IF_LO == 44400000UL) { 2240 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2241 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2242 Fref = 355200000UL ; 2243 } 2244 if (state->IF_LO == 44150000UL) { 2245 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); 2246 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2247 Fref = 353200000UL ; 2248 } 2249 if (state->IF_LO == 37050000UL) { 2250 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2251 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2252 Fref = 370500000UL ; 2253 } 2254 if (state->IF_LO == 36550000UL) { 2255 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2256 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2257 Fref = 365500000UL ; 2258 } 2259 if (state->IF_LO == 36125000UL) { 2260 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); 2261 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2262 Fref = 361250000UL ; 2263 } 2264 if (state->IF_LO == 6000000UL) { 2265 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); 2266 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2267 Fref = 360000000UL ; 2268 } 2269 if (state->IF_LO == 5400000UL) { 2270 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); 2271 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2272 Fref = 324000000UL ; 2273 } 2274 if (state->IF_LO == 5380000UL) { 2275 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); 2276 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); 2277 Fref = 322800000UL ; 2278 } 2279 if (state->IF_LO == 5200000UL) { 2280 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); 2281 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2282 Fref = 374400000UL ; 2283 } 2284 if (state->IF_LO == 4900000UL) { 2285 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); 2286 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2287 Fref = 352800000UL ; 2288 } 2289 if (state->IF_LO == 4400000UL) { 2290 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); 2291 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2292 Fref = 352000000UL ; 2293 } 2294 if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { 2295 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); 2296 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); 2297 Fref = 365670000UL ; 2298 } 2299 } 2300 /* CHCAL_INT_MOD_IF */ 2301 /* CHCAL_FRAC_MOD_IF */ 2302 intModVal = Fref / (state->Fxtal * Kdbl/2); 2303 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal); 2304 2305 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * 2306 intModVal); 2307 2308 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); 2309 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal); 2310 2311 return status ; 2312 } 2313 2314 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) 2315 { 2316 struct mxl5005s_state *state = fe->tuner_priv; 2317 u16 status = 0; 2318 u32 divider_val, E3, E4, E5, E5A; 2319 u32 Fmax, Fmin, FmaxBin, FminBin; 2320 u32 Kdbl_RF = 2; 2321 u32 tg_divval; 2322 u32 tg_lo; 2323 2324 u32 Fref_TG; 2325 u32 Fvco; 2326 2327 state->RF_IN = RF_Freq; 2328 2329 MXL_SynthRFTGLO_Calc(fe); 2330 2331 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) 2332 Kdbl_RF = 2; 2333 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) 2334 Kdbl_RF = 1; 2335 2336 /* Downconverter Controls 2337 * Look-Up Table Implementation for: 2338 * DN_POLY 2339 * DN_RFGAIN 2340 * DN_CAP_RFLPF 2341 * DN_EN_VHFUHFBAR 2342 * DN_GAIN_ADJUST 2343 * Change the boundary reference from RF_IN to RF_LO 2344 */ 2345 if (state->RF_LO < 40000000UL) 2346 return -1; 2347 2348 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { 2349 status += MXL_ControlWrite(fe, DN_POLY, 2); 2350 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2351 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); 2352 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); 2353 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); 2354 } 2355 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { 2356 status += MXL_ControlWrite(fe, DN_POLY, 3); 2357 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2358 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); 2359 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); 2360 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); 2361 } 2362 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { 2363 status += MXL_ControlWrite(fe, DN_POLY, 3); 2364 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2365 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); 2366 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); 2367 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); 2368 } 2369 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { 2370 status += MXL_ControlWrite(fe, DN_POLY, 3); 2371 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2372 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); 2373 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); 2374 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); 2375 } 2376 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { 2377 status += MXL_ControlWrite(fe, DN_POLY, 3); 2378 status += MXL_ControlWrite(fe, DN_RFGAIN, 3); 2379 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); 2380 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); 2381 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); 2382 } 2383 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { 2384 status += MXL_ControlWrite(fe, DN_POLY, 3); 2385 status += MXL_ControlWrite(fe, DN_RFGAIN, 1); 2386 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); 2387 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); 2388 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); 2389 } 2390 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { 2391 status += MXL_ControlWrite(fe, DN_POLY, 3); 2392 status += MXL_ControlWrite(fe, DN_RFGAIN, 2); 2393 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); 2394 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); 2395 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); 2396 } 2397 if (state->RF_LO > 900000000UL) 2398 return -1; 2399 2400 /* DN_IQTNBUF_AMP */ 2401 /* DN_IQTNGNBFBIAS_BST */ 2402 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { 2403 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2404 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2405 } 2406 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { 2407 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2408 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2409 } 2410 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { 2411 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2412 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2413 } 2414 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { 2415 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2416 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2417 } 2418 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { 2419 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2420 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2421 } 2422 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { 2423 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2424 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2425 } 2426 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { 2427 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2428 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2429 } 2430 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { 2431 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2432 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2433 } 2434 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { 2435 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2436 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2437 } 2438 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { 2439 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2440 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2441 } 2442 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { 2443 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2444 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2445 } 2446 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { 2447 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2448 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2449 } 2450 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { 2451 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2452 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2453 } 2454 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { 2455 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); 2456 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); 2457 } 2458 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { 2459 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); 2460 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); 2461 } 2462 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { 2463 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); 2464 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); 2465 } 2466 2467 /* 2468 * Set RF Synth and LO Path Control 2469 * 2470 * Look-Up table implementation for: 2471 * RFSYN_EN_OUTMUX 2472 * RFSYN_SEL_VCO_OUT 2473 * RFSYN_SEL_VCO_HI 2474 * RFSYN_SEL_DIVM 2475 * RFSYN_RF_DIV_BIAS 2476 * DN_SEL_FREQ 2477 * 2478 * Set divider_val, Fmax, Fmix to use in Equations 2479 */ 2480 FminBin = 28000000UL ; 2481 FmaxBin = 42500000UL ; 2482 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { 2483 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); 2484 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); 2485 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2486 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2487 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2488 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); 2489 divider_val = 64 ; 2490 Fmax = FmaxBin ; 2491 Fmin = FminBin ; 2492 } 2493 FminBin = 42500000UL ; 2494 FmaxBin = 56000000UL ; 2495 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2496 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); 2497 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); 2498 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 2499 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2500 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2501 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); 2502 divider_val = 64 ; 2503 Fmax = FmaxBin ; 2504 Fmin = FminBin ; 2505 } 2506 FminBin = 56000000UL ; 2507 FmaxBin = 85000000UL ; 2508 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2509 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2510 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2511 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2512 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2513 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2514 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); 2515 divider_val = 32 ; 2516 Fmax = FmaxBin ; 2517 Fmin = FminBin ; 2518 } 2519 FminBin = 85000000UL ; 2520 FmaxBin = 112000000UL ; 2521 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2522 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2523 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2524 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 2525 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2526 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2527 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); 2528 divider_val = 32 ; 2529 Fmax = FmaxBin ; 2530 Fmin = FminBin ; 2531 } 2532 FminBin = 112000000UL ; 2533 FmaxBin = 170000000UL ; 2534 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2535 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2536 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2537 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2538 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2539 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2540 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); 2541 divider_val = 16 ; 2542 Fmax = FmaxBin ; 2543 Fmin = FminBin ; 2544 } 2545 FminBin = 170000000UL ; 2546 FmaxBin = 225000000UL ; 2547 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2548 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2549 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2550 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 2551 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2552 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2553 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); 2554 divider_val = 16 ; 2555 Fmax = FmaxBin ; 2556 Fmin = FminBin ; 2557 } 2558 FminBin = 225000000UL ; 2559 FmaxBin = 300000000UL ; 2560 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2561 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2562 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2563 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2564 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2565 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2566 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4); 2567 divider_val = 8 ; 2568 Fmax = 340000000UL ; 2569 Fmin = FminBin ; 2570 } 2571 FminBin = 300000000UL ; 2572 FmaxBin = 340000000UL ; 2573 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2574 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); 2575 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); 2576 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2577 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2578 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2579 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 2580 divider_val = 8 ; 2581 Fmax = FmaxBin ; 2582 Fmin = 225000000UL ; 2583 } 2584 FminBin = 340000000UL ; 2585 FmaxBin = 450000000UL ; 2586 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2587 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); 2588 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); 2589 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 2590 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 2591 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2); 2592 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 2593 divider_val = 8 ; 2594 Fmax = FmaxBin ; 2595 Fmin = FminBin ; 2596 } 2597 FminBin = 450000000UL ; 2598 FmaxBin = 680000000UL ; 2599 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2600 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2601 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2602 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 2603 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); 2604 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2605 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 2606 divider_val = 4 ; 2607 Fmax = FmaxBin ; 2608 Fmin = FminBin ; 2609 } 2610 FminBin = 680000000UL ; 2611 FmaxBin = 900000000UL ; 2612 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { 2613 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 2614 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 2615 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 2616 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); 2617 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 2618 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 2619 divider_val = 4 ; 2620 Fmax = FmaxBin ; 2621 Fmin = FminBin ; 2622 } 2623 2624 /* CHCAL_INT_MOD_RF 2625 * CHCAL_FRAC_MOD_RF 2626 * RFSYN_LPF_R 2627 * CHCAL_EN_INT_RF 2628 */ 2629 /* Equation E3 RFSYN_VCO_BIAS */ 2630 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; 2631 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3); 2632 2633 /* Equation E4 CHCAL_INT_MOD_RF */ 2634 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); 2635 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4); 2636 2637 /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */ 2638 E5 = ((2<<17)*(state->RF_LO/10000*divider_val - 2639 (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / 2640 (2*state->Fxtal*Kdbl_RF/10000); 2641 2642 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); 2643 2644 /* Equation E5A RFSYN_LPF_R */ 2645 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; 2646 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A); 2647 2648 /* Equation E5B CHCAL_EN_INIT_RF */ 2649 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); 2650 /*if (E5 == 0) 2651 * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); 2652 *else 2653 * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); 2654 */ 2655 2656 /* 2657 * Set TG Synth 2658 * 2659 * Look-Up table implementation for: 2660 * TG_LO_DIVVAL 2661 * TG_LO_SELVAL 2662 * 2663 * Set divider_val, Fmax, Fmix to use in Equations 2664 */ 2665 if (state->TG_LO < 33000000UL) 2666 return -1; 2667 2668 FminBin = 33000000UL ; 2669 FmaxBin = 50000000UL ; 2670 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { 2671 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6); 2672 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); 2673 divider_val = 36 ; 2674 Fmax = FmaxBin ; 2675 Fmin = FminBin ; 2676 } 2677 FminBin = 50000000UL ; 2678 FmaxBin = 67000000UL ; 2679 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2680 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1); 2681 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); 2682 divider_val = 24 ; 2683 Fmax = FmaxBin ; 2684 Fmin = FminBin ; 2685 } 2686 FminBin = 67000000UL ; 2687 FmaxBin = 100000000UL ; 2688 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2689 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC); 2690 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); 2691 divider_val = 18 ; 2692 Fmax = FmaxBin ; 2693 Fmin = FminBin ; 2694 } 2695 FminBin = 100000000UL ; 2696 FmaxBin = 150000000UL ; 2697 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2698 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); 2699 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); 2700 divider_val = 12 ; 2701 Fmax = FmaxBin ; 2702 Fmin = FminBin ; 2703 } 2704 FminBin = 150000000UL ; 2705 FmaxBin = 200000000UL ; 2706 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2707 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); 2708 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); 2709 divider_val = 8 ; 2710 Fmax = FmaxBin ; 2711 Fmin = FminBin ; 2712 } 2713 FminBin = 200000000UL ; 2714 FmaxBin = 300000000UL ; 2715 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2716 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); 2717 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); 2718 divider_val = 6 ; 2719 Fmax = FmaxBin ; 2720 Fmin = FminBin ; 2721 } 2722 FminBin = 300000000UL ; 2723 FmaxBin = 400000000UL ; 2724 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2725 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); 2726 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); 2727 divider_val = 4 ; 2728 Fmax = FmaxBin ; 2729 Fmin = FminBin ; 2730 } 2731 FminBin = 400000000UL ; 2732 FmaxBin = 600000000UL ; 2733 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2734 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); 2735 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); 2736 divider_val = 3 ; 2737 Fmax = FmaxBin ; 2738 Fmin = FminBin ; 2739 } 2740 FminBin = 600000000UL ; 2741 FmaxBin = 900000000UL ; 2742 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { 2743 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); 2744 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); 2745 divider_val = 2 ; 2746 } 2747 2748 /* TG_DIV_VAL */ 2749 tg_divval = (state->TG_LO*divider_val/100000) * 2750 (MXL_Ceiling(state->Fxtal, 1000000) * 100) / 2751 (state->Fxtal/1000); 2752 2753 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval); 2754 2755 if (state->TG_LO > 600000000UL) 2756 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1); 2757 2758 Fmax = 1800000000UL ; 2759 Fmin = 1200000000UL ; 2760 2761 /* prevent overflow of 32 bit unsigned integer, use 2762 * following equation. Edit for v2.6.4 2763 */ 2764 /* Fref_TF = Fref_TG * 1000 */ 2765 Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000); 2766 2767 /* Fvco = Fvco/10 */ 2768 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; 2769 2770 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; 2771 2772 /* below equation is same as above but much harder to debug. 2773 * 2774 * static u32 MXL_GetXtalInt(u32 Xtal_Freq) 2775 * { 2776 * if ((Xtal_Freq % 1000000) == 0) 2777 * return (Xtal_Freq / 10000); 2778 * else 2779 * return (((Xtal_Freq / 1000000) + 1)*100); 2780 * } 2781 * 2782 * u32 Xtal_Int = MXL_GetXtalInt(state->Fxtal); 2783 * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - 2784 * ((state->TG_LO/10000)*divider_val * 2785 * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * 2786 * Xtal_Int/100) + 8; 2787 */ 2788 2789 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo); 2790 2791 /* add for 2.6.5 Special setting for QAM */ 2792 if (state->Mod_Type == MXL_QAM) { 2793 if (state->config->qam_gain != 0) 2794 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2795 state->config->qam_gain); 2796 else if (state->RF_IN < 680000000) 2797 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); 2798 else 2799 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); 2800 } 2801 2802 /* Off Chip Tracking Filter Control */ 2803 if (state->TF_Type == MXL_TF_OFF) { 2804 /* Tracking Filter Off State; turn off all the banks */ 2805 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2806 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2807 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */ 2808 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */ 2809 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */ 2810 } 2811 2812 if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { 2813 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 2814 status += MXL_ControlWrite(fe, DAC_DIN_A, 0); 2815 2816 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { 2817 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2818 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2819 status += MXL_SetGPIO(fe, 3, 0); 2820 status += MXL_SetGPIO(fe, 1, 1); 2821 status += MXL_SetGPIO(fe, 4, 1); 2822 } 2823 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { 2824 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2825 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2826 status += MXL_SetGPIO(fe, 3, 1); 2827 status += MXL_SetGPIO(fe, 1, 0); 2828 status += MXL_SetGPIO(fe, 4, 1); 2829 } 2830 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { 2831 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2832 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2833 status += MXL_SetGPIO(fe, 3, 1); 2834 status += MXL_SetGPIO(fe, 1, 0); 2835 status += MXL_SetGPIO(fe, 4, 0); 2836 } 2837 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { 2838 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2839 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2840 status += MXL_SetGPIO(fe, 3, 1); 2841 status += MXL_SetGPIO(fe, 1, 1); 2842 status += MXL_SetGPIO(fe, 4, 0); 2843 } 2844 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { 2845 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2846 status += MXL_ControlWrite(fe, DAC_DIN_B, 29); 2847 status += MXL_SetGPIO(fe, 3, 1); 2848 status += MXL_SetGPIO(fe, 1, 1); 2849 status += MXL_SetGPIO(fe, 4, 0); 2850 } 2851 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { 2852 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2853 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2854 status += MXL_SetGPIO(fe, 3, 1); 2855 status += MXL_SetGPIO(fe, 1, 1); 2856 status += MXL_SetGPIO(fe, 4, 0); 2857 } 2858 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { 2859 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2860 status += MXL_ControlWrite(fe, DAC_DIN_B, 16); 2861 status += MXL_SetGPIO(fe, 3, 1); 2862 status += MXL_SetGPIO(fe, 1, 1); 2863 status += MXL_SetGPIO(fe, 4, 1); 2864 } 2865 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { 2866 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2867 status += MXL_ControlWrite(fe, DAC_DIN_B, 7); 2868 status += MXL_SetGPIO(fe, 3, 1); 2869 status += MXL_SetGPIO(fe, 1, 1); 2870 status += MXL_SetGPIO(fe, 4, 1); 2871 } 2872 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { 2873 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2874 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2875 status += MXL_SetGPIO(fe, 3, 1); 2876 status += MXL_SetGPIO(fe, 1, 1); 2877 status += MXL_SetGPIO(fe, 4, 1); 2878 } 2879 } 2880 2881 if (state->TF_Type == MXL_TF_C_H) { 2882 2883 /* Tracking Filter type C-H for Hauppauge only */ 2884 status += MXL_ControlWrite(fe, DAC_DIN_A, 0); 2885 2886 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { 2887 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2888 status += MXL_SetGPIO(fe, 4, 0); 2889 status += MXL_SetGPIO(fe, 3, 1); 2890 status += MXL_SetGPIO(fe, 1, 1); 2891 } 2892 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { 2893 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2894 status += MXL_SetGPIO(fe, 4, 1); 2895 status += MXL_SetGPIO(fe, 3, 0); 2896 status += MXL_SetGPIO(fe, 1, 1); 2897 } 2898 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { 2899 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2900 status += MXL_SetGPIO(fe, 4, 1); 2901 status += MXL_SetGPIO(fe, 3, 0); 2902 status += MXL_SetGPIO(fe, 1, 0); 2903 } 2904 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { 2905 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 2906 status += MXL_SetGPIO(fe, 4, 1); 2907 status += MXL_SetGPIO(fe, 3, 1); 2908 status += MXL_SetGPIO(fe, 1, 0); 2909 } 2910 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { 2911 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2912 status += MXL_SetGPIO(fe, 4, 1); 2913 status += MXL_SetGPIO(fe, 3, 1); 2914 status += MXL_SetGPIO(fe, 1, 0); 2915 } 2916 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { 2917 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2918 status += MXL_SetGPIO(fe, 4, 1); 2919 status += MXL_SetGPIO(fe, 3, 1); 2920 status += MXL_SetGPIO(fe, 1, 0); 2921 } 2922 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { 2923 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2924 status += MXL_SetGPIO(fe, 4, 1); 2925 status += MXL_SetGPIO(fe, 3, 1); 2926 status += MXL_SetGPIO(fe, 1, 1); 2927 } 2928 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { 2929 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2930 status += MXL_SetGPIO(fe, 4, 1); 2931 status += MXL_SetGPIO(fe, 3, 1); 2932 status += MXL_SetGPIO(fe, 1, 1); 2933 } 2934 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { 2935 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 2936 status += MXL_SetGPIO(fe, 4, 1); 2937 status += MXL_SetGPIO(fe, 3, 1); 2938 status += MXL_SetGPIO(fe, 1, 1); 2939 } 2940 } 2941 2942 if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ 2943 2944 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 2945 2946 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { 2947 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2948 status += MXL_SetGPIO(fe, 4, 0); 2949 status += MXL_SetGPIO(fe, 1, 1); 2950 status += MXL_SetGPIO(fe, 3, 1); 2951 } 2952 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { 2953 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2954 status += MXL_SetGPIO(fe, 4, 0); 2955 status += MXL_SetGPIO(fe, 1, 0); 2956 status += MXL_SetGPIO(fe, 3, 1); 2957 } 2958 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { 2959 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2960 status += MXL_SetGPIO(fe, 4, 1); 2961 status += MXL_SetGPIO(fe, 1, 0); 2962 status += MXL_SetGPIO(fe, 3, 1); 2963 } 2964 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { 2965 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2966 status += MXL_SetGPIO(fe, 4, 1); 2967 status += MXL_SetGPIO(fe, 1, 0); 2968 status += MXL_SetGPIO(fe, 3, 0); 2969 } 2970 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { 2971 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 2972 status += MXL_SetGPIO(fe, 4, 1); 2973 status += MXL_SetGPIO(fe, 1, 1); 2974 status += MXL_SetGPIO(fe, 3, 0); 2975 } 2976 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { 2977 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 2978 status += MXL_SetGPIO(fe, 4, 1); 2979 status += MXL_SetGPIO(fe, 1, 1); 2980 status += MXL_SetGPIO(fe, 3, 0); 2981 } 2982 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { 2983 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 2984 status += MXL_SetGPIO(fe, 4, 1); 2985 status += MXL_SetGPIO(fe, 1, 1); 2986 status += MXL_SetGPIO(fe, 3, 1); 2987 } 2988 } 2989 2990 if (state->TF_Type == MXL_TF_D_L) { 2991 2992 /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */ 2993 status += MXL_ControlWrite(fe, DAC_DIN_A, 0); 2994 2995 /* if UHF and terrestrial => Turn off Tracking Filter */ 2996 if (state->RF_IN >= 471000000 && 2997 (state->RF_IN - 471000000)%6000000 != 0) { 2998 /* Turn off all the banks */ 2999 status += MXL_SetGPIO(fe, 3, 1); 3000 status += MXL_SetGPIO(fe, 1, 1); 3001 status += MXL_SetGPIO(fe, 4, 1); 3002 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3003 status += MXL_ControlWrite(fe, AGC_IF, 10); 3004 } else { 3005 /* if VHF or cable => Turn on Tracking Filter */ 3006 if (state->RF_IN >= 43000000 && 3007 state->RF_IN < 140000000) { 3008 3009 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3010 status += MXL_SetGPIO(fe, 4, 1); 3011 status += MXL_SetGPIO(fe, 1, 1); 3012 status += MXL_SetGPIO(fe, 3, 0); 3013 } 3014 if (state->RF_IN >= 140000000 && 3015 state->RF_IN < 240000000) { 3016 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3017 status += MXL_SetGPIO(fe, 4, 1); 3018 status += MXL_SetGPIO(fe, 1, 0); 3019 status += MXL_SetGPIO(fe, 3, 0); 3020 } 3021 if (state->RF_IN >= 240000000 && 3022 state->RF_IN < 340000000) { 3023 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3024 status += MXL_SetGPIO(fe, 4, 0); 3025 status += MXL_SetGPIO(fe, 1, 1); 3026 status += MXL_SetGPIO(fe, 3, 0); 3027 } 3028 if (state->RF_IN >= 340000000 && 3029 state->RF_IN < 430000000) { 3030 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3031 status += MXL_SetGPIO(fe, 4, 0); 3032 status += MXL_SetGPIO(fe, 1, 0); 3033 status += MXL_SetGPIO(fe, 3, 1); 3034 } 3035 if (state->RF_IN >= 430000000 && 3036 state->RF_IN < 470000000) { 3037 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 3038 status += MXL_SetGPIO(fe, 4, 1); 3039 status += MXL_SetGPIO(fe, 1, 0); 3040 status += MXL_SetGPIO(fe, 3, 1); 3041 } 3042 if (state->RF_IN >= 470000000 && 3043 state->RF_IN < 570000000) { 3044 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 3045 status += MXL_SetGPIO(fe, 4, 0); 3046 status += MXL_SetGPIO(fe, 1, 0); 3047 status += MXL_SetGPIO(fe, 3, 1); 3048 } 3049 if (state->RF_IN >= 570000000 && 3050 state->RF_IN < 620000000) { 3051 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); 3052 status += MXL_SetGPIO(fe, 4, 0); 3053 status += MXL_SetGPIO(fe, 1, 1); 3054 status += MXL_SetGPIO(fe, 3, 1); 3055 } 3056 if (state->RF_IN >= 620000000 && 3057 state->RF_IN < 760000000) { 3058 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 3059 status += MXL_SetGPIO(fe, 4, 0); 3060 status += MXL_SetGPIO(fe, 1, 1); 3061 status += MXL_SetGPIO(fe, 3, 1); 3062 } 3063 if (state->RF_IN >= 760000000 && 3064 state->RF_IN <= 900000000) { 3065 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); 3066 status += MXL_SetGPIO(fe, 4, 1); 3067 status += MXL_SetGPIO(fe, 1, 1); 3068 status += MXL_SetGPIO(fe, 3, 1); 3069 } 3070 } 3071 } 3072 3073 if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { 3074 3075 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 3076 3077 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { 3078 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3079 status += MXL_SetGPIO(fe, 4, 0); 3080 status += MXL_SetGPIO(fe, 1, 1); 3081 status += MXL_SetGPIO(fe, 3, 1); 3082 } 3083 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { 3084 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3085 status += MXL_SetGPIO(fe, 4, 0); 3086 status += MXL_SetGPIO(fe, 1, 0); 3087 status += MXL_SetGPIO(fe, 3, 1); 3088 } 3089 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { 3090 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3091 status += MXL_SetGPIO(fe, 4, 1); 3092 status += MXL_SetGPIO(fe, 1, 0); 3093 status += MXL_SetGPIO(fe, 3, 1); 3094 } 3095 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { 3096 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3097 status += MXL_SetGPIO(fe, 4, 1); 3098 status += MXL_SetGPIO(fe, 1, 0); 3099 status += MXL_SetGPIO(fe, 3, 0); 3100 } 3101 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { 3102 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3103 status += MXL_SetGPIO(fe, 4, 1); 3104 status += MXL_SetGPIO(fe, 1, 1); 3105 status += MXL_SetGPIO(fe, 3, 0); 3106 } 3107 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { 3108 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3109 status += MXL_SetGPIO(fe, 4, 1); 3110 status += MXL_SetGPIO(fe, 1, 1); 3111 status += MXL_SetGPIO(fe, 3, 0); 3112 } 3113 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { 3114 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3115 status += MXL_SetGPIO(fe, 4, 1); 3116 status += MXL_SetGPIO(fe, 1, 1); 3117 status += MXL_SetGPIO(fe, 3, 1); 3118 } 3119 } 3120 3121 if (state->TF_Type == MXL_TF_F) { 3122 3123 /* Tracking Filter type F */ 3124 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 3125 3126 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { 3127 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3128 status += MXL_SetGPIO(fe, 4, 0); 3129 status += MXL_SetGPIO(fe, 1, 1); 3130 status += MXL_SetGPIO(fe, 3, 1); 3131 } 3132 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { 3133 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3134 status += MXL_SetGPIO(fe, 4, 0); 3135 status += MXL_SetGPIO(fe, 1, 0); 3136 status += MXL_SetGPIO(fe, 3, 1); 3137 } 3138 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { 3139 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3140 status += MXL_SetGPIO(fe, 4, 1); 3141 status += MXL_SetGPIO(fe, 1, 0); 3142 status += MXL_SetGPIO(fe, 3, 1); 3143 } 3144 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { 3145 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3146 status += MXL_SetGPIO(fe, 4, 1); 3147 status += MXL_SetGPIO(fe, 1, 0); 3148 status += MXL_SetGPIO(fe, 3, 0); 3149 } 3150 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { 3151 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3152 status += MXL_SetGPIO(fe, 4, 1); 3153 status += MXL_SetGPIO(fe, 1, 1); 3154 status += MXL_SetGPIO(fe, 3, 0); 3155 } 3156 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { 3157 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3158 status += MXL_SetGPIO(fe, 4, 1); 3159 status += MXL_SetGPIO(fe, 1, 1); 3160 status += MXL_SetGPIO(fe, 3, 0); 3161 } 3162 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { 3163 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3164 status += MXL_SetGPIO(fe, 4, 1); 3165 status += MXL_SetGPIO(fe, 1, 1); 3166 status += MXL_SetGPIO(fe, 3, 1); 3167 } 3168 } 3169 3170 if (state->TF_Type == MXL_TF_E_2) { 3171 3172 /* Tracking Filter type E_2 */ 3173 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 3174 3175 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { 3176 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3177 status += MXL_SetGPIO(fe, 4, 0); 3178 status += MXL_SetGPIO(fe, 1, 1); 3179 status += MXL_SetGPIO(fe, 3, 1); 3180 } 3181 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { 3182 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3183 status += MXL_SetGPIO(fe, 4, 0); 3184 status += MXL_SetGPIO(fe, 1, 0); 3185 status += MXL_SetGPIO(fe, 3, 1); 3186 } 3187 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { 3188 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3189 status += MXL_SetGPIO(fe, 4, 1); 3190 status += MXL_SetGPIO(fe, 1, 0); 3191 status += MXL_SetGPIO(fe, 3, 1); 3192 } 3193 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { 3194 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3195 status += MXL_SetGPIO(fe, 4, 1); 3196 status += MXL_SetGPIO(fe, 1, 0); 3197 status += MXL_SetGPIO(fe, 3, 0); 3198 } 3199 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { 3200 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3201 status += MXL_SetGPIO(fe, 4, 1); 3202 status += MXL_SetGPIO(fe, 1, 1); 3203 status += MXL_SetGPIO(fe, 3, 0); 3204 } 3205 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { 3206 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3207 status += MXL_SetGPIO(fe, 4, 1); 3208 status += MXL_SetGPIO(fe, 1, 1); 3209 status += MXL_SetGPIO(fe, 3, 0); 3210 } 3211 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { 3212 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3213 status += MXL_SetGPIO(fe, 4, 1); 3214 status += MXL_SetGPIO(fe, 1, 1); 3215 status += MXL_SetGPIO(fe, 3, 1); 3216 } 3217 } 3218 3219 if (state->TF_Type == MXL_TF_G) { 3220 3221 /* Tracking Filter type G add for v2.6.8 */ 3222 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 3223 3224 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { 3225 3226 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3227 status += MXL_SetGPIO(fe, 4, 0); 3228 status += MXL_SetGPIO(fe, 1, 1); 3229 status += MXL_SetGPIO(fe, 3, 1); 3230 } 3231 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { 3232 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3233 status += MXL_SetGPIO(fe, 4, 0); 3234 status += MXL_SetGPIO(fe, 1, 0); 3235 status += MXL_SetGPIO(fe, 3, 1); 3236 } 3237 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { 3238 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3239 status += MXL_SetGPIO(fe, 4, 1); 3240 status += MXL_SetGPIO(fe, 1, 0); 3241 status += MXL_SetGPIO(fe, 3, 1); 3242 } 3243 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { 3244 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3245 status += MXL_SetGPIO(fe, 4, 1); 3246 status += MXL_SetGPIO(fe, 1, 0); 3247 status += MXL_SetGPIO(fe, 3, 0); 3248 } 3249 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { 3250 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3251 status += MXL_SetGPIO(fe, 4, 1); 3252 status += MXL_SetGPIO(fe, 1, 0); 3253 status += MXL_SetGPIO(fe, 3, 1); 3254 } 3255 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { 3256 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3257 status += MXL_SetGPIO(fe, 4, 1); 3258 status += MXL_SetGPIO(fe, 1, 1); 3259 status += MXL_SetGPIO(fe, 3, 0); 3260 } 3261 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { 3262 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3263 status += MXL_SetGPIO(fe, 4, 1); 3264 status += MXL_SetGPIO(fe, 1, 1); 3265 status += MXL_SetGPIO(fe, 3, 0); 3266 } 3267 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { 3268 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3269 status += MXL_SetGPIO(fe, 4, 1); 3270 status += MXL_SetGPIO(fe, 1, 1); 3271 status += MXL_SetGPIO(fe, 3, 1); 3272 } 3273 } 3274 3275 if (state->TF_Type == MXL_TF_E_NA) { 3276 3277 /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */ 3278 status += MXL_ControlWrite(fe, DAC_DIN_B, 0); 3279 3280 /* if UHF and terrestrial=> Turn off Tracking Filter */ 3281 if (state->RF_IN >= 471000000 && 3282 (state->RF_IN - 471000000)%6000000 != 0) { 3283 3284 /* Turn off all the banks */ 3285 status += MXL_SetGPIO(fe, 3, 1); 3286 status += MXL_SetGPIO(fe, 1, 1); 3287 status += MXL_SetGPIO(fe, 4, 1); 3288 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3289 3290 /* 2.6.12 Turn on RSSI */ 3291 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); 3292 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); 3293 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); 3294 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); 3295 3296 /* RSSI reference point */ 3297 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); 3298 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); 3299 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); 3300 3301 /* following parameter is from analog OTA mode, 3302 * can be change to seek better performance */ 3303 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); 3304 } else { 3305 /* if VHF or Cable => Turn on Tracking Filter */ 3306 3307 /* 2.6.12 Turn off RSSI */ 3308 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); 3309 3310 /* change back from above condition */ 3311 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); 3312 3313 3314 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { 3315 3316 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3317 status += MXL_SetGPIO(fe, 4, 0); 3318 status += MXL_SetGPIO(fe, 1, 1); 3319 status += MXL_SetGPIO(fe, 3, 1); 3320 } 3321 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { 3322 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3323 status += MXL_SetGPIO(fe, 4, 0); 3324 status += MXL_SetGPIO(fe, 1, 0); 3325 status += MXL_SetGPIO(fe, 3, 1); 3326 } 3327 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { 3328 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3329 status += MXL_SetGPIO(fe, 4, 1); 3330 status += MXL_SetGPIO(fe, 1, 0); 3331 status += MXL_SetGPIO(fe, 3, 1); 3332 } 3333 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { 3334 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3335 status += MXL_SetGPIO(fe, 4, 1); 3336 status += MXL_SetGPIO(fe, 1, 0); 3337 status += MXL_SetGPIO(fe, 3, 0); 3338 } 3339 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { 3340 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); 3341 status += MXL_SetGPIO(fe, 4, 1); 3342 status += MXL_SetGPIO(fe, 1, 1); 3343 status += MXL_SetGPIO(fe, 3, 0); 3344 } 3345 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { 3346 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3347 status += MXL_SetGPIO(fe, 4, 1); 3348 status += MXL_SetGPIO(fe, 1, 1); 3349 status += MXL_SetGPIO(fe, 3, 0); 3350 } 3351 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { 3352 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); 3353 status += MXL_SetGPIO(fe, 4, 1); 3354 status += MXL_SetGPIO(fe, 1, 1); 3355 status += MXL_SetGPIO(fe, 3, 1); 3356 } 3357 } 3358 } 3359 return status ; 3360 } 3361 3362 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) 3363 { 3364 u16 status = 0; 3365 3366 if (GPIO_Num == 1) 3367 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1); 3368 3369 /* GPIO2 is not available */ 3370 3371 if (GPIO_Num == 3) { 3372 if (GPIO_Val == 1) { 3373 status += MXL_ControlWrite(fe, GPIO_3, 0); 3374 status += MXL_ControlWrite(fe, GPIO_3B, 0); 3375 } 3376 if (GPIO_Val == 0) { 3377 status += MXL_ControlWrite(fe, GPIO_3, 1); 3378 status += MXL_ControlWrite(fe, GPIO_3B, 1); 3379 } 3380 if (GPIO_Val == 3) { /* tri-state */ 3381 status += MXL_ControlWrite(fe, GPIO_3, 0); 3382 status += MXL_ControlWrite(fe, GPIO_3B, 1); 3383 } 3384 } 3385 if (GPIO_Num == 4) { 3386 if (GPIO_Val == 1) { 3387 status += MXL_ControlWrite(fe, GPIO_4, 0); 3388 status += MXL_ControlWrite(fe, GPIO_4B, 0); 3389 } 3390 if (GPIO_Val == 0) { 3391 status += MXL_ControlWrite(fe, GPIO_4, 1); 3392 status += MXL_ControlWrite(fe, GPIO_4B, 1); 3393 } 3394 if (GPIO_Val == 3) { /* tri-state */ 3395 status += MXL_ControlWrite(fe, GPIO_4, 0); 3396 status += MXL_ControlWrite(fe, GPIO_4B, 1); 3397 } 3398 } 3399 3400 return status; 3401 } 3402 3403 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) 3404 { 3405 u16 status = 0; 3406 3407 /* Will write ALL Matching Control Name */ 3408 /* Write Matching INIT Control */ 3409 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); 3410 /* Write Matching CH Control */ 3411 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); 3412 #ifdef _MXL_INTERNAL 3413 /* Write Matching MXL Control */ 3414 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); 3415 #endif 3416 return status; 3417 } 3418 3419 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, 3420 u32 value, u16 controlGroup) 3421 { 3422 struct mxl5005s_state *state = fe->tuner_priv; 3423 u16 i, j; 3424 u32 highLimit; 3425 3426 if (controlGroup == 1) /* Initial Control */ { 3427 3428 for (i = 0; i < state->Init_Ctrl_Num; i++) { 3429 3430 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { 3431 3432 u16 size = min_t(u16, state->Init_Ctrl[i].size, 3433 ARRAY_SIZE(state->Init_Ctrl[i].val)); 3434 highLimit = 1 << size; 3435 if (value < highLimit) { 3436 for (j = 0; j < size; j++) { 3437 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3438 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), 3439 (u8)(state->Init_Ctrl[i].bit[j]), 3440 (u8)((value>>j) & 0x01)); 3441 } 3442 } else 3443 return -1; 3444 } 3445 } 3446 } 3447 if (controlGroup == 2) /* Chan change Control */ { 3448 3449 for (i = 0; i < state->CH_Ctrl_Num; i++) { 3450 3451 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { 3452 3453 u16 size = min_t(u16, state->CH_Ctrl[i].size, 3454 ARRAY_SIZE(state->CH_Ctrl[i].val)); 3455 highLimit = 1 << size; 3456 if (value < highLimit) { 3457 for (j = 0; j < size; j++) { 3458 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3459 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), 3460 (u8)(state->CH_Ctrl[i].bit[j]), 3461 (u8)((value>>j) & 0x01)); 3462 } 3463 } else 3464 return -1; 3465 } 3466 } 3467 } 3468 #ifdef _MXL_INTERNAL 3469 if (controlGroup == 3) /* Maxlinear Control */ { 3470 3471 for (i = 0; i < state->MXL_Ctrl_Num; i++) { 3472 3473 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { 3474 3475 highLimit = (1 << state->MXL_Ctrl[i].size); 3476 if (value < highLimit) { 3477 for (j = 0; j < state->MXL_Ctrl[i].size; j++) { 3478 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); 3479 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), 3480 (u8)(state->MXL_Ctrl[i].bit[j]), 3481 (u8)((value>>j) & 0x01)); 3482 } 3483 } else 3484 return -1; 3485 } 3486 } 3487 } 3488 #endif 3489 return 0 ; /* successful return */ 3490 } 3491 3492 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) 3493 { 3494 struct mxl5005s_state *state = fe->tuner_priv; 3495 int i ; 3496 3497 for (i = 0; i < 104; i++) { 3498 if (RegNum == state->TunerRegs[i].Reg_Num) { 3499 *RegVal = (u8)(state->TunerRegs[i].Reg_Val); 3500 return 0; 3501 } 3502 } 3503 3504 return 1; 3505 } 3506 3507 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) 3508 { 3509 struct mxl5005s_state *state = fe->tuner_priv; 3510 u32 ctrlVal ; 3511 u16 i, k ; 3512 3513 for (i = 0; i < state->Init_Ctrl_Num ; i++) { 3514 3515 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { 3516 3517 ctrlVal = 0; 3518 for (k = 0; k < state->Init_Ctrl[i].size; k++) 3519 ctrlVal += state->Init_Ctrl[i].val[k] * (1<<k); 3520 *value = ctrlVal; 3521 return 0; 3522 } 3523 } 3524 3525 for (i = 0; i < state->CH_Ctrl_Num ; i++) { 3526 3527 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { 3528 3529 ctrlVal = 0; 3530 for (k = 0; k < state->CH_Ctrl[i].size; k++) 3531 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); 3532 *value = ctrlVal; 3533 return 0; 3534 3535 } 3536 } 3537 3538 #ifdef _MXL_INTERNAL 3539 for (i = 0; i < state->MXL_Ctrl_Num ; i++) { 3540 3541 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { 3542 3543 ctrlVal = 0; 3544 for (k = 0; k < state->MXL_Ctrl[i].size; k++) 3545 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k); 3546 *value = ctrlVal; 3547 return 0; 3548 3549 } 3550 } 3551 #endif 3552 return 1; 3553 } 3554 3555 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, 3556 u8 bitVal) 3557 { 3558 struct mxl5005s_state *state = fe->tuner_priv; 3559 int i ; 3560 3561 const u8 AND_MAP[8] = { 3562 0xFE, 0xFD, 0xFB, 0xF7, 3563 0xEF, 0xDF, 0xBF, 0x7F } ; 3564 3565 const u8 OR_MAP[8] = { 3566 0x01, 0x02, 0x04, 0x08, 3567 0x10, 0x20, 0x40, 0x80 } ; 3568 3569 for (i = 0; i < state->TunerRegs_Num; i++) { 3570 if (state->TunerRegs[i].Reg_Num == address) { 3571 if (bitVal) 3572 state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; 3573 else 3574 state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; 3575 break ; 3576 } 3577 } 3578 } 3579 3580 static u32 MXL_Ceiling(u32 value, u32 resolution) 3581 { 3582 return value / resolution + (value % resolution > 0 ? 1 : 0); 3583 } 3584 3585 /* Retrieve the Initialization Registers */ 3586 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, 3587 u8 *RegVal, int *count) 3588 { 3589 u16 status = 0; 3590 int i ; 3591 3592 static const u8 RegAddr[] = { 3593 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, 3594 76, 77, 91, 134, 135, 137, 147, 3595 156, 166, 167, 168, 25 3596 }; 3597 3598 *count = ARRAY_SIZE(RegAddr); 3599 3600 status += MXL_BlockInit(fe); 3601 3602 for (i = 0 ; i < *count; i++) { 3603 RegNum[i] = RegAddr[i]; 3604 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); 3605 } 3606 3607 return status; 3608 } 3609 3610 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, 3611 int *count) 3612 { 3613 u16 status = 0; 3614 int i ; 3615 3616 /* add 77, 166, 167, 168 register for 2.6.12 */ 3617 #ifdef _MXL_PRODUCTION 3618 static const u8 RegAddr[] = { 3619 14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 3620 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 3621 }; 3622 #else 3623 static const u8 RegAddr[] = { 3624 14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 3625 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 3626 }; 3627 /* 3628 u8 RegAddr[171]; 3629 for (i = 0; i <= 170; i++) 3630 RegAddr[i] = i; 3631 */ 3632 #endif 3633 3634 *count = ARRAY_SIZE(RegAddr); 3635 3636 for (i = 0 ; i < *count; i++) { 3637 RegNum[i] = RegAddr[i]; 3638 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); 3639 } 3640 3641 return status; 3642 } 3643 3644 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, 3645 u8 *RegVal, int *count) 3646 { 3647 u16 status = 0; 3648 int i; 3649 3650 static const u8 RegAddr[] = {43, 136}; 3651 3652 *count = ARRAY_SIZE(RegAddr); 3653 3654 for (i = 0; i < *count; i++) { 3655 RegNum[i] = RegAddr[i]; 3656 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); 3657 } 3658 3659 return status; 3660 } 3661 3662 static u16 MXL_GetMasterControl(u8 *MasterReg, int state) 3663 { 3664 if (state == 1) /* Load_Start */ 3665 *MasterReg = 0xF3; 3666 if (state == 2) /* Power_Down */ 3667 *MasterReg = 0x41; 3668 if (state == 3) /* Synth_Reset */ 3669 *MasterReg = 0xB1; 3670 if (state == 4) /* Seq_Off */ 3671 *MasterReg = 0xF1; 3672 3673 return 0; 3674 } 3675 3676 #ifdef _MXL_PRODUCTION 3677 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) 3678 { 3679 struct mxl5005s_state *state = fe->tuner_priv; 3680 u16 status = 0 ; 3681 3682 if (VCO_Range == 1) { 3683 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); 3684 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 3685 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 3686 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); 3687 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 3688 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 3689 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 3690 if (state->Mode == 0 && state->IF_Mode == 1) { 3691 /* Analog Low IF Mode */ 3692 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3693 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3694 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3695 status += MXL_ControlWrite(fe, 3696 CHCAL_FRAC_MOD_RF, 180224); 3697 } 3698 if (state->Mode == 0 && state->IF_Mode == 0) { 3699 /* Analog Zero IF Mode */ 3700 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3701 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3702 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3703 status += MXL_ControlWrite(fe, 3704 CHCAL_FRAC_MOD_RF, 222822); 3705 } 3706 if (state->Mode == 1) /* Digital Mode */ { 3707 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3708 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3709 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); 3710 status += MXL_ControlWrite(fe, 3711 CHCAL_FRAC_MOD_RF, 229376); 3712 } 3713 } 3714 3715 if (VCO_Range == 2) { 3716 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); 3717 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 3718 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 3719 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); 3720 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 3721 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 3722 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 3723 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3724 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3725 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); 3726 if (state->Mode == 0 && state->IF_Mode == 1) { 3727 /* Analog Low IF Mode */ 3728 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3729 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3730 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3731 status += MXL_ControlWrite(fe, 3732 CHCAL_FRAC_MOD_RF, 206438); 3733 } 3734 if (state->Mode == 0 && state->IF_Mode == 0) { 3735 /* Analog Zero IF Mode */ 3736 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3737 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3738 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3739 status += MXL_ControlWrite(fe, 3740 CHCAL_FRAC_MOD_RF, 206438); 3741 } 3742 if (state->Mode == 1) /* Digital Mode */ { 3743 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); 3744 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3745 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); 3746 status += MXL_ControlWrite(fe, 3747 CHCAL_FRAC_MOD_RF, 16384); 3748 } 3749 } 3750 3751 if (VCO_Range == 3) { 3752 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); 3753 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 3754 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 3755 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); 3756 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 3757 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 3758 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 3759 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3760 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3761 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3762 if (state->Mode == 0 && state->IF_Mode == 1) { 3763 /* Analog Low IF Mode */ 3764 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3765 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3766 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); 3767 status += MXL_ControlWrite(fe, 3768 CHCAL_FRAC_MOD_RF, 173670); 3769 } 3770 if (state->Mode == 0 && state->IF_Mode == 0) { 3771 /* Analog Zero IF Mode */ 3772 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3773 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3774 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); 3775 status += MXL_ControlWrite(fe, 3776 CHCAL_FRAC_MOD_RF, 173670); 3777 } 3778 if (state->Mode == 1) /* Digital Mode */ { 3779 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3780 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); 3781 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); 3782 status += MXL_ControlWrite(fe, 3783 CHCAL_FRAC_MOD_RF, 245760); 3784 } 3785 } 3786 3787 if (VCO_Range == 4) { 3788 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); 3789 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); 3790 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); 3791 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); 3792 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); 3793 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); 3794 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); 3795 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3796 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3797 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3798 if (state->Mode == 0 && state->IF_Mode == 1) { 3799 /* Analog Low IF Mode */ 3800 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3801 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3802 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3803 status += MXL_ControlWrite(fe, 3804 CHCAL_FRAC_MOD_RF, 206438); 3805 } 3806 if (state->Mode == 0 && state->IF_Mode == 0) { 3807 /* Analog Zero IF Mode */ 3808 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3809 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3810 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3811 status += MXL_ControlWrite(fe, 3812 CHCAL_FRAC_MOD_RF, 206438); 3813 } 3814 if (state->Mode == 1) /* Digital Mode */ { 3815 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); 3816 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); 3817 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); 3818 status += MXL_ControlWrite(fe, 3819 CHCAL_FRAC_MOD_RF, 212992); 3820 } 3821 } 3822 3823 return status; 3824 } 3825 3826 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) 3827 { 3828 struct mxl5005s_state *state = fe->tuner_priv; 3829 u16 status = 0; 3830 3831 if (Hystersis == 1) 3832 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); 3833 3834 return status; 3835 } 3836 #endif 3837 /* End: Reference driver code found in the Realtek driver that 3838 * is copyright MaxLinear */ 3839 3840 /* ---------------------------------------------------------------- 3841 * Begin: Everything after here is new code to adapt the 3842 * proprietary Realtek driver into a Linux API tuner. 3843 * Copyright (C) 2008 Steven Toth <stoth@linuxtv.org> 3844 */ 3845 static int mxl5005s_reset(struct dvb_frontend *fe) 3846 { 3847 struct mxl5005s_state *state = fe->tuner_priv; 3848 int ret = 0; 3849 3850 u8 buf[2] = { 0xff, 0x00 }; 3851 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, 3852 .buf = buf, .len = 2 }; 3853 3854 dprintk(2, "%s()\n", __func__); 3855 3856 if (fe->ops.i2c_gate_ctrl) 3857 fe->ops.i2c_gate_ctrl(fe, 1); 3858 3859 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 3860 printk(KERN_WARNING "mxl5005s I2C reset failed\n"); 3861 ret = -EREMOTEIO; 3862 } 3863 3864 if (fe->ops.i2c_gate_ctrl) 3865 fe->ops.i2c_gate_ctrl(fe, 0); 3866 3867 return ret; 3868 } 3869 3870 /* Write a single byte to a single reg, latch the value if required by 3871 * following the transaction with the latch byte. 3872 */ 3873 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) 3874 { 3875 struct mxl5005s_state *state = fe->tuner_priv; 3876 u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; 3877 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, 3878 .buf = buf, .len = 3 }; 3879 3880 if (latch == 0) 3881 msg.len = 2; 3882 3883 dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); 3884 3885 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 3886 printk(KERN_WARNING "mxl5005s I2C write failed\n"); 3887 return -EREMOTEIO; 3888 } 3889 return 0; 3890 } 3891 3892 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, 3893 u8 *datatable, u8 len) 3894 { 3895 int ret = 0, i; 3896 3897 if (fe->ops.i2c_gate_ctrl) 3898 fe->ops.i2c_gate_ctrl(fe, 1); 3899 3900 for (i = 0 ; i < len-1; i++) { 3901 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); 3902 if (ret < 0) 3903 break; 3904 } 3905 3906 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); 3907 3908 if (fe->ops.i2c_gate_ctrl) 3909 fe->ops.i2c_gate_ctrl(fe, 0); 3910 3911 return ret; 3912 } 3913 3914 static int mxl5005s_init(struct dvb_frontend *fe) 3915 { 3916 struct mxl5005s_state *state = fe->tuner_priv; 3917 3918 dprintk(1, "%s()\n", __func__); 3919 state->current_mode = MXL_QAM; 3920 return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); 3921 } 3922 3923 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, 3924 u32 bandwidth) 3925 { 3926 struct mxl5005s_state *state = fe->tuner_priv; 3927 u8 *AddrTable; 3928 u8 *ByteTable; 3929 int TableLen; 3930 3931 dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); 3932 3933 mxl5005s_reset(fe); 3934 3935 AddrTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8), 3936 GFP_KERNEL); 3937 if (!AddrTable) 3938 return -ENOMEM; 3939 3940 ByteTable = kcalloc(MXL5005S_REG_WRITING_TABLE_LEN_MAX, sizeof(u8), 3941 GFP_KERNEL); 3942 if (!ByteTable) { 3943 kfree(AddrTable); 3944 return -ENOMEM; 3945 } 3946 3947 /* Tuner initialization stage 0 */ 3948 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); 3949 AddrTable[0] = MASTER_CONTROL_ADDR; 3950 ByteTable[0] |= state->config->AgcMasterByte; 3951 3952 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); 3953 3954 mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); 3955 3956 /* Tuner initialization stage 1 */ 3957 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); 3958 3959 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); 3960 3961 kfree(AddrTable); 3962 kfree(ByteTable); 3963 3964 return 0; 3965 } 3966 3967 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, 3968 u32 bandwidth) 3969 { 3970 struct mxl5005s_state *state = fe->tuner_priv; 3971 struct mxl5005s_config *c = state->config; 3972 3973 InitTunerControls(fe); 3974 3975 /* Set MxL5005S parameters. */ 3976 MXL5005_TunerConfig( 3977 fe, 3978 c->mod_mode, 3979 c->if_mode, 3980 bandwidth, 3981 c->if_freq, 3982 c->xtal_freq, 3983 c->agc_mode, 3984 c->top, 3985 c->output_load, 3986 c->clock_out, 3987 c->div_out, 3988 c->cap_select, 3989 c->rssi_enable, 3990 mod_type, 3991 c->tracking_filter); 3992 3993 return 0; 3994 } 3995 3996 static int mxl5005s_set_params(struct dvb_frontend *fe) 3997 { 3998 struct mxl5005s_state *state = fe->tuner_priv; 3999 struct dtv_frontend_properties *c = &fe->dtv_property_cache; 4000 u32 delsys = c->delivery_system; 4001 u32 bw = c->bandwidth_hz; 4002 u32 req_mode, req_bw = 0; 4003 int ret; 4004 4005 dprintk(1, "%s()\n", __func__); 4006 4007 switch (delsys) { 4008 case SYS_ATSC: 4009 req_mode = MXL_ATSC; 4010 req_bw = MXL5005S_BANDWIDTH_6MHZ; 4011 break; 4012 case SYS_DVBC_ANNEX_B: 4013 req_mode = MXL_QAM; 4014 req_bw = MXL5005S_BANDWIDTH_6MHZ; 4015 break; 4016 default: /* Assume DVB-T */ 4017 req_mode = MXL_DVBT; 4018 switch (bw) { 4019 case 6000000: 4020 req_bw = MXL5005S_BANDWIDTH_6MHZ; 4021 break; 4022 case 7000000: 4023 req_bw = MXL5005S_BANDWIDTH_7MHZ; 4024 break; 4025 case 8000000: 4026 case 0: 4027 req_bw = MXL5005S_BANDWIDTH_8MHZ; 4028 break; 4029 default: 4030 return -EINVAL; 4031 } 4032 } 4033 4034 /* Change tuner for new modulation type if reqd */ 4035 if (req_mode != state->current_mode || 4036 req_bw != state->Chan_Bandwidth) { 4037 state->current_mode = req_mode; 4038 ret = mxl5005s_reconfigure(fe, req_mode, req_bw); 4039 4040 } else 4041 ret = 0; 4042 4043 if (ret == 0) { 4044 dprintk(1, "%s() freq=%d\n", __func__, c->frequency); 4045 ret = mxl5005s_SetRfFreqHz(fe, c->frequency); 4046 } 4047 4048 return ret; 4049 } 4050 4051 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) 4052 { 4053 struct mxl5005s_state *state = fe->tuner_priv; 4054 dprintk(1, "%s()\n", __func__); 4055 4056 *frequency = state->RF_IN; 4057 4058 return 0; 4059 } 4060 4061 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) 4062 { 4063 struct mxl5005s_state *state = fe->tuner_priv; 4064 dprintk(1, "%s()\n", __func__); 4065 4066 *bandwidth = state->Chan_Bandwidth; 4067 4068 return 0; 4069 } 4070 4071 static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) 4072 { 4073 struct mxl5005s_state *state = fe->tuner_priv; 4074 dprintk(1, "%s()\n", __func__); 4075 4076 *frequency = state->IF_OUT; 4077 4078 return 0; 4079 } 4080 4081 static void mxl5005s_release(struct dvb_frontend *fe) 4082 { 4083 dprintk(1, "%s()\n", __func__); 4084 kfree(fe->tuner_priv); 4085 fe->tuner_priv = NULL; 4086 } 4087 4088 static const struct dvb_tuner_ops mxl5005s_tuner_ops = { 4089 .info = { 4090 .name = "MaxLinear MXL5005S", 4091 .frequency_min_hz = 48 * MHz, 4092 .frequency_max_hz = 860 * MHz, 4093 .frequency_step_hz = 50 * kHz, 4094 }, 4095 4096 .release = mxl5005s_release, 4097 .init = mxl5005s_init, 4098 4099 .set_params = mxl5005s_set_params, 4100 .get_frequency = mxl5005s_get_frequency, 4101 .get_bandwidth = mxl5005s_get_bandwidth, 4102 .get_if_frequency = mxl5005s_get_if_frequency, 4103 }; 4104 4105 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, 4106 struct i2c_adapter *i2c, 4107 struct mxl5005s_config *config) 4108 { 4109 struct mxl5005s_state *state = NULL; 4110 dprintk(1, "%s()\n", __func__); 4111 4112 state = kzalloc_obj(struct mxl5005s_state); 4113 if (state == NULL) 4114 return NULL; 4115 4116 state->frontend = fe; 4117 state->config = config; 4118 state->i2c = i2c; 4119 4120 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", 4121 config->i2c_address); 4122 4123 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, 4124 sizeof(struct dvb_tuner_ops)); 4125 4126 fe->tuner_priv = state; 4127 return fe; 4128 } 4129 EXPORT_SYMBOL_GPL(mxl5005s_attach); 4130 4131 MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); 4132 MODULE_AUTHOR("Steven Toth"); 4133 MODULE_LICENSE("GPL"); 4134