Home
last modified time | relevance | path

Searched refs:lower_32_bits (Results 1 – 25 of 461) sorted by relevance

12345678910>>...19

/linux/drivers/firmware/smccc/
H A Dkvm_guest.c30 val[0] = lower_32_bits(res.a0); in kvm_init_hyp_services()
31 val[1] = lower_32_bits(res.a1); in kvm_init_hyp_services()
32 val[2] = lower_32_bits(res.a2); in kvm_init_hyp_services()
33 val[3] = lower_32_bits(res.a3); in kvm_init_hyp_services()
71 ver = lower_32_bits(res.a1); in kvm_arm_target_impl_cpu_init()
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dring_mode.c43 desc->des2 = cpu_to_le32(lower_32_bits(des2)); in jumbo_frm()
51 desc->des3 = cpu_to_le32(lower_32_bits(des2) + BUF_SIZE_4KiB); in jumbo_frm()
64 desc->des2 = cpu_to_le32(lower_32_bits(des2)); in jumbo_frm()
71 desc->des3 = cpu_to_le32(lower_32_bits(des2) + BUF_SIZE_4KiB); in jumbo_frm()
78 desc->des2 = cpu_to_le32(lower_32_bits(des2)); in jumbo_frm()
84 desc->des3 = cpu_to_le32(lower_32_bits(des2) + BUF_SIZE_4KiB); in jumbo_frm()
/linux/drivers/tee/tstee/
H A Dcore.c37 args[0] = lower_32_bits(data->data0); in arg_list_from_ffa_data()
38 args[1] = lower_32_bits(data->data1); in arg_list_from_ffa_data()
39 args[2] = lower_32_bits(data->data2); in arg_list_from_ffa_data()
40 args[3] = lower_32_bits(data->data3); in arg_list_from_ffa_data()
41 args[4] = lower_32_bits(data->data4); in arg_list_from_ffa_data()
190 shm_id = lower_32_bits(param[0].u.value.a); in tstee_invoke_func()
191 req_len = lower_32_bits(param[0].u.value.b); in tstee_invoke_func()
212 ffa_args[TS_RPC_SERVICE_MEM_HANDLE_LSW] = lower_32_bits(handle); in tstee_invoke_func()
281 lower_32_bits(shm->sec_world_id); in tstee_shm_register()
319 lower_32_bits(shm->sec_world_id); in tstee_shm_unregister()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c400 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
412 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
420 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
428 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr)); in vcn_v2_0_mc_resume()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
489 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
509 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
521 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
975 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
986 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
[all …]
H A Dsdma_v7_0.c149 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
217 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2), in sdma_v7_0_ring_set_wptr()
236 lower_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
283 sdma_v7_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v7_0_ring_emit_ib()
288 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_0_ring_emit_ib()
291 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v7_0_ring_emit_ib()
367 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
369 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v7_0_ring_emit_fence()
378 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
[all …]
H A Dsdma_v6_0.c151 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
217 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2), in sdma_v6_0_ring_set_wptr()
235 lower_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
281 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v6_0_ring_emit_ib()
286 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v6_0_ring_emit_ib()
289 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
365 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
367 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
376 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
[all …]
H A Dsdma_v7_1.c143 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_init_cond_exec()
211 lower_32_bits(ring->wptr << 2), in sdma_v7_1_ring_set_wptr()
224 lower_32_bits(ring->wptr << 2), in sdma_v7_1_ring_set_wptr()
230 lower_32_bits(ring->wptr << 2)); in sdma_v7_1_ring_set_wptr()
277 sdma_v7_1_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v7_1_ring_emit_ib()
282 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v7_1_ring_emit_ib()
285 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v7_1_ring_emit_ib()
335 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
337 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v7_1_ring_emit_fence()
346 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v7_1_ring_emit_fence()
[all …]
H A Dvcn_v3_0.c537 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); in vcn_v3_0_mc_resume()
548 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); in vcn_v3_0_mc_resume()
556 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v3_0_mc_resume()
564 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); in vcn_v3_0_mc_resume()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
624 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
644 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
656 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1161 lower_32_bits(ring->gpu_addr)); in vcn_v3_0_start_dpg_mode()
1172 lower_32_bits(ring->wptr)); in vcn_v3_0_start_dpg_mode()
[all …]
H A Dsdma_v5_2.c148 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
221 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
235 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
244 lower_32_bits(ring->wptr << 2), in sdma_v5_2_ring_set_wptr()
248 lower_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
293 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_2_ring_emit_ib()
298 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_2_ring_emit_ib()
301 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
381 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
383 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
[all …]
H A Dsdma_v5_0.c308 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
381 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
394 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
399 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
445 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
450 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
453 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
531 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
533 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
542 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
[all …]
H A Dsdma_v4_4_2.c275 lower_32_bits(ring->wptr << 2), in sdma_v4_4_2_ring_set_wptr()
287 lower_32_bits(ring->wptr << 2), in sdma_v4_4_2_ring_set_wptr()
291 lower_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
342 lower_32_bits(wptr)); in sdma_v4_4_2_page_ring_set_wptr()
379 sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v4_4_2_ring_emit_ib()
384 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_4_2_ring_emit_ib()
459 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_4_2_ring_emit_fence()
461 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v4_4_2_ring_emit_fence()
469 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_4_2_ring_emit_fence()
703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v4_4_2_gfx_resume()
[all …]
H A Dumsch_mm_v4_0.c90 lower_32_bits(adev->umsch_mm.irq_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
95 lower_32_bits(adev->umsch_mm.uc_start_addr >> 2)); in umsch_mm_v4_0_load_microcode()
103 WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
108 WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
114 lower_32_bits(adev->umsch_mm.data_start_addr)); in umsch_mm_v4_0_load_microcode()
124 WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data)); in umsch_mm_v4_0_load_microcode()
147 WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, lower_32_bits(umsch->log_gpu_addr)); in umsch_mm_v4_0_load_microcode()
228 WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); in umsch_mm_v4_0_ring_start()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c126 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
149 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
196 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
199 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
201 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
222 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
338 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
340 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
342 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_vi.c116 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
130 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
132 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
142 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
189 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
192 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
194 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
220 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
382 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
384 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v12_1.c186 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
210 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
253 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
265 lower_32_bits((q->queue_address + q->queue_size) >> 8); in update_mqd()
277 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
279 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
300 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
413 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
415 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
417 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
[all …]
H A Dkfd_mqd_manager_v11.c147 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
174 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
221 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
224 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
226 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
247 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
464 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
466 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
468 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c73 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
76 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
79 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
95 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
99 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
101 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c41 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
44 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
60 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
64 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/linux/drivers/media/pci/pt3/
H A Dpt3_dma.c52 iowrite32(lower_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
184 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
190 d->addr_l = lower_32_bits(data_addr); in pt3_alloc_dmabuf()
195 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
204 d->next_l = lower_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux/include/linux/
H A Dwordpart.h20 #define lower_32_bits(n) ((u32)((n) & 0xffffffff)) macro
48 #define REPEAT_BYTE_U32(x) lower_32_bits(REPEAT_BYTE(x))
/linux/drivers/accel/habanalabs/common/
H A Dmemory_mgr.c25 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_get()
67 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_release()
86 idr_remove(&buf->mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_remove_idr_locked()
118 buf = idr_find(&mmg->handles, lower_32_bits(handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_put_handle()
185 idr_remove(&mmg->handles, lower_32_bits(buf->handle >> PAGE_SHIFT)); in hl_mmap_mem_buf_alloc()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bo74c1.c49 0x030c, lower_32_bits(mem->vma[0].addr), in nv84_bo_move_exec()
51 0x0314, lower_32_bits(mem->vma[1].addr), in nv84_bo_move_exec()
/linux/drivers/pci/controller/
H A Dpcie-rcar.c91 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F, in rcar_pcie_set_outbound()
110 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), in rcar_pcie_set_inbound()
112 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx)); in rcar_pcie_set_inbound()
/linux/drivers/gpu/drm/tegra/
H A Driscv.c79 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_PKCPARAM_LO); in tegra_drm_riscv_boot_bootrom()
83 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCCODE_LO); in tegra_drm_riscv_boot_bootrom()
87 riscv_writel(riscv, lower_32_bits(addr >> 8), RISCV_BCR_DMAADDR_FMCDATA_LO); in tegra_drm_riscv_boot_bootrom()
/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194-acpi.c52 atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr), in program_outbound_atu()
56 atu_reg_write(pcie_ecam, index, lower_32_bits(pci_addr), in program_outbound_atu()
58 atu_reg_write(pcie_ecam, index, lower_32_bits(cpu_addr + size - 1), in program_outbound_atu()

12345678910>>...19