Searched refs:link_width_cntl (Results 1 – 3 of 3) sorted by relevance
/linux/drivers/gpu/drm/radeon/ |
H A D | rv770.c | 2022 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local 2045 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable() 2046 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in rv770_pcie_gen2_enable() 2047 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable() 2048 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in rv770_pcie_gen2_enable() 2049 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { in rv770_pcie_gen2_enable() 2050 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable() 2051 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | in rv770_pcie_gen2_enable() 2053 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable() 2055 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in rv770_pcie_gen2_enable() [all...] |
H A D | evergreen.c | 5325 u32 link_width_cntl, speed_cntl; in evergreen_pcie_gen2_enable() local 5355 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable() 5356 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable() 5357 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable() 5376 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in evergreen_pcie_gen2_enable() 5379 link_width_cntl |= LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable() 5381 link_width_cntl &= ~LC_UPCONFIGURE_DIS; in evergreen_pcie_gen2_enable() 5382 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in evergreen_pcie_gen2_enable()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | si.c | 1517 u32 link_width_cntl; in si_get_pcie_lanes() local 1522 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_get_pcie_lanes() 1524 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { in si_get_pcie_lanes() 1542 u32 link_width_cntl, mask; in si_set_pcie_lanes() local 1571 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); in si_set_pcie_lanes() 1572 link_width_cntl &= ~LC_LINK_WIDTH_MASK; in si_set_pcie_lanes() 1573 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; in si_set_pcie_lanes() 1574 link_width_cntl |= (LC_RECONFIG_NOW | in si_set_pcie_lanes() 1577 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); in si_set_pcie_lanes()
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