4397 	u32 link_width_cntl, mask;  in r600_set_pcie_lanes()  local
4439 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_set_pcie_lanes()
4440 	link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;  in r600_set_pcie_lanes()
4441 	link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;  in r600_set_pcie_lanes()
4442 	link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |  in r600_set_pcie_lanes()
4445 	WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_set_pcie_lanes()
4450 	u32 link_width_cntl;  in r600_get_pcie_lanes()  local
4464 	link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);  in r600_get_pcie_lanes()
4466 …switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIF…  in r600_get_pcie_lanes()
4487 	u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;  in r600_pcie_gen2_enable()  local
4524 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4525 		link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4526 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4527 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4528 		if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {  in r600_pcie_gen2_enable()
4529 			lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;  in r600_pcie_gen2_enable()
4530 			link_width_cntl &= ~(LC_LINK_WIDTH_MASK |  in r600_pcie_gen2_enable()
4532 			link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;  in r600_pcie_gen2_enable()
4533 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4535 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4536 			WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()
4589 		link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);  in r600_pcie_gen2_enable()
4592 			link_width_cntl |= LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4594 			link_width_cntl &= ~LC_UPCONFIGURE_DIS;  in r600_pcie_gen2_enable()
4595 		WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);  in r600_pcie_gen2_enable()