| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | mad.h | 399 u16 tx_link_width(u16 link_width);
400 u64 get_xmit_wait_counters(struct hfi1_pportdata *ppd, u16 link_width,
430 static inline u64 convert_xmit_counter(u64 xmit_wait_val, u16 link_width, in convert_xmit_counter() argument
433 return (xmit_wait_val * 2 * (FACTOR_LINK_WIDTH / link_width) in convert_xmit_counter()
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| /linux/include/uapi/linux/ |
| H A D | rio_mport_cdev.h | 77 __u8 link_width; member
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| /linux/drivers/ntb/hw/mscc/ |
| H A D | ntb_hw_switchtec.c | 88 enum ntb_width link_width; member
442 sndev->link_width = NTB_WIDTH_NONE; in switchtec_ntb_set_link_speed()
452 sndev->link_width = min(self_width, peer_width); in switchtec_ntb_set_link_speed()
568 *width = sndev->link_width; in switchtec_ntb_link_is_up()
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| /linux/include/linux/ |
| H A D | rio.h | 368 int link_width; member
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| H A D | thunderbolt.h | 214 * @link_width: Width of the downstream facing link
265 enum tb_link_width link_width;
264 enum tb_link_width link_width; global() member
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| /linux/drivers/net/thunderbolt/ |
| H A D | main.c | 1313 if (xd->link_width == 2) in tbnet_get_link_ksettings()
1320 if (xd->link_width == 2) { in tbnet_get_link_ksettings()
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| /linux/drivers/scsi/qla4xxx/ |
| H A D | ql4_def.h | 749 int link_width; member
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| H A D | ql4_nx.c | 1757 ha->link_width = (lnk >> 4) & 0x3f; in qla4_82xx_start_firmware()
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| /linux/drivers/net/ethernet/myricom/myri10ge/ |
| H A D | myri10ge.c | 3220 int link_width; in myri10ge_select_firmware() local
3224 link_width = (lnk >> 4) & 0x3f; in myri10ge_select_firmware()
3229 if (link_width < 8) { in myri10ge_select_firmware()
3231 link_width); in myri10ge_select_firmware()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_device.c | 5914 enum pcie_link_width platform_link_width, link_width; in amdgpu_device_get_pcie_info() local
5936 amdgpu_device_gpu_bandwidth(adev, &speed_cap, &link_width); in amdgpu_device_get_pcie_info()
5996 if (link_width == PCIE_LNK_WIDTH_UNKNOWN) { in amdgpu_device_get_pcie_info()
5999 switch (link_width) { in amdgpu_device_get_pcie_info()
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| /linux/drivers/thunderbolt/ |
| H A D | icm.c | 884 sw->link_width = dual_lane ? TB_LINK_WIDTH_DUAL : in icm_fr_device_connected()
1318 sw->link_width = dual_lane ? TB_LINK_WIDTH_DUAL : in __icm_tr_device_connected()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_hwmgr.c | 225 uint32_t link_width; in smu7_get_current_pcie_lane_number() local
228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
231 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()
234 return decode_pcie_lane_width(link_width); in smu7_get_current_pcie_lane_number()
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| H A D | vega12_hwmgr.c | 54 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
2236 return link_width[width_level]; in vega12_get_current_pcie_link_width()
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| H A D | vega20_hwmgr.c | 59 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
3327 return link_width[width_level]; in vega20_get_current_pcie_link_width()
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | ci_dpm.c | 4778 u32 link_width = 0; in ci_get_current_pcie_lane_number() local
4780 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()
4781 link_width >>= LC_LINK_WIDTH_RD_SHIFT; in ci_get_current_pcie_lane_number()
4783 switch (link_width) { in ci_get_current_pcie_lane_number()
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