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Searched refs:lane_width (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h97 uint8_t lane_width; member
H A Dvega20_hwmgr.c3365 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_emit_clock_levels()
3479 lane_width = pptable->PcieLaneCount[i]; in vega20_emit_clock_levels()
3488 (lane_width == 1) ? "x1" : in vega20_emit_clock_levels()
3489 (lane_width == 2) ? "x2" : in vega20_emit_clock_levels()
3490 (lane_width == 3) ? "x4" : in vega20_emit_clock_levels()
3491 (lane_width == 4) ? "x8" : in vega20_emit_clock_levels()
3492 (lane_width == 5) ? "x12" : in vega20_emit_clock_levels()
3493 (lane_width == 6) ? "x16" : in vega20_emit_clock_levels()
3498 lane_width) ? in vega20_emit_clock_levels()
3381 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; vega20_emit_clock_levels() local
H A Dvega10_hwmgr.c1281 bios_pcie_table->entries[i].lane_width); in vega10_setup_default_pcie_table()
4673 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_get_current_pcie_link_speed_level()
4747 lane_width = pptable->PcieLaneCount[i]; in vega10_emit_clock_levels()
4754 (lane_width == 1) ? "x1" : in vega10_emit_clock_levels()
4755 (lane_width == 2) ? "x2" : in vega10_emit_clock_levels()
4756 (lane_width == 3) ? "x4" : in vega10_emit_clock_levels()
4757 (lane_width == 4) ? "x8" : in vega10_emit_clock_levels()
4758 (lane_width == 5) ? "x12" : in vega10_emit_clock_levels()
4759 (lane_width == 6) ? "x16" : "", in vega10_emit_clock_levels()
4761 (current_lane_width == lane_width) in vega10_emit_clock_levels()
4690 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; vega10_emit_clock_levels() local
[all...]
H A Dprocess_pptables_v1_0.c517 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
554 pcie_record->lane_width = le16_to_cpu(atom_pcie_record->usPCIELaneWidth); in get_pcie_table()
H A Dvega10_processpptables.c814 pcie_table->entries[i].lane_width = in get_pcie_table()
H A Dsmu7_hwmgr.c677 pcie_table->entries[i].lane_width)); in smu7_setup_default_pcie_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c1221 uint32_t gen_speed, lane_width; in smu_v13_0_7_emit_clk_levels() local
1263 &lane_width); in smu_v13_0_7_emit_clk_levels()
1270 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v13_0_7_emit_clk_levels()
H A Dsmu_v13_0_0_ppt.c1211 uint32_t gen_speed, lane_width; in smu_v13_0_0_emit_clk_levels() local
1253 &lane_width); in smu_v13_0_0_emit_clk_levels()
1260 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v13_0_0_emit_clk_levels()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c1041 uint32_t gen_speed, lane_width; in smu_v14_0_2_emit_clk_levels() local
1084 &lane_width); in smu_v14_0_2_emit_clk_levels()
1091 SMU_DPM_PCIE_WIDTH_IDX(lane_width), in smu_v14_0_2_emit_clk_levels()
/linux/drivers/gpu/drm/radeon/
H A Dsi_dpm.c4644 u32 lane_width; in si_init_smc_table() local
4715 lane_width = radeon_get_pcie_lanes(rdev); in si_init_smc_table()
4716 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
5861 u32 lane_width; in si_set_pcie_lane_width_in_smc() local
5869 lane_width = radeon_get_pcie_lanes(rdev); in si_set_pcie_lane_width_in_smc()
5870 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c5245 u32 lane_width; in si_init_smc_table()
5316 lane_width = amdgpu_get_pcie_lanes(adev); in si_init_smc_table()
5317 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_init_smc_table()
6446 u32 lane_width; in si_set_pcie_lane_width_in_smc()
6454 lane_width = amdgpu_get_pcie_lanes(adev); in si_set_pcie_lane_width_in_smc()
6455 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); in si_set_pcie_lane_width_in_smc()
5243 u32 lane_width; si_init_smc_table() local
6444 u32 lane_width; si_set_pcie_lane_width_in_smc() local