1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef KFD_PRIV_H_INCLUDED
25 #define KFD_PRIV_H_INCLUDED
26
27 #include <linux/hashtable.h>
28 #include <linux/mmu_notifier.h>
29 #include <linux/memremap.h>
30 #include <linux/mutex.h>
31 #include <linux/types.h>
32 #include <linux/atomic.h>
33 #include <linux/workqueue.h>
34 #include <linux/spinlock.h>
35 #include <uapi/linux/kfd_ioctl.h>
36 #include <linux/idr.h>
37 #include <linux/kfifo.h>
38 #include <linux/seq_file.h>
39 #include <linux/kref.h>
40 #include <linux/sysfs.h>
41 #include <linux/device_cgroup.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_drv.h>
44 #include <drm/drm_device.h>
45 #include <drm/drm_ioctl.h>
46 #include <kgd_kfd_interface.h>
47 #include <linux/swap.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu.h"
51
52 #define KFD_MAX_RING_ENTRY_SIZE 8
53
54 #define KFD_SYSFS_FILE_MODE 0444
55
56 /* GPU ID hash width in bits */
57 #define KFD_GPU_ID_HASH_WIDTH 16
58
59 /* Use upper bits of mmap offset to store KFD driver specific information.
60 * BITS[63:62] - Encode MMAP type
61 * BITS[61:46] - Encode gpu_id. To identify to which GPU the offset belongs to
62 * BITS[45:0] - MMAP offset value
63 *
64 * NOTE: struct vm_area_struct.vm_pgoff uses offset in pages. Hence, these
65 * defines are w.r.t to PAGE_SIZE
66 */
67 #define KFD_MMAP_TYPE_SHIFT 62
68 #define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT)
69 #define KFD_MMAP_TYPE_DOORBELL (0x3ULL << KFD_MMAP_TYPE_SHIFT)
70 #define KFD_MMAP_TYPE_EVENTS (0x2ULL << KFD_MMAP_TYPE_SHIFT)
71 #define KFD_MMAP_TYPE_RESERVED_MEM (0x1ULL << KFD_MMAP_TYPE_SHIFT)
72 #define KFD_MMAP_TYPE_MMIO (0x0ULL << KFD_MMAP_TYPE_SHIFT)
73
74 #define KFD_MMAP_GPU_ID_SHIFT 46
75 #define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
76 << KFD_MMAP_GPU_ID_SHIFT)
77 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
78 & KFD_MMAP_GPU_ID_MASK)
79 #define KFD_MMAP_GET_GPU_ID(offset) ((offset & KFD_MMAP_GPU_ID_MASK) \
80 >> KFD_MMAP_GPU_ID_SHIFT)
81
82 /*
83 * When working with cp scheduler we should assign the HIQ manually or via
84 * the amdgpu driver to a fixed hqd slot, here are the fixed HIQ hqd slot
85 * definitions for Kaveri. In Kaveri only the first ME queues participates
86 * in the cp scheduling taking that in mind we set the HIQ slot in the
87 * second ME.
88 */
89 #define KFD_CIK_HIQ_PIPE 4
90 #define KFD_CIK_HIQ_QUEUE 0
91
92 /* Macro for allocating structures */
93 #define kfd_alloc_struct(ptr_to_struct) \
94 ((typeof(ptr_to_struct)) kzalloc_obj(*ptr_to_struct))
95
96 #define KFD_MAX_NUM_OF_PROCESSES 512
97 #define KFD_MAX_NUM_OF_QUEUES_PER_PROCESS 1024
98
99 /*
100 * Size of the per-process TBA+TMA buffer: 2 pages
101 *
102 * The first chunk is the TBA used for the CWSR ISA code. The second
103 * chunk is used as TMA for user-mode trap handler setup in daisy-chain mode.
104 */
105 #define KFD_CWSR_TBA_TMA_SIZE (AMDGPU_GPU_PAGE_SIZE * 2)
106 #define KFD_CWSR_TMA_OFFSET (AMDGPU_GPU_PAGE_SIZE + 2048)
107
108 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE \
109 (KFD_MAX_NUM_OF_PROCESSES * \
110 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
111
112 #define KFD_KERNEL_QUEUE_SIZE 2048
113
114 /* KFD_UNMAP_LATENCY_MS is the timeout CP waiting for SDMA preemption. One XCC
115 * can be associated to 2 SDMA engines. queue_preemption_timeout_ms is the time
116 * driver waiting for CP returning the UNMAP_QUEUE fence. Thus the math is
117 * queue_preemption_timeout_ms = sdma_preemption_time * 2 + cp workload
118 * The format here makes CP workload 10% of total timeout
119 */
120 #define KFD_UNMAP_LATENCY_MS \
121 ((queue_preemption_timeout_ms - queue_preemption_timeout_ms / 10) >> 1)
122
123 #define KFD_MAX_SDMA_QUEUES 128
124
125 /*
126 * 512 = 0x200
127 * The doorbell index distance between SDMA RLC (2*i) and (2*i+1) in the
128 * same SDMA engine on SOC15, which has 8-byte doorbells for SDMA.
129 * 512 8-byte doorbell distance (i.e. one page away) ensures that SDMA RLC
130 * (2*i+1) doorbells (in terms of the lower 12 bit address) lie exactly in
131 * the OFFSET and SIZE set in registers like BIF_SDMA0_DOORBELL_RANGE.
132 */
133 #define KFD_QUEUE_DOORBELL_MIRROR_OFFSET 512
134
135 /**
136 * enum kfd_ioctl_flags - KFD ioctl flags
137 * Various flags that can be set in &amdkfd_ioctl_desc.flags to control how
138 * userspace can use a given ioctl.
139 */
140 enum kfd_ioctl_flags {
141 /*
142 * @KFD_IOC_FLAG_CHECKPOINT_RESTORE:
143 * Certain KFD ioctls such as AMDKFD_IOC_CRIU_OP can potentially
144 * perform privileged operations and load arbitrary data into MQDs and
145 * eventually HQD registers when the queue is mapped by HWS. In order to
146 * prevent this we should perform additional security checks.
147 *
148 * This is equivalent to callers with the CHECKPOINT_RESTORE capability.
149 *
150 * Note: Since earlier versions of docker do not support CHECKPOINT_RESTORE,
151 * we also allow ioctls with SYS_ADMIN capability.
152 */
153 KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0),
154 };
155 /*
156 * Kernel module parameter to specify maximum number of supported queues per
157 * device
158 */
159 extern int max_num_of_queues_per_device;
160
161
162 /* Kernel module parameter to specify the scheduling policy */
163 extern int sched_policy;
164
165 /*
166 * Kernel module parameter to specify the maximum process
167 * number per HW scheduler
168 */
169 extern int hws_max_conc_proc;
170
171 extern int cwsr_enable;
172
173 /*
174 * Kernel module parameter to specify whether to send sigterm to HSA process on
175 * unhandled exception
176 */
177 extern int send_sigterm;
178
179 /*
180 * This kernel module is used to simulate large bar machine on non-large bar
181 * enabled machines.
182 */
183 extern int debug_largebar;
184
185 /* Set sh_mem_config.retry_disable on GFX v9 */
186 extern int amdgpu_noretry;
187
188 /* Halt if HWS hang is detected */
189 extern int halt_if_hws_hang;
190
191 /* Whether MEC FW support GWS barriers */
192 extern bool hws_gws_support;
193
194 /* Queue preemption timeout in ms */
195 extern int queue_preemption_timeout_ms;
196
197 /*
198 * Don't evict process queues on vm fault
199 */
200 extern int amdgpu_no_queue_eviction_on_vm_fault;
201
202 /* Enable eviction debug messages */
203 extern bool debug_evictions;
204
205 extern struct mutex kfd_processes_mutex;
206
207 enum cache_policy {
208 cache_policy_coherent,
209 cache_policy_noncoherent
210 };
211
212 #define KFD_GC_VERSION(dev) (amdgpu_ip_version((dev)->adev, GC_HWIP, 0))
213 #define KFD_IS_SOC15(dev) ((KFD_GC_VERSION(dev)) >= (IP_VERSION(9, 0, 1)))
214 #define KFD_SUPPORT_XNACK_PER_PROCESS(dev)\
215 ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \
216 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \
217 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \
218 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) || \
219 (KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0)))
220
221 struct kfd_node;
222
223 struct kfd_event_interrupt_class {
224 bool (*interrupt_isr)(struct kfd_node *dev,
225 const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
226 bool *patched_flag);
227 void (*interrupt_wq)(struct kfd_node *dev,
228 const uint32_t *ih_ring_entry);
229 };
230
231 struct kfd_device_info {
232 uint32_t gfx_target_version;
233 const struct kfd_event_interrupt_class *event_interrupt_class;
234 unsigned int max_pasid_bits;
235 unsigned int max_no_of_hqd;
236 unsigned int doorbell_size;
237 size_t ih_ring_entry_size;
238 uint8_t num_of_watch_points;
239 uint16_t mqd_size_aligned;
240 bool supports_cwsr;
241 bool needs_pci_atomics;
242 uint32_t no_atomic_fw_version;
243 unsigned int num_sdma_queues_per_engine;
244 unsigned int num_reserved_sdma_queues_per_engine;
245 };
246
247 unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
248 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev);
249
250 struct kfd_mem_obj {
251 uint32_t range_start;
252 uint32_t range_end;
253 uint64_t gpu_addr;
254 uint32_t *cpu_ptr;
255 void *mem;
256 };
257
258 struct kfd_vmid_info {
259 uint32_t first_vmid_kfd;
260 uint32_t last_vmid_kfd;
261 uint32_t vmid_num_kfd;
262 };
263
264 #define MAX_KFD_NODES 8
265
266 struct kfd_dev;
267
268 struct kfd_node {
269 unsigned int node_id;
270 struct amdgpu_device *adev; /* Duplicated here along with keeping
271 * a copy in kfd_dev to save a hop
272 */
273 const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with
274 * keeping a copy in kfd_dev to
275 * save a hop
276 */
277 struct kfd_vmid_info vm_info;
278 unsigned int id; /* topology stub index */
279 uint32_t xcc_mask; /* Instance mask of XCCs present */
280 struct amdgpu_xcp *xcp;
281
282 /* Interrupts */
283 struct kfifo ih_fifo;
284 struct work_struct interrupt_work;
285 spinlock_t interrupt_lock;
286
287 /*
288 * Interrupts of interest to KFD are copied
289 * from the HW ring into a SW ring.
290 */
291 bool interrupts_active;
292 uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */
293
294 /* QCM Device instance */
295 struct device_queue_manager *dqm;
296
297 /* Global GWS resource shared between processes */
298 void *gws;
299
300 /* Clients watching SMI events */
301 struct list_head smi_clients;
302 spinlock_t smi_lock;
303 uint32_t reset_seq_num;
304
305 /* SRAM ECC flag */
306 atomic_t sram_ecc_flag;
307
308 /*spm process id */
309 unsigned int spm_pasid;
310
311 /* Maximum process number mapped to HW scheduler */
312 unsigned int max_proc_per_quantum;
313
314 unsigned int compute_vmid_bitmap;
315
316 struct kfd_local_mem_info local_mem_info;
317
318 struct kfd_dev *kfd;
319
320 /* Track per device allocated watch points */
321 uint32_t alloc_watch_ids;
322 spinlock_t watch_points_lock;
323 };
324
325 struct kfd_dev {
326 struct amdgpu_device *adev;
327
328 struct kfd_device_info device_info;
329
330 u32 __iomem *doorbell_kernel_ptr; /* This is a pointer for a doorbells
331 * page used by kernel queue
332 */
333
334 struct kgd2kfd_shared_resources shared_resources;
335
336 const struct kfd2kgd_calls *kfd2kgd;
337 struct mutex doorbell_mutex;
338
339 void *gtt_mem;
340 uint64_t gtt_start_gpu_addr;
341 void *gtt_start_cpu_ptr;
342 void *gtt_sa_bitmap;
343 struct mutex gtt_sa_lock;
344 unsigned int gtt_sa_chunk_size;
345 unsigned int gtt_sa_num_of_chunks;
346
347 bool init_complete;
348
349 /* Firmware versions */
350 uint16_t mec_fw_version;
351 uint16_t mec2_fw_version;
352 uint16_t sdma_fw_version;
353
354 /* CWSR */
355 bool cwsr_enabled;
356 const void *cwsr_isa;
357 unsigned int cwsr_isa_size;
358
359 /* xGMI */
360 uint64_t hive_id;
361
362 bool pci_atomic_requested;
363
364 /* Compute Profile ref. count */
365 atomic_t compute_profile;
366
367 struct ida doorbell_ida;
368 unsigned int max_doorbell_slices;
369
370 int noretry;
371
372 struct kfd_node *nodes[MAX_KFD_NODES];
373 unsigned int num_nodes;
374
375 struct workqueue_struct *ih_wq;
376
377 /* Kernel doorbells for KFD device */
378 struct amdgpu_bo *doorbells;
379
380 /* bitmap for dynamic doorbell allocation from doorbell object */
381 unsigned long *doorbell_bitmap;
382
383 /* for dynamic partitioning */
384 int kfd_dev_lock;
385
386 atomic_t kfd_processes_count;
387 };
388
389 enum kfd_mempool {
390 KFD_MEMPOOL_SYSTEM_CACHEABLE = 1,
391 KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2,
392 KFD_MEMPOOL_FRAMEBUFFER = 3,
393 };
394
395 /* Character device interface */
396 int kfd_chardev_init(void);
397 void kfd_chardev_exit(void);
398 void kfd_dev_unmap_mapping_range(loff_t const holebegin, loff_t const holelen);
399
400 /**
401 * enum kfd_unmap_queues_filter - Enum for queue filters.
402 *
403 * @KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES: Preempts all queues in the
404 * running queues list.
405 *
406 * @KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES: Preempts all non-static queues
407 * in the run list.
408 *
409 * @KFD_UNMAP_QUEUES_FILTER_BY_PASID: Preempts queues that belongs to
410 * specific process.
411 *
412 */
413 enum kfd_unmap_queues_filter {
414 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES = 1,
415 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES = 2,
416 KFD_UNMAP_QUEUES_FILTER_BY_PASID = 3
417 };
418
419 /**
420 * enum kfd_queue_type - Enum for various queue types.
421 *
422 * @KFD_QUEUE_TYPE_COMPUTE: Regular user mode queue type.
423 *
424 * @KFD_QUEUE_TYPE_SDMA: SDMA user mode queue type.
425 *
426 * @KFD_QUEUE_TYPE_HIQ: HIQ queue type.
427 *
428 * @KFD_QUEUE_TYPE_DIQ: DIQ queue type.
429 *
430 * @KFD_QUEUE_TYPE_SDMA_XGMI: Special SDMA queue for XGMI interface.
431 *
432 * @KFD_QUEUE_TYPE_SDMA_BY_ENG_ID: SDMA user mode queue with target SDMA engine ID.
433 */
434 enum kfd_queue_type {
435 KFD_QUEUE_TYPE_COMPUTE,
436 KFD_QUEUE_TYPE_SDMA,
437 KFD_QUEUE_TYPE_HIQ,
438 KFD_QUEUE_TYPE_SDMA_XGMI,
439 KFD_QUEUE_TYPE_SDMA_BY_ENG_ID
440 };
441
442 enum kfd_queue_format {
443 KFD_QUEUE_FORMAT_PM4,
444 KFD_QUEUE_FORMAT_AQL
445 };
446
447 enum KFD_QUEUE_PRIORITY {
448 KFD_QUEUE_PRIORITY_MINIMUM = 0,
449 KFD_QUEUE_PRIORITY_MAXIMUM = 15
450 };
451
452 /**
453 * struct queue_properties
454 *
455 * @type: The queue type.
456 *
457 * @queue_id: Queue identifier.
458 *
459 * @queue_address: Queue ring buffer address.
460 *
461 * @queue_size: Queue ring buffer size.
462 *
463 * @priority: Defines the queue priority relative to other queues in the
464 * process.
465 * This is just an indication and HW scheduling may override the priority as
466 * necessary while keeping the relative prioritization.
467 * the priority granularity is from 0 to f which f is the highest priority.
468 * currently all queues are initialized with the highest priority.
469 *
470 * @queue_percent: This field is partially implemented and currently a zero in
471 * this field defines that the queue is non active.
472 *
473 * @read_ptr: User space address which points to the number of dwords the
474 * cp read from the ring buffer. This field updates automatically by the H/W.
475 *
476 * @write_ptr: Defines the number of dwords written to the ring buffer.
477 *
478 * @doorbell_ptr: Notifies the H/W of new packet written to the queue ring
479 * buffer. This field should be similar to write_ptr and the user should
480 * update this field after updating the write_ptr.
481 *
482 * @doorbell_off: The doorbell offset in the doorbell pci-bar.
483 *
484 * @is_interop: Defines if this is a interop queue. Interop queue means that
485 * the queue can access both graphics and compute resources.
486 *
487 * @is_evicted: Defines if the queue is evicted. Only active queues
488 * are evicted, rendering them inactive.
489 *
490 * @is_active: Defines if the queue is active or not. @is_active and
491 * @is_evicted are protected by the DQM lock.
492 *
493 * @is_gws: Defines if the queue has been updated to be GWS-capable or not.
494 * @is_gws should be protected by the DQM lock, since changing it can yield the
495 * possibility of updating DQM state on number of GWS queues.
496 *
497 * @vmid: If the scheduling mode is no cp scheduling the field defines the vmid
498 * of the queue.
499 *
500 * This structure represents the queue properties for each queue no matter if
501 * it's user mode or kernel mode queue.
502 *
503 */
504
505 struct queue_properties {
506 enum kfd_queue_type type;
507 enum kfd_queue_format format;
508 unsigned int queue_id;
509 uint64_t queue_address;
510 uint64_t queue_size;
511 uint64_t metadata_queue_size;
512 uint32_t priority;
513 uint32_t queue_percent;
514 void __user *read_ptr;
515 void __user *write_ptr;
516 void __iomem *doorbell_ptr;
517 uint32_t doorbell_off;
518 bool is_interop;
519 bool is_evicted;
520 bool is_suspended;
521 bool is_being_destroyed;
522 bool is_active;
523 bool is_gws;
524 uint32_t pm4_target_xcc;
525 bool is_dbg_wa;
526 bool is_user_cu_masked;
527 /* Not relevant for user mode queues in cp scheduling */
528 unsigned int vmid;
529 /* Relevant only for sdma queues*/
530 uint32_t sdma_engine_id;
531 uint32_t sdma_queue_id;
532 uint32_t sdma_vm_addr;
533 /* Relevant only for VI */
534 uint64_t eop_ring_buffer_address;
535 uint32_t eop_ring_buffer_size;
536 uint64_t ctx_save_restore_area_address;
537 uint32_t ctx_save_restore_area_size;
538 uint32_t ctl_stack_size;
539 uint64_t tba_addr;
540 uint64_t tma_addr;
541 uint64_t exception_status;
542
543 struct amdgpu_bo *wptr_bo;
544 struct amdgpu_bo *rptr_bo;
545 struct amdgpu_bo *ring_bo;
546 struct amdgpu_bo *eop_buf_bo;
547 struct amdgpu_bo *cwsr_bo;
548 };
549
550 #define QUEUE_IS_ACTIVE(q) ((q).queue_size > 0 && \
551 (q).queue_address != 0 && \
552 (q).queue_percent > 0 && \
553 !(q).is_evicted && \
554 !(q).is_suspended)
555
556 enum mqd_update_flag {
557 UPDATE_FLAG_DBG_WA_ENABLE = 1,
558 UPDATE_FLAG_DBG_WA_DISABLE = 2,
559 UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */
560 };
561
562 struct mqd_update_info {
563 union {
564 struct {
565 uint32_t count; /* Must be a multiple of 32 */
566 uint32_t *ptr;
567 } cu_mask;
568 };
569 enum mqd_update_flag update_flag;
570 };
571
572 /**
573 * struct queue
574 *
575 * @list: Queue linked list.
576 *
577 * @mqd: The queue MQD (memory queue descriptor).
578 *
579 * @mqd_mem_obj: The MQD local gpu memory object.
580 *
581 * @gart_mqd_addr: The MQD gart mc address.
582 *
583 * @properties: The queue properties.
584 *
585 * @mec: Used only in no cp scheduling mode and identifies to micro engine id
586 * that the queue should be executed on.
587 *
588 * @pipe: Used only in no cp scheduling mode and identifies the queue's pipe
589 * id.
590 *
591 * @queue: Used only in no cp scheduliong mode and identifies the queue's slot.
592 *
593 * @process: The kfd process that created this queue.
594 *
595 * @device: The kfd device that created this queue.
596 *
597 * @gws: Pointing to gws kgd_mem if this is a gws control queue; NULL
598 * otherwise.
599 *
600 * This structure represents user mode compute queues.
601 * It contains all the necessary data to handle such queues.
602 *
603 */
604
605 struct queue {
606 struct list_head list;
607 void *mqd;
608 struct kfd_mem_obj *mqd_mem_obj;
609 uint64_t gart_mqd_addr;
610 struct queue_properties properties;
611
612 uint32_t mec;
613 uint32_t pipe;
614 uint32_t queue;
615
616 unsigned int sdma_id;
617 unsigned int doorbell_id;
618
619 struct kfd_process *process;
620 struct kfd_node *device;
621 void *gws;
622
623 /* procfs */
624 struct kobject kobj;
625
626 void *gang_ctx_bo;
627 uint64_t gang_ctx_gpu_addr;
628 void *gang_ctx_cpu_ptr;
629
630 struct amdgpu_bo *wptr_bo_gart;
631 };
632
633 enum KFD_MQD_TYPE {
634 KFD_MQD_TYPE_HIQ = 0, /* for hiq */
635 KFD_MQD_TYPE_CP, /* for cp queues and diq */
636 KFD_MQD_TYPE_SDMA, /* for sdma queues */
637 KFD_MQD_TYPE_DIQ, /* for diq */
638 KFD_MQD_TYPE_MAX
639 };
640
641 enum KFD_PIPE_PRIORITY {
642 KFD_PIPE_PRIORITY_CS_LOW = 0,
643 KFD_PIPE_PRIORITY_CS_MEDIUM,
644 KFD_PIPE_PRIORITY_CS_HIGH
645 };
646
647 struct scheduling_resources {
648 unsigned int vmid_mask;
649 enum kfd_queue_type type;
650 uint64_t queue_mask;
651 uint64_t gws_mask;
652 uint32_t oac_mask;
653 uint32_t gds_heap_base;
654 uint32_t gds_heap_size;
655 };
656
657 struct process_queue_manager {
658 /* data */
659 struct kfd_process *process;
660 struct list_head queues;
661 unsigned long *queue_slot_bitmap;
662 };
663
664 struct qcm_process_device {
665 /* The Device Queue Manager that owns this data */
666 struct device_queue_manager *dqm;
667 struct process_queue_manager *pqm;
668 /* Queues list */
669 struct list_head queues_list;
670 struct list_head priv_queue_list;
671
672 unsigned int queue_count;
673 unsigned int vmid;
674 bool is_debug;
675 unsigned int evicted; /* eviction counter, 0=active */
676
677 /* This flag tells if we should reset all wavefronts on
678 * process termination
679 */
680 bool reset_wavefronts;
681
682 /* This flag tells us if this process has a GWS-capable
683 * queue that will be mapped into the runlist. It's
684 * possible to request a GWS BO, but not have the queue
685 * currently mapped, and this changes how the MAP_PROCESS
686 * PM4 packet is configured.
687 */
688 bool mapped_gws_queue;
689
690 /* All the memory management data should be here too */
691 uint64_t gds_context_area;
692 /* Contains page table flags such as AMDGPU_PTE_VALID since gfx9 */
693 uint64_t page_table_base;
694 uint32_t sh_mem_config;
695 uint32_t sh_mem_bases;
696 uint32_t sh_mem_ape1_base;
697 uint32_t sh_mem_ape1_limit;
698 uint32_t gds_size;
699 uint32_t num_gws;
700 uint32_t num_oac;
701 uint32_t sh_hidden_private_base;
702 uint32_t vm_cntx_cntl;
703
704 /* CWSR memory */
705 struct kgd_mem *cwsr_mem;
706 void *cwsr_kaddr;
707 uint64_t cwsr_base;
708 uint64_t tba_addr;
709 uint64_t tma_addr;
710
711 /* IB memory */
712 struct kgd_mem *ib_mem;
713 uint64_t ib_base;
714 void *ib_kaddr;
715
716 /* doorbells for kfd process */
717 struct amdgpu_bo *proc_doorbells;
718
719 /* bitmap for dynamic doorbell allocation from the bo */
720 unsigned long *doorbell_bitmap;
721 };
722
723 /* KFD Memory Eviction */
724
725 /* Approx. wait time before attempting to restore evicted BOs */
726 #define PROCESS_RESTORE_TIME_MS 100
727 /* Approx. back off time if restore fails due to lack of memory */
728 #define PROCESS_BACK_OFF_TIME_MS 100
729 /* Approx. time before evicting the process again */
730 #define PROCESS_ACTIVE_TIME_MS 10
731
732 /* 8 byte handle containing GPU ID in the most significant 4 bytes and
733 * idr_handle in the least significant 4 bytes
734 */
735 #define MAKE_HANDLE(gpu_id, idr_handle) \
736 (((uint64_t)(gpu_id) << 32) + idr_handle)
737 #define GET_GPU_ID(handle) (handle >> 32)
738 #define GET_IDR_HANDLE(handle) (handle & 0xFFFFFFFF)
739
740 enum kfd_pdd_bound {
741 PDD_UNBOUND = 0,
742 PDD_BOUND,
743 PDD_BOUND_SUSPENDED,
744 };
745
746 #define MAX_SYSFS_FILENAME_LEN 15
747
748 /*
749 * SDMA counter runs at 100MHz frequency.
750 * We display SDMA activity in microsecond granularity in sysfs.
751 * As a result, the divisor is 100.
752 */
753 #define SDMA_ACTIVITY_DIVISOR 100
754
755 /* Data that is per-process-per device. */
756 struct kfd_process_device {
757 /* The device that owns this data. */
758 struct kfd_node *dev;
759
760 /* The process that owns this kfd_process_device. */
761 struct kfd_process *process;
762
763 /* per-process-per device QCM data structure */
764 struct qcm_process_device qpd;
765
766 /*Apertures*/
767 uint64_t lds_base;
768 uint64_t lds_limit;
769 uint64_t gpuvm_base;
770 uint64_t gpuvm_limit;
771 uint64_t scratch_base;
772 uint64_t scratch_limit;
773
774 /* VM context for GPUVM allocations */
775 struct file *drm_file;
776 void *drm_priv;
777
778 /* GPUVM allocations storage */
779 struct idr alloc_idr;
780
781 /* Flag used to tell the pdd has dequeued from the dqm.
782 * This is used to prevent dev->dqm->ops.process_termination() from
783 * being called twice when it is already called in IOMMU callback
784 * function.
785 */
786 bool already_dequeued;
787 bool runtime_inuse;
788
789 /* Is this process/pasid bound to this device? (amd_iommu_bind_pasid) */
790 enum kfd_pdd_bound bound;
791
792 /* VRAM usage */
793 atomic64_t vram_usage;
794 struct attribute attr_vram;
795 char vram_filename[MAX_SYSFS_FILENAME_LEN];
796
797 /* SDMA activity tracking */
798 uint64_t sdma_past_activity_counter;
799 struct attribute attr_sdma;
800 char sdma_filename[MAX_SYSFS_FILENAME_LEN];
801
802 /* Eviction activity tracking */
803 uint64_t last_evict_timestamp;
804 atomic64_t evict_duration_counter;
805 struct attribute attr_evict;
806
807 struct kobject *kobj_stats;
808
809 /*
810 * @cu_occupancy: Reports occupancy of Compute Units (CU) of a process
811 * that is associated with device encoded by "this" struct instance. The
812 * value reflects CU usage by all of the waves launched by this process
813 * on this device. A very important property of occupancy parameter is
814 * that its value is a snapshot of current use.
815 *
816 * Following is to be noted regarding how this parameter is reported:
817 *
818 * The number of waves that a CU can launch is limited by couple of
819 * parameters. These are encoded by struct amdgpu_cu_info instance
820 * that is part of every device definition. For GFX9 devices this
821 * translates to 40 waves (simd_per_cu * max_waves_per_simd) when waves
822 * do not use scratch memory and 32 waves (max_scratch_slots_per_cu)
823 * when they do use scratch memory. This could change for future
824 * devices and therefore this example should be considered as a guide.
825 *
826 * All CU's of a device are available for the process. This may not be true
827 * under certain conditions - e.g. CU masking.
828 *
829 * Finally number of CU's that are occupied by a process is affected by both
830 * number of CU's a device has along with number of other competing processes
831 */
832 struct attribute attr_cu_occupancy;
833
834 /* sysfs counters for GPU retry fault and page migration tracking */
835 struct kobject *kobj_counters;
836 struct attribute attr_faults;
837 struct attribute attr_page_in;
838 struct attribute attr_page_out;
839 uint64_t faults;
840 uint64_t page_in;
841 uint64_t page_out;
842
843 /* Exception code status*/
844 uint64_t exception_status;
845 void *vm_fault_exc_data;
846 size_t vm_fault_exc_data_size;
847
848 /* Tracks debug per-vmid request settings */
849 uint32_t spi_dbg_override;
850 uint32_t spi_dbg_launch_mode;
851 uint32_t watch_points[4];
852 uint32_t alloc_watch_ids;
853
854 /*
855 * If this process has been checkpointed before, then the user
856 * application will use the original gpu_id on the
857 * checkpointed node to refer to this device.
858 */
859 uint32_t user_gpu_id;
860
861 void *proc_ctx_bo;
862 uint64_t proc_ctx_gpu_addr;
863 void *proc_ctx_cpu_ptr;
864
865 /* Tracks queue reset status */
866 bool has_reset_queue;
867
868 u32 pasid;
869 };
870
871 #define qpd_to_pdd(x) container_of(x, struct kfd_process_device, qpd)
872
873 struct svm_range_list {
874 struct mutex lock;
875 struct rb_root_cached objects;
876 struct list_head list;
877 struct work_struct deferred_list_work;
878 struct list_head deferred_range_list;
879 struct list_head criu_svm_metadata_list;
880 spinlock_t deferred_list_lock;
881 atomic_t evicted_ranges;
882 atomic_t drain_pagefaults;
883 struct delayed_work restore_work;
884 DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
885 struct task_struct *faulting_task;
886 /* check point ts decides if page fault recovery need be dropped */
887 uint64_t checkpoint_ts[MAX_GPU_INSTANCE];
888
889 /* Default granularity to use in buffer migration
890 * and restoration of backing memory while handling
891 * recoverable page faults
892 */
893 uint8_t default_granularity;
894 };
895
896 /* Process data */
897 struct kfd_process {
898 /*
899 * kfd_process are stored in an mm_struct*->kfd_process*
900 * hash table (kfd_processes in kfd_process.c)
901 */
902 struct hlist_node kfd_processes;
903
904 /*
905 * Opaque pointer to mm_struct. We don't hold a reference to
906 * it so it should never be dereferenced from here. This is
907 * only used for looking up processes by their mm.
908 */
909 void *mm;
910
911 struct kref ref;
912 struct work_struct release_work;
913
914 struct mutex mutex;
915
916 /*
917 * In any process, the thread that started main() is the lead
918 * thread and outlives the rest.
919 * It is here because amd_iommu_bind_pasid wants a task_struct.
920 * It can also be used for safely getting a reference to the
921 * mm_struct of the process.
922 */
923 struct task_struct *lead_thread;
924
925 /* We want to receive a notification when the mm_struct is destroyed */
926 struct mmu_notifier mmu_notifier;
927
928 /*
929 * Array of kfd_process_device pointers,
930 * one for each device the process is using.
931 */
932 struct kfd_process_device *pdds[MAX_GPU_INSTANCE];
933 uint32_t n_pdds;
934
935 struct process_queue_manager pqm;
936
937 /*Is the user space process 32 bit?*/
938 bool is_32bit_user_mode;
939
940 /* Event-related data */
941 struct mutex event_mutex;
942 /* Event ID allocator and lookup */
943 struct idr event_idr;
944 /* Event page */
945 u64 signal_handle;
946 struct kfd_signal_page *signal_page;
947 size_t signal_mapped_size;
948 size_t signal_event_count;
949 bool signal_event_limit_reached;
950
951 /* Information used for memory eviction */
952 void *kgd_process_info;
953 /* Eviction fence that is attached to all the BOs of this process. The
954 * fence will be triggered during eviction and new one will be created
955 * during restore
956 */
957 struct dma_fence __rcu *ef;
958
959 /* Work items for evicting and restoring BOs */
960 struct delayed_work eviction_work;
961 struct delayed_work restore_work;
962 /* seqno of the last scheduled eviction */
963 unsigned int last_eviction_seqno;
964 /* Approx. the last timestamp (in jiffies) when the process was
965 * restored after an eviction
966 */
967 unsigned long last_restore_timestamp;
968
969 /* Indicates device process is debug attached with reserved vmid. */
970 bool debug_trap_enabled;
971
972 /* per-process-per device debug event fd file */
973 struct file *dbg_ev_file;
974
975 /* If the process is a kfd debugger, we need to know so we can clean
976 * up at exit time. If a process enables debugging on itself, it does
977 * its own clean-up, so we don't set the flag here. We track this by
978 * counting the number of processes this process is debugging.
979 */
980 atomic_t debugged_process_count;
981
982 /* If the process is a debugged, this is the debugger process */
983 struct kfd_process *debugger_process;
984
985 /* Kobj for our procfs */
986 struct kobject *kobj;
987 struct kobject *kobj_queues;
988 struct attribute attr_pasid;
989
990 /* Keep track cwsr init */
991 bool has_cwsr;
992
993 /* Exception code enable mask and status */
994 uint64_t exception_enable_mask;
995 uint64_t exception_status;
996
997 /* Used to drain stale interrupts */
998 wait_queue_head_t wait_irq_drain;
999 bool irq_drain_is_open;
1000
1001 /* shared virtual memory registered by this process */
1002 struct svm_range_list svms;
1003
1004 bool xnack_enabled;
1005
1006 /* Work area for debugger event writer worker. */
1007 struct work_struct debug_event_workarea;
1008
1009 /* Tracks debug per-vmid request for debug flags */
1010 u32 dbg_flags;
1011
1012 atomic_t poison;
1013 /* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
1014 bool queues_paused;
1015
1016 /* Tracks runtime enable status */
1017 struct semaphore runtime_enable_sema;
1018 bool is_runtime_retry;
1019 struct kfd_runtime_info runtime_info;
1020
1021 /* if gpu page fault sent to KFD */
1022 bool gpu_page_fault;
1023
1024 /*kfd context id */
1025 u16 context_id;
1026
1027 /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */
1028 struct ida id_table;
1029
1030 };
1031
1032 #define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */
1033 #define KFD_CONTEXT_ID_PRIMARY 0xFFFF
1034 #define KFD_CONTEXT_ID_MIN 0
1035
1036 extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE);
1037 extern struct srcu_struct kfd_processes_srcu;
1038
1039 /**
1040 * typedef amdkfd_ioctl_t - typedef for ioctl function pointer.
1041 *
1042 * @filep: pointer to file structure.
1043 * @p: amdkfd process pointer.
1044 * @data: pointer to arg that was copied from user.
1045 *
1046 * Return: returns ioctl completion code.
1047 */
1048 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
1049 void *data);
1050
1051 typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize);
1052
1053 struct amdkfd_ioctl_desc {
1054 unsigned int cmd;
1055 int flags;
1056 amdkfd_ioctl_t *func;
1057 amdkfd_ioctl_validate_t *validate;
1058 unsigned int cmd_drv;
1059 const char *name;
1060 };
1061 bool kfd_dev_is_large_bar(struct kfd_node *dev);
1062
1063 struct kfd_process *create_process(const struct task_struct *thread, bool primary);
1064 int kfd_process_create_wq(void);
1065 void kfd_process_destroy_wq(void);
1066 void kfd_cleanup_processes(void);
1067 struct kfd_process *kfd_create_process(struct task_struct *thread);
1068 int kfd_create_process_sysfs(struct kfd_process *process);
1069 struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid,
1070 struct kfd_process_device **pdd);
1071 struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);
1072 struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id);
1073
1074 int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id);
1075 int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node,
1076 uint32_t *gpuid, uint32_t *gpuidx);
kfd_process_gpuid_from_gpuidx(struct kfd_process * p,uint32_t gpuidx,uint32_t * gpuid)1077 static inline int kfd_process_gpuid_from_gpuidx(struct kfd_process *p,
1078 uint32_t gpuidx, uint32_t *gpuid) {
1079 return gpuidx < p->n_pdds ? p->pdds[gpuidx]->dev->id : -EINVAL;
1080 }
kfd_process_device_from_gpuidx(struct kfd_process * p,uint32_t gpuidx)1081 static inline struct kfd_process_device *kfd_process_device_from_gpuidx(
1082 struct kfd_process *p, uint32_t gpuidx) {
1083 return gpuidx < p->n_pdds ? p->pdds[gpuidx] : NULL;
1084 }
1085
1086 void kfd_unref_process(struct kfd_process *p);
1087 int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger);
1088 int kfd_process_restore_queues(struct kfd_process *p);
1089 void kfd_suspend_all_processes(void);
1090 int kfd_resume_all_processes(void);
1091
1092 struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process,
1093 uint32_t gpu_id);
1094
1095 int kfd_process_get_user_gpu_id(struct kfd_process *p, uint32_t actual_gpu_id);
1096
1097 int kfd_process_device_init_vm(struct kfd_process_device *pdd,
1098 struct file *drm_file);
1099 struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev,
1100 struct kfd_process *p);
1101 struct kfd_process_device *kfd_get_process_device_data(struct kfd_node *dev,
1102 struct kfd_process *p);
1103 struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev,
1104 struct kfd_process *p);
1105
1106 bool kfd_process_xnack_mode(struct kfd_process *p, bool supported);
1107
1108 int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process,
1109 struct vm_area_struct *vma);
1110 void kfd_process_notifier_release_internal(struct kfd_process *p);
1111
1112 /* KFD process API for creating and translating handles */
1113 int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd,
1114 void *mem);
1115 void *kfd_process_device_translate_handle(struct kfd_process_device *p,
1116 int handle);
1117 void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd,
1118 int handle);
1119 struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid);
1120
1121 /* PASIDs */
1122 int kfd_pasid_init(void);
1123 void kfd_pasid_exit(void);
1124 u32 kfd_pasid_alloc(void);
1125 void kfd_pasid_free(u32 pasid);
1126
1127 /* Doorbells */
1128 size_t kfd_doorbell_process_slice(struct kfd_dev *kfd);
1129 int kfd_doorbell_init(struct kfd_dev *kfd);
1130 void kfd_doorbell_fini(struct kfd_dev *kfd);
1131 int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process,
1132 struct vm_area_struct *vma);
1133 void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd,
1134 unsigned int *doorbell_off);
1135 void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr);
1136 u32 read_kernel_doorbell(u32 __iomem *db);
1137 void write_kernel_doorbell(void __iomem *db, u32 value);
1138 void write_kernel_doorbell64(void __iomem *db, u64 value);
1139 unsigned int kfd_get_doorbell_dw_offset_in_bar(struct kfd_dev *kfd,
1140 struct kfd_process_device *pdd,
1141 unsigned int doorbell_id);
1142 phys_addr_t kfd_get_process_doorbells(struct kfd_process_device *pdd);
1143 int kfd_alloc_process_doorbells(struct kfd_dev *kfd,
1144 struct kfd_process_device *pdd);
1145 void kfd_free_process_doorbells(struct kfd_dev *kfd,
1146 struct kfd_process_device *pdd);
1147 /* GTT Sub-Allocator */
1148
1149 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1150 struct kfd_mem_obj **mem_obj);
1151
1152 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj);
1153
1154 extern struct device *kfd_device;
1155
1156 /* KFD's procfs */
1157 void kfd_procfs_init(void);
1158 void kfd_procfs_shutdown(void);
1159 int kfd_procfs_add_queue(struct queue *q);
1160 void kfd_procfs_del_queue(struct queue *q);
1161
1162 /* Topology */
1163 int kfd_topology_init(void);
1164 void kfd_topology_shutdown(void);
1165 int kfd_topology_add_device(struct kfd_node *gpu);
1166 int kfd_topology_remove_device(struct kfd_node *gpu);
1167 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
1168 uint32_t proximity_domain);
1169 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
1170 uint32_t proximity_domain);
1171 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id);
1172 struct kfd_node *kfd_device_by_id(uint32_t gpu_id);
kfd_irq_is_from_node(struct kfd_node * node,uint32_t node_id,uint32_t vmid)1173 static inline bool kfd_irq_is_from_node(struct kfd_node *node, uint32_t node_id,
1174 uint32_t vmid)
1175 {
1176 return (node->interrupt_bitmap & (1 << node_id)) != 0 &&
1177 (node->compute_vmid_bitmap & (1 << vmid)) != 0;
1178 }
kfd_node_by_irq_ids(struct amdgpu_device * adev,uint32_t node_id,uint32_t vmid)1179 static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev,
1180 uint32_t node_id, uint32_t vmid) {
1181 struct kfd_dev *dev = adev->kfd.dev;
1182 uint32_t i;
1183
1184 /*
1185 * On multi-aid system, attempt per-node matching. Otherwise,
1186 * fall back to the first node.
1187 */
1188 if (!amdgpu_is_multi_aid(adev))
1189 return dev->nodes[0];
1190
1191 for (i = 0; i < dev->num_nodes; i++)
1192 if (kfd_irq_is_from_node(dev->nodes[i], node_id, vmid))
1193 return dev->nodes[i];
1194
1195 return NULL;
1196 }
1197 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev);
1198 uint32_t kfd_topology_get_num_devices(void);
1199 int kfd_numa_node_to_apic_id(int numa_node_id);
1200 uint32_t kfd_gpu_node_num(void);
1201
1202 /* Interrupts */
1203 #define KFD_IRQ_FENCE_CLIENTID 0xff
1204 #define KFD_IRQ_FENCE_SOURCEID 0xff
1205 #define KFD_IRQ_IS_FENCE(client, source) \
1206 ((client) == KFD_IRQ_FENCE_CLIENTID && \
1207 (source) == KFD_IRQ_FENCE_SOURCEID)
1208 int kfd_interrupt_init(struct kfd_node *dev);
1209 void kfd_interrupt_exit(struct kfd_node *dev);
1210 bool enqueue_ih_ring_entry(struct kfd_node *kfd, const void *ih_ring_entry);
1211 bool interrupt_is_wanted(struct kfd_node *dev,
1212 const uint32_t *ih_ring_entry,
1213 uint32_t *patched_ihre, bool *flag);
1214 int kfd_process_drain_interrupts(struct kfd_process_device *pdd);
1215 void kfd_process_close_interrupt_drain(unsigned int pasid);
1216
1217 /* amdkfd Apertures */
1218 int kfd_init_apertures(struct kfd_process *process);
1219
1220 void kfd_process_set_trap_handler(struct qcm_process_device *qpd,
1221 uint64_t tba_addr,
1222 uint64_t tma_addr);
1223 void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd,
1224 bool enabled);
1225
1226 /* CWSR initialization */
1227 int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep);
1228
1229 /* CRIU */
1230 /*
1231 * Need to increment KFD_CRIU_PRIV_VERSION each time a change is made to any of the CRIU private
1232 * structures:
1233 * kfd_criu_process_priv_data
1234 * kfd_criu_device_priv_data
1235 * kfd_criu_bo_priv_data
1236 * kfd_criu_queue_priv_data
1237 * kfd_criu_event_priv_data
1238 * kfd_criu_svm_range_priv_data
1239 */
1240
1241 #define KFD_CRIU_PRIV_VERSION 1
1242
1243 struct kfd_criu_process_priv_data {
1244 uint32_t version;
1245 uint32_t xnack_mode;
1246 };
1247
1248 struct kfd_criu_device_priv_data {
1249 /* For future use */
1250 uint64_t reserved;
1251 };
1252
1253 struct kfd_criu_bo_priv_data {
1254 uint64_t user_addr;
1255 uint32_t idr_handle;
1256 uint32_t mapped_gpuids[MAX_GPU_INSTANCE];
1257 };
1258
1259 /*
1260 * The first 4 bytes of kfd_criu_queue_priv_data, kfd_criu_event_priv_data,
1261 * kfd_criu_svm_range_priv_data is the object type
1262 */
1263 enum kfd_criu_object_type {
1264 KFD_CRIU_OBJECT_TYPE_QUEUE,
1265 KFD_CRIU_OBJECT_TYPE_EVENT,
1266 KFD_CRIU_OBJECT_TYPE_SVM_RANGE,
1267 };
1268
1269 struct kfd_criu_svm_range_priv_data {
1270 uint32_t object_type;
1271 uint64_t start_addr;
1272 uint64_t size;
1273 /* Variable length array of attributes */
1274 struct kfd_ioctl_svm_attribute attrs[];
1275 };
1276
1277 struct kfd_criu_queue_priv_data {
1278 uint32_t object_type;
1279 uint64_t q_address;
1280 uint64_t q_size;
1281 uint64_t read_ptr_addr;
1282 uint64_t write_ptr_addr;
1283 uint64_t doorbell_off;
1284 uint64_t eop_ring_buffer_address;
1285 uint64_t ctx_save_restore_area_address;
1286 uint32_t gpu_id;
1287 uint32_t type;
1288 uint32_t format;
1289 uint32_t q_id;
1290 uint32_t priority;
1291 uint32_t q_percent;
1292 uint32_t doorbell_id;
1293 uint32_t gws;
1294 uint32_t sdma_id;
1295 uint32_t eop_ring_buffer_size;
1296 uint32_t ctx_save_restore_area_size;
1297 uint32_t ctl_stack_size;
1298 uint32_t mqd_size;
1299 };
1300
1301 struct kfd_criu_event_priv_data {
1302 uint32_t object_type;
1303 uint64_t user_handle;
1304 uint32_t event_id;
1305 uint32_t auto_reset;
1306 uint32_t type;
1307 uint32_t signaled;
1308
1309 union {
1310 struct kfd_hsa_memory_exception_data memory_exception_data;
1311 struct kfd_hsa_hw_exception_data hw_exception_data;
1312 };
1313 };
1314
1315 int kfd_process_get_queue_info(struct kfd_process *p,
1316 uint32_t *num_queues,
1317 uint64_t *priv_data_sizes);
1318
1319 int kfd_criu_checkpoint_queues(struct kfd_process *p,
1320 uint8_t __user *user_priv_data,
1321 uint64_t *priv_data_offset);
1322
1323 int kfd_criu_restore_queue(struct kfd_process *p,
1324 uint8_t __user *user_priv_data,
1325 uint64_t *priv_data_offset,
1326 uint64_t max_priv_data_size);
1327
1328 int kfd_criu_checkpoint_events(struct kfd_process *p,
1329 uint8_t __user *user_priv_data,
1330 uint64_t *priv_data_offset);
1331
1332 int kfd_criu_restore_event(struct file *devkfd,
1333 struct kfd_process *p,
1334 uint8_t __user *user_priv_data,
1335 uint64_t *priv_data_offset,
1336 uint64_t max_priv_data_size);
1337 /* CRIU - End */
1338
1339 /* Queue Context Management */
1340 int init_queue(struct queue **q, const struct queue_properties *properties);
1341 void uninit_queue(struct queue *q);
1342 void print_queue_properties(struct queue_properties *q);
1343 void print_queue(struct queue *q);
1344 int kfd_queue_buffer_get(struct amdgpu_vm *vm, void __user *addr, struct amdgpu_bo **pbo,
1345 u64 expected_size);
1346 void kfd_queue_buffer_put(struct amdgpu_bo **bo);
1347 int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1348 int kfd_queue_release_buffers(struct kfd_process_device *pdd, struct queue_properties *properties);
1349 void kfd_queue_unref_bo_va(struct amdgpu_vm *vm, struct amdgpu_bo **bo);
1350 int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd,
1351 struct queue_properties *properties);
1352 void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev);
1353
1354 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
1355 struct kfd_node *dev);
1356 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
1357 struct kfd_node *dev);
1358 struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type,
1359 struct kfd_node *dev);
1360 struct mqd_manager *mqd_manager_init_v10(enum KFD_MQD_TYPE type,
1361 struct kfd_node *dev);
1362 struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
1363 struct kfd_node *dev);
1364 struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type,
1365 struct kfd_node *dev);
1366 struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type,
1367 struct kfd_node *dev);
1368 struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev);
1369 void device_queue_manager_uninit(struct device_queue_manager *dqm);
1370 struct kernel_queue *kernel_queue_init(struct kfd_node *dev,
1371 enum kfd_queue_type type);
1372 void kernel_queue_uninit(struct kernel_queue *kq);
1373 int kfd_evict_process_device(struct kfd_process_device *pdd);
1374 int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id);
1375
1376 /* Process Queue Manager */
1377 struct process_queue_node {
1378 struct queue *q;
1379 struct kernel_queue *kq;
1380 struct list_head process_queue_list;
1381 };
1382
1383 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd);
1384 void kfd_process_dequeue_from_all_devices(struct kfd_process *p);
1385 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p);
1386 void pqm_uninit(struct process_queue_manager *pqm);
1387 int pqm_create_queue(struct process_queue_manager *pqm,
1388 struct kfd_node *dev,
1389 struct queue_properties *properties,
1390 unsigned int *qid,
1391 const struct kfd_criu_queue_priv_data *q_data,
1392 const void *restore_mqd,
1393 const void *restore_ctl_stack,
1394 uint32_t *p_doorbell_offset_in_process);
1395 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid);
1396 int pqm_update_queue_properties(struct process_queue_manager *pqm, unsigned int qid,
1397 struct queue_properties *p);
1398 int pqm_update_mqd(struct process_queue_manager *pqm, unsigned int qid,
1399 struct mqd_update_info *minfo);
1400 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
1401 void *gws);
1402 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
1403 unsigned int qid);
1404 int pqm_get_wave_state(struct process_queue_manager *pqm,
1405 unsigned int qid,
1406 void __user *ctl_stack,
1407 u32 *ctl_stack_used_size,
1408 u32 *save_area_used_size);
1409 int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
1410 uint64_t exception_clear_mask,
1411 void __user *buf,
1412 int *num_qss_entries,
1413 uint32_t *entry_size);
1414
1415 int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,
1416 uint64_t fence_value,
1417 unsigned int timeout_ms);
1418
1419 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
1420 unsigned int qid,
1421 u32 *mqd_size,
1422 u32 *ctl_stack_size);
1423 /* Packet Manager */
1424
1425 #define KFD_FENCE_COMPLETED (100)
1426 #define KFD_FENCE_INIT (10)
1427
1428 /**
1429 * enum kfd_config_dequeue_wait_counts_cmd - Command for configuring
1430 * dequeue wait counts.
1431 *
1432 * @KFD_DEQUEUE_WAIT_INIT: Set optimized dequeue wait counts for a
1433 * certain ASICs. For these ASICs, this is default value used by RESET
1434 * @KFD_DEQUEUE_WAIT_RESET: Reset dequeue wait counts to the optimized value
1435 * for certain ASICs. For others set it to default hardware reset value
1436 * @KFD_DEQUEUE_WAIT_SET_SCH_WAVE: Set context switch latency wait
1437 *
1438 */
1439 enum kfd_config_dequeue_wait_counts_cmd {
1440 KFD_DEQUEUE_WAIT_INIT = 1,
1441 KFD_DEQUEUE_WAIT_RESET = 2,
1442 KFD_DEQUEUE_WAIT_SET_SCH_WAVE = 3
1443 };
1444
1445
1446 struct packet_manager {
1447 struct device_queue_manager *dqm;
1448 struct kernel_queue *priv_queue;
1449 struct mutex lock;
1450 bool allocated;
1451 struct kfd_mem_obj *ib_buffer_obj;
1452 unsigned int ib_size_bytes;
1453 bool is_over_subscription;
1454
1455 const struct packet_manager_funcs *pmf;
1456 };
1457
1458 struct packet_manager_funcs {
1459 /* Support ASIC-specific packet formats for PM4 packets */
1460 int (*map_process)(struct packet_manager *pm, uint32_t *buffer,
1461 struct qcm_process_device *qpd);
1462 int (*runlist)(struct packet_manager *pm, uint32_t *buffer,
1463 uint64_t ib, size_t ib_size_in_dwords, bool chain);
1464 int (*set_resources)(struct packet_manager *pm, uint32_t *buffer,
1465 struct scheduling_resources *res);
1466 int (*map_queues)(struct packet_manager *pm, uint32_t *buffer,
1467 struct queue *q, bool is_static);
1468 int (*unmap_queues)(struct packet_manager *pm, uint32_t *buffer,
1469 enum kfd_unmap_queues_filter mode,
1470 uint32_t filter_param, bool reset);
1471 int (*config_dequeue_wait_counts)(struct packet_manager *pm, uint32_t *buffer,
1472 enum kfd_config_dequeue_wait_counts_cmd cmd, uint32_t value);
1473 int (*query_status)(struct packet_manager *pm, uint32_t *buffer,
1474 uint64_t fence_address, uint64_t fence_value);
1475 int (*release_mem)(uint64_t gpu_addr, uint32_t *buffer);
1476
1477 /* Packet sizes */
1478 int map_process_size;
1479 int runlist_size;
1480 int set_resources_size;
1481 int map_queues_size;
1482 int unmap_queues_size;
1483 int config_dequeue_wait_counts_size;
1484 int query_status_size;
1485 int release_mem_size;
1486 };
1487
1488 extern const struct packet_manager_funcs kfd_vi_pm_funcs;
1489 extern const struct packet_manager_funcs kfd_v9_pm_funcs;
1490 extern const struct packet_manager_funcs kfd_aldebaran_pm_funcs;
1491
1492 int pm_init(struct packet_manager *pm, struct device_queue_manager *dqm);
1493 void pm_uninit(struct packet_manager *pm);
1494 int pm_send_set_resources(struct packet_manager *pm,
1495 struct scheduling_resources *res);
1496 int pm_send_runlist(struct packet_manager *pm, struct list_head *dqm_queues);
1497 int pm_send_query_status(struct packet_manager *pm, uint64_t fence_address,
1498 uint64_t fence_value);
1499
1500 int pm_send_unmap_queue(struct packet_manager *pm,
1501 enum kfd_unmap_queues_filter mode,
1502 uint32_t filter_param, bool reset);
1503
1504 void pm_release_ib(struct packet_manager *pm);
1505
1506 int pm_config_dequeue_wait_counts(struct packet_manager *pm,
1507 enum kfd_config_dequeue_wait_counts_cmd cmd,
1508 uint32_t wait_counts_config);
1509
1510 /* Following PM funcs can be shared among VI and AI */
1511 unsigned int pm_build_pm4_header(unsigned int opcode, size_t packet_size);
1512
1513 uint64_t kfd_get_number_elems(struct kfd_dev *kfd);
1514
1515 /* Events */
1516 extern const struct kfd_event_interrupt_class event_interrupt_class_cik;
1517 extern const struct kfd_event_interrupt_class event_interrupt_class_v9;
1518 extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3;
1519 extern const struct kfd_event_interrupt_class event_interrupt_class_v10;
1520 extern const struct kfd_event_interrupt_class event_interrupt_class_v11;
1521 extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1;
1522
1523 extern const struct kfd_device_global_init_class device_global_init_class_cik;
1524
1525 int kfd_event_init_process(struct kfd_process *p);
1526 void kfd_event_free_process(struct kfd_process *p);
1527 int kfd_event_mmap(struct kfd_process *process, struct vm_area_struct *vma);
1528 int kfd_wait_on_events(struct kfd_process *p,
1529 uint32_t num_events, void __user *data,
1530 bool all, uint32_t *user_timeout_ms,
1531 uint32_t *wait_result);
1532 void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id,
1533 uint32_t valid_id_bits, bool signal_mailbox_updated);
1534 void kfd_signal_hw_exception_event(u32 pasid);
1535 int kfd_set_event(struct kfd_process *p, uint32_t event_id);
1536 int kfd_reset_event(struct kfd_process *p, uint32_t event_id);
1537 int kfd_kmap_event_page(struct kfd_process *p, uint64_t event_page_offset);
1538
1539 int kfd_event_create(struct file *devkfd, struct kfd_process *p,
1540 uint32_t event_type, bool auto_reset, uint32_t node_id,
1541 uint32_t *event_id, uint32_t *event_trigger_data,
1542 uint64_t *event_page_offset, uint32_t *event_slot_index);
1543
1544 int kfd_get_num_events(struct kfd_process *p);
1545 int kfd_event_destroy(struct kfd_process *p, uint32_t event_id);
1546
1547 void kfd_signal_vm_fault_event_with_userptr(struct kfd_process *p, uint64_t gpu_va);
1548
1549 void kfd_signal_vm_fault_event(struct kfd_process_device *pdd,
1550 struct kfd_vm_fault_info *info,
1551 struct kfd_hsa_memory_exception_data *data);
1552
1553 void kfd_signal_reset_event(struct kfd_node *dev);
1554
1555 void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid);
1556 void kfd_signal_process_terminate_event(struct kfd_process *p);
1557
kfd_flush_tlb(struct kfd_process_device * pdd)1558 static inline void kfd_flush_tlb(struct kfd_process_device *pdd)
1559 {
1560 struct amdgpu_device *adev = pdd->dev->adev;
1561 struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
1562
1563 amdgpu_vm_flush_compute_tlb(adev, vm, TLB_FLUSH_HEAVYWEIGHT,
1564 pdd->dev->xcc_mask);
1565 }
1566
kfd_flush_tlb_after_unmap(struct kfd_dev * dev)1567 static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
1568 {
1569 return KFD_GC_VERSION(dev) >= IP_VERSION(9, 4, 2) ||
1570 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) ||
1571 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
1572 }
1573
1574 int kfd_send_exception_to_runtime(struct kfd_process *p,
1575 unsigned int queue_id,
1576 uint64_t error_reason);
1577 bool kfd_is_locked(struct kfd_dev *kfd);
1578
1579 /* Compute profile */
1580 void kfd_inc_compute_active(struct kfd_node *dev);
1581 void kfd_dec_compute_active(struct kfd_node *dev);
1582
1583 /* Cgroup Support */
1584 /* Check with device cgroup if @kfd device is accessible */
kfd_devcgroup_check_permission(struct kfd_node * node)1585 static inline int kfd_devcgroup_check_permission(struct kfd_node *node)
1586 {
1587 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF)
1588 struct drm_device *ddev;
1589
1590 if (node->xcp)
1591 ddev = node->xcp->ddev;
1592 else
1593 ddev = adev_to_drm(node->adev);
1594
1595 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR,
1596 ddev->render->index,
1597 DEVCG_ACC_WRITE | DEVCG_ACC_READ);
1598 #else
1599 return 0;
1600 #endif
1601 }
1602
kfd_is_first_node(struct kfd_node * node)1603 static inline bool kfd_is_first_node(struct kfd_node *node)
1604 {
1605 return (node == node->kfd->nodes[0]);
1606 }
1607
1608 /* Debugfs */
1609 #if defined(CONFIG_DEBUG_FS)
1610
1611 void kfd_debugfs_init(void);
1612 void kfd_debugfs_fini(void);
1613 int kfd_debugfs_mqds_by_process(struct seq_file *m, void *data);
1614 int pqm_debugfs_mqds(struct seq_file *m, void *data);
1615 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data);
1616 int dqm_debugfs_hqds(struct seq_file *m, void *data);
1617 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data);
1618 int pm_debugfs_runlist(struct seq_file *m, void *data);
1619
1620 int kfd_debugfs_hang_hws(struct kfd_node *dev);
1621 int pm_debugfs_hang_hws(struct packet_manager *pm);
1622 int dqm_debugfs_hang_hws(struct device_queue_manager *dqm);
1623
1624 void kfd_debugfs_add_process(struct kfd_process *p);
1625 void kfd_debugfs_remove_process(struct kfd_process *p);
1626
1627 #else
1628
kfd_debugfs_init(void)1629 static inline void kfd_debugfs_init(void) {}
kfd_debugfs_fini(void)1630 static inline void kfd_debugfs_fini(void) {}
kfd_debugfs_add_process(struct kfd_process * p)1631 static inline void kfd_debugfs_add_process(struct kfd_process *p) {}
kfd_debugfs_remove_process(struct kfd_process * p)1632 static inline void kfd_debugfs_remove_process(struct kfd_process *p) {}
1633
1634 #endif
1635
1636 #endif
1637