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Searched refs:ixUVD_CGC_MEM_CTRL (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c601 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
603 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
610 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
612 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
H A Duvd_v4_2.c614 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
616 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
623 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
625 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
H A Duvd_v5_0.c773 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
775 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
782 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
784 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
H A Duvd_v6_0.c1433 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1435 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
1442 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1444 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h27 #define ixUVD_CGC_MEM_CTRL 0x00C0 macro
H A Duvd_4_2_d.h86 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
H A Duvd_3_1_d.h88 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
H A Duvd_5_0_d.h97 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
H A Duvd_6_0_d.h113 #define ixUVD_CGC_MEM_CTRL 0xc0 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_3_0_0_offset.h1509 #define ixUVD_CGC_MEM_CTRL … macro
H A Dvcn_5_0_0_offset.h1624 #define ixUVD_CGC_MEM_CTRL … macro
H A Dvcn_4_0_0_offset.h1984 #define ixUVD_CGC_MEM_CTRL … macro
H A Dvcn_4_0_3_offset.h2284 #define ixUVD_CGC_MEM_CTRL … macro