1/* 2 * Copyright 2016 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23#include <dt-bindings/interrupt-controller/irq.h> 24#include <dt-bindings/gpio/gpio.h> 25 26/ { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-pbx"; 30 31 chosen { }; 32 33 aliases { 34 serial0 = &serial0; 35 serial1 = &serial1; 36 serial2 = &serial2; 37 serial3 = &serial3; 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 }; 41 42 memory { 43 device_type = "memory"; 44 /* 128 MiB memory @ 0x0 */ 45 reg = <0x00000000 0x08000000>; 46 }; 47 48 /* The voltage to the MMC card is hardwired at 3.3V */ 49 vmmc: regulator-vmmc { 50 compatible = "regulator-fixed"; 51 regulator-name = "vmmc"; 52 regulator-min-microvolt = <3300000>; 53 regulator-max-microvolt = <3300000>; 54 regulator-boot-on; 55 }; 56 57 veth: regulator-veth { 58 compatible = "regulator-fixed"; 59 regulator-name = "veth"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 regulator-boot-on; 63 }; 64 65 xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <24000000>; 69 }; 70 71 refclk32khz: clock-32768 { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <32768>; 75 }; 76 77 timclk: clock-1000000 { 78 #clock-cells = <0>; 79 compatible = "fixed-factor-clock"; 80 clock-div = <24>; 81 clock-mult = <1>; 82 clocks = <&xtal24mhz>; 83 }; 84 85 /* FIXME: this actually hangs off the PLL clocks */ 86 pclk: clock-pclk { 87 #clock-cells = <0>; 88 compatible = "fixed-clock"; 89 clock-frequency = <0>; 90 }; 91 92 flash0@40000000 { 93 /* 2 * 32MiB NOR Flash memory */ 94 compatible = "arm,versatile-flash", "cfi-flash"; 95 reg = <0x40000000 0x04000000>; 96 bank-width = <4>; 97 partitions { 98 compatible = "arm,arm-firmware-suite"; 99 }; 100 }; 101 102 flash1@44000000 { 103 /* 2 * 32MiB NOR Flash memory */ 104 compatible = "arm,versatile-flash", "cfi-flash"; 105 reg = <0x44000000 0x04000000>; 106 bank-width = <4>; 107 partitions { 108 compatible = "arm,arm-firmware-suite"; 109 }; 110 }; 111 112 /* SMSC 9118 ethernet with PHY and EEPROM */ 113 ethernet: ethernet@4e000000 { 114 compatible = "smsc,lan9118", "smsc,lan9115"; 115 reg = <0x4e000000 0x10000>; 116 phy-mode = "mii"; 117 reg-io-width = <4>; 118 smsc,irq-active-high; 119 smsc,irq-push-pull; 120 vdd33a-supply = <&veth>; 121 vddvario-supply = <&veth>; 122 }; 123 124 usb: usb@4f000000 { 125 compatible = "nxp,usb-isp1761"; 126 reg = <0x4f000000 0x20000>; 127 dr_mode = "peripheral"; 128 }; 129 130 bridge { 131 compatible = "ti,ths8134a", "ti,ths8134"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 port@0 { 140 reg = <0>; 141 142 vga_bridge_in: endpoint { 143 remote-endpoint = <&clcd_pads>; 144 }; 145 }; 146 147 port@1 { 148 reg = <1>; 149 150 vga_bridge_out: endpoint { 151 remote-endpoint = <&vga_con_in>; 152 }; 153 }; 154 }; 155 }; 156 157 vga { 158 /* 159 * This DDC I2C is connected directly to the DVI portions 160 * of the connector, so it's not really working when the 161 * monitor is connected to the VGA connector. 162 */ 163 compatible = "vga-connector"; 164 ddc-i2c-bus = <&i2c1>; 165 166 port { 167 vga_con_in: endpoint { 168 remote-endpoint = <&vga_bridge_out>; 169 }; 170 }; 171 }; 172 173 soc: soc { 174 compatible = "arm,realview-pbx-soc", "simple-bus"; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 regmap = <&syscon>; 178 ranges; 179 180 syscon: syscon@10000000 { 181 compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; 182 reg = <0x10000000 0x1000>; 183 ranges = <0x0 0x10000000 0x1000>; 184 #address-cells = <1>; 185 #size-cells = <1>; 186 187 led@8,0 { 188 compatible = "register-bit-led"; 189 reg = <0x08 0x04>; 190 offset = <0x08>; 191 mask = <0x01>; 192 label = "versatile:0"; 193 linux,default-trigger = "heartbeat"; 194 default-state = "on"; 195 }; 196 led@8,1 { 197 compatible = "register-bit-led"; 198 reg = <0x08 0x04>; 199 offset = <0x08>; 200 mask = <0x02>; 201 label = "versatile:1"; 202 linux,default-trigger = "mmc0"; 203 default-state = "off"; 204 }; 205 led@8,2 { 206 compatible = "register-bit-led"; 207 reg = <0x08 0x04>; 208 offset = <0x08>; 209 mask = <0x04>; 210 label = "versatile:2"; 211 linux,default-trigger = "cpu0"; 212 default-state = "off"; 213 }; 214 led@8,3 { 215 compatible = "register-bit-led"; 216 reg = <0x08 0x04>; 217 offset = <0x08>; 218 mask = <0x08>; 219 label = "versatile:3"; 220 default-state = "off"; 221 }; 222 led@8,4 { 223 compatible = "register-bit-led"; 224 reg = <0x08 0x04>; 225 offset = <0x08>; 226 mask = <0x10>; 227 label = "versatile:4"; 228 default-state = "off"; 229 }; 230 led@8,5 { 231 compatible = "register-bit-led"; 232 reg = <0x08 0x04>; 233 offset = <0x08>; 234 mask = <0x20>; 235 label = "versatile:5"; 236 default-state = "off"; 237 }; 238 led@8,6 { 239 compatible = "register-bit-led"; 240 reg = <0x08 0x04>; 241 offset = <0x08>; 242 mask = <0x40>; 243 label = "versatile:6"; 244 default-state = "off"; 245 }; 246 led@8,7 { 247 compatible = "register-bit-led"; 248 reg = <0x08 0x04>; 249 offset = <0x08>; 250 mask = <0x80>; 251 label = "versatile:7"; 252 default-state = "off"; 253 }; 254 oscclk0: clock-controller@c { 255 compatible = "arm,syscon-icst307"; 256 reg = <0x0c 0x04>; 257 #clock-cells = <0>; 258 lock-offset = <0x20>; 259 vco-offset = <0x0C>; 260 clocks = <&xtal24mhz>; 261 }; 262 oscclk1: clock-controller@10 { 263 compatible = "arm,syscon-icst307"; 264 reg = <0x10 0x04>; 265 #clock-cells = <0>; 266 lock-offset = <0x20>; 267 vco-offset = <0x10>; 268 clocks = <&xtal24mhz>; 269 }; 270 oscclk2: clock-controller@14 { 271 compatible = "arm,syscon-icst307"; 272 reg = <0x14 0x04>; 273 #clock-cells = <0>; 274 lock-offset = <0x20>; 275 vco-offset = <0x14>; 276 clocks = <&xtal24mhz>; 277 }; 278 oscclk3: clock-controller@18 { 279 compatible = "arm,syscon-icst307"; 280 reg = <0x18 0x04>; 281 #clock-cells = <0>; 282 lock-offset = <0x20>; 283 vco-offset = <0x18>; 284 clocks = <&xtal24mhz>; 285 }; 286 oscclk4: clock-controller@1c { 287 compatible = "arm,syscon-icst307"; 288 reg = <0x1c 0x04>; 289 #clock-cells = <0>; 290 lock-offset = <0x20>; 291 vco-offset = <0x1c>; 292 clocks = <&xtal24mhz>; 293 }; 294 }; 295 296 sp810_syscon0: sysctl@10001000 { 297 compatible = "arm,sp810", "arm,primecell"; 298 reg = <0x10001000 0x1000>; 299 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 300 clock-names = "refclk", "timclk", "apb_pclk"; 301 #clock-cells = <1>; 302 clock-output-names = "timerclk0", 303 "timerclk1", 304 "timerclk2", 305 "timerclk3"; 306 assigned-clocks = <&sp810_syscon0 0>, 307 <&sp810_syscon0 1>, 308 <&sp810_syscon0 2>, 309 <&sp810_syscon0 3>; 310 assigned-clock-parents = <&timclk>, 311 <&timclk>, 312 <&timclk>, 313 <&timclk>; 314 }; 315 316 i2c0: i2c@10002000 { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 compatible = "arm,versatile-i2c"; 320 reg = <0x10002000 0x1000>; 321 322 rtc@68 { 323 compatible = "dallas,ds1338"; 324 reg = <0x68>; 325 }; 326 }; 327 328 serial0: serial@10009000 { 329 compatible = "arm,pl011", "arm,primecell"; 330 reg = <0x10009000 0x1000>; 331 clocks = <&uartclk>, <&pclk>; 332 clock-names = "uartclk", "apb_pclk"; 333 }; 334 335 serial1: serial@1000a000 { 336 compatible = "arm,pl011", "arm,primecell"; 337 reg = <0x1000a000 0x1000>; 338 clocks = <&uartclk>, <&pclk>; 339 clock-names = "uartclk", "apb_pclk"; 340 }; 341 342 serial2: serial@1000b000 { 343 compatible = "arm,pl011", "arm,primecell"; 344 reg = <0x1000b000 0x1000>; 345 clocks = <&uartclk>, <&pclk>; 346 clock-names = "uartclk", "apb_pclk"; 347 }; 348 349 ssp: spi@1000d000 { 350 compatible = "arm,pl022", "arm,primecell"; 351 reg = <0x1000d000 0x1000>; 352 clocks = <&sspclk>, <&pclk>; 353 clock-names = "sspclk", "apb_pclk"; 354 }; 355 356 wdog0: watchdog@1000f000 { 357 compatible = "arm,sp805", "arm,primecell"; 358 reg = <0x1000f000 0x1000>; 359 clocks = <&wdogclk>, <&pclk>; 360 clock-names = "wdog_clk", "apb_pclk"; 361 status = "disabled"; 362 }; 363 364 wdog1: watchdog@10010000 { 365 compatible = "arm,sp805", "arm,primecell"; 366 reg = <0x10010000 0x1000>; 367 clocks = <&wdogclk>, <&pclk>; 368 clock-names = "wdog_clk", "apb_pclk"; 369 status = "disabled"; 370 }; 371 372 timer01: timer@10011000 { 373 compatible = "arm,sp804", "arm,primecell"; 374 reg = <0x10011000 0x1000>; 375 clocks = <&sp810_syscon0 0>, 376 <&sp810_syscon0 1>, 377 <&pclk>; 378 clock-names = "timerclk0", 379 "timerclk1", 380 "apb_pclk"; 381 }; 382 383 timer23: timer@10012000 { 384 compatible = "arm,sp804", "arm,primecell"; 385 reg = <0x10012000 0x1000>; 386 clocks = <&sp810_syscon0 2>, 387 <&sp810_syscon0 3>, 388 <&pclk>; 389 clock-names = "timerclk2", 390 "timerclk3", 391 "apb_pclk"; 392 }; 393 394 gpio0: gpio@10013000 { 395 compatible = "arm,pl061", "arm,primecell"; 396 reg = <0x10013000 0x1000>; 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 clocks = <&pclk>; 402 clock-names = "apb_pclk"; 403 }; 404 405 gpio1: gpio@10014000 { 406 compatible = "arm,pl061", "arm,primecell"; 407 reg = <0x10014000 0x1000>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 clocks = <&pclk>; 413 clock-names = "apb_pclk"; 414 }; 415 416 gpio2: gpio@10015000 { 417 compatible = "arm,pl061", "arm,primecell"; 418 reg = <0x10015000 0x1000>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 clocks = <&pclk>; 424 clock-names = "apb_pclk"; 425 }; 426 427 i2c1: i2c@10016000 { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 compatible = "arm,versatile-i2c"; 431 reg = <0x10016000 0x1000>; 432 }; 433 434 rtc: rtc@10017000 { 435 compatible = "arm,pl031", "arm,primecell"; 436 reg = <0x10017000 0x1000>; 437 clocks = <&pclk>; 438 clock-names = "apb_pclk"; 439 }; 440 441 timer45: timer@10018000 { 442 compatible = "arm,sp804", "arm,primecell"; 443 reg = <0x10018000 0x1000>; 444 clocks = <&timclk>, <&timclk>, <&pclk>; 445 clock-names = "timerclk4", "timerclk5", "apb_pclk"; 446 }; 447 448 timer67: timer@10019000 { 449 compatible = "arm,sp804", "arm,primecell"; 450 reg = <0x10019000 0x1000>; 451 clocks = <&timclk>, <&timclk>, <&pclk>; 452 clock-names = "timerclk6", "timerclk7", "apb_pclk"; 453 }; 454 455 sp810_syscon1: sysctl@1001a000 { 456 compatible = "arm,sp810", "arm,primecell"; 457 reg = <0x1001a000 0x1000>; 458 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; 459 clock-names = "refclk", "timclk", "apb_pclk"; 460 #clock-cells = <1>; 461 clock-output-names = "timerclk4", 462 "timerclk5", 463 "timerclk6", 464 "timerclk7"; 465 assigned-clocks = <&sp810_syscon1 0>, 466 <&sp810_syscon1 1>, 467 <&sp810_syscon1 2>, 468 <&sp810_syscon1 3>; 469 assigned-clock-parents = <&timclk>, 470 <&timclk>, 471 <&timclk>, 472 <&timclk>; 473 }; 474 }; 475 476 477 /* These peripherals are inside the FPGA */ 478 fpga { 479 #address-cells = <1>; 480 #size-cells = <1>; 481 compatible = "simple-bus"; 482 ranges; 483 484 aaci: aaci@10004000 { 485 compatible = "arm,pl041", "arm,primecell"; 486 reg = <0x10004000 0x1000>; 487 clocks = <&pclk>; 488 clock-names = "apb_pclk"; 489 }; 490 491 mmc: mmcsd@10005000 { 492 compatible = "arm,pl18x", "arm,primecell"; 493 reg = <0x10005000 0x1000>; 494 495 /* Due to frequent FIFO overruns, use just 500 kHz */ 496 max-frequency = <500000>; 497 bus-width = <4>; 498 cap-sd-highspeed; 499 cap-mmc-highspeed; 500 clocks = <&mclk>, <&pclk>; 501 clock-names = "mclk", "apb_pclk"; 502 vmmc-supply = <&vmmc>; 503 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 504 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 505 }; 506 507 kmi0: kmi@10006000 { 508 compatible = "arm,pl050", "arm,primecell"; 509 reg = <0x10006000 0x1000>; 510 clocks = <&kmiclk>, <&pclk>; 511 clock-names = "KMIREFCLK", "apb_pclk"; 512 }; 513 514 kmi1: kmi@10007000 { 515 compatible = "arm,pl050", "arm,primecell"; 516 reg = <0x10007000 0x1000>; 517 clocks = <&kmiclk>, <&pclk>; 518 clock-names = "KMIREFCLK", "apb_pclk"; 519 }; 520 521 serial3: serial@1000c000 { 522 compatible = "arm,pl011", "arm,primecell"; 523 reg = <0x1000c000 0x1000>; 524 clocks = <&uartclk>, <&pclk>; 525 clock-names = "uartclk", "apb_pclk"; 526 }; 527 }; 528 529 /* These peripherals are inside the NEC ISSP */ 530 issp { 531 #address-cells = <1>; 532 #size-cells = <1>; 533 compatible = "simple-bus"; 534 ranges; 535 536 clcd: clcd@10020000 { 537 compatible = "arm,pl111", "arm,primecell"; 538 reg = <0x10020000 0x1000>; 539 interrupt-names = "combined"; 540 clocks = <&oscclk4>, <&pclk>; 541 clock-names = "clcdclk", "apb_pclk"; 542 /* 1024x768 16bpp @65MHz works fine */ 543 max-memory-bandwidth = <95000000>; 544 545 port { 546 clcd_pads: endpoint { 547 remote-endpoint = <&vga_bridge_in>; 548 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 549 }; 550 }; 551 }; 552 }; 553}; 554