1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * CS42L43 core driver
4 *
5 * Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8
9 #include <linux/array_size.h>
10 #include <linux/bitops.h>
11 #include <linux/build_bug.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/jiffies.h>
18 #include <linux/mfd/core.h>
19 #include <linux/mfd/cs42l43.h>
20 #include <linux/mfd/cs42l43-regs.h>
21 #include <linux/module.h>
22 #include <linux/pm.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/soundwire/sdw.h>
26 #include <linux/types.h>
27
28 #include "cs42l43.h"
29
30 #define CS42L43_RESET_DELAY_MS 20
31
32 #define CS42L43_SDW_ATTACH_TIMEOUT_MS 5000
33 #define CS42L43_SDW_DETACH_TIMEOUT_MS 100
34
35 #define CS42L43_MCU_BOOT_STAGE1 1
36 #define CS42L43_MCU_BOOT_STAGE2 2
37 #define CS42L43_MCU_BOOT_STAGE3 3
38 #define CS42L43_MCU_BOOT_STAGE4 4
39 #define CS42L43_MCU_POLL_US 5000
40 #define CS42L43_MCU_CMD_TIMEOUT_US 20000
41 #define CS42L43_MCU_UPDATE_FORMAT 3
42 #define CS42L43_MCU_UPDATE_OFFSET 0x100000
43 #define CS42L43_MCU_UPDATE_TIMEOUT_US 500000
44 #define CS42L43_MCU_UPDATE_RETRIES 5
45
46 #define CS42L43_MCU_ROM_REV 0x2001
47 #define CS42L43_MCU_ROM_BIOS_REV 0x0000
48
49 #define CS42L43_MCU_SUPPORTED_REV 0x2105
50 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
51 #define CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV 0x1002
52 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
53
54 #define CS42L43_VDDP_DELAY_US 50
55 #define CS42L43_VDDD_DELAY_US 1000
56
57 #define CS42L43_AUTOSUSPEND_TIME_MS 250
58
59 struct cs42l43_patch_header {
60 __le16 version;
61 __le16 size;
62 __u8 reserved;
63 __u8 secure;
64 __le16 bss_size;
65 __le32 apply_addr;
66 __le32 checksum;
67 __le32 sha;
68 __le16 swrev;
69 __le16 patchid;
70 __le16 ipxid;
71 __le16 romver;
72 __le32 load_addr;
73 } __packed;
74
75 static const struct reg_sequence cs42l43_reva_patch[] = {
76 { 0x4000, 0x00000055 },
77 { 0x4000, 0x000000AA },
78 { 0x10084, 0x00000000 },
79 { 0x1741C, 0x00CD2000 },
80 { 0x1718C, 0x00000003 },
81 { 0x4000, 0x00000000 },
82 { CS42L43_CCM_BLK_CLK_CONTROL, 0x00000002 },
83 { CS42L43_HPPATHVOL, 0x011B011B },
84 { CS42L43_OSC_DIV_SEL, 0x00000001 },
85 { CS42L43_DACCNFG2, 0x00000005 },
86 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
87 { CS42L43_RELID, 0x0000000F },
88 };
89
90 const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
91 { CS42L43_DRV_CTRL1, 0x000186C0 },
92 { CS42L43_DRV_CTRL3, 0x286DB018 },
93 { CS42L43_DRV_CTRL4, 0x000006D8 },
94 { CS42L43_DRV_CTRL_5, 0x136C00C0 },
95 { CS42L43_GPIO_CTRL1, 0x00000707 },
96 { CS42L43_GPIO_CTRL2, 0x00000000 },
97 { CS42L43_GPIO_FN_SEL, 0x00000004 },
98 { CS42L43_MCLK_SRC_SEL, 0x00000000 },
99 { CS42L43_SAMPLE_RATE1, 0x00000003 },
100 { CS42L43_SAMPLE_RATE2, 0x00000003 },
101 { CS42L43_SAMPLE_RATE3, 0x00000003 },
102 { CS42L43_SAMPLE_RATE4, 0x00000003 },
103 { CS42L43_PLL_CONTROL, 0x00000000 },
104 { CS42L43_FS_SELECT1, 0x00000000 },
105 { CS42L43_FS_SELECT2, 0x00000000 },
106 { CS42L43_FS_SELECT3, 0x00000000 },
107 { CS42L43_FS_SELECT4, 0x00000000 },
108 { CS42L43_PDM_CONTROL, 0x00000000 },
109 { CS42L43_ASP_CLK_CONFIG1, 0x00010001 },
110 { CS42L43_ASP_CLK_CONFIG2, 0x00000000 },
111 { CS42L43_OSC_DIV_SEL, 0x00000001 },
112 { CS42L43_ADC_B_CTRL1, 0x00000000 },
113 { CS42L43_ADC_B_CTRL2, 0x00000000 },
114 { CS42L43_DECIM_HPF_WNF_CTRL1, 0x00000001 },
115 { CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 },
116 { CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 },
117 { CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 },
118 { CS42L43_DMIC_PDM_CTRL, 0x00000000 },
119 { CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
120 { CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
121 { CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
122 { CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
123 { CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 0x20122012 },
124 { CS42L43B_DECIM_HPF_WNF_CTRL5, 0x00000001 },
125 { CS42L43B_DECIM_HPF_WNF_CTRL6, 0x00000001 },
126 { CS42L43_INTP_VOLUME_CTRL1, 0x00000180 },
127 { CS42L43_INTP_VOLUME_CTRL2, 0x00000180 },
128 { CS42L43_AMP1_2_VOL_RAMP, 0x00000022 },
129 { CS42L43_ASP_CTRL, 0x00000004 },
130 { CS42L43_ASP_FSYNC_CTRL1, 0x000000FA },
131 { CS42L43_ASP_FSYNC_CTRL2, 0x00000001 },
132 { CS42L43_ASP_FSYNC_CTRL3, 0x00000000 },
133 { CS42L43_ASP_FSYNC_CTRL4, 0x000001F4 },
134 { CS42L43_ASP_DATA_CTRL, 0x0000003A },
135 { CS42L43_ASP_RX_EN, 0x00000000 },
136 { CS42L43_ASP_TX_EN, 0x00000000 },
137 { CS42L43_ASP_RX_CH1_CTRL, 0x00170001 },
138 { CS42L43_ASP_RX_CH2_CTRL, 0x00170031 },
139 { CS42L43_ASP_RX_CH3_CTRL, 0x00170061 },
140 { CS42L43_ASP_RX_CH4_CTRL, 0x00170091 },
141 { CS42L43_ASP_RX_CH5_CTRL, 0x001700C1 },
142 { CS42L43_ASP_RX_CH6_CTRL, 0x001700F1 },
143 { CS42L43_ASP_TX_CH1_CTRL, 0x00170001 },
144 { CS42L43_ASP_TX_CH2_CTRL, 0x00170031 },
145 { CS42L43_ASP_TX_CH3_CTRL, 0x00170061 },
146 { CS42L43_ASP_TX_CH4_CTRL, 0x00170091 },
147 { CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 },
148 { CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 },
149 { CS42L43_ASPTX1_INPUT, 0x00000000 },
150 { CS42L43_ASPTX2_INPUT, 0x00000000 },
151 { CS42L43_ASPTX3_INPUT, 0x00000000 },
152 { CS42L43_ASPTX4_INPUT, 0x00000000 },
153 { CS42L43_ASPTX5_INPUT, 0x00000000 },
154 { CS42L43_ASPTX6_INPUT, 0x00000000 },
155 { CS42L43_SWIRE_DP1_CH1_INPUT, 0x00000000 },
156 { CS42L43_SWIRE_DP1_CH2_INPUT, 0x00000000 },
157 { CS42L43_SWIRE_DP1_CH3_INPUT, 0x00000000 },
158 { CS42L43_SWIRE_DP1_CH4_INPUT, 0x00000000 },
159 { CS42L43_SWIRE_DP2_CH1_INPUT, 0x00000000 },
160 { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 },
161 { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 },
162 { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 },
163 { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 },
164 { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 },
165 { CS42L43B_SWIRE_DP3_CH3_INPUT, 0x00000000 },
166 { CS42L43B_SWIRE_DP3_CH4_INPUT, 0x00000000 },
167 { CS42L43B_SWIRE_DP4_CH3_INPUT, 0x00000000 },
168 { CS42L43B_SWIRE_DP4_CH4_INPUT, 0x00000000 },
169 { CS42L43_ASRC_INT1_INPUT1, 0x00000000 },
170 { CS42L43_ASRC_INT2_INPUT1, 0x00000000 },
171 { CS42L43_ASRC_INT3_INPUT1, 0x00000000 },
172 { CS42L43_ASRC_INT4_INPUT1, 0x00000000 },
173 { CS42L43_ASRC_DEC1_INPUT1, 0x00000000 },
174 { CS42L43_ASRC_DEC2_INPUT1, 0x00000000 },
175 { CS42L43_ASRC_DEC3_INPUT1, 0x00000000 },
176 { CS42L43_ASRC_DEC4_INPUT1, 0x00000000 },
177 { CS42L43_ISRC1INT1_INPUT1, 0x00000000 },
178 { CS42L43_ISRC1INT2_INPUT1, 0x00000000 },
179 { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 },
180 { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 },
181 { CS42L43_ISRC2INT1_INPUT1, 0x00000000 },
182 { CS42L43_ISRC2INT2_INPUT1, 0x00000000 },
183 { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 },
184 { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 },
185 { CS42L43_EQ1MIX_INPUT1, 0x00800000 },
186 { CS42L43_EQ1MIX_INPUT2, 0x00800000 },
187 { CS42L43_EQ1MIX_INPUT3, 0x00800000 },
188 { CS42L43_EQ1MIX_INPUT4, 0x00800000 },
189 { CS42L43_EQ2MIX_INPUT1, 0x00800000 },
190 { CS42L43_EQ2MIX_INPUT2, 0x00800000 },
191 { CS42L43_EQ2MIX_INPUT3, 0x00800000 },
192 { CS42L43_EQ2MIX_INPUT4, 0x00800000 },
193 { CS42L43_SPDIF1_INPUT1, 0x00000000 },
194 { CS42L43_SPDIF2_INPUT1, 0x00000000 },
195 { CS42L43_AMP1MIX_INPUT1, 0x00800000 },
196 { CS42L43_AMP1MIX_INPUT2, 0x00800000 },
197 { CS42L43_AMP1MIX_INPUT3, 0x00800000 },
198 { CS42L43_AMP1MIX_INPUT4, 0x00800000 },
199 { CS42L43_AMP2MIX_INPUT1, 0x00800000 },
200 { CS42L43_AMP2MIX_INPUT2, 0x00800000 },
201 { CS42L43_AMP2MIX_INPUT3, 0x00800000 },
202 { CS42L43_AMP2MIX_INPUT4, 0x00800000 },
203 { CS42L43_AMP3MIX_INPUT1, 0x00800000 },
204 { CS42L43_AMP3MIX_INPUT2, 0x00800000 },
205 { CS42L43_AMP3MIX_INPUT3, 0x00800000 },
206 { CS42L43_AMP3MIX_INPUT4, 0x00800000 },
207 { CS42L43_AMP4MIX_INPUT1, 0x00800000 },
208 { CS42L43_AMP4MIX_INPUT2, 0x00800000 },
209 { CS42L43_AMP4MIX_INPUT3, 0x00800000 },
210 { CS42L43_AMP4MIX_INPUT4, 0x00800000 },
211 { CS42L43B_ISRC1DEC3_INPUT1, 0x00000000 },
212 { CS42L43B_ISRC1DEC4_INPUT1, 0x00000000 },
213 { CS42L43B_ISRC2DEC3_INPUT1, 0x00000000 },
214 { CS42L43B_ISRC2DEC4_INPUT1, 0x00000000 },
215 { CS42L43_ASRC_INT_ENABLES, 0x00000100 },
216 { CS42L43_ASRC_DEC_ENABLES, 0x00000100 },
217 { CS42L43_PDNCNTL, 0x00000000 },
218 { CS42L43_RINGSENSE_DEB_CTRL, 0x0000001B },
219 { CS42L43_TIPSENSE_DEB_CTRL, 0x0000001B },
220 { CS42L43_HS2, 0x050106F3 },
221 { CS42L43_STEREO_MIC_CTRL, 0x00000000 },
222 { CS42L43_STEREO_MIC_CLAMP_CTRL, 0x00000001 },
223 { CS42L43_BLOCK_EN2, 0x00000000 },
224 { CS42L43_BLOCK_EN3, 0x00000000 },
225 { CS42L43_BLOCK_EN4, 0x00000000 },
226 { CS42L43_BLOCK_EN5, 0x00000000 },
227 { CS42L43_BLOCK_EN6, 0x00000000 },
228 { CS42L43_BLOCK_EN7, 0x00000000 },
229 { CS42L43_BLOCK_EN8, 0x00000000 },
230 { CS42L43_BLOCK_EN9, 0x00000000 },
231 { CS42L43_BLOCK_EN10, 0x00000000 },
232 { CS42L43_BLOCK_EN11, 0x00000000 },
233 { CS42L43_TONE_CH1_CTRL, 0x00000000 },
234 { CS42L43_TONE_CH2_CTRL, 0x00000000 },
235 { CS42L43_MIC_DETECT_CONTROL_1, 0x00000003 },
236 { CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL, 0x02000003 },
237 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
238 { CS42L43_ISRC1_CTRL, 0x00000000 },
239 { CS42L43_ISRC2_CTRL, 0x00000000 },
240 { CS42L43_CTRL_REG, 0x00000006 },
241 { CS42L43_FDIV_FRAC, 0x40000000 },
242 { CS42L43_CAL_RATIO, 0x00000080 },
243 { CS42L43_SPI_CLK_CONFIG1, 0x00000001 },
244 { CS42L43_SPI_CONFIG1, 0x00000000 },
245 { CS42L43_SPI_CONFIG2, 0x00000000 },
246 { CS42L43_SPI_CONFIG3, 0x00000001 },
247 { CS42L43_SPI_CONFIG4, 0x00000000 },
248 { CS42L43_TRAN_CONFIG3, 0x00000000 },
249 { CS42L43_TRAN_CONFIG4, 0x00000000 },
250 { CS42L43_TRAN_CONFIG5, 0x00000000 },
251 { CS42L43_TRAN_CONFIG6, 0x00000000 },
252 { CS42L43_TRAN_CONFIG7, 0x00000000 },
253 { CS42L43_TRAN_CONFIG8, 0x00000000 },
254 { CS42L43_DACCNFG1, 0x00000008 },
255 { CS42L43_DACCNFG2, 0x00000005 },
256 { CS42L43_HPPATHVOL, 0x011B011B },
257 { CS42L43_PGAVOL, 0x00003470 },
258 { CS42L43_LOADDETENA, 0x00000000 },
259 { CS42L43_CTRL, 0x00000037 },
260 { CS42L43_COEFF_DATA_IN0, 0x00000000 },
261 { CS42L43_COEFF_RD_WR0, 0x00000000 },
262 { CS42L43_START_EQZ0, 0x00000000 },
263 { CS42L43_MUTE_EQ_IN0, 0x00000000 },
264 { CS42L43_DECIM_MASK, 0x0000000F },
265 { CS42L43_EQ_MIX_MASK, 0x0000000F },
266 { CS42L43_ASP_MASK, 0x000000FF },
267 { CS42L43_PLL_MASK, 0x00000003 },
268 { CS42L43_SOFT_MASK, 0x0000FFFF },
269 { CS42L43_SWIRE_MASK, 0x00007FFF },
270 { CS42L43_MSM_MASK, 0x00000FFF },
271 { CS42L43_ACC_DET_MASK, 0x00000FFF },
272 { CS42L43_I2C_TGT_MASK, 0x00000003 },
273 { CS42L43_SPI_MSTR_MASK, 0x00000007 },
274 { CS42L43_SW_TO_SPI_BRIDGE_MASK, 0x00000001 },
275 { CS42L43_OTP_MASK, 0x00000007 },
276 { CS42L43_CLASS_D_AMP_MASK, 0x00003FFF },
277 { CS42L43_GPIO_INT_MASK, 0x0000003F },
278 { CS42L43_ASRC_MASK, 0x0000000F },
279 { CS42L43_HPOUT_MASK, 0x00000003 },
280 };
281 EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, "MFD_CS42L43");
282
cs42l43_readable_register(struct device * dev,unsigned int reg)283 bool cs42l43_readable_register(struct device *dev, unsigned int reg)
284 {
285 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
286
287 switch (reg) {
288 case CS42L43_DEVID:
289 case CS42L43_REVID:
290 case CS42L43_RELID:
291 case CS42L43_SFT_RESET:
292 case CS42L43_DRV_CTRL1:
293 case CS42L43_DRV_CTRL3:
294 case CS42L43_DRV_CTRL4:
295 case CS42L43_DRV_CTRL_5:
296 case CS42L43_GPIO_CTRL1:
297 case CS42L43_GPIO_CTRL2:
298 case CS42L43_GPIO_STS:
299 case CS42L43_GPIO_FN_SEL:
300 case CS42L43_MCLK_SRC_SEL:
301 case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
302 case CS42L43_PLL_CONTROL:
303 case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
304 case CS42L43_PDM_CONTROL:
305 case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
306 case CS42L43_OSC_DIV_SEL:
307 case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2:
308 case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
309 case CS42L43_DMIC_PDM_CTRL:
310 case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
311 case CS42L43_AMP1_2_VOL_RAMP:
312 case CS42L43_ASP_CTRL:
313 case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
314 case CS42L43_ASP_DATA_CTRL:
315 case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
316 case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
317 case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
318 case CS42L43_OTP_REVISION_ID:
319 case CS42L43_ASPTX1_INPUT:
320 case CS42L43_ASPTX2_INPUT:
321 case CS42L43_ASPTX3_INPUT:
322 case CS42L43_ASPTX4_INPUT:
323 case CS42L43_ASPTX5_INPUT:
324 case CS42L43_ASPTX6_INPUT:
325 case CS42L43_SWIRE_DP1_CH1_INPUT:
326 case CS42L43_SWIRE_DP1_CH2_INPUT:
327 case CS42L43_SWIRE_DP1_CH3_INPUT:
328 case CS42L43_SWIRE_DP1_CH4_INPUT:
329 case CS42L43_SWIRE_DP2_CH1_INPUT:
330 case CS42L43_SWIRE_DP2_CH2_INPUT:
331 case CS42L43_SWIRE_DP3_CH1_INPUT:
332 case CS42L43_SWIRE_DP3_CH2_INPUT:
333 case CS42L43_SWIRE_DP4_CH1_INPUT:
334 case CS42L43_SWIRE_DP4_CH2_INPUT:
335 case CS42L43_ASRC_INT1_INPUT1:
336 case CS42L43_ASRC_INT2_INPUT1:
337 case CS42L43_ASRC_INT3_INPUT1:
338 case CS42L43_ASRC_INT4_INPUT1:
339 case CS42L43_ASRC_DEC1_INPUT1:
340 case CS42L43_ASRC_DEC2_INPUT1:
341 case CS42L43_ASRC_DEC3_INPUT1:
342 case CS42L43_ASRC_DEC4_INPUT1:
343 case CS42L43_ISRC1INT1_INPUT1:
344 case CS42L43_ISRC1INT2_INPUT1:
345 case CS42L43_ISRC1DEC1_INPUT1:
346 case CS42L43_ISRC1DEC2_INPUT1:
347 case CS42L43_ISRC2INT1_INPUT1:
348 case CS42L43_ISRC2INT2_INPUT1:
349 case CS42L43_ISRC2DEC1_INPUT1:
350 case CS42L43_ISRC2DEC2_INPUT1:
351 case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
352 case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
353 case CS42L43_SPDIF1_INPUT1:
354 case CS42L43_SPDIF2_INPUT1:
355 case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
356 case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
357 case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
358 case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
359 case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
360 case CS42L43_PDNCNTL:
361 case CS42L43_RINGSENSE_DEB_CTRL:
362 case CS42L43_TIPSENSE_DEB_CTRL:
363 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
364 case CS42L43_HS2:
365 case CS42L43_HS_STAT:
366 case CS42L43_MCU_SW_INTERRUPT:
367 case CS42L43_STEREO_MIC_CTRL:
368 case CS42L43_STEREO_MIC_CLAMP_CTRL:
369 case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
370 case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
371 case CS42L43_MIC_DETECT_CONTROL_1:
372 case CS42L43_DETECT_STATUS_1:
373 case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
374 case CS42L43_MIC_DETECT_CONTROL_ANDROID:
375 case CS42L43_ISRC1_CTRL:
376 case CS42L43_ISRC2_CTRL:
377 case CS42L43_CTRL_REG:
378 case CS42L43_FDIV_FRAC:
379 case CS42L43_CAL_RATIO:
380 case CS42L43_SPI_CLK_CONFIG1:
381 case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
382 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
383 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
384 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
385 case CS42L43_TX_DATA:
386 case CS42L43_RX_DATA:
387 case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
388 case CS42L43_HPPATHVOL:
389 case CS42L43_PGAVOL:
390 case CS42L43_LOADDETRESULTS:
391 case CS42L43_LOADDETENA:
392 case CS42L43_CTRL:
393 case CS42L43_COEFF_DATA_IN0:
394 case CS42L43_COEFF_RD_WR0:
395 case CS42L43_INIT_DONE0:
396 case CS42L43_START_EQZ0:
397 case CS42L43_MUTE_EQ_IN0:
398 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
399 case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
400 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
401 case CS42L43_BOOT_CONTROL:
402 case CS42L43_BLOCK_EN:
403 case CS42L43_SHUTTER_CONTROL:
404 case CS42L43B_MCU_SW_REV ... CS42L43B_MCU_RAM_MAX:
405 return true; // registers present on all variants
406 case CS42L43_MCU_SW_REV ... CS42L43B_MCU_SW_REV - 1:
407 case CS42L43B_MCU_RAM_MAX + 1 ... CS42L43_MCU_RAM_MAX:
408 case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
409 return cs42l43->variant_id == CS42L43_DEVID_VAL; // regs only in CS42L43 variant
410 case CS42L43B_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43B_DECIM_HPF_WNF_CTRL6:
411 case CS42L43B_SWIRE_DP3_CH3_INPUT ... CS42L43B_SWIRE_DP4_CH4_INPUT:
412 case CS42L43B_ISRC1DEC3_INPUT1 ... CS42L43B_ISRC2DEC4_INPUT1:
413 return cs42l43->variant_id == CS42L43B_DEVID_VAL; // regs only in CS42L43B variant
414 default:
415 return false;
416 }
417 }
418 EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, "MFD_CS42L43");
419
cs42l43_precious_register(struct device * dev,unsigned int reg)420 bool cs42l43_precious_register(struct device *dev, unsigned int reg)
421 {
422 switch (reg) {
423 case CS42L43_SFT_RESET:
424 case CS42L43_TX_DATA:
425 case CS42L43_RX_DATA:
426 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
427 case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
428 return true;
429 default:
430 return false;
431 }
432 }
433 EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, "MFD_CS42L43");
434
cs42l43_volatile_register(struct device * dev,unsigned int reg)435 bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
436 {
437 switch (reg) {
438 case CS42L43_DEVID:
439 case CS42L43_REVID:
440 case CS42L43_RELID:
441 case CS42L43_GPIO_STS:
442 case CS42L43_OTP_REVISION_ID:
443 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
444 case CS42L43_HS_STAT:
445 case CS42L43_MCU_SW_INTERRUPT:
446 case CS42L43_DETECT_STATUS_1:
447 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
448 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
449 case CS42L43_TRAN_CONFIG8:
450 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
451 case CS42L43_LOADDETRESULTS:
452 case CS42L43_INIT_DONE0:
453 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
454 case CS42L43_BOOT_CONTROL:
455 case CS42L43_BLOCK_EN:
456 return true;
457 default:
458 return cs42l43_precious_register(dev, reg);
459 }
460 }
461 EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, "MFD_CS42L43");
462
463 #define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
464
465 #define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
466 CS42L43_IRQ_OFFSET(reg), \
467 CS42L43_##name##_INT_MASK)
468
469 static const struct regmap_irq cs42l43_regmap_irqs[] = {
470 CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL),
471 CS42L43_IRQ_REG(PLL_READY, PLL),
472
473 CS42L43_IRQ_REG(HP_STARTUP_DONE, MSM),
474 CS42L43_IRQ_REG(HP_SHUTDOWN_DONE, MSM),
475 CS42L43_IRQ_REG(HSDET_DONE, MSM),
476 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB, MSM),
477 CS42L43_IRQ_REG(TIPSENSE_PLUG_DB, MSM),
478 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB, MSM),
479 CS42L43_IRQ_REG(RINGSENSE_PLUG_DB, MSM),
480 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET, MSM),
481 CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET, MSM),
482 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET, MSM),
483 CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET, MSM),
484
485 CS42L43_IRQ_REG(HS2_BIAS_SENSE, ACC_DET),
486 CS42L43_IRQ_REG(HS1_BIAS_SENSE, ACC_DET),
487 CS42L43_IRQ_REG(DC_DETECT1_FALSE, ACC_DET),
488 CS42L43_IRQ_REG(DC_DETECT1_TRUE, ACC_DET),
489 CS42L43_IRQ_REG(HSBIAS_CLAMPED, ACC_DET),
490 CS42L43_IRQ_REG(HS3_4_BIAS_SENSE, ACC_DET),
491
492 CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT, CLASS_D_AMP),
493 CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT, CLASS_D_AMP),
494 CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT, CLASS_D_AMP),
495 CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT, CLASS_D_AMP),
496 CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE, CLASS_D_AMP),
497 CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE, CLASS_D_AMP),
498 CS42L43_IRQ_REG(AMP2_STARTUP_DONE, CLASS_D_AMP),
499 CS42L43_IRQ_REG(AMP1_STARTUP_DONE, CLASS_D_AMP),
500 CS42L43_IRQ_REG(AMP2_THERM_SHDN, CLASS_D_AMP),
501 CS42L43_IRQ_REG(AMP1_THERM_SHDN, CLASS_D_AMP),
502 CS42L43_IRQ_REG(AMP2_THERM_WARN, CLASS_D_AMP),
503 CS42L43_IRQ_REG(AMP1_THERM_WARN, CLASS_D_AMP),
504 CS42L43_IRQ_REG(AMP2_SCDET, CLASS_D_AMP),
505 CS42L43_IRQ_REG(AMP1_SCDET, CLASS_D_AMP),
506
507 CS42L43_IRQ_REG(GPIO3_FALL, GPIO),
508 CS42L43_IRQ_REG(GPIO3_RISE, GPIO),
509 CS42L43_IRQ_REG(GPIO2_FALL, GPIO),
510 CS42L43_IRQ_REG(GPIO2_RISE, GPIO),
511 CS42L43_IRQ_REG(GPIO1_FALL, GPIO),
512 CS42L43_IRQ_REG(GPIO1_RISE, GPIO),
513
514 CS42L43_IRQ_REG(HP_ILIMIT, HPOUT),
515 CS42L43_IRQ_REG(HP_LOADDET_DONE, HPOUT),
516 };
517
518 static const struct regmap_irq_chip cs42l43_irq_chip = {
519 .name = "cs42l43",
520
521 .status_base = CS42L43_DECIM_INT,
522 .mask_base = CS42L43_DECIM_MASK,
523 .num_regs = 16,
524
525 .irqs = cs42l43_regmap_irqs,
526 .num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
527
528 .runtime_pm = true,
529 };
530
531 static const char * const cs42l43_core_supplies[] = {
532 "vdd-a", "vdd-io", "vdd-cp",
533 };
534
535 static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
536
537 static const struct mfd_cell cs42l43_devs[] = {
538 { .name = "cs42l43-pinctrl", },
539 { .name = "cs42l43-spi", },
540 {
541 .name = "cs42l43-codec",
542 .parent_supplies = cs42l43_parent_supplies,
543 .num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
544 },
545 };
546
547 /*
548 * If the device is connected over Soundwire, as well as soft resetting the
549 * device, this function will also way for the device to detach from the bus
550 * before returning.
551 */
cs42l43_soft_reset(struct cs42l43 * cs42l43)552 static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
553 {
554 static const struct reg_sequence reset[] = {
555 { CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
556 };
557
558 reinit_completion(&cs42l43->device_detach);
559
560 /*
561 * Apply cache only because the soft reset will cause the device to
562 * detach from the soundwire bus.
563 */
564 regcache_cache_only(cs42l43->regmap, true);
565 regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
566
567 msleep(CS42L43_RESET_DELAY_MS);
568
569 if (cs42l43->sdw) {
570 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT_MS);
571 unsigned long time;
572
573 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
574 if (!time) {
575 dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
576 return -ETIMEDOUT;
577 }
578 }
579
580 return -EAGAIN;
581 }
582
583 /*
584 * This function is essentially a no-op on I2C, but will wait for the device to
585 * attach when the device is used on a SoundWire bus.
586 */
cs42l43_wait_for_attach(struct cs42l43 * cs42l43)587 static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
588 {
589 int ret;
590
591 ret = sdw_slave_wait_for_init(cs42l43->sdw, CS42L43_SDW_ATTACH_TIMEOUT_MS);
592 if (ret)
593 return ret;
594
595 regcache_cache_only(cs42l43->regmap, false);
596
597 /* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
598 if (cs42l43->sdw)
599 regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
600 CS42L43_OSC_DIV2_EN_MASK);
601
602 return 0;
603 }
604
605 /*
606 * This function will advance the firmware into boot stage 3 from boot stage 2.
607 * Boot stage 3 is required to send commands to the firmware. This is achieved
608 * by setting the firmware NEED configuration register to zero, this indicates
609 * no configuration is required forcing the firmware to advance to boot stage 3.
610 *
611 * Later revisions of the firmware require the use of an alternative register
612 * for this purpose, which is indicated through the shadow flag.
613 */
cs42l43_mcu_stage_2_3(struct cs42l43 * cs42l43,bool shadow)614 static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
615 {
616 unsigned int need_reg = CS42L43_NEED_CONFIGS;
617 unsigned int boot_reg;
618 unsigned int val;
619 int ret;
620
621 switch (cs42l43->variant_id) {
622 case CS42L43_DEVID_VAL:
623 if (shadow)
624 need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
625 boot_reg = CS42L43_BOOT_STATUS;
626 break;
627 case CS42L43B_DEVID_VAL:
628 need_reg = CS42L43B_NEED_CONFIGS;
629 boot_reg = CS42L43B_BOOT_STATUS;
630 break;
631 default:
632 return -EINVAL;
633 }
634
635 regmap_write(cs42l43->regmap, need_reg, 0);
636
637 ret = regmap_read_poll_timeout(cs42l43->regmap, boot_reg,
638 val, (val == CS42L43_MCU_BOOT_STAGE3),
639 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
640 if (ret) {
641 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
642 return ret;
643 }
644
645 return -EAGAIN;
646 }
647
648 /*
649 * This function will return the firmware to boot stage 2 from boot stage 3.
650 * Boot stage 2 is required to apply updates to the firmware. This is achieved
651 * by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
652 * setting the HAVE configuration register to 0, and soft resetting. The
653 * firmware will see it is missing a patch configuration and will pause in boot
654 * stage 2.
655 *
656 * Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
657 * register here as the driver will only return to boot stage 2 if the firmware
658 * requires update which means the revision does not include shadow register
659 * support.
660 */
cs42l43_mcu_stage_3_2(struct cs42l43 * cs42l43)661 static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
662 {
663 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
664 CS42L43_FW_PATCH_NEED_CFG_MASK);
665 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
666
667 return cs42l43_soft_reset(cs42l43);
668 }
669
670 /*
671 * Disable the firmware running on the device such that the driver can access
672 * the registers without fear of the MCU changing them under it.
673 */
cs42l43_mcu_disable(struct cs42l43 * cs42l43)674 static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
675 {
676 unsigned int val, cfg_reg, ctrl_reg;
677 int ret;
678
679 switch (cs42l43->variant_id) {
680 case CS42L43_DEVID_VAL:
681 cfg_reg = CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG;
682 ctrl_reg = CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION;
683 break;
684 case CS42L43B_DEVID_VAL:
685 cfg_reg = CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG;
686 ctrl_reg = CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION;
687 break;
688 default:
689 return -EINVAL;
690 }
691
692 regmap_write(cs42l43->regmap, cfg_reg, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
693 regmap_write(cs42l43->regmap, ctrl_reg, CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
694
695 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
696 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
697
698 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
699 (val & CS42L43_CONTROL_APPLIED_INT_MASK),
700 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
701 if (ret) {
702 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
703 return ret;
704 }
705
706 /* Soft reset to clear any register state the firmware left behind. */
707 return cs42l43_soft_reset(cs42l43);
708 }
709
710 /*
711 * Callback to load firmware updates.
712 */
cs42l43_mcu_load_firmware(const struct firmware * firmware,void * context)713 static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
714 {
715 struct cs42l43 *cs42l43 = context;
716 const struct cs42l43_patch_header *hdr;
717 unsigned int loadaddr, val;
718 int ret;
719
720 if (!firmware || firmware->size < sizeof(*hdr)) {
721 dev_err(cs42l43->dev, "Failed to load firmware\n");
722 cs42l43->firmware_error = -ENODEV;
723 goto err;
724 }
725
726 hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
727 loadaddr = le32_to_cpu(hdr->load_addr);
728
729 if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
730 dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
731 cs42l43->firmware_error = -EINVAL;
732 goto err_release;
733 }
734
735 regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
736 regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
737 &firmware->data[0], firmware->size / sizeof(u32));
738
739 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
740 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
741
742 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
743 (val & CS42L43_PATCH_APPLIED_INT_MASK),
744 CS42L43_MCU_POLL_US, CS42L43_MCU_UPDATE_TIMEOUT_US);
745 if (ret) {
746 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
747 cs42l43->firmware_error = ret;
748 goto err_release;
749 }
750
751 err_release:
752 release_firmware(firmware);
753 err:
754 complete(&cs42l43->firmware_download);
755 }
756
cs42l43_mcu_is_hw_compatible(struct cs42l43 * cs42l43,unsigned int mcu_rev,unsigned int bios_rev)757 static int cs42l43_mcu_is_hw_compatible(struct cs42l43 *cs42l43,
758 unsigned int mcu_rev,
759 unsigned int bios_rev)
760 {
761 /*
762 * The firmware has two revision numbers bringing either of them up to a
763 * supported version will provide the disable the driver requires.
764 */
765 if (mcu_rev < CS42L43_MCU_SUPPORTED_REV &&
766 bios_rev < CS42L43_MCU_SUPPORTED_BIOS_REV) {
767 dev_err(cs42l43->dev, "Firmware too old to support disable\n");
768 return -EINVAL;
769 }
770
771 return 0;
772 }
773
774 /*
775 * The process of updating the firmware is split into a series of steps, at the
776 * end of each step a soft reset of the device might be required which will
777 * require the driver to wait for the device to re-attach on the SoundWire bus,
778 * if that control bus is being used.
779 */
cs42l43_mcu_update_step(struct cs42l43 * cs42l43)780 static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
781 {
782 unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
783 bool patched, shadow;
784 int boot_status_reg, mcu_sw_rev_reg;
785 int ret;
786
787 switch (cs42l43->variant_id) {
788 case CS42L43_DEVID_VAL:
789 boot_status_reg = CS42L43_BOOT_STATUS;
790 mcu_sw_rev_reg = CS42L43_MCU_SW_REV;
791 break;
792 case CS42L43B_DEVID_VAL:
793 boot_status_reg = CS42L43B_BOOT_STATUS;
794 mcu_sw_rev_reg = CS42L43B_MCU_SW_REV;
795 break;
796 default:
797 return -EINVAL;
798 }
799
800 /* Clear any stale software interrupt bits. */
801 regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
802
803 ret = regmap_read(cs42l43->regmap, boot_status_reg, &boot_status);
804 if (ret) {
805 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
806 return ret;
807 }
808
809 ret = regmap_read(cs42l43->regmap, mcu_sw_rev_reg, &mcu_rev);
810 if (ret) {
811 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
812 return ret;
813 }
814
815 bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
816 ((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
817 ((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
818 CS42L43_BIOS_MAJOR_REV_SHIFT;
819 mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
820 ((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
821 ((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
822
823 /*
824 * The firmware has two revision numbers both of them being at the ROM
825 * revision indicates no patch has been applied.
826 */
827 patched = mcu_rev != CS42L43_MCU_ROM_REV || bios_rev != CS42L43_MCU_ROM_BIOS_REV;
828 /*
829 * Later versions of the firmwware require the driver to access some
830 * features through a set of shadow registers.
831 */
832 shadow = (mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV) ||
833 (bios_rev >= CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV);
834
835 ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
836 if (ret) {
837 dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
838 return ret;
839 }
840
841 cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
842
843 if (!patched && cs42l43->hw_lock) {
844 dev_err(cs42l43->dev, "Unpatched secure device\n");
845 return -EPERM;
846 }
847
848 dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
849 mcu_rev, bios_rev, boot_status);
850
851 switch (boot_status) {
852 case CS42L43_MCU_BOOT_STAGE2:
853 if (!patched) {
854 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
855 "cs42l43.bin", cs42l43->dev,
856 GFP_KERNEL, cs42l43,
857 cs42l43_mcu_load_firmware);
858 if (ret) {
859 dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
860 return ret;
861 }
862
863 wait_for_completion(&cs42l43->firmware_download);
864
865 if (cs42l43->firmware_error)
866 return cs42l43->firmware_error;
867
868 return -EAGAIN;
869 } else {
870 return cs42l43_mcu_stage_2_3(cs42l43, shadow);
871 }
872 case CS42L43_MCU_BOOT_STAGE3:
873 if (patched) {
874 ret = cs42l43_mcu_is_hw_compatible(cs42l43, mcu_rev, bios_rev);
875 if (ret)
876 return ret;
877
878 return cs42l43_mcu_disable(cs42l43);
879 } else {
880 return cs42l43_mcu_stage_3_2(cs42l43);
881 }
882 case CS42L43_MCU_BOOT_STAGE4:
883 return 0;
884 default:
885 dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
886 return -EINVAL;
887 }
888 }
889
890 /*
891 * Update the firmware running on the device.
892 */
cs42l43_mcu_update(struct cs42l43 * cs42l43)893 static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
894 {
895 int i, ret;
896
897 for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
898 ret = cs42l43_mcu_update_step(cs42l43);
899 if (ret != -EAGAIN)
900 return ret;
901
902 ret = cs42l43_wait_for_attach(cs42l43);
903 if (ret)
904 return ret;
905 }
906
907 dev_err(cs42l43->dev, "Failed retrying update\n");
908 return -ETIMEDOUT;
909 }
910
cs42l43_irq_config(struct cs42l43 * cs42l43)911 static int cs42l43_irq_config(struct cs42l43 *cs42l43)
912 {
913 struct irq_data *irq_data;
914 unsigned long irq_flags;
915 int ret;
916
917 if (cs42l43->sdw)
918 cs42l43->irq = cs42l43->sdw->irq;
919
920 cs42l43->irq_chip = cs42l43_irq_chip;
921 cs42l43->irq_chip.irq_drv_data = cs42l43;
922
923 irq_data = irq_get_irq_data(cs42l43->irq);
924 if (!irq_data) {
925 dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
926 return -EINVAL;
927 }
928
929 irq_flags = irqd_get_trigger_type(irq_data);
930 switch (irq_flags) {
931 case IRQF_TRIGGER_LOW:
932 case IRQF_TRIGGER_HIGH:
933 case IRQF_TRIGGER_RISING:
934 case IRQF_TRIGGER_FALLING:
935 break;
936 case IRQ_TYPE_NONE:
937 default:
938 irq_flags = IRQF_TRIGGER_LOW;
939 break;
940 }
941
942 irq_flags |= IRQF_ONESHOT;
943
944 ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
945 cs42l43->irq, irq_flags, 0,
946 &cs42l43->irq_chip, &cs42l43->irq_data);
947 if (ret) {
948 dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
949 return ret;
950 }
951
952 dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
953 cs42l43->irq, irq_flags);
954
955 return 0;
956 }
957
cs42l43_boot_work(struct work_struct * work)958 static void cs42l43_boot_work(struct work_struct *work)
959 {
960 struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
961 unsigned int devid, revid, otp;
962 int ret;
963
964 ret = cs42l43_wait_for_attach(cs42l43);
965 if (ret)
966 goto err;
967
968 ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
969 if (ret) {
970 dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
971 goto err;
972 }
973
974 switch (devid) {
975 case CS42L43_DEVID_VAL:
976 case CS42L43B_DEVID_VAL:
977 if (devid != cs42l43->variant_id) {
978 dev_err(cs42l43->dev,
979 "Device ID (0x%06x) does not match variant ID (0x%06lx)\n",
980 devid, cs42l43->variant_id);
981 goto err;
982 }
983 break;
984 default:
985 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
986 goto err;
987 }
988
989 ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
990 if (ret) {
991 dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
992 goto err;
993 }
994
995 ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
996 if (ret) {
997 dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
998 goto err;
999 }
1000
1001 dev_info(cs42l43->dev,
1002 "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
1003
1004 ret = cs42l43_mcu_update(cs42l43);
1005 if (ret)
1006 goto err;
1007
1008 ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
1009 ARRAY_SIZE(cs42l43_reva_patch));
1010 if (ret) {
1011 dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
1012 goto err;
1013 }
1014
1015 ret = cs42l43_irq_config(cs42l43);
1016 if (ret)
1017 goto err;
1018
1019 ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
1020 cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
1021 NULL, 0, NULL);
1022 if (ret) {
1023 dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
1024 goto err;
1025 }
1026
1027 pm_runtime_put_autosuspend(cs42l43->dev);
1028
1029 return;
1030
1031 err:
1032 pm_runtime_put_sync(cs42l43->dev);
1033 }
1034
cs42l43_power_up(struct cs42l43 * cs42l43)1035 static int cs42l43_power_up(struct cs42l43 *cs42l43)
1036 {
1037 int ret;
1038
1039 ret = regulator_enable(cs42l43->vdd_p);
1040 if (ret) {
1041 dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
1042 return ret;
1043 }
1044
1045 /* vdd-p must be on for 50uS before any other supply */
1046 usleep_range(CS42L43_VDDP_DELAY_US, 2 * CS42L43_VDDP_DELAY_US);
1047
1048 gpiod_set_raw_value_cansleep(cs42l43->reset, 1);
1049
1050 ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1051 if (ret) {
1052 dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
1053 goto err_reset;
1054 }
1055
1056 ret = regulator_enable(cs42l43->vdd_d);
1057 if (ret) {
1058 dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
1059 goto err_core_supplies;
1060 }
1061
1062 usleep_range(CS42L43_VDDD_DELAY_US, 2 * CS42L43_VDDD_DELAY_US);
1063
1064 return 0;
1065
1066 err_core_supplies:
1067 regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1068 err_reset:
1069 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1070 regulator_disable(cs42l43->vdd_p);
1071
1072 return ret;
1073 }
1074
cs42l43_power_down(struct cs42l43 * cs42l43)1075 static int cs42l43_power_down(struct cs42l43 *cs42l43)
1076 {
1077 int ret;
1078
1079 ret = regulator_disable(cs42l43->vdd_d);
1080 if (ret) {
1081 dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
1082 return ret;
1083 }
1084
1085 ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1086 if (ret) {
1087 dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
1088 return ret;
1089 }
1090
1091 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1092
1093 ret = regulator_disable(cs42l43->vdd_p);
1094 if (ret) {
1095 dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
1096 return ret;
1097 }
1098
1099 return 0;
1100 }
1101
cs42l43_dev_remove(void * data)1102 static void cs42l43_dev_remove(void *data)
1103 {
1104 struct cs42l43 *cs42l43 = data;
1105
1106 cancel_work_sync(&cs42l43->boot_work);
1107
1108 cs42l43_power_down(cs42l43);
1109 }
1110
cs42l43_dev_probe(struct cs42l43 * cs42l43)1111 int cs42l43_dev_probe(struct cs42l43 *cs42l43)
1112 {
1113 int i, ret;
1114
1115 dev_set_drvdata(cs42l43->dev, cs42l43);
1116
1117 mutex_init(&cs42l43->pll_lock);
1118 init_completion(&cs42l43->device_detach);
1119 init_completion(&cs42l43->firmware_download);
1120 INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
1121
1122 regcache_cache_only(cs42l43->regmap, true);
1123
1124 cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_HIGH);
1125 if (IS_ERR(cs42l43->reset))
1126 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
1127 "Failed to get reset\n");
1128
1129 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1130
1131 cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
1132 if (IS_ERR(cs42l43->vdd_p))
1133 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
1134 "Failed to get vdd-p\n");
1135
1136 cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
1137 if (IS_ERR(cs42l43->vdd_d))
1138 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
1139 "Failed to get vdd-d\n");
1140
1141 BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
1142
1143 for (i = 0; i < CS42L43_N_SUPPLIES; i++)
1144 cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
1145
1146 ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
1147 cs42l43->core_supplies);
1148 if (ret)
1149 return dev_err_probe(cs42l43->dev, ret,
1150 "Failed to get core supplies\n");
1151
1152 ret = cs42l43_power_up(cs42l43);
1153 if (ret)
1154 return ret;
1155
1156 ret = devm_add_action_or_reset(cs42l43->dev, cs42l43_dev_remove, cs42l43);
1157 if (ret)
1158 return ret;
1159
1160 pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME_MS);
1161 pm_runtime_use_autosuspend(cs42l43->dev);
1162 pm_runtime_set_active(cs42l43->dev);
1163 /*
1164 * The device is already powered up, but keep it from suspending until
1165 * the boot work runs.
1166 */
1167 pm_runtime_get_noresume(cs42l43->dev);
1168 ret = devm_pm_runtime_enable(cs42l43->dev);
1169 if (ret)
1170 return ret;
1171
1172 queue_work(system_long_wq, &cs42l43->boot_work);
1173
1174 return 0;
1175 }
1176 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, "MFD_CS42L43");
1177
cs42l43_suspend(struct device * dev)1178 static int cs42l43_suspend(struct device *dev)
1179 {
1180 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1181 int ret;
1182
1183 ret = pm_runtime_resume_and_get(dev);
1184 if (ret) {
1185 dev_err(cs42l43->dev, "Failed to resume for suspend: %d\n", ret);
1186 return ret;
1187 }
1188
1189 disable_irq(cs42l43->irq);
1190
1191 ret = pm_runtime_force_suspend(dev);
1192 if (ret) {
1193 dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
1194 pm_runtime_put_noidle(dev);
1195 return ret;
1196 }
1197
1198 pm_runtime_put_noidle(dev);
1199
1200 ret = cs42l43_power_down(cs42l43);
1201 if (ret)
1202 return ret;
1203
1204 return 0;
1205 }
1206
cs42l43_suspend_noirq(struct device * dev)1207 static int cs42l43_suspend_noirq(struct device *dev)
1208 {
1209 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1210
1211 enable_irq(cs42l43->irq);
1212
1213 return 0;
1214 }
1215
cs42l43_resume_noirq(struct device * dev)1216 static int cs42l43_resume_noirq(struct device *dev)
1217 {
1218 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1219
1220 disable_irq(cs42l43->irq);
1221
1222 return 0;
1223 }
1224
cs42l43_resume(struct device * dev)1225 static int cs42l43_resume(struct device *dev)
1226 {
1227 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1228 int ret;
1229
1230 ret = cs42l43_power_up(cs42l43);
1231 if (ret)
1232 return ret;
1233
1234 ret = pm_runtime_force_resume(dev);
1235 if (ret) {
1236 dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
1237 return ret;
1238 }
1239
1240 enable_irq(cs42l43->irq);
1241
1242 return 0;
1243 }
1244
cs42l43_runtime_suspend(struct device * dev)1245 static int cs42l43_runtime_suspend(struct device *dev)
1246 {
1247 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1248
1249 /*
1250 * Whilst the driver doesn't power the chip down here, going into runtime
1251 * suspend lets the SoundWire bus power down, which means the driver
1252 * can't communicate with the device any more.
1253 */
1254 regcache_cache_only(cs42l43->regmap, true);
1255
1256 return 0;
1257 }
1258
cs42l43_runtime_resume(struct device * dev)1259 static int cs42l43_runtime_resume(struct device *dev)
1260 {
1261 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1262 unsigned int reset_canary;
1263 int ret;
1264
1265 ret = cs42l43_wait_for_attach(cs42l43);
1266 if (ret)
1267 return ret;
1268
1269 ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
1270 if (ret) {
1271 dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
1272 goto err;
1273 }
1274
1275 if (!reset_canary) {
1276 /*
1277 * If the canary has cleared the chip has reset, re-handle the
1278 * MCU and mark the cache as dirty to indicate the chip reset.
1279 */
1280 ret = cs42l43_mcu_update(cs42l43);
1281 if (ret)
1282 goto err;
1283
1284 regcache_mark_dirty(cs42l43->regmap);
1285 }
1286
1287 ret = regcache_sync(cs42l43->regmap);
1288 if (ret) {
1289 dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
1290 goto err;
1291 }
1292
1293 return 0;
1294
1295 err:
1296 regcache_cache_only(cs42l43->regmap, true);
1297
1298 return ret;
1299 }
1300
1301 EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1302 SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
1303 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend_noirq, cs42l43_resume_noirq)
1304 RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1305 };
1306
1307 MODULE_DESCRIPTION("CS42L43 Core Driver");
1308 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1309 MODULE_LICENSE("GPL");
1310 MODULE_FIRMWARE("cs42l43.bin");
1311