1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/string_helpers.h>
28 #include <linux/uaccess.h>
29 #include <media/cec-notifier.h>
30
31 #include "dc.h"
32 #include "amdgpu.h"
33 #include "amdgpu_dm.h"
34 #include "amdgpu_dm_debugfs.h"
35 #include "amdgpu_dm_replay.h"
36 #include "dm_helpers.h"
37 #include "dmub/dmub_srv.h"
38 #include "resource.h"
39 #include "dsc.h"
40 #include "link_hwss.h"
41 #include "dc/dc_dmub_srv.h"
42 #include "link/protocols/link_dp_capability.h"
43 #include "inc/hw/dchubbub.h"
44
45 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
46 #include "amdgpu_dm_psr.h"
47 #endif
48
49 #define MULTIPLIER_TO_LR 270000
50 struct dmub_debugfs_trace_header {
51 uint32_t entry_count;
52 uint32_t reserved[3];
53 };
54
55 struct dmub_debugfs_trace_entry {
56 uint32_t trace_code;
57 uint32_t tick_count;
58 uint32_t param0;
59 uint32_t param1;
60 };
61
62 static const char *const mst_progress_status[] = {
63 "probe",
64 "remote_edid",
65 "allocate_new_payload",
66 "clear_allocated_payload",
67 };
68
69 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
70 *
71 * Function takes in attributes passed to debugfs write entry
72 * and writes into param array.
73 * The user passes max_param_num to identify maximum number of
74 * parameters that could be parsed.
75 *
76 */
parse_write_buffer_into_params(char * wr_buf,uint32_t wr_buf_size,long * param,const char __user * buf,int max_param_num,uint8_t * param_nums)77 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
78 long *param, const char __user *buf,
79 int max_param_num,
80 uint8_t *param_nums)
81 {
82 char *wr_buf_ptr = NULL;
83 uint32_t wr_buf_count = 0;
84 int r;
85 char *sub_str = NULL;
86 const char delimiter[3] = {' ', '\n', '\0'};
87 uint8_t param_index = 0;
88
89 *param_nums = 0;
90
91 wr_buf_ptr = wr_buf;
92
93 /* r is bytes not be copied */
94 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
95 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
96 return -EFAULT;
97 }
98
99 /* check number of parameters. isspace could not differ space and\n */
100 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
101 /* skip space*/
102 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
103 wr_buf_ptr++;
104 wr_buf_count++;
105 }
106
107 if (wr_buf_count == wr_buf_size)
108 break;
109
110 /* skip non-space*/
111 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
112 wr_buf_ptr++;
113 wr_buf_count++;
114 }
115
116 (*param_nums)++;
117
118 if (wr_buf_count == wr_buf_size)
119 break;
120 }
121
122 if (*param_nums > max_param_num)
123 *param_nums = max_param_num;
124
125 wr_buf_ptr = wr_buf; /* reset buf pointer */
126 wr_buf_count = 0; /* number of char already checked */
127
128 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
129 wr_buf_ptr++;
130 wr_buf_count++;
131 }
132
133 while (param_index < *param_nums) {
134 /* after strsep, wr_buf_ptr will be moved to after space */
135 sub_str = strsep(&wr_buf_ptr, delimiter);
136
137 r = kstrtol(sub_str, 16, &(param[param_index]));
138
139 if (r)
140 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
141
142 param_index++;
143 }
144
145 return 0;
146 }
147
148 /* function description
149 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
150 *
151 * valid lane count value: 1, 2, 4
152 * valid link rate value:
153 * 06h = 1.62Gbps per lane
154 * 0Ah = 2.7Gbps per lane
155 * 0Ch = 3.24Gbps per lane
156 * 14h = 5.4Gbps per lane
157 * 1Eh = 8.1Gbps per lane
158 *
159 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
160 *
161 * --- to get dp configuration
162 *
163 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
164 *
165 * It will list current, verified, reported, preferred dp configuration.
166 * current -- for current video mode
167 * verified --- maximum configuration which pass link training
168 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
169 * preferred --- user force settings
170 *
171 * --- set (or force) dp configuration
172 *
173 * echo <lane_count> <link_rate> > link_settings
174 *
175 * for example, to force to 2 lane, 2.7GHz,
176 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
177 *
178 * spread_spectrum could not be changed dynamically.
179 *
180 * in case invalid lane count, link rate are force, no hw programming will be
181 * done. please check link settings after force operation to see if HW get
182 * programming.
183 *
184 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
185 *
186 * check current and preferred settings.
187 *
188 */
dp_link_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)189 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
190 size_t size, loff_t *pos)
191 {
192 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
193 struct dc_link *link = connector->dc_link;
194 char *rd_buf = NULL;
195 char *rd_buf_ptr = NULL;
196 const uint32_t rd_buf_size = 100;
197 uint32_t result = 0;
198 uint8_t str_len = 0;
199 int r;
200
201 if (*pos & 3 || size & 3)
202 return -EINVAL;
203
204 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
205 if (!rd_buf)
206 return 0;
207
208 rd_buf_ptr = rd_buf;
209
210 str_len = strlen("Current: %d 0x%x %d ");
211 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ",
212 link->cur_link_settings.lane_count,
213 link->cur_link_settings.link_rate,
214 link->cur_link_settings.link_spread);
215 rd_buf_ptr += str_len;
216
217 str_len = strlen("Verified: %d 0x%x %d ");
218 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ",
219 link->verified_link_cap.lane_count,
220 link->verified_link_cap.link_rate,
221 link->verified_link_cap.link_spread);
222 rd_buf_ptr += str_len;
223
224 str_len = strlen("Reported: %d 0x%x %d ");
225 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ",
226 link->reported_link_cap.lane_count,
227 link->reported_link_cap.link_rate,
228 link->reported_link_cap.link_spread);
229 rd_buf_ptr += str_len;
230
231 str_len = strlen("Preferred: %d 0x%x %d ");
232 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n",
233 link->preferred_link_setting.lane_count,
234 link->preferred_link_setting.link_rate,
235 link->preferred_link_setting.link_spread);
236
237 while (size) {
238 if (*pos >= rd_buf_size)
239 break;
240
241 r = put_user(*(rd_buf + result), buf);
242 if (r) {
243 kfree(rd_buf);
244 return r; /* r = -EFAULT */
245 }
246
247 buf += 1;
248 size -= 1;
249 *pos += 1;
250 result += 1;
251 }
252
253 kfree(rd_buf);
254 return result;
255 }
256
dp_link_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)257 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
258 size_t size, loff_t *pos)
259 {
260 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
261 struct dc_link *link = connector->dc_link;
262 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
263 struct dc *dc = (struct dc *)link->dc;
264 struct dc_link_settings prefer_link_settings = {0};
265 char *wr_buf = NULL;
266 const uint32_t wr_buf_size = 40;
267 /* 0: lane_count; 1: link_rate */
268 int max_param_num = 2;
269 uint8_t param_nums = 0;
270 long param[2];
271 bool valid_input = true;
272
273 if (size == 0)
274 return -EINVAL;
275
276 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
277 if (!wr_buf)
278 return -ENOSPC;
279
280 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
281 (long *)param, buf,
282 max_param_num,
283 ¶m_nums)) {
284 kfree(wr_buf);
285 return -EINVAL;
286 }
287
288 if (param_nums <= 0) {
289 kfree(wr_buf);
290 DRM_DEBUG_DRIVER("user data not be read\n");
291 return -EINVAL;
292 }
293
294 switch (param[0]) {
295 case LANE_COUNT_ONE:
296 case LANE_COUNT_TWO:
297 case LANE_COUNT_FOUR:
298 break;
299 default:
300 valid_input = false;
301 break;
302 }
303
304 switch (param[1]) {
305 case LINK_RATE_LOW:
306 case LINK_RATE_RATE_2:
307 case LINK_RATE_RATE_3:
308 case LINK_RATE_HIGH:
309 case LINK_RATE_RBR2:
310 case LINK_RATE_RATE_6:
311 case LINK_RATE_HIGH2:
312 case LINK_RATE_HIGH3:
313 case LINK_RATE_UHBR10:
314 case LINK_RATE_UHBR13_5:
315 case LINK_RATE_UHBR20:
316 break;
317 default:
318 valid_input = false;
319 break;
320 }
321
322 if (!valid_input) {
323 kfree(wr_buf);
324 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
325 mutex_lock(&adev->dm.dc_lock);
326 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
327 mutex_unlock(&adev->dm.dc_lock);
328 return size;
329 }
330
331 /* save user force lane_count, link_rate to preferred settings
332 * spread spectrum will not be changed
333 */
334 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
335 prefer_link_settings.use_link_rate_set = false;
336 prefer_link_settings.lane_count = param[0];
337 prefer_link_settings.link_rate = param[1];
338
339 mutex_lock(&adev->dm.dc_lock);
340 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
341 mutex_unlock(&adev->dm.dc_lock);
342
343 kfree(wr_buf);
344 return size;
345 }
346
dp_mst_is_end_device(struct amdgpu_dm_connector * aconnector)347 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
348 {
349 bool is_end_device = false;
350 struct drm_dp_mst_topology_mgr *mgr = NULL;
351 struct drm_dp_mst_port *port = NULL;
352
353 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
354 mgr = &aconnector->mst_root->mst_mgr;
355 port = aconnector->mst_output_port;
356
357 drm_modeset_lock(&mgr->base.lock, NULL);
358 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
359 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
360 is_end_device = true;
361 drm_modeset_unlock(&mgr->base.lock);
362 }
363
364 return is_end_device;
365 }
366
367 /* Change MST link setting
368 *
369 * valid lane count value: 1, 2, 4
370 * valid link rate value:
371 * 06h = 1.62Gbps per lane
372 * 0Ah = 2.7Gbps per lane
373 * 0Ch = 3.24Gbps per lane
374 * 14h = 5.4Gbps per lane
375 * 1Eh = 8.1Gbps per lane
376 * 3E8h = 10.0Gbps per lane
377 * 546h = 13.5Gbps per lane
378 * 7D0h = 20.0Gbps per lane
379 *
380 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
381 *
382 * for example, to force to 2 lane, 10.0GHz,
383 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
384 *
385 * Valid input will trigger hotplug event to get new link setting applied
386 * Invalid input will trigger training setting reset
387 *
388 * The usage can be referred to link_settings entry
389 *
390 */
dp_mst_link_setting(struct file * f,const char __user * buf,size_t size,loff_t * pos)391 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
392 size_t size, loff_t *pos)
393 {
394 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
395 struct dc_link *link = aconnector->dc_link;
396 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
397 struct dc *dc = (struct dc *)link->dc;
398 struct dc_link_settings prefer_link_settings = {0};
399 char *wr_buf = NULL;
400 const uint32_t wr_buf_size = 40;
401 /* 0: lane_count; 1: link_rate */
402 int max_param_num = 2;
403 uint8_t param_nums = 0;
404 long param[2];
405 bool valid_input = true;
406
407 if (!dp_mst_is_end_device(aconnector))
408 return -EINVAL;
409
410 if (size == 0)
411 return -EINVAL;
412
413 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
414 if (!wr_buf)
415 return -ENOSPC;
416
417 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
418 (long *)param, buf,
419 max_param_num,
420 ¶m_nums)) {
421 kfree(wr_buf);
422 return -EINVAL;
423 }
424
425 if (param_nums <= 0) {
426 kfree(wr_buf);
427 DRM_DEBUG_DRIVER("user data not be read\n");
428 return -EINVAL;
429 }
430
431 switch (param[0]) {
432 case LANE_COUNT_ONE:
433 case LANE_COUNT_TWO:
434 case LANE_COUNT_FOUR:
435 break;
436 default:
437 valid_input = false;
438 break;
439 }
440
441 switch (param[1]) {
442 case LINK_RATE_LOW:
443 case LINK_RATE_HIGH:
444 case LINK_RATE_RBR2:
445 case LINK_RATE_HIGH2:
446 case LINK_RATE_HIGH3:
447 case LINK_RATE_UHBR10:
448 case LINK_RATE_UHBR13_5:
449 case LINK_RATE_UHBR20:
450 break;
451 default:
452 valid_input = false;
453 break;
454 }
455
456 if (!valid_input) {
457 kfree(wr_buf);
458 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
459 mutex_lock(&adev->dm.dc_lock);
460 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
461 mutex_unlock(&adev->dm.dc_lock);
462 return -EINVAL;
463 }
464
465 /* save user force lane_count, link_rate to preferred settings
466 * spread spectrum will not be changed
467 */
468 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
469 prefer_link_settings.use_link_rate_set = false;
470 prefer_link_settings.lane_count = param[0];
471 prefer_link_settings.link_rate = param[1];
472
473 /* skip immediate retrain, and train to new link setting after hotplug event triggered */
474 mutex_lock(&adev->dm.dc_lock);
475 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
476 mutex_unlock(&adev->dm.dc_lock);
477
478 mutex_lock(&aconnector->base.dev->mode_config.mutex);
479 aconnector->base.force = DRM_FORCE_OFF;
480 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
481 drm_kms_helper_hotplug_event(aconnector->base.dev);
482
483 msleep(100);
484
485 mutex_lock(&aconnector->base.dev->mode_config.mutex);
486 aconnector->base.force = DRM_FORCE_UNSPECIFIED;
487 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
488 drm_kms_helper_hotplug_event(aconnector->base.dev);
489
490 kfree(wr_buf);
491 return size;
492 }
493
494 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
495 * post-cursor2 (defined by VESA DP specification)
496 *
497 * valid values
498 * voltage swing: 0,1,2,3
499 * pre-emphasis : 0,1,2,3
500 * post cursor2 : 0,1,2,3
501 *
502 *
503 * how to use this debugfs
504 *
505 * debugfs is located at /sys/kernel/debug/dri/0/DP-x
506 *
507 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
508 *
509 * To figure out which DP-x is the display for DP to be check,
510 * cd DP-x
511 * ls -ll
512 * There should be debugfs file, like link_settings, phy_settings.
513 * cat link_settings
514 * from lane_count, link_rate to figure which DP-x is for display to be worked
515 * on
516 *
517 * To get current DP PHY settings,
518 * cat phy_settings
519 *
520 * To change DP PHY settings,
521 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
522 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
523 * 0,
524 * echo 2 3 0 > phy_settings
525 *
526 * To check if change be applied, get current phy settings by
527 * cat phy_settings
528 *
529 * In case invalid values are set by user, like
530 * echo 1 4 0 > phy_settings
531 *
532 * HW will NOT be programmed by these settings.
533 * cat phy_settings will show the previous valid settings.
534 */
dp_phy_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)535 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
536 size_t size, loff_t *pos)
537 {
538 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
539 struct dc_link *link = connector->dc_link;
540 char *rd_buf = NULL;
541 const uint32_t rd_buf_size = 20;
542 uint32_t result = 0;
543 int r;
544
545 if (*pos & 3 || size & 3)
546 return -EINVAL;
547
548 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
549 if (!rd_buf)
550 return -EINVAL;
551
552 snprintf(rd_buf, rd_buf_size, " %d %d %d\n",
553 link->cur_lane_setting[0].VOLTAGE_SWING,
554 link->cur_lane_setting[0].PRE_EMPHASIS,
555 link->cur_lane_setting[0].POST_CURSOR2);
556
557 while (size) {
558 if (*pos >= rd_buf_size)
559 break;
560
561 r = put_user((*(rd_buf + result)), buf);
562 if (r) {
563 kfree(rd_buf);
564 return r; /* r = -EFAULT */
565 }
566
567 buf += 1;
568 size -= 1;
569 *pos += 1;
570 result += 1;
571 }
572
573 kfree(rd_buf);
574 return result;
575 }
576
dp_lttpr_status_show(struct seq_file * m,void * unused)577 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
578 {
579 struct drm_connector *connector = m->private;
580 struct amdgpu_dm_connector *aconnector =
581 to_amdgpu_dm_connector(connector);
582 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
583
584 if (connector->status != connector_status_connected)
585 return -ENODEV;
586
587 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
588 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
589 caps.phy_repeater_cnt);
590
591 seq_puts(m, "phy repeater mode: ");
592
593 switch (caps.mode) {
594 case DP_PHY_REPEATER_MODE_TRANSPARENT:
595 seq_puts(m, "transparent");
596 break;
597 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
598 seq_puts(m, "non-transparent");
599 break;
600 case 0x00:
601 seq_puts(m, "non lttpr");
602 break;
603 default:
604 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
605 break;
606 }
607
608 seq_puts(m, "\n");
609 return 0;
610 }
611
dp_phy_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)612 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
613 size_t size, loff_t *pos)
614 {
615 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
616 struct dc_link *link = connector->dc_link;
617 struct dc *dc = (struct dc *)link->dc;
618 char *wr_buf = NULL;
619 uint32_t wr_buf_size = 40;
620 long param[3];
621 bool use_prefer_link_setting;
622 struct link_training_settings link_lane_settings = {0};
623 int max_param_num = 3;
624 uint8_t param_nums = 0;
625 int r = 0;
626
627
628 if (size == 0)
629 return -EINVAL;
630
631 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
632 if (!wr_buf)
633 return -ENOSPC;
634
635 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
636 (long *)param, buf,
637 max_param_num,
638 ¶m_nums)) {
639 kfree(wr_buf);
640 return -EINVAL;
641 }
642
643 if (param_nums <= 0) {
644 kfree(wr_buf);
645 DRM_DEBUG_DRIVER("user data not be read\n");
646 return -EINVAL;
647 }
648
649 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
650 (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
651 (param[2] > POST_CURSOR2_MAX_LEVEL)) {
652 kfree(wr_buf);
653 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
654 return size;
655 }
656
657 /* get link settings: lane count, link rate */
658 use_prefer_link_setting =
659 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
660 (link->test_pattern_enabled));
661
662 memset(&link_lane_settings, 0, sizeof(link_lane_settings));
663
664 if (use_prefer_link_setting) {
665 link_lane_settings.link_settings.lane_count =
666 link->preferred_link_setting.lane_count;
667 link_lane_settings.link_settings.link_rate =
668 link->preferred_link_setting.link_rate;
669 link_lane_settings.link_settings.link_spread =
670 link->preferred_link_setting.link_spread;
671 } else {
672 link_lane_settings.link_settings.lane_count =
673 link->cur_link_settings.lane_count;
674 link_lane_settings.link_settings.link_rate =
675 link->cur_link_settings.link_rate;
676 link_lane_settings.link_settings.link_spread =
677 link->cur_link_settings.link_spread;
678 }
679
680 /* apply phy settings from user */
681 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
682 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
683 (enum dc_voltage_swing) (param[0]);
684 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
685 (enum dc_pre_emphasis) (param[1]);
686 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
687 (enum dc_post_cursor2) (param[2]);
688 }
689
690 /* program ASIC registers and DPCD registers */
691 dc_link_set_drive_settings(dc, &link_lane_settings, link);
692
693 kfree(wr_buf);
694 return size;
695 }
696
697 /* function description
698 *
699 * set PHY layer or Link layer test pattern
700 * PHY test pattern is used for PHY SI check.
701 * Link layer test will not affect PHY SI.
702 *
703 * Reset Test Pattern:
704 * 0 = DP_TEST_PATTERN_VIDEO_MODE
705 *
706 * PHY test pattern supported:
707 * 1 = DP_TEST_PATTERN_D102
708 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
709 * 3 = DP_TEST_PATTERN_PRBS7
710 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
711 * 5 = DP_TEST_PATTERN_CP2520_1
712 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
713 * 7 = DP_TEST_PATTERN_CP2520_3
714 *
715 * DP PHY Link Training Patterns
716 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
717 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
718 * a = DP_TEST_PATTERN_TRAINING_PATTERN3
719 * b = DP_TEST_PATTERN_TRAINING_PATTERN4
720 *
721 * DP Link Layer Test pattern
722 * c = DP_TEST_PATTERN_COLOR_SQUARES
723 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
724 * e = DP_TEST_PATTERN_VERTICAL_BARS
725 * f = DP_TEST_PATTERN_HORIZONTAL_BARS
726 * 10= DP_TEST_PATTERN_COLOR_RAMP
727 *
728 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
729 *
730 * --- set test pattern
731 * echo <test pattern #> > test_pattern
732 *
733 * If test pattern # is not supported, NO HW programming will be done.
734 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
735 * for the user pattern. input 10 bytes data are separated by space
736 *
737 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
738 *
739 * --- reset test pattern
740 * echo 0 > test_pattern
741 *
742 * --- HPD detection is disabled when set PHY test pattern
743 *
744 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
745 * is disable. User could unplug DP display from DP connected and plug scope to
746 * check test pattern PHY SI.
747 * If there is need unplug scope and plug DP display back, do steps below:
748 * echo 0 > phy_test_pattern
749 * unplug scope
750 * plug DP display.
751 *
752 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
753 * driver could detect "unplug scope" and "plug DP display"
754 */
dp_phy_test_pattern_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)755 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
756 size_t size, loff_t *pos)
757 {
758 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
759 struct dc_link *link = connector->dc_link;
760 char *wr_buf = NULL;
761 uint32_t wr_buf_size = 100;
762 long param[11] = {0x0};
763 int max_param_num = 11;
764 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
765 bool disable_hpd = false;
766 bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID;
767 bool valid_test_pattern = false;
768 uint8_t param_nums = 0;
769 /* init with default 80bit custom pattern */
770 uint8_t custom_pattern[10] = {
771 0x1f, 0x7c, 0xf0, 0xc1, 0x07,
772 0x1f, 0x7c, 0xf0, 0xc1, 0x07
773 };
774 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
775 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
776 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
777 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
778 struct link_training_settings link_training_settings = {0};
779 int i;
780
781 if (size == 0)
782 return -EINVAL;
783
784 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
785 if (!wr_buf)
786 return -ENOSPC;
787
788 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
789 (long *)param, buf,
790 max_param_num,
791 ¶m_nums)) {
792 kfree(wr_buf);
793 return -EINVAL;
794 }
795
796 if (param_nums <= 0) {
797 kfree(wr_buf);
798 DRM_DEBUG_DRIVER("user data not be read\n");
799 return -EINVAL;
800 }
801
802
803 test_pattern = param[0];
804
805 switch (test_pattern) {
806 case DP_TEST_PATTERN_VIDEO_MODE:
807 case DP_TEST_PATTERN_COLOR_SQUARES:
808 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
809 case DP_TEST_PATTERN_VERTICAL_BARS:
810 case DP_TEST_PATTERN_HORIZONTAL_BARS:
811 case DP_TEST_PATTERN_COLOR_RAMP:
812 valid_test_pattern = true;
813 break;
814
815 case DP_TEST_PATTERN_D102:
816 case DP_TEST_PATTERN_SYMBOL_ERROR:
817 case DP_TEST_PATTERN_PRBS7:
818 case DP_TEST_PATTERN_80BIT_CUSTOM:
819 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
820 case DP_TEST_PATTERN_TRAINING_PATTERN4:
821 disable_hpd = true;
822 valid_test_pattern = true;
823 break;
824
825 default:
826 valid_test_pattern = false;
827 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
828 break;
829 }
830
831 if (!valid_test_pattern) {
832 kfree(wr_buf);
833 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
834 return size;
835 }
836
837 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
838 for (i = 0; i < 10; i++) {
839 if ((uint8_t) param[i + 1] != 0x0)
840 break;
841 }
842
843 if (i < 10) {
844 /* not use default value */
845 for (i = 0; i < 10; i++)
846 custom_pattern[i] = (uint8_t) param[i + 1];
847 }
848 }
849
850 /* Usage: set DP physical test pattern using debugfs with normal DP
851 * panel. Then plug out DP panel and connect a scope to measure
852 * For normal video mode and test pattern generated from CRCT,
853 * they are visibile to user. So do not disable HPD.
854 * Video Mode is also set to clear the test pattern, so enable HPD
855 * because it might have been disabled after a test pattern was set.
856 * AUX depends on HPD * sequence dependent, do not move!
857 */
858 if (supports_hpd && !disable_hpd)
859 dc_link_enable_hpd(link);
860
861 prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
862 prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
863 prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
864
865 cur_link_settings.lane_count = link->cur_link_settings.lane_count;
866 cur_link_settings.link_rate = link->cur_link_settings.link_rate;
867 cur_link_settings.link_spread = link->cur_link_settings.link_spread;
868
869 link_training_settings.link_settings = cur_link_settings;
870
871
872 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
873 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
874 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN &&
875 (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
876 prefer_link_settings.link_rate != cur_link_settings.link_rate))
877 link_training_settings.link_settings = prefer_link_settings;
878 }
879
880 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
881 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
882
883 dc_link_dp_set_test_pattern(
884 link,
885 test_pattern,
886 DP_TEST_PATTERN_COLOR_SPACE_RGB,
887 &link_training_settings,
888 custom_pattern,
889 10);
890
891 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
892 * Then plug out DP panel and connect a scope to measure DP PHY signal.
893 * Need disable interrupt to avoid SW driver disable DP output. This is
894 * done after the test pattern is set.
895 */
896 if (valid_test_pattern && supports_hpd && disable_hpd)
897 dc_link_disable_hpd(link);
898
899 kfree(wr_buf);
900
901 return size;
902 }
903
904 /*
905 * Returns the DMCUB tracebuffer contents.
906 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
907 */
dmub_tracebuffer_show(struct seq_file * m,void * data)908 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
909 {
910 struct amdgpu_device *adev = m->private;
911 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
912 struct dmub_fw_meta_info *fw_meta_info = NULL;
913 struct dmub_debugfs_trace_entry *entries;
914 uint8_t *tbuf_base;
915 uint32_t tbuf_size, max_entries, num_entries, first_entry, i;
916
917 if (!fb_info)
918 return 0;
919
920 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
921 if (!tbuf_base)
922 return 0;
923
924 if (adev->dm.dmub_srv)
925 fw_meta_info = &adev->dm.dmub_srv->meta_info;
926
927 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size :
928 DMUB_TRACE_BUFFER_SIZE;
929 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
930 sizeof(struct dmub_debugfs_trace_entry);
931
932 num_entries =
933 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
934
935 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that
936 * entries are being overwritten.
937 */
938 if (num_entries > max_entries)
939 seq_printf(m, "...\n");
940
941 first_entry = num_entries % max_entries;
942 num_entries = min(num_entries, max_entries);
943
944 entries = (struct dmub_debugfs_trace_entry
945 *)(tbuf_base +
946 sizeof(struct dmub_debugfs_trace_header));
947
948 /* To print entries chronologically, start from the first entry till the
949 * top of buffer, then from base of buffer to first entry.
950 */
951 for (i = first_entry; i < num_entries; ++i) {
952 struct dmub_debugfs_trace_entry *entry = &entries[i];
953
954 seq_printf(m,
955 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
956 entry->trace_code, entry->tick_count, entry->param0,
957 entry->param1);
958 }
959 for (i = 0; i < first_entry; ++i) {
960 struct dmub_debugfs_trace_entry *entry = &entries[i];
961
962 seq_printf(m,
963 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
964 entry->trace_code, entry->tick_count, entry->param0,
965 entry->param1);
966 }
967
968 return 0;
969 }
970
971 /*
972 * Returns the DMCUB firmware state contents.
973 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
974 */
dmub_fw_state_show(struct seq_file * m,void * data)975 static int dmub_fw_state_show(struct seq_file *m, void *data)
976 {
977 struct amdgpu_device *adev = m->private;
978 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
979 uint8_t *state_base;
980 uint32_t state_size;
981
982 if (!fb_info)
983 return 0;
984
985 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
986 if (!state_base)
987 return 0;
988
989 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
990
991 return seq_write(m, state_base, state_size);
992 }
993
994 /* replay_capability_show() - show eDP panel replay capability
995 *
996 * The read function: replay_capability_show
997 * Shows if sink and driver has Replay capability or not.
998 *
999 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
1000 *
1001 * Expected output:
1002 * "Sink support: no\n" - if panel doesn't support Replay
1003 * "Sink support: yes\n" - if panel supports Replay
1004 * "Driver support: no\n" - if driver doesn't support Replay
1005 * "Driver support: yes\n" - if driver supports Replay
1006 */
replay_capability_show(struct seq_file * m,void * data)1007 static int replay_capability_show(struct seq_file *m, void *data)
1008 {
1009 struct drm_connector *connector = m->private;
1010 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1011 struct dc_link *link = aconnector->dc_link;
1012 bool sink_support_replay = false;
1013 bool driver_support_replay = false;
1014
1015 if (!link)
1016 return -ENODEV;
1017
1018 if (link->type == dc_connection_none)
1019 return -ENODEV;
1020
1021 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1022 return -ENODEV;
1023
1024 /* If Replay is already set to support, skip the checks */
1025 if (link->replay_settings.config.replay_supported) {
1026 sink_support_replay = true;
1027 driver_support_replay = true;
1028 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
1029 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1030 } else {
1031 struct dc *dc = link->ctx->dc;
1032
1033 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1034 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1035 driver_support_replay =
1036 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1037 }
1038
1039 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
1040 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
1041 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
1042
1043 return 0;
1044 }
1045
1046 /* psr_capability_show() - show eDP panel PSR capability
1047 *
1048 * The read function: sink_psr_capability_show
1049 * Shows if sink has PSR capability or not.
1050 * If yes - the PSR version is appended
1051 *
1052 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1053 *
1054 * Expected output:
1055 * "Sink support: no\n" - if panel doesn't support PSR
1056 * "Sink support: yes [0x01]\n" - if panel supports PSR1
1057 * "Driver support: no\n" - if driver doesn't support PSR
1058 * "Driver support: yes [0x01]\n" - if driver supports PSR1
1059 */
psr_capability_show(struct seq_file * m,void * data)1060 static int psr_capability_show(struct seq_file *m, void *data)
1061 {
1062 struct drm_connector *connector = m->private;
1063 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1064 struct dc_link *link = aconnector->dc_link;
1065
1066 if (!link)
1067 return -ENODEV;
1068
1069 if (link->type == dc_connection_none)
1070 return -ENODEV;
1071
1072 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1073 return -ENODEV;
1074
1075 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
1076 if (link->dpcd_caps.psr_info.psr_version)
1077 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1078 seq_puts(m, "\n");
1079
1080 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
1081 if (link->psr_settings.psr_version)
1082 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1083 seq_puts(m, "\n");
1084
1085 return 0;
1086 }
1087
1088 /*
1089 * Returns the current bpc for the crtc.
1090 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1091 */
amdgpu_current_bpc_show(struct seq_file * m,void * data)1092 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1093 {
1094 struct drm_crtc *crtc = m->private;
1095 struct drm_device *dev = crtc->dev;
1096 struct dm_crtc_state *dm_crtc_state = NULL;
1097 int res = -ENODEV;
1098 unsigned int bpc;
1099
1100 mutex_lock(&dev->mode_config.mutex);
1101 drm_modeset_lock(&crtc->mutex, NULL);
1102 if (crtc->state == NULL)
1103 goto unlock;
1104
1105 dm_crtc_state = to_dm_crtc_state(crtc->state);
1106 if (dm_crtc_state->stream == NULL)
1107 goto unlock;
1108
1109 switch (dm_crtc_state->stream->timing.display_color_depth) {
1110 case COLOR_DEPTH_666:
1111 bpc = 6;
1112 break;
1113 case COLOR_DEPTH_888:
1114 bpc = 8;
1115 break;
1116 case COLOR_DEPTH_101010:
1117 bpc = 10;
1118 break;
1119 case COLOR_DEPTH_121212:
1120 bpc = 12;
1121 break;
1122 case COLOR_DEPTH_161616:
1123 bpc = 16;
1124 break;
1125 default:
1126 goto unlock;
1127 }
1128
1129 seq_printf(m, "Current: %u\n", bpc);
1130 res = 0;
1131
1132 unlock:
1133 drm_modeset_unlock(&crtc->mutex);
1134 mutex_unlock(&dev->mode_config.mutex);
1135
1136 return res;
1137 }
1138 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1139
1140 /*
1141 * Returns the current colorspace for the crtc.
1142 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1143 */
amdgpu_current_colorspace_show(struct seq_file * m,void * data)1144 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1145 {
1146 struct drm_crtc *crtc = m->private;
1147 struct drm_device *dev = crtc->dev;
1148 struct dm_crtc_state *dm_crtc_state = NULL;
1149 int res = -ENODEV;
1150
1151 mutex_lock(&dev->mode_config.mutex);
1152 drm_modeset_lock(&crtc->mutex, NULL);
1153 if (crtc->state == NULL)
1154 goto unlock;
1155
1156 dm_crtc_state = to_dm_crtc_state(crtc->state);
1157 if (dm_crtc_state->stream == NULL)
1158 goto unlock;
1159
1160 switch (dm_crtc_state->stream->output_color_space) {
1161 case COLOR_SPACE_SRGB:
1162 seq_puts(m, "sRGB");
1163 break;
1164 case COLOR_SPACE_YCBCR601:
1165 case COLOR_SPACE_YCBCR601_LIMITED:
1166 seq_puts(m, "BT601_YCC");
1167 break;
1168 case COLOR_SPACE_YCBCR709:
1169 case COLOR_SPACE_YCBCR709_LIMITED:
1170 seq_puts(m, "BT709_YCC");
1171 break;
1172 case COLOR_SPACE_ADOBERGB:
1173 seq_puts(m, "opRGB");
1174 break;
1175 case COLOR_SPACE_2020_RGB_FULLRANGE:
1176 seq_puts(m, "BT2020_RGB");
1177 break;
1178 case COLOR_SPACE_2020_YCBCR_LIMITED:
1179 seq_puts(m, "BT2020_YCC");
1180 break;
1181 default:
1182 goto unlock;
1183 }
1184 res = 0;
1185
1186 unlock:
1187 drm_modeset_unlock(&crtc->mutex);
1188 mutex_unlock(&dev->mode_config.mutex);
1189
1190 return res;
1191 }
1192 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1193
1194
1195 /*
1196 * Example usage:
1197 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1198 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1199 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1200 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1201 */
dp_dsc_passthrough_set(struct file * f,const char __user * buf,size_t size,loff_t * pos)1202 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1203 size_t size, loff_t *pos)
1204 {
1205 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1206 char *wr_buf = NULL;
1207 uint32_t wr_buf_size = 42;
1208 int max_param_num = 1;
1209 long param;
1210 uint8_t param_nums = 0;
1211
1212 if (size == 0)
1213 return -EINVAL;
1214
1215 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1216
1217 if (!wr_buf) {
1218 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1219 return -ENOSPC;
1220 }
1221
1222 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1223 ¶m, buf,
1224 max_param_num,
1225 ¶m_nums)) {
1226 kfree(wr_buf);
1227 return -EINVAL;
1228 }
1229
1230 aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1231
1232 kfree(wr_buf);
1233 return 0;
1234 }
1235
1236 /*
1237 * Returns the HDCP capability of the Display (1.4 for now).
1238 *
1239 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1240 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1241 *
1242 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1243 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1244 */
hdcp_sink_capability_show(struct seq_file * m,void * data)1245 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1246 {
1247 struct drm_connector *connector = m->private;
1248 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1249 bool hdcp_cap, hdcp2_cap;
1250
1251 if (connector->status != connector_status_connected)
1252 return -ENODEV;
1253
1254 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1255
1256 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1257 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1258
1259
1260 if (hdcp_cap)
1261 seq_printf(m, "%s ", "HDCP1.4");
1262 if (hdcp2_cap)
1263 seq_printf(m, "%s ", "HDCP2.2");
1264
1265 if (!hdcp_cap && !hdcp2_cap)
1266 seq_printf(m, "%s ", "None");
1267
1268 seq_puts(m, "\n");
1269
1270 return 0;
1271 }
1272
1273 /*
1274 * Returns whether the connected display is internal and not hotpluggable.
1275 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1276 */
internal_display_show(struct seq_file * m,void * data)1277 static int internal_display_show(struct seq_file *m, void *data)
1278 {
1279 struct drm_connector *connector = m->private;
1280 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1281 struct dc_link *link = aconnector->dc_link;
1282
1283 seq_printf(m, "Internal: %u\n", link->is_internal_display);
1284
1285 return 0;
1286 }
1287
1288 /*
1289 * Returns the number of segments used if ODM Combine mode is enabled.
1290 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1291 */
odm_combine_segments_show(struct seq_file * m,void * unused)1292 static int odm_combine_segments_show(struct seq_file *m, void *unused)
1293 {
1294 struct drm_connector *connector = m->private;
1295 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1296 struct dc_link *link = aconnector->dc_link;
1297 struct pipe_ctx *pipe_ctx = NULL;
1298 int i, segments = -EOPNOTSUPP;
1299
1300 for (i = 0; i < MAX_PIPES; i++) {
1301 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1302 if (pipe_ctx->stream &&
1303 pipe_ctx->stream->link == link)
1304 break;
1305 }
1306
1307 if (connector->status != connector_status_connected)
1308 return -ENODEV;
1309
1310 if (pipe_ctx && pipe_ctx->stream_res.tg &&
1311 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1312 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1313
1314 seq_printf(m, "%d\n", segments);
1315 return 0;
1316 }
1317
1318 /* function description
1319 *
1320 * generic SDP message access for testing
1321 *
1322 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1323 *
1324 * SDP header
1325 * Hb0 : Secondary-Data Packet ID
1326 * Hb1 : Secondary-Data Packet type
1327 * Hb2 : Secondary-Data-packet-specific header, Byte 0
1328 * Hb3 : Secondary-Data-packet-specific header, Byte 1
1329 *
1330 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1331 */
dp_sdp_message_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1332 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1333 size_t size, loff_t *pos)
1334 {
1335 int r;
1336 uint8_t data[36] = {0};
1337 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1338 struct dm_crtc_state *acrtc_state;
1339 uint32_t write_size = 36;
1340
1341 if (connector->base.status != connector_status_connected)
1342 return -ENODEV;
1343
1344 if (size == 0)
1345 return 0;
1346
1347 if (!connector->base.state || !connector->base.state->crtc)
1348 return -ENODEV;
1349
1350 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1351
1352 write_size = min_t(size_t, size, sizeof(data));
1353
1354 r = copy_from_user(data, buf, write_size);
1355
1356 write_size -= r;
1357
1358 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1359
1360 return write_size;
1361 }
1362
1363 /* function: Read link's DSC & FEC capabilities
1364 *
1365 *
1366 * Access it with the following command (you need to specify
1367 * connector like DP-1):
1368 *
1369 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1370 *
1371 */
dp_dsc_fec_support_show(struct seq_file * m,void * data)1372 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1373 {
1374 struct drm_connector *connector = m->private;
1375 struct drm_modeset_acquire_ctx ctx;
1376 struct drm_device *dev = connector->dev;
1377 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1378 int ret = 0;
1379 bool try_again = false;
1380 bool is_fec_supported = false;
1381 bool is_dsc_supported = false;
1382 struct dpcd_caps dpcd_caps;
1383
1384 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1385 do {
1386 try_again = false;
1387 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1388 if (ret) {
1389 if (ret == -EDEADLK) {
1390 ret = drm_modeset_backoff(&ctx);
1391 if (!ret) {
1392 try_again = true;
1393 continue;
1394 }
1395 }
1396 break;
1397 }
1398 if (connector->status != connector_status_connected) {
1399 ret = -ENODEV;
1400 break;
1401 }
1402 dpcd_caps = aconnector->dc_link->dpcd_caps;
1403 if (aconnector->mst_output_port) {
1404 /* aconnector sets dsc_aux during get_modes call
1405 * if MST connector has it means it can either
1406 * enable DSC on the sink device or on MST branch
1407 * its connected to.
1408 */
1409 if (aconnector->dsc_aux) {
1410 is_fec_supported = true;
1411 is_dsc_supported = true;
1412 }
1413 } else {
1414 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1415 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1416 }
1417 } while (try_again);
1418
1419 drm_modeset_drop_locks(&ctx);
1420 drm_modeset_acquire_fini(&ctx);
1421
1422 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1423 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1424
1425 return ret;
1426 }
1427
1428 /* function: Trigger virtual HPD redetection on connector
1429 *
1430 * This function will perform link rediscovery, link disable
1431 * and enable, and dm connector state update.
1432 *
1433 * Retrigger HPD on an existing connector by echoing 1 into
1434 * its respectful "trigger_hotplug" debugfs entry:
1435 *
1436 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1437 *
1438 * This function can perform HPD unplug:
1439 *
1440 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1441 *
1442 */
trigger_hotplug(struct file * f,const char __user * buf,size_t size,loff_t * pos)1443 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1444 size_t size, loff_t *pos)
1445 {
1446 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1447 struct drm_connector *connector = &aconnector->base;
1448 struct dc_link *link = NULL;
1449 struct drm_device *dev = connector->dev;
1450 struct amdgpu_device *adev = drm_to_adev(dev);
1451 enum dc_connection_type new_connection_type = dc_connection_none;
1452 char *wr_buf = NULL;
1453 uint32_t wr_buf_size = 42;
1454 int max_param_num = 1;
1455 long param[1] = {0};
1456 uint8_t param_nums = 0;
1457 bool ret = false;
1458
1459 if (!aconnector->dc_link)
1460 return -EINVAL;
1461
1462 if (size == 0)
1463 return -EINVAL;
1464
1465 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1466
1467 if (!wr_buf) {
1468 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1469 return -ENOSPC;
1470 }
1471
1472 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1473 (long *)param, buf,
1474 max_param_num,
1475 ¶m_nums)) {
1476 kfree(wr_buf);
1477 return -EINVAL;
1478 }
1479
1480 kfree(wr_buf);
1481
1482 if (param_nums <= 0) {
1483 DRM_DEBUG_DRIVER("user data not be read\n");
1484 return -EINVAL;
1485 }
1486
1487 mutex_lock(&aconnector->hpd_lock);
1488
1489 /* Don't support for mst end device*/
1490 if (aconnector->mst_root) {
1491 mutex_unlock(&aconnector->hpd_lock);
1492 return -EINVAL;
1493 }
1494
1495 if (param[0] == 1) {
1496
1497 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1498 new_connection_type != dc_connection_none)
1499 goto unlock;
1500
1501 mutex_lock(&adev->dm.dc_lock);
1502 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1503 mutex_unlock(&adev->dm.dc_lock);
1504
1505 if (!ret)
1506 goto unlock;
1507
1508 amdgpu_dm_update_connector_after_detect(aconnector);
1509
1510 drm_modeset_lock_all(dev);
1511 dm_restore_drm_connector_state(dev, connector);
1512 drm_modeset_unlock_all(dev);
1513
1514 drm_kms_helper_connector_hotplug_event(connector);
1515 } else if (param[0] == 0) {
1516 if (!aconnector->dc_link)
1517 goto unlock;
1518
1519 link = aconnector->dc_link;
1520
1521 if (link->local_sink) {
1522 dc_sink_release(link->local_sink);
1523 link->local_sink = NULL;
1524 }
1525
1526 link->dpcd_sink_count = 0;
1527 link->type = dc_connection_none;
1528 link->dongle_max_pix_clk = 0;
1529
1530 amdgpu_dm_update_connector_after_detect(aconnector);
1531
1532 /* If the aconnector is the root node in mst topology */
1533 if (aconnector->mst_mgr.mst_state == true)
1534 dc_link_reset_cur_dp_mst_topology(link);
1535
1536 drm_modeset_lock_all(dev);
1537 dm_restore_drm_connector_state(dev, connector);
1538 drm_modeset_unlock_all(dev);
1539
1540 drm_kms_helper_connector_hotplug_event(connector);
1541 }
1542
1543 unlock:
1544 mutex_unlock(&aconnector->hpd_lock);
1545
1546 return size;
1547 }
1548
1549 /* function: read DSC status on the connector
1550 *
1551 * The read function: dp_dsc_clock_en_read
1552 * returns current status of DSC clock on the connector.
1553 * The return is a boolean flag: 1 or 0.
1554 *
1555 * Access it with the following command (you need to specify
1556 * connector like DP-1):
1557 *
1558 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1559 *
1560 * Expected output:
1561 * 1 - means that DSC is currently enabled
1562 * 0 - means that DSC is disabled
1563 */
dp_dsc_clock_en_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1564 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1565 size_t size, loff_t *pos)
1566 {
1567 char *rd_buf = NULL;
1568 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1569 struct display_stream_compressor *dsc;
1570 struct dcn_dsc_state dsc_state = {0};
1571 const uint32_t rd_buf_size = 10;
1572 struct pipe_ctx *pipe_ctx;
1573 ssize_t result = 0;
1574 int i, r, str_len = 10;
1575
1576 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1577
1578 if (!rd_buf)
1579 return -ENOMEM;
1580
1581 for (i = 0; i < MAX_PIPES; i++) {
1582 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1583 if (pipe_ctx->stream &&
1584 pipe_ctx->stream->link == aconnector->dc_link &&
1585 pipe_ctx->stream->sink &&
1586 pipe_ctx->stream->sink == aconnector->dc_sink)
1587 break;
1588 }
1589
1590 dsc = pipe_ctx->stream_res.dsc;
1591 if (dsc)
1592 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1593
1594 snprintf(rd_buf, str_len,
1595 "%d\n",
1596 dsc_state.dsc_clock_en);
1597
1598 while (size) {
1599 if (*pos >= rd_buf_size)
1600 break;
1601
1602 r = put_user(*(rd_buf + result), buf);
1603 if (r) {
1604 kfree(rd_buf);
1605 return r; /* r = -EFAULT */
1606 }
1607
1608 buf += 1;
1609 size -= 1;
1610 *pos += 1;
1611 result += 1;
1612 }
1613
1614 kfree(rd_buf);
1615 return result;
1616 }
1617
1618 /* function: write force DSC on the connector
1619 *
1620 * The write function: dp_dsc_clock_en_write
1621 * enables to force DSC on the connector.
1622 * User can write to either force enable or force disable DSC
1623 * on the next modeset or set it to driver default
1624 *
1625 * Accepted inputs:
1626 * 0 - default DSC enablement policy
1627 * 1 - force enable DSC on the connector
1628 * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1629 *
1630 * Writing DSC settings is done with the following command:
1631 * - To force enable DSC (you need to specify
1632 * connector like DP-1):
1633 *
1634 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1635 *
1636 * - To return to default state set the flag to zero and
1637 * let driver deal with DSC automatically
1638 * (you need to specify connector like DP-1):
1639 *
1640 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1641 *
1642 */
dp_dsc_clock_en_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1643 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1644 size_t size, loff_t *pos)
1645 {
1646 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1647 struct drm_connector *connector = &aconnector->base;
1648 struct drm_device *dev = connector->dev;
1649 struct drm_crtc *crtc = NULL;
1650 struct dm_crtc_state *dm_crtc_state = NULL;
1651 struct pipe_ctx *pipe_ctx;
1652 int i;
1653 char *wr_buf = NULL;
1654 uint32_t wr_buf_size = 42;
1655 int max_param_num = 1;
1656 long param[1] = {0};
1657 uint8_t param_nums = 0;
1658
1659 if (size == 0)
1660 return -EINVAL;
1661
1662 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1663
1664 if (!wr_buf) {
1665 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1666 return -ENOSPC;
1667 }
1668
1669 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1670 (long *)param, buf,
1671 max_param_num,
1672 ¶m_nums)) {
1673 kfree(wr_buf);
1674 return -EINVAL;
1675 }
1676
1677 if (param_nums <= 0) {
1678 DRM_DEBUG_DRIVER("user data not be read\n");
1679 kfree(wr_buf);
1680 return -EINVAL;
1681 }
1682
1683 for (i = 0; i < MAX_PIPES; i++) {
1684 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1685 if (pipe_ctx->stream &&
1686 pipe_ctx->stream->link == aconnector->dc_link &&
1687 pipe_ctx->stream->sink &&
1688 pipe_ctx->stream->sink == aconnector->dc_sink)
1689 break;
1690 }
1691
1692 if (!pipe_ctx->stream)
1693 goto done;
1694
1695 // Get CRTC state
1696 mutex_lock(&dev->mode_config.mutex);
1697 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1698
1699 if (connector->state == NULL)
1700 goto unlock;
1701
1702 crtc = connector->state->crtc;
1703 if (crtc == NULL)
1704 goto unlock;
1705
1706 drm_modeset_lock(&crtc->mutex, NULL);
1707 if (crtc->state == NULL)
1708 goto unlock;
1709
1710 dm_crtc_state = to_dm_crtc_state(crtc->state);
1711 if (dm_crtc_state->stream == NULL)
1712 goto unlock;
1713
1714 if (param[0] == 1)
1715 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1716 else if (param[0] == 2)
1717 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1718 else
1719 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1720
1721 dm_crtc_state->dsc_force_changed = true;
1722
1723 unlock:
1724 if (crtc)
1725 drm_modeset_unlock(&crtc->mutex);
1726 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1727 mutex_unlock(&dev->mode_config.mutex);
1728
1729 done:
1730 kfree(wr_buf);
1731 return size;
1732 }
1733
1734 /* function: read DSC slice width parameter on the connector
1735 *
1736 * The read function: dp_dsc_slice_width_read
1737 * returns dsc slice width used in the current configuration
1738 * The return is an integer: 0 or other positive number
1739 *
1740 * Access the status with the following command:
1741 *
1742 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1743 *
1744 * 0 - means that DSC is disabled
1745 *
1746 * Any other number more than zero represents the
1747 * slice width currently used by DSC in pixels
1748 *
1749 */
dp_dsc_slice_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1750 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1751 size_t size, loff_t *pos)
1752 {
1753 char *rd_buf = NULL;
1754 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1755 struct display_stream_compressor *dsc;
1756 struct dcn_dsc_state dsc_state = {0};
1757 const uint32_t rd_buf_size = 100;
1758 struct pipe_ctx *pipe_ctx;
1759 ssize_t result = 0;
1760 int i, r, str_len = 30;
1761
1762 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1763
1764 if (!rd_buf)
1765 return -ENOMEM;
1766
1767 for (i = 0; i < MAX_PIPES; i++) {
1768 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1769 if (pipe_ctx->stream &&
1770 pipe_ctx->stream->link == aconnector->dc_link &&
1771 pipe_ctx->stream->sink &&
1772 pipe_ctx->stream->sink == aconnector->dc_sink)
1773 break;
1774 }
1775
1776 dsc = pipe_ctx->stream_res.dsc;
1777 if (dsc)
1778 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1779
1780 snprintf(rd_buf, str_len,
1781 "%d\n",
1782 dsc_state.dsc_slice_width);
1783
1784 while (size) {
1785 if (*pos >= rd_buf_size)
1786 break;
1787
1788 r = put_user(*(rd_buf + result), buf);
1789 if (r) {
1790 kfree(rd_buf);
1791 return r; /* r = -EFAULT */
1792 }
1793
1794 buf += 1;
1795 size -= 1;
1796 *pos += 1;
1797 result += 1;
1798 }
1799
1800 kfree(rd_buf);
1801 return result;
1802 }
1803
1804 /* function: write DSC slice width parameter
1805 *
1806 * The write function: dp_dsc_slice_width_write
1807 * overwrites automatically generated DSC configuration
1808 * of slice width.
1809 *
1810 * The user has to write the slice width divisible by the
1811 * picture width.
1812 *
1813 * Also the user has to write width in hexidecimal
1814 * rather than in decimal.
1815 *
1816 * Writing DSC settings is done with the following command:
1817 * - To force overwrite slice width: (example sets to 1920 pixels)
1818 *
1819 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1820 *
1821 * - To stop overwriting and let driver find the optimal size,
1822 * set the width to zero:
1823 *
1824 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1825 *
1826 */
dp_dsc_slice_width_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1827 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1828 size_t size, loff_t *pos)
1829 {
1830 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1831 struct pipe_ctx *pipe_ctx;
1832 struct drm_connector *connector = &aconnector->base;
1833 struct drm_device *dev = connector->dev;
1834 struct drm_crtc *crtc = NULL;
1835 struct dm_crtc_state *dm_crtc_state = NULL;
1836 int i;
1837 char *wr_buf = NULL;
1838 uint32_t wr_buf_size = 42;
1839 int max_param_num = 1;
1840 long param[1] = {0};
1841 uint8_t param_nums = 0;
1842
1843 if (size == 0)
1844 return -EINVAL;
1845
1846 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1847
1848 if (!wr_buf) {
1849 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1850 return -ENOSPC;
1851 }
1852
1853 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1854 (long *)param, buf,
1855 max_param_num,
1856 ¶m_nums)) {
1857 kfree(wr_buf);
1858 return -EINVAL;
1859 }
1860
1861 if (param_nums <= 0) {
1862 DRM_DEBUG_DRIVER("user data not be read\n");
1863 kfree(wr_buf);
1864 return -EINVAL;
1865 }
1866
1867 for (i = 0; i < MAX_PIPES; i++) {
1868 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1869 if (pipe_ctx->stream &&
1870 pipe_ctx->stream->link == aconnector->dc_link &&
1871 pipe_ctx->stream->sink &&
1872 pipe_ctx->stream->sink == aconnector->dc_sink)
1873 break;
1874 }
1875
1876 if (!pipe_ctx->stream)
1877 goto done;
1878
1879 // Safely get CRTC state
1880 mutex_lock(&dev->mode_config.mutex);
1881 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1882
1883 if (connector->state == NULL)
1884 goto unlock;
1885
1886 crtc = connector->state->crtc;
1887 if (crtc == NULL)
1888 goto unlock;
1889
1890 drm_modeset_lock(&crtc->mutex, NULL);
1891 if (crtc->state == NULL)
1892 goto unlock;
1893
1894 dm_crtc_state = to_dm_crtc_state(crtc->state);
1895 if (dm_crtc_state->stream == NULL)
1896 goto unlock;
1897
1898 if (param[0] > 0)
1899 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1900 pipe_ctx->stream->timing.h_addressable,
1901 param[0]);
1902 else
1903 aconnector->dsc_settings.dsc_num_slices_h = 0;
1904
1905 dm_crtc_state->dsc_force_changed = true;
1906
1907 unlock:
1908 if (crtc)
1909 drm_modeset_unlock(&crtc->mutex);
1910 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1911 mutex_unlock(&dev->mode_config.mutex);
1912
1913 done:
1914 kfree(wr_buf);
1915 return size;
1916 }
1917
1918 /* function: read DSC slice height parameter on the connector
1919 *
1920 * The read function: dp_dsc_slice_height_read
1921 * returns dsc slice height used in the current configuration
1922 * The return is an integer: 0 or other positive number
1923 *
1924 * Access the status with the following command:
1925 *
1926 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1927 *
1928 * 0 - means that DSC is disabled
1929 *
1930 * Any other number more than zero represents the
1931 * slice height currently used by DSC in pixels
1932 *
1933 */
dp_dsc_slice_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1934 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1935 size_t size, loff_t *pos)
1936 {
1937 char *rd_buf = NULL;
1938 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1939 struct display_stream_compressor *dsc;
1940 struct dcn_dsc_state dsc_state = {0};
1941 const uint32_t rd_buf_size = 100;
1942 struct pipe_ctx *pipe_ctx;
1943 ssize_t result = 0;
1944 int i, r, str_len = 30;
1945
1946 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1947
1948 if (!rd_buf)
1949 return -ENOMEM;
1950
1951 for (i = 0; i < MAX_PIPES; i++) {
1952 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1953 if (pipe_ctx->stream &&
1954 pipe_ctx->stream->link == aconnector->dc_link &&
1955 pipe_ctx->stream->sink &&
1956 pipe_ctx->stream->sink == aconnector->dc_sink)
1957 break;
1958 }
1959
1960 dsc = pipe_ctx->stream_res.dsc;
1961 if (dsc)
1962 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1963
1964 snprintf(rd_buf, str_len,
1965 "%d\n",
1966 dsc_state.dsc_slice_height);
1967
1968 while (size) {
1969 if (*pos >= rd_buf_size)
1970 break;
1971
1972 r = put_user(*(rd_buf + result), buf);
1973 if (r) {
1974 kfree(rd_buf);
1975 return r; /* r = -EFAULT */
1976 }
1977
1978 buf += 1;
1979 size -= 1;
1980 *pos += 1;
1981 result += 1;
1982 }
1983
1984 kfree(rd_buf);
1985 return result;
1986 }
1987
1988 /* function: write DSC slice height parameter
1989 *
1990 * The write function: dp_dsc_slice_height_write
1991 * overwrites automatically generated DSC configuration
1992 * of slice height.
1993 *
1994 * The user has to write the slice height divisible by the
1995 * picture height.
1996 *
1997 * Also the user has to write height in hexidecimal
1998 * rather than in decimal.
1999 *
2000 * Writing DSC settings is done with the following command:
2001 * - To force overwrite slice height (example sets to 128 pixels):
2002 *
2003 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2004 *
2005 * - To stop overwriting and let driver find the optimal size,
2006 * set the height to zero:
2007 *
2008 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2009 *
2010 */
dp_dsc_slice_height_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2011 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
2012 size_t size, loff_t *pos)
2013 {
2014 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2015 struct drm_connector *connector = &aconnector->base;
2016 struct drm_device *dev = connector->dev;
2017 struct drm_crtc *crtc = NULL;
2018 struct dm_crtc_state *dm_crtc_state = NULL;
2019 struct pipe_ctx *pipe_ctx;
2020 int i;
2021 char *wr_buf = NULL;
2022 uint32_t wr_buf_size = 42;
2023 int max_param_num = 1;
2024 uint8_t param_nums = 0;
2025 long param[1] = {0};
2026
2027 if (size == 0)
2028 return -EINVAL;
2029
2030 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2031
2032 if (!wr_buf) {
2033 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2034 return -ENOSPC;
2035 }
2036
2037 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2038 (long *)param, buf,
2039 max_param_num,
2040 ¶m_nums)) {
2041 kfree(wr_buf);
2042 return -EINVAL;
2043 }
2044
2045 if (param_nums <= 0) {
2046 DRM_DEBUG_DRIVER("user data not be read\n");
2047 kfree(wr_buf);
2048 return -EINVAL;
2049 }
2050
2051 for (i = 0; i < MAX_PIPES; i++) {
2052 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2053 if (pipe_ctx->stream &&
2054 pipe_ctx->stream->link == aconnector->dc_link &&
2055 pipe_ctx->stream->sink &&
2056 pipe_ctx->stream->sink == aconnector->dc_sink)
2057 break;
2058 }
2059
2060 if (!pipe_ctx->stream)
2061 goto done;
2062
2063 // Get CRTC state
2064 mutex_lock(&dev->mode_config.mutex);
2065 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2066
2067 if (connector->state == NULL)
2068 goto unlock;
2069
2070 crtc = connector->state->crtc;
2071 if (crtc == NULL)
2072 goto unlock;
2073
2074 drm_modeset_lock(&crtc->mutex, NULL);
2075 if (crtc->state == NULL)
2076 goto unlock;
2077
2078 dm_crtc_state = to_dm_crtc_state(crtc->state);
2079 if (dm_crtc_state->stream == NULL)
2080 goto unlock;
2081
2082 if (param[0] > 0)
2083 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2084 pipe_ctx->stream->timing.v_addressable,
2085 param[0]);
2086 else
2087 aconnector->dsc_settings.dsc_num_slices_v = 0;
2088
2089 dm_crtc_state->dsc_force_changed = true;
2090
2091 unlock:
2092 if (crtc)
2093 drm_modeset_unlock(&crtc->mutex);
2094 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2095 mutex_unlock(&dev->mode_config.mutex);
2096
2097 done:
2098 kfree(wr_buf);
2099 return size;
2100 }
2101
2102 /* function: read DSC target rate on the connector in bits per pixel
2103 *
2104 * The read function: dp_dsc_bits_per_pixel_read
2105 * returns target rate of compression in bits per pixel
2106 * The return is an integer: 0 or other positive integer
2107 *
2108 * Access it with the following command:
2109 *
2110 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2111 *
2112 * 0 - means that DSC is disabled
2113 */
dp_dsc_bits_per_pixel_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2114 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2115 size_t size, loff_t *pos)
2116 {
2117 char *rd_buf = NULL;
2118 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2119 struct display_stream_compressor *dsc;
2120 struct dcn_dsc_state dsc_state = {0};
2121 const uint32_t rd_buf_size = 100;
2122 struct pipe_ctx *pipe_ctx;
2123 ssize_t result = 0;
2124 int i, r, str_len = 30;
2125
2126 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2127
2128 if (!rd_buf)
2129 return -ENOMEM;
2130
2131 for (i = 0; i < MAX_PIPES; i++) {
2132 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2133 if (pipe_ctx->stream &&
2134 pipe_ctx->stream->link == aconnector->dc_link &&
2135 pipe_ctx->stream->sink &&
2136 pipe_ctx->stream->sink == aconnector->dc_sink)
2137 break;
2138 }
2139
2140 dsc = pipe_ctx->stream_res.dsc;
2141 if (dsc)
2142 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2143
2144 snprintf(rd_buf, str_len,
2145 "%d\n",
2146 dsc_state.dsc_bits_per_pixel);
2147
2148 while (size) {
2149 if (*pos >= rd_buf_size)
2150 break;
2151
2152 r = put_user(*(rd_buf + result), buf);
2153 if (r) {
2154 kfree(rd_buf);
2155 return r; /* r = -EFAULT */
2156 }
2157
2158 buf += 1;
2159 size -= 1;
2160 *pos += 1;
2161 result += 1;
2162 }
2163
2164 kfree(rd_buf);
2165 return result;
2166 }
2167
2168 /* function: write DSC target rate in bits per pixel
2169 *
2170 * The write function: dp_dsc_bits_per_pixel_write
2171 * overwrites automatically generated DSC configuration
2172 * of DSC target bit rate.
2173 *
2174 * Also the user has to write bpp in hexidecimal
2175 * rather than in decimal.
2176 *
2177 * Writing DSC settings is done with the following command:
2178 * - To force overwrite rate (example sets to 256 bpp x 1/16):
2179 *
2180 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2181 *
2182 * - To stop overwriting and let driver find the optimal rate,
2183 * set the rate to zero:
2184 *
2185 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2186 *
2187 */
dp_dsc_bits_per_pixel_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2188 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2189 size_t size, loff_t *pos)
2190 {
2191 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2192 struct drm_connector *connector = &aconnector->base;
2193 struct drm_device *dev = connector->dev;
2194 struct drm_crtc *crtc = NULL;
2195 struct dm_crtc_state *dm_crtc_state = NULL;
2196 struct pipe_ctx *pipe_ctx;
2197 int i;
2198 char *wr_buf = NULL;
2199 uint32_t wr_buf_size = 42;
2200 int max_param_num = 1;
2201 uint8_t param_nums = 0;
2202 long param[1] = {0};
2203
2204 if (size == 0)
2205 return -EINVAL;
2206
2207 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2208
2209 if (!wr_buf) {
2210 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2211 return -ENOSPC;
2212 }
2213
2214 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2215 (long *)param, buf,
2216 max_param_num,
2217 ¶m_nums)) {
2218 kfree(wr_buf);
2219 return -EINVAL;
2220 }
2221
2222 if (param_nums <= 0) {
2223 DRM_DEBUG_DRIVER("user data not be read\n");
2224 kfree(wr_buf);
2225 return -EINVAL;
2226 }
2227
2228 for (i = 0; i < MAX_PIPES; i++) {
2229 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2230 if (pipe_ctx->stream &&
2231 pipe_ctx->stream->link == aconnector->dc_link &&
2232 pipe_ctx->stream->sink &&
2233 pipe_ctx->stream->sink == aconnector->dc_sink)
2234 break;
2235 }
2236
2237 if (!pipe_ctx->stream)
2238 goto done;
2239
2240 // Get CRTC state
2241 mutex_lock(&dev->mode_config.mutex);
2242 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2243
2244 if (connector->state == NULL)
2245 goto unlock;
2246
2247 crtc = connector->state->crtc;
2248 if (crtc == NULL)
2249 goto unlock;
2250
2251 drm_modeset_lock(&crtc->mutex, NULL);
2252 if (crtc->state == NULL)
2253 goto unlock;
2254
2255 dm_crtc_state = to_dm_crtc_state(crtc->state);
2256 if (dm_crtc_state->stream == NULL)
2257 goto unlock;
2258
2259 aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2260
2261 dm_crtc_state->dsc_force_changed = true;
2262
2263 unlock:
2264 if (crtc)
2265 drm_modeset_unlock(&crtc->mutex);
2266 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2267 mutex_unlock(&dev->mode_config.mutex);
2268
2269 done:
2270 kfree(wr_buf);
2271 return size;
2272 }
2273
2274 /* function: read DSC picture width parameter on the connector
2275 *
2276 * The read function: dp_dsc_pic_width_read
2277 * returns dsc picture width used in the current configuration
2278 * It is the same as h_addressable of the current
2279 * display's timing
2280 * The return is an integer: 0 or other positive integer
2281 * If 0 then DSC is disabled.
2282 *
2283 * Access it with the following command:
2284 *
2285 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2286 *
2287 * 0 - means that DSC is disabled
2288 */
dp_dsc_pic_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2289 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2290 size_t size, loff_t *pos)
2291 {
2292 char *rd_buf = NULL;
2293 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2294 struct display_stream_compressor *dsc;
2295 struct dcn_dsc_state dsc_state = {0};
2296 const uint32_t rd_buf_size = 100;
2297 struct pipe_ctx *pipe_ctx;
2298 ssize_t result = 0;
2299 int i, r, str_len = 30;
2300
2301 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2302
2303 if (!rd_buf)
2304 return -ENOMEM;
2305
2306 for (i = 0; i < MAX_PIPES; i++) {
2307 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2308 if (pipe_ctx->stream &&
2309 pipe_ctx->stream->link == aconnector->dc_link &&
2310 pipe_ctx->stream->sink &&
2311 pipe_ctx->stream->sink == aconnector->dc_sink)
2312 break;
2313 }
2314
2315 dsc = pipe_ctx->stream_res.dsc;
2316 if (dsc)
2317 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2318
2319 snprintf(rd_buf, str_len,
2320 "%d\n",
2321 dsc_state.dsc_pic_width);
2322
2323 while (size) {
2324 if (*pos >= rd_buf_size)
2325 break;
2326
2327 r = put_user(*(rd_buf + result), buf);
2328 if (r) {
2329 kfree(rd_buf);
2330 return r; /* r = -EFAULT */
2331 }
2332
2333 buf += 1;
2334 size -= 1;
2335 *pos += 1;
2336 result += 1;
2337 }
2338
2339 kfree(rd_buf);
2340 return result;
2341 }
2342
dp_dsc_pic_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2343 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2344 size_t size, loff_t *pos)
2345 {
2346 char *rd_buf = NULL;
2347 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2348 struct display_stream_compressor *dsc;
2349 struct dcn_dsc_state dsc_state = {0};
2350 const uint32_t rd_buf_size = 100;
2351 struct pipe_ctx *pipe_ctx;
2352 ssize_t result = 0;
2353 int i, r, str_len = 30;
2354
2355 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2356
2357 if (!rd_buf)
2358 return -ENOMEM;
2359
2360 for (i = 0; i < MAX_PIPES; i++) {
2361 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2362 if (pipe_ctx->stream &&
2363 pipe_ctx->stream->link == aconnector->dc_link &&
2364 pipe_ctx->stream->sink &&
2365 pipe_ctx->stream->sink == aconnector->dc_sink)
2366 break;
2367 }
2368
2369 dsc = pipe_ctx->stream_res.dsc;
2370 if (dsc)
2371 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2372
2373 snprintf(rd_buf, str_len,
2374 "%d\n",
2375 dsc_state.dsc_pic_height);
2376
2377 while (size) {
2378 if (*pos >= rd_buf_size)
2379 break;
2380
2381 r = put_user(*(rd_buf + result), buf);
2382 if (r) {
2383 kfree(rd_buf);
2384 return r; /* r = -EFAULT */
2385 }
2386
2387 buf += 1;
2388 size -= 1;
2389 *pos += 1;
2390 result += 1;
2391 }
2392
2393 kfree(rd_buf);
2394 return result;
2395 }
2396
2397 /* function: read DSC chunk size parameter on the connector
2398 *
2399 * The read function: dp_dsc_chunk_size_read
2400 * returns dsc chunk size set in the current configuration
2401 * The value is calculated automatically by DSC code
2402 * and depends on slice parameters and bpp target rate
2403 * The return is an integer: 0 or other positive integer
2404 * If 0 then DSC is disabled.
2405 *
2406 * Access it with the following command:
2407 *
2408 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2409 *
2410 * 0 - means that DSC is disabled
2411 */
dp_dsc_chunk_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2412 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2413 size_t size, loff_t *pos)
2414 {
2415 char *rd_buf = NULL;
2416 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2417 struct display_stream_compressor *dsc;
2418 struct dcn_dsc_state dsc_state = {0};
2419 const uint32_t rd_buf_size = 100;
2420 struct pipe_ctx *pipe_ctx;
2421 ssize_t result = 0;
2422 int i, r, str_len = 30;
2423
2424 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2425
2426 if (!rd_buf)
2427 return -ENOMEM;
2428
2429 for (i = 0; i < MAX_PIPES; i++) {
2430 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2431 if (pipe_ctx->stream &&
2432 pipe_ctx->stream->link == aconnector->dc_link &&
2433 pipe_ctx->stream->sink &&
2434 pipe_ctx->stream->sink == aconnector->dc_sink)
2435 break;
2436 }
2437
2438 dsc = pipe_ctx->stream_res.dsc;
2439 if (dsc)
2440 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2441
2442 snprintf(rd_buf, str_len,
2443 "%d\n",
2444 dsc_state.dsc_chunk_size);
2445
2446 while (size) {
2447 if (*pos >= rd_buf_size)
2448 break;
2449
2450 r = put_user(*(rd_buf + result), buf);
2451 if (r) {
2452 kfree(rd_buf);
2453 return r; /* r = -EFAULT */
2454 }
2455
2456 buf += 1;
2457 size -= 1;
2458 *pos += 1;
2459 result += 1;
2460 }
2461
2462 kfree(rd_buf);
2463 return result;
2464 }
2465
2466 /* function: read DSC slice bpg offset on the connector
2467 *
2468 * The read function: dp_dsc_slice_bpg_offset_read
2469 * returns dsc bpg slice offset set in the current configuration
2470 * The value is calculated automatically by DSC code
2471 * and depends on slice parameters and bpp target rate
2472 * The return is an integer: 0 or other positive integer
2473 * If 0 then DSC is disabled.
2474 *
2475 * Access it with the following command:
2476 *
2477 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2478 *
2479 * 0 - means that DSC is disabled
2480 */
dp_dsc_slice_bpg_offset_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2481 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2482 size_t size, loff_t *pos)
2483 {
2484 char *rd_buf = NULL;
2485 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2486 struct display_stream_compressor *dsc;
2487 struct dcn_dsc_state dsc_state = {0};
2488 const uint32_t rd_buf_size = 100;
2489 struct pipe_ctx *pipe_ctx;
2490 ssize_t result = 0;
2491 int i, r, str_len = 30;
2492
2493 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2494
2495 if (!rd_buf)
2496 return -ENOMEM;
2497
2498 for (i = 0; i < MAX_PIPES; i++) {
2499 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2500 if (pipe_ctx->stream &&
2501 pipe_ctx->stream->link == aconnector->dc_link &&
2502 pipe_ctx->stream->sink &&
2503 pipe_ctx->stream->sink == aconnector->dc_sink)
2504 break;
2505 }
2506
2507 dsc = pipe_ctx->stream_res.dsc;
2508 if (dsc)
2509 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2510
2511 snprintf(rd_buf, str_len,
2512 "%d\n",
2513 dsc_state.dsc_slice_bpg_offset);
2514
2515 while (size) {
2516 if (*pos >= rd_buf_size)
2517 break;
2518
2519 r = put_user(*(rd_buf + result), buf);
2520 if (r) {
2521 kfree(rd_buf);
2522 return r; /* r = -EFAULT */
2523 }
2524
2525 buf += 1;
2526 size -= 1;
2527 *pos += 1;
2528 result += 1;
2529 }
2530
2531 kfree(rd_buf);
2532 return result;
2533 }
2534
2535
2536 /*
2537 * function description: Read max_requested_bpc property from the connector
2538 *
2539 * Access it with the following command:
2540 *
2541 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2542 *
2543 */
dp_max_bpc_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2544 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2545 size_t size, loff_t *pos)
2546 {
2547 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2548 struct drm_connector *connector = &aconnector->base;
2549 struct drm_device *dev = connector->dev;
2550 struct dm_connector_state *state;
2551 ssize_t result = 0;
2552 char *rd_buf = NULL;
2553 char *rd_buf_ptr = NULL;
2554 const uint32_t rd_buf_size = 10;
2555 int r;
2556
2557 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2558
2559 if (!rd_buf)
2560 return -ENOMEM;
2561
2562 mutex_lock(&dev->mode_config.mutex);
2563 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2564
2565 if (connector->state == NULL)
2566 goto unlock;
2567
2568 state = to_dm_connector_state(connector->state);
2569
2570 rd_buf_ptr = rd_buf;
2571 snprintf(rd_buf_ptr, rd_buf_size,
2572 "%u\n",
2573 state->base.max_requested_bpc);
2574
2575 while (size) {
2576 if (*pos >= rd_buf_size)
2577 break;
2578
2579 r = put_user(*(rd_buf + result), buf);
2580 if (r) {
2581 result = r; /* r = -EFAULT */
2582 goto unlock;
2583 }
2584 buf += 1;
2585 size -= 1;
2586 *pos += 1;
2587 result += 1;
2588 }
2589 unlock:
2590 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2591 mutex_unlock(&dev->mode_config.mutex);
2592 kfree(rd_buf);
2593 return result;
2594 }
2595
2596
2597 /*
2598 * function description: Set max_requested_bpc property on the connector
2599 *
2600 * This function will not force the input BPC on connector, it will only
2601 * change the max value. This is equivalent to setting max_bpc through
2602 * xrandr.
2603 *
2604 * The BPC value written must be >= 6 and <= 16. Values outside of this
2605 * range will result in errors.
2606 *
2607 * BPC values:
2608 * 0x6 - 6 BPC
2609 * 0x8 - 8 BPC
2610 * 0xa - 10 BPC
2611 * 0xc - 12 BPC
2612 * 0x10 - 16 BPC
2613 *
2614 * Write the max_bpc in the following way:
2615 *
2616 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2617 *
2618 */
dp_max_bpc_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2619 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2620 size_t size, loff_t *pos)
2621 {
2622 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2623 struct drm_connector *connector = &aconnector->base;
2624 struct dm_connector_state *state;
2625 struct drm_device *dev = connector->dev;
2626 char *wr_buf = NULL;
2627 uint32_t wr_buf_size = 42;
2628 int max_param_num = 1;
2629 long param[1] = {0};
2630 uint8_t param_nums = 0;
2631
2632 if (size == 0)
2633 return -EINVAL;
2634
2635 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2636
2637 if (!wr_buf) {
2638 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2639 return -ENOSPC;
2640 }
2641
2642 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2643 (long *)param, buf,
2644 max_param_num,
2645 ¶m_nums)) {
2646 kfree(wr_buf);
2647 return -EINVAL;
2648 }
2649
2650 if (param_nums <= 0) {
2651 DRM_DEBUG_DRIVER("user data not be read\n");
2652 kfree(wr_buf);
2653 return -EINVAL;
2654 }
2655
2656 if (param[0] < 6 || param[0] > 16) {
2657 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2658 kfree(wr_buf);
2659 return -EINVAL;
2660 }
2661
2662 mutex_lock(&dev->mode_config.mutex);
2663 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2664
2665 if (connector->state == NULL)
2666 goto unlock;
2667
2668 state = to_dm_connector_state(connector->state);
2669 state->base.max_requested_bpc = param[0];
2670 unlock:
2671 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2672 mutex_unlock(&dev->mode_config.mutex);
2673
2674 kfree(wr_buf);
2675 return size;
2676 }
2677
2678 /*
2679 * IPS status. Read only.
2680 *
2681 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2682 */
ips_status_show(struct seq_file * m,void * unused)2683 static int ips_status_show(struct seq_file *m, void *unused)
2684 {
2685 struct amdgpu_device *adev = m->private;
2686 struct dc *dc = adev->dm.dc;
2687 struct dc_dmub_srv *dc_dmub_srv;
2688
2689 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
2690 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2691
2692 if (adev->dm.idle_workqueue) {
2693 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2694 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2695 }
2696
2697 dc_dmub_srv = dc->ctx->dmub_srv;
2698 if (dc_dmub_srv && dc_dmub_srv->dmub) {
2699 uint32_t rcg_count, ips1_count, ips2_count;
2700 volatile const struct dmub_shared_state_ips_fw *ips_fw =
2701 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2702 rcg_count = ips_fw->rcg_entry_count;
2703 ips1_count = ips_fw->ips1_entry_count;
2704 ips2_count = ips_fw->ips2_entry_count;
2705 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
2706 rcg_count,
2707 ips1_count,
2708 ips2_count);
2709 rcg_count = ips_fw->rcg_exit_count;
2710 ips1_count = ips_fw->ips1_exit_count;
2711 ips2_count = ips_fw->ips2_exit_count;
2712 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u",
2713 rcg_count,
2714 ips1_count,
2715 ips2_count);
2716 seq_puts(m, "\n");
2717 }
2718 return 0;
2719 }
2720
2721 /*
2722 * IPS residency information from DMUB service. Read only.
2723 *
2724 * For time-window (segment) measurement:
2725 * 1) echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2726 * 2) sleep <seconds>
2727 * 3) echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2728 * 4) cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency
2729 */
ips_residency_show(struct seq_file * m,void * unused)2730 static int ips_residency_show(struct seq_file *m, void *unused)
2731 {
2732 struct amdgpu_device *adev = m->private;
2733 struct dc *dc = adev->dm.dc;
2734 uint8_t panel_inst = 0;
2735 enum ips_residency_mode mode;
2736 struct dmub_ips_residency_info info;
2737
2738 mutex_lock(&adev->dm.dc_lock);
2739
2740 mode = IPS_RESIDENCY__IPS1_RCG;
2741 if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {
2742 seq_printf(m, "ISP query failed\n");
2743 } else {
2744 unsigned int pct, frac;
2745 pct = info.residency_millipercent / 1000;
2746 frac = info.residency_millipercent % 1000;
2747
2748 seq_printf(m, "IPS residency: %u.%03u%% \n", pct, frac);
2749 seq_printf(m, " entry_counter: %u\n", info.entry_counter);
2750 seq_printf(m, " total_time_us: %llu\n",
2751 (unsigned long long)info.total_time_us);
2752 seq_printf(m, " total_inactive_time_us: %llu\n",
2753 (unsigned long long)info.total_inactive_time_us);
2754 }
2755 mutex_unlock(&adev->dm.dc_lock);
2756 return 0;
2757 }
2758
ips_residency_cntl_get(void * data,u64 * val)2759 static int ips_residency_cntl_get(void *data, u64 *val)
2760 {
2761 *val = 0;
2762 return 0;
2763 }
2764
ips_residency_cntl_set(void * data,u64 val)2765 static int ips_residency_cntl_set(void *data, u64 val)
2766 {
2767 struct amdgpu_device *adev = data;
2768 struct dc *dc = adev->dm.dc;
2769 uint8_t panel_inst = 0;
2770 int ret = 0;
2771
2772 mutex_lock(&adev->dm.dc_lock);
2773 if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))
2774 ret = -EIO;
2775 mutex_unlock(&adev->dm.dc_lock);
2776
2777 return ret;
2778 }
2779
2780 /*
2781 * Backlight at this moment. Read only.
2782 * As written to display, taking ABM and backlight lut into account.
2783 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2784 *
2785 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2786 */
current_backlight_show(struct seq_file * m,void * unused)2787 static int current_backlight_show(struct seq_file *m, void *unused)
2788 {
2789 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2790 struct dc_link *link = aconnector->dc_link;
2791 unsigned int backlight;
2792
2793 backlight = dc_link_get_backlight_level(link);
2794 seq_printf(m, "0x%x\n", backlight);
2795
2796 return 0;
2797 }
2798
2799 /*
2800 * Backlight value that is being approached. Read only.
2801 * As written to display, taking ABM and backlight lut into account.
2802 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2803 *
2804 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2805 */
target_backlight_show(struct seq_file * m,void * unused)2806 static int target_backlight_show(struct seq_file *m, void *unused)
2807 {
2808 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2809 struct dc_link *link = aconnector->dc_link;
2810 unsigned int backlight;
2811
2812 backlight = dc_link_get_target_backlight_pwm(link);
2813 seq_printf(m, "0x%x\n", backlight);
2814
2815 return 0;
2816 }
2817
2818 /*
2819 * function description: Determine if the connector is mst connector
2820 *
2821 * This function helps to determine whether a connector is a mst connector.
2822 * - "root" stands for the root connector of the topology
2823 * - "branch" stands for branch device of the topology
2824 * - "end" stands for leaf node connector of the topology
2825 * - "no" stands for the connector is not a device of a mst topology
2826 * Access it with the following command:
2827 *
2828 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2829 *
2830 */
dp_is_mst_connector_show(struct seq_file * m,void * unused)2831 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2832 {
2833 struct drm_connector *connector = m->private;
2834 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2835 struct drm_dp_mst_topology_mgr *mgr = NULL;
2836 struct drm_dp_mst_port *port = NULL;
2837 char *role = NULL;
2838
2839 mutex_lock(&aconnector->hpd_lock);
2840
2841 if (aconnector->mst_mgr.mst_state) {
2842 role = "root";
2843 } else if (aconnector->mst_root &&
2844 aconnector->mst_root->mst_mgr.mst_state) {
2845
2846 role = "end";
2847
2848 mgr = &aconnector->mst_root->mst_mgr;
2849 port = aconnector->mst_output_port;
2850
2851 drm_modeset_lock(&mgr->base.lock, NULL);
2852 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2853 port->mcs)
2854 role = "branch";
2855 drm_modeset_unlock(&mgr->base.lock);
2856
2857 } else {
2858 role = "no";
2859 }
2860
2861 seq_printf(m, "%s\n", role);
2862
2863 mutex_unlock(&aconnector->hpd_lock);
2864
2865 return 0;
2866 }
2867
2868 /*
2869 * function description: Read out the mst progress status
2870 *
2871 * This function helps to determine the mst progress status of
2872 * a mst connector.
2873 *
2874 * Access it with the following command:
2875 *
2876 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2877 *
2878 */
dp_mst_progress_status_show(struct seq_file * m,void * unused)2879 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2880 {
2881 struct drm_connector *connector = m->private;
2882 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2883 struct amdgpu_device *adev = drm_to_adev(connector->dev);
2884 int i;
2885
2886 mutex_lock(&aconnector->hpd_lock);
2887 mutex_lock(&adev->dm.dc_lock);
2888
2889 if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2890 seq_puts(m, "disabled\n");
2891 } else {
2892 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2893 seq_printf(m, "%s:%s\n",
2894 mst_progress_status[i],
2895 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2896 }
2897
2898 mutex_unlock(&adev->dm.dc_lock);
2899 mutex_unlock(&aconnector->hpd_lock);
2900
2901 return 0;
2902 }
2903
2904 /*
2905 * Reports whether the connected display is a USB4 DPIA tunneled display
2906 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2907 */
is_dpia_link_show(struct seq_file * m,void * data)2908 static int is_dpia_link_show(struct seq_file *m, void *data)
2909 {
2910 struct drm_connector *connector = m->private;
2911 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2912 struct dc_link *link = aconnector->dc_link;
2913
2914 if (connector->status != connector_status_connected)
2915 return -ENODEV;
2916
2917 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2918 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2919
2920 return 0;
2921 }
2922
2923 /**
2924 * hdmi_cec_state_show - Read out the HDMI-CEC feature status
2925 * @m: sequence file.
2926 * @data: unused.
2927 *
2928 * Return 0 on success
2929 */
hdmi_cec_state_show(struct seq_file * m,void * data)2930 static int hdmi_cec_state_show(struct seq_file *m, void *data)
2931 {
2932 struct drm_connector *connector = m->private;
2933 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2934
2935 seq_printf(m, "%s:%d\n", connector->name, connector->base.id);
2936 seq_printf(m, "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0);
2937
2938 return 0;
2939 }
2940
2941 /**
2942 * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side
2943 * @f: file structure.
2944 * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.
2945 * @size: size of buffer from userpsace.
2946 * @pos: unused.
2947 *
2948 * Return size on success, error code on failure
2949 */
hdmi_cec_state_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2950 static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,
2951 size_t size, loff_t *pos)
2952 {
2953 int ret;
2954 bool enable;
2955 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2956 struct drm_device *ddev = aconnector->base.dev;
2957
2958 if (size == 0)
2959 return -EINVAL;
2960
2961 ret = kstrtobool_from_user(buf, size, &enable);
2962 if (ret) {
2963 drm_dbg_driver(ddev, "invalid user data !\n");
2964 return ret;
2965 }
2966
2967 if (enable) {
2968 if (aconnector->notifier)
2969 return -EINVAL;
2970 ret = amdgpu_dm_initialize_hdmi_connector(aconnector);
2971 if (ret)
2972 return ret;
2973 hdmi_cec_set_edid(aconnector);
2974 } else {
2975 if (!aconnector->notifier)
2976 return -EINVAL;
2977 cec_notifier_conn_unregister(aconnector->notifier);
2978 aconnector->notifier = NULL;
2979 }
2980
2981 return size;
2982 }
2983
2984 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2985 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2986 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2987 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2988 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2989 DEFINE_SHOW_ATTRIBUTE(internal_display);
2990 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2991 DEFINE_SHOW_ATTRIBUTE(replay_capability);
2992 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2993 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2994 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2995 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2996 DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);
2997
2998 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2999 .owner = THIS_MODULE,
3000 .read = dp_dsc_clock_en_read,
3001 .write = dp_dsc_clock_en_write,
3002 .llseek = default_llseek
3003 };
3004
3005 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
3006 .owner = THIS_MODULE,
3007 .read = dp_dsc_slice_width_read,
3008 .write = dp_dsc_slice_width_write,
3009 .llseek = default_llseek
3010 };
3011
3012 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
3013 .owner = THIS_MODULE,
3014 .read = dp_dsc_slice_height_read,
3015 .write = dp_dsc_slice_height_write,
3016 .llseek = default_llseek
3017 };
3018
3019 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
3020 .owner = THIS_MODULE,
3021 .read = dp_dsc_bits_per_pixel_read,
3022 .write = dp_dsc_bits_per_pixel_write,
3023 .llseek = default_llseek
3024 };
3025
3026 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
3027 .owner = THIS_MODULE,
3028 .read = dp_dsc_pic_width_read,
3029 .llseek = default_llseek
3030 };
3031
3032 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
3033 .owner = THIS_MODULE,
3034 .read = dp_dsc_pic_height_read,
3035 .llseek = default_llseek
3036 };
3037
3038 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
3039 .owner = THIS_MODULE,
3040 .read = dp_dsc_chunk_size_read,
3041 .llseek = default_llseek
3042 };
3043
3044 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
3045 .owner = THIS_MODULE,
3046 .read = dp_dsc_slice_bpg_offset_read,
3047 .llseek = default_llseek
3048 };
3049
3050 static const struct file_operations trigger_hotplug_debugfs_fops = {
3051 .owner = THIS_MODULE,
3052 .write = trigger_hotplug,
3053 .llseek = default_llseek
3054 };
3055
3056 static const struct file_operations dp_link_settings_debugfs_fops = {
3057 .owner = THIS_MODULE,
3058 .read = dp_link_settings_read,
3059 .write = dp_link_settings_write,
3060 .llseek = default_llseek
3061 };
3062
3063 static const struct file_operations dp_phy_settings_debugfs_fop = {
3064 .owner = THIS_MODULE,
3065 .read = dp_phy_settings_read,
3066 .write = dp_phy_settings_write,
3067 .llseek = default_llseek
3068 };
3069
3070 static const struct file_operations dp_phy_test_pattern_fops = {
3071 .owner = THIS_MODULE,
3072 .write = dp_phy_test_pattern_debugfs_write,
3073 .llseek = default_llseek
3074 };
3075
3076 static const struct file_operations sdp_message_fops = {
3077 .owner = THIS_MODULE,
3078 .write = dp_sdp_message_debugfs_write,
3079 .llseek = default_llseek
3080 };
3081
3082 static const struct file_operations dp_max_bpc_debugfs_fops = {
3083 .owner = THIS_MODULE,
3084 .read = dp_max_bpc_read,
3085 .write = dp_max_bpc_write,
3086 .llseek = default_llseek
3087 };
3088
3089 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
3090 .owner = THIS_MODULE,
3091 .write = dp_dsc_passthrough_set,
3092 .llseek = default_llseek
3093 };
3094
3095 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
3096 .owner = THIS_MODULE,
3097 .write = dp_mst_link_setting,
3098 .llseek = default_llseek
3099 };
3100
3101 static const struct {
3102 char *name;
3103 const struct file_operations *fops;
3104 } dp_debugfs_entries[] = {
3105 {"link_settings", &dp_link_settings_debugfs_fops},
3106 {"phy_settings", &dp_phy_settings_debugfs_fop},
3107 {"lttpr_status", &dp_lttpr_status_fops},
3108 {"test_pattern", &dp_phy_test_pattern_fops},
3109 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3110 {"sdp_message", &sdp_message_fops},
3111 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
3112 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
3113 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
3114 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
3115 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
3116 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
3117 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
3118 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
3119 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
3120 {"max_bpc", &dp_max_bpc_debugfs_fops},
3121 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
3122 {"is_mst_connector", &dp_is_mst_connector_fops},
3123 {"mst_progress_status", &dp_mst_progress_status_fops},
3124 {"is_dpia_link", &is_dpia_link_fops},
3125 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
3126 };
3127
3128 static const struct {
3129 char *name;
3130 const struct file_operations *fops;
3131 } hdmi_debugfs_entries[] = {
3132 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3133 {"hdmi_cec_state", &hdmi_cec_state_fops}
3134 };
3135
3136 /*
3137 * Force YUV420 output if available from the given mode
3138 */
force_yuv420_output_set(void * data,u64 val)3139 static int force_yuv420_output_set(void *data, u64 val)
3140 {
3141 struct amdgpu_dm_connector *connector = data;
3142
3143 connector->force_yuv420_output = (bool)val;
3144
3145 return 0;
3146 }
3147
3148 /*
3149 * Check if YUV420 is forced when available from the given mode
3150 */
force_yuv420_output_get(void * data,u64 * val)3151 static int force_yuv420_output_get(void *data, u64 *val)
3152 {
3153 struct amdgpu_dm_connector *connector = data;
3154
3155 *val = connector->force_yuv420_output;
3156
3157 return 0;
3158 }
3159
3160 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
3161 force_yuv420_output_set, "%llu\n");
3162
3163 /*
3164 * Read Replay state
3165 */
replay_get_state(void * data,u64 * val)3166 static int replay_get_state(void *data, u64 *val)
3167 {
3168 struct amdgpu_dm_connector *connector = data;
3169 struct dc_link *link = connector->dc_link;
3170 uint64_t state = REPLAY_STATE_INVALID;
3171
3172 dc_link_get_replay_state(link, &state);
3173
3174 *val = state;
3175
3176 return 0;
3177 }
3178
3179 /*
3180 * Start / Stop capture Replay residency
3181 */
replay_set_residency(void * data,u64 val)3182 static int replay_set_residency(void *data, u64 val)
3183 {
3184 struct amdgpu_dm_connector *connector = data;
3185 struct dc_link *link = connector->dc_link;
3186 bool is_start = (val != 0);
3187 u32 residency = 0;
3188
3189 link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
3190 return 0;
3191 }
3192
3193 /*
3194 * Read Replay residency
3195 */
replay_get_residency(void * data,u64 * val)3196 static int replay_get_residency(void *data, u64 *val)
3197 {
3198 struct amdgpu_dm_connector *connector = data;
3199 struct dc_link *link = connector->dc_link;
3200 u32 residency = 0;
3201
3202 link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
3203 *val = (u64)residency;
3204
3205 return 0;
3206 }
3207
3208 /*
3209 * Read PSR state
3210 */
psr_get(void * data,u64 * val)3211 static int psr_get(void *data, u64 *val)
3212 {
3213 struct amdgpu_dm_connector *connector = data;
3214 struct dc_link *link = connector->dc_link;
3215 enum dc_psr_state state = PSR_STATE0;
3216
3217 dc_link_get_psr_state(link, &state);
3218
3219 *val = state;
3220
3221 return 0;
3222 }
3223
3224 /*
3225 * Read PSR state residency
3226 */
psr_read_residency(void * data,u64 * val)3227 static int psr_read_residency(void *data, u64 *val)
3228 {
3229 struct amdgpu_dm_connector *connector = data;
3230 struct dc_link *link = connector->dc_link;
3231 u32 residency = 0;
3232
3233 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3234
3235 *val = (u64)residency;
3236
3237 return 0;
3238 }
3239
3240 /* read allow_edp_hotplug_detection */
allow_edp_hotplug_detection_get(void * data,u64 * val)3241 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3242 {
3243 struct amdgpu_dm_connector *aconnector = data;
3244 struct drm_connector *connector = &aconnector->base;
3245 struct drm_device *dev = connector->dev;
3246 struct amdgpu_device *adev = drm_to_adev(dev);
3247
3248 *val = adev->dm.dc->config.allow_edp_hotplug_detection;
3249
3250 return 0;
3251 }
3252
3253 /* set allow_edp_hotplug_detection */
allow_edp_hotplug_detection_set(void * data,u64 val)3254 static int allow_edp_hotplug_detection_set(void *data, u64 val)
3255 {
3256 struct amdgpu_dm_connector *aconnector = data;
3257 struct drm_connector *connector = &aconnector->base;
3258 struct drm_device *dev = connector->dev;
3259 struct amdgpu_device *adev = drm_to_adev(dev);
3260
3261 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3262
3263 return 0;
3264 }
3265
3266 /* check if kernel disallow eDP enter psr state
3267 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3268 * 0: allow edp enter psr; 1: disallow
3269 */
disallow_edp_enter_psr_get(void * data,u64 * val)3270 static int disallow_edp_enter_psr_get(void *data, u64 *val)
3271 {
3272 struct amdgpu_dm_connector *aconnector = data;
3273
3274 *val = (u64) aconnector->disallow_edp_enter_psr;
3275 return 0;
3276 }
3277
3278 /* set kernel disallow eDP enter psr state
3279 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3280 * 0: allow edp enter psr; 1: disallow
3281 *
3282 * usage: test app read crc from PSR eDP rx.
3283 *
3284 * during kernel boot up, kernel write dpcd 0x170 = 5.
3285 * this notify eDP rx psr enable and let rx check crc.
3286 * rx fw will start checking crc for rx internal logic.
3287 * crc read count within dpcd 0x246 is not updated and
3288 * value is 0. when eDP tx driver wants to read rx crc
3289 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3290 * timeout.
3291 *
3292 * to avoid this, we add this debugfs to let test app to disbable
3293 * rx crc checking for rx internal logic. then test app can read
3294 * non-zero crc read count.
3295 *
3296 * expected app sequence is as below:
3297 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3298 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3299 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3300 * without dpcd 0x170 = 5.
3301 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3302 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3303 * this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3304 */
disallow_edp_enter_psr_set(void * data,u64 val)3305 static int disallow_edp_enter_psr_set(void *data, u64 val)
3306 {
3307 struct amdgpu_dm_connector *aconnector = data;
3308
3309 aconnector->disallow_edp_enter_psr = val ? true : false;
3310 return 0;
3311 }
3312
3313 /* check if kernel disallow eDP enter replay state
3314 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3315 * 0: allow edp enter replay; 1: disallow
3316 */
disallow_edp_enter_replay_get(void * data,u64 * val)3317 static int disallow_edp_enter_replay_get(void *data, u64 *val)
3318 {
3319 struct amdgpu_dm_connector *aconnector = data;
3320
3321 *val = (u64) aconnector->disallow_edp_enter_replay;
3322 return 0;
3323 }
3324
3325 /* set kernel disallow eDP enter replay state
3326 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3327 * 0: allow edp enter replay; 1: disallow
3328 *
3329 * usage: test app read crc from PSR eDP rx.
3330 *
3331 * during kernel boot up, kernel write dpcd 0x37b to
3332 * notify eDP rx replay enable.
3333 * rx fw will start checking crc for rx internal logic.
3334 * crc read count within dpcd 0x246 is not updated and
3335 * value is 0. when eDP tx driver wants to read rx crc
3336 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3337 * timeout.
3338 *
3339 * to avoid this, we add this debugfs to let test app to disbable
3340 * rx replay. then test app can read non-zero crc read count.
3341 *
3342 * expected app sequence is as below:
3343 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3344 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3345 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3346 * without programming dpcd 0x37b.
3347 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3348 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay.
3349 * this will let eDP back to normal with replay setup dpcd 0x37b.
3350 */
disallow_edp_enter_replay_set(void * data,u64 val)3351 static int disallow_edp_enter_replay_set(void *data, u64 val)
3352 {
3353 struct amdgpu_dm_connector *aconnector = data;
3354
3355 aconnector->disallow_edp_enter_replay = val ? true : false;
3356 return 0;
3357 }
3358
dmub_trace_mask_set(void * data,u64 val)3359 static int dmub_trace_mask_set(void *data, u64 val)
3360 {
3361 struct amdgpu_device *adev = data;
3362 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3363 enum dmub_gpint_command cmd;
3364 u64 mask = 0xffff;
3365 u8 shift = 0;
3366 u32 res;
3367 int i;
3368
3369 if (!srv->fw_version)
3370 return -EINVAL;
3371
3372 for (i = 0; i < 4; i++) {
3373 res = (val & mask) >> shift;
3374
3375 switch (i) {
3376 case 0:
3377 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3378 break;
3379 case 1:
3380 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3381 break;
3382 case 2:
3383 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3384 break;
3385 case 3:
3386 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3387 break;
3388 }
3389
3390 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3391 return -EIO;
3392
3393 usleep_range(100, 1000);
3394
3395 mask <<= 16;
3396 shift += 16;
3397 }
3398
3399 return 0;
3400 }
3401
dmub_trace_mask_show(void * data,u64 * val)3402 static int dmub_trace_mask_show(void *data, u64 *val)
3403 {
3404 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3405 struct amdgpu_device *adev = data;
3406 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3407 u8 shift = 0;
3408 u64 raw = 0;
3409 u64 res = 0;
3410 int i = 0;
3411
3412 if (!srv->fw_version)
3413 return -EINVAL;
3414
3415 while (i < 4) {
3416 uint32_t response;
3417
3418 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3419 return -EIO;
3420
3421 raw = response;
3422 usleep_range(100, 1000);
3423
3424 cmd++;
3425 res |= (raw << shift);
3426 shift += 16;
3427 i++;
3428 }
3429
3430 *val = res;
3431
3432 return 0;
3433 }
3434
3435 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3436 dmub_trace_mask_set, "0x%llx\n");
3437
3438 /*
3439 * Set dmcub trace event IRQ enable or disable.
3440 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3441 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3442 */
dmcub_trace_event_state_set(void * data,u64 val)3443 static int dmcub_trace_event_state_set(void *data, u64 val)
3444 {
3445 struct amdgpu_device *adev = data;
3446
3447 if (val == 1 || val == 0) {
3448 dc_dmub_trace_event_control(adev->dm.dc, val);
3449 adev->dm.dmcub_trace_event_en = (bool)val;
3450 } else
3451 return 0;
3452
3453 return 0;
3454 }
3455
3456 /*
3457 * The interface doesn't need get function, so it will return the
3458 * value of zero
3459 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3460 */
dmcub_trace_event_state_get(void * data,u64 * val)3461 static int dmcub_trace_event_state_get(void *data, u64 *val)
3462 {
3463 struct amdgpu_device *adev = data;
3464
3465 *val = adev->dm.dmcub_trace_event_en;
3466 return 0;
3467 }
3468
3469 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3470 dmcub_trace_event_state_set, "%llu\n");
3471
3472 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3473 DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency,
3474 "%llu\n");
3475 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3476 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3477 "%llu\n");
3478
3479 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3480 allow_edp_hotplug_detection_get,
3481 allow_edp_hotplug_detection_set, "%llu\n");
3482
3483 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3484 disallow_edp_enter_psr_get,
3485 disallow_edp_enter_psr_set, "%llu\n");
3486
3487 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops,
3488 disallow_edp_enter_replay_get,
3489 disallow_edp_enter_replay_set, "%llu\n");
3490
3491 DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get,
3492 ips_residency_cntl_set, "%llu\n");
3493 DEFINE_SHOW_ATTRIBUTE(current_backlight);
3494 DEFINE_SHOW_ATTRIBUTE(target_backlight);
3495 DEFINE_SHOW_ATTRIBUTE(ips_status);
3496 DEFINE_SHOW_ATTRIBUTE(ips_residency);
3497
3498 static const struct {
3499 char *name;
3500 const struct file_operations *fops;
3501 } connector_debugfs_entries[] = {
3502 {"force_yuv420_output", &force_yuv420_output_fops},
3503 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3504 {"internal_display", &internal_display_fops},
3505 {"odm_combine_segments", &odm_combine_segments_fops}
3506 };
3507
3508 /*
3509 * Returns supported customized link rates by this eDP panel.
3510 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3511 */
edp_ilr_show(struct seq_file * m,void * unused)3512 static int edp_ilr_show(struct seq_file *m, void *unused)
3513 {
3514 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3515 struct dc_link *link = aconnector->dc_link;
3516 uint8_t supported_link_rates[16];
3517 uint32_t link_rate_in_khz;
3518 uint32_t entry = 0;
3519 uint8_t dpcd_rev;
3520
3521 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3522 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3523 supported_link_rates, sizeof(supported_link_rates));
3524
3525 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3526
3527 if (dpcd_rev >= DP_DPCD_REV_13 &&
3528 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3529
3530 for (entry = 0; entry < 16; entry += 2) {
3531 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3532 supported_link_rates[entry]) * 200;
3533 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3534 }
3535 } else {
3536 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3537 }
3538
3539 return 0;
3540 }
3541
3542 /*
3543 * Set supported customized link rate to eDP panel.
3544 *
3545 * echo <lane_count> <link_rate option> > ilr_setting
3546 *
3547 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3548 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3549 * to set 4 lanes and 2.16 GHz
3550 */
edp_ilr_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3551 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3552 size_t size, loff_t *pos)
3553 {
3554 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3555 struct dc_link *link = connector->dc_link;
3556 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3557 struct dc *dc = (struct dc *)link->dc;
3558 struct dc_link_settings prefer_link_settings;
3559 char *wr_buf = NULL;
3560 const uint32_t wr_buf_size = 40;
3561 /* 0: lane_count; 1: link_rate */
3562 int max_param_num = 2;
3563 uint8_t param_nums = 0;
3564 long param[2];
3565 bool valid_input = true;
3566 uint8_t supported_link_rates[16] = {0};
3567 uint32_t entry = 0;
3568 uint32_t link_rate_in_khz = 0;
3569 uint8_t dpcd_rev = 0;
3570
3571 if (size == 0)
3572 return -EINVAL;
3573
3574 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3575 if (!wr_buf)
3576 return -ENOMEM;
3577
3578 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3579 (long *)param, buf,
3580 max_param_num,
3581 ¶m_nums)) {
3582 kfree(wr_buf);
3583 return -EINVAL;
3584 }
3585
3586 if (param_nums <= 0) {
3587 kfree(wr_buf);
3588 return -EINVAL;
3589 }
3590
3591 switch (param[0]) {
3592 case LANE_COUNT_ONE:
3593 case LANE_COUNT_TWO:
3594 case LANE_COUNT_FOUR:
3595 break;
3596 default:
3597 valid_input = false;
3598 break;
3599 }
3600
3601 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3602 valid_input = false;
3603
3604 if (!valid_input) {
3605 kfree(wr_buf);
3606 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3607 prefer_link_settings.use_link_rate_set = false;
3608 mutex_lock(&adev->dm.dc_lock);
3609 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3610 mutex_unlock(&adev->dm.dc_lock);
3611 return size;
3612 }
3613
3614 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3615 supported_link_rates, sizeof(supported_link_rates)))
3616 return -EINVAL;
3617
3618 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3619 if (dpcd_rev < DP_DPCD_REV_13 ||
3620 (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) {
3621 return size;
3622 }
3623
3624 entry = param[1] * 2;
3625 link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 +
3626 supported_link_rates[entry]) * 200;
3627
3628 /* save user force lane_count, link_rate to preferred settings
3629 * spread spectrum will not be changed
3630 */
3631 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3632 prefer_link_settings.lane_count = param[0];
3633 prefer_link_settings.use_link_rate_set = true;
3634 prefer_link_settings.link_rate_set = param[1];
3635 prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR;
3636
3637 mutex_lock(&adev->dm.dc_lock);
3638 dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3639 NULL, link, false);
3640 mutex_unlock(&adev->dm.dc_lock);
3641
3642 kfree(wr_buf);
3643 return size;
3644 }
3645
edp_ilr_open(struct inode * inode,struct file * file)3646 static int edp_ilr_open(struct inode *inode, struct file *file)
3647 {
3648 return single_open(file, edp_ilr_show, inode->i_private);
3649 }
3650
3651 static const struct file_operations edp_ilr_debugfs_fops = {
3652 .owner = THIS_MODULE,
3653 .open = edp_ilr_open,
3654 .read = seq_read,
3655 .llseek = seq_lseek,
3656 .release = single_release,
3657 .write = edp_ilr_write
3658 };
3659
connector_debugfs_init(struct amdgpu_dm_connector * connector)3660 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3661 {
3662 int i;
3663 struct dentry *dir = connector->base.debugfs_entry;
3664
3665 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3666 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3667 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3668 debugfs_create_file(dp_debugfs_entries[i].name,
3669 0644, dir, connector,
3670 dp_debugfs_entries[i].fops);
3671 }
3672 }
3673 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3674 debugfs_create_file("replay_capability", 0444, dir, connector,
3675 &replay_capability_fops);
3676 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3677 debugfs_create_file_unsafe("replay_residency", 0444, dir,
3678 connector, &replay_residency_fops);
3679 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3680 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3681 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3682 connector, &psr_residency_fops);
3683 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3684 ¤t_backlight_fops);
3685 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3686 &target_backlight_fops);
3687 debugfs_create_file("ilr_setting", 0644, dir, connector,
3688 &edp_ilr_debugfs_fops);
3689 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3690 &allow_edp_hotplug_detection_fops);
3691 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3692 &disallow_edp_enter_psr_fops);
3693 debugfs_create_file("disallow_edp_enter_replay", 0644, dir, connector,
3694 &disallow_edp_enter_replay_fops);
3695 }
3696
3697 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3698 debugfs_create_file(connector_debugfs_entries[i].name,
3699 0644, dir, connector,
3700 connector_debugfs_entries[i].fops);
3701 }
3702
3703 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3704 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3705 debugfs_create_file(hdmi_debugfs_entries[i].name,
3706 0644, dir, connector,
3707 hdmi_debugfs_entries[i].fops);
3708 }
3709 }
3710 }
3711
3712 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3713 /*
3714 * Set crc window coordinate x start
3715 */
crc_win_x_start_set(void * data,u64 val)3716 static int crc_win_x_start_set(void *data, u64 val)
3717 {
3718 struct drm_crtc *crtc = data;
3719 struct drm_device *drm_dev = crtc->dev;
3720 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3721
3722 spin_lock_irq(&drm_dev->event_lock);
3723 acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
3724 acrtc->dm_irq_params.window_param[0].update_win = false;
3725 spin_unlock_irq(&drm_dev->event_lock);
3726
3727 return 0;
3728 }
3729
3730 /*
3731 * Get crc window coordinate x start
3732 */
crc_win_x_start_get(void * data,u64 * val)3733 static int crc_win_x_start_get(void *data, u64 *val)
3734 {
3735 struct drm_crtc *crtc = data;
3736 struct drm_device *drm_dev = crtc->dev;
3737 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3738
3739 spin_lock_irq(&drm_dev->event_lock);
3740 *val = acrtc->dm_irq_params.window_param[0].x_start;
3741 spin_unlock_irq(&drm_dev->event_lock);
3742
3743 return 0;
3744 }
3745
3746 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3747 crc_win_x_start_set, "%llu\n");
3748
3749
3750 /*
3751 * Set crc window coordinate y start
3752 */
crc_win_y_start_set(void * data,u64 val)3753 static int crc_win_y_start_set(void *data, u64 val)
3754 {
3755 struct drm_crtc *crtc = data;
3756 struct drm_device *drm_dev = crtc->dev;
3757 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3758
3759 spin_lock_irq(&drm_dev->event_lock);
3760 acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
3761 acrtc->dm_irq_params.window_param[0].update_win = false;
3762 spin_unlock_irq(&drm_dev->event_lock);
3763
3764 return 0;
3765 }
3766
3767 /*
3768 * Get crc window coordinate y start
3769 */
crc_win_y_start_get(void * data,u64 * val)3770 static int crc_win_y_start_get(void *data, u64 *val)
3771 {
3772 struct drm_crtc *crtc = data;
3773 struct drm_device *drm_dev = crtc->dev;
3774 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3775
3776 spin_lock_irq(&drm_dev->event_lock);
3777 *val = acrtc->dm_irq_params.window_param[0].y_start;
3778 spin_unlock_irq(&drm_dev->event_lock);
3779
3780 return 0;
3781 }
3782
3783 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3784 crc_win_y_start_set, "%llu\n");
3785
3786 /*
3787 * Set crc window coordinate x end
3788 */
crc_win_x_end_set(void * data,u64 val)3789 static int crc_win_x_end_set(void *data, u64 val)
3790 {
3791 struct drm_crtc *crtc = data;
3792 struct drm_device *drm_dev = crtc->dev;
3793 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3794
3795 spin_lock_irq(&drm_dev->event_lock);
3796 acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
3797 acrtc->dm_irq_params.window_param[0].update_win = false;
3798 spin_unlock_irq(&drm_dev->event_lock);
3799
3800 return 0;
3801 }
3802
3803 /*
3804 * Get crc window coordinate x end
3805 */
crc_win_x_end_get(void * data,u64 * val)3806 static int crc_win_x_end_get(void *data, u64 *val)
3807 {
3808 struct drm_crtc *crtc = data;
3809 struct drm_device *drm_dev = crtc->dev;
3810 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3811
3812 spin_lock_irq(&drm_dev->event_lock);
3813 *val = acrtc->dm_irq_params.window_param[0].x_end;
3814 spin_unlock_irq(&drm_dev->event_lock);
3815
3816 return 0;
3817 }
3818
3819 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3820 crc_win_x_end_set, "%llu\n");
3821
3822 /*
3823 * Set crc window coordinate y end
3824 */
crc_win_y_end_set(void * data,u64 val)3825 static int crc_win_y_end_set(void *data, u64 val)
3826 {
3827 struct drm_crtc *crtc = data;
3828 struct drm_device *drm_dev = crtc->dev;
3829 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3830
3831 spin_lock_irq(&drm_dev->event_lock);
3832 acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
3833 acrtc->dm_irq_params.window_param[0].update_win = false;
3834 spin_unlock_irq(&drm_dev->event_lock);
3835
3836 return 0;
3837 }
3838
3839 /*
3840 * Get crc window coordinate y end
3841 */
crc_win_y_end_get(void * data,u64 * val)3842 static int crc_win_y_end_get(void *data, u64 *val)
3843 {
3844 struct drm_crtc *crtc = data;
3845 struct drm_device *drm_dev = crtc->dev;
3846 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3847
3848 spin_lock_irq(&drm_dev->event_lock);
3849 *val = acrtc->dm_irq_params.window_param[0].y_end;
3850 spin_unlock_irq(&drm_dev->event_lock);
3851
3852 return 0;
3853 }
3854
3855 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3856 crc_win_y_end_set, "%llu\n");
3857 /*
3858 * Trigger to commit crc window
3859 */
crc_win_update_set(void * data,u64 val)3860 static int crc_win_update_set(void *data, u64 val)
3861 {
3862 struct drm_crtc *crtc = data;
3863 struct amdgpu_crtc *acrtc;
3864 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3865
3866 if (val) {
3867 acrtc = to_amdgpu_crtc(crtc);
3868 mutex_lock(&adev->dm.dc_lock);
3869 /* PSR may write to OTG CRC window control register,
3870 * so close it before starting secure_display.
3871 */
3872 amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
3873
3874 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3875
3876 acrtc->dm_irq_params.window_param[0].enable = true;
3877 acrtc->dm_irq_params.window_param[0].update_win = true;
3878 acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
3879 acrtc->dm_irq_params.crc_window_activated = true;
3880
3881 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3882 mutex_unlock(&adev->dm.dc_lock);
3883 }
3884
3885 return 0;
3886 }
3887
3888 /*
3889 * Get crc window update flag
3890 */
crc_win_update_get(void * data,u64 * val)3891 static int crc_win_update_get(void *data, u64 *val)
3892 {
3893 *val = 0;
3894 return 0;
3895 }
3896
3897 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3898 crc_win_update_set, "%llu\n");
3899
3900 /*
3901 * Trigger to set crc polynomial mode
3902 * 0: 16-bit CRC, 1: 32-bit CRC
3903 * only accepts 0 or 1 for supported hwip versions
3904 */
crc_poly_mode_set(void * data,u64 val)3905 static int crc_poly_mode_set(void *data, u64 val)
3906 {
3907 struct drm_crtc *crtc = data;
3908 struct amdgpu_crtc *acrtc;
3909 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
3910
3911 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) &&
3912 (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) &&
3913 (val < 2)) {
3914 acrtc = to_amdgpu_crtc(crtc);
3915 mutex_lock(&adev->dm.dc_lock);
3916 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3917 acrtc->dm_irq_params.crc_poly_mode = val;
3918 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3919 mutex_unlock(&adev->dm.dc_lock);
3920 }
3921
3922 return 0;
3923 }
3924
3925 /*
3926 * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC)
3927 */
crc_poly_mode_get(void * data,u64 * val)3928 static int crc_poly_mode_get(void *data, u64 *val)
3929 {
3930 struct drm_crtc *crtc = data;
3931 struct drm_device *drm_dev = crtc->dev;
3932 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3933
3934 spin_lock_irq(&drm_dev->event_lock);
3935 *val = acrtc->dm_irq_params.crc_poly_mode;
3936 spin_unlock_irq(&drm_dev->event_lock);
3937
3938 return 0;
3939 }
3940
3941 DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get,
3942 crc_poly_mode_set, "%llu\n");
3943 #endif
crtc_debugfs_init(struct drm_crtc * crtc)3944 void crtc_debugfs_init(struct drm_crtc *crtc)
3945 {
3946 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3947 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3948
3949 if (!dir)
3950 return;
3951
3952 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3953 &crc_win_x_start_fops);
3954 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3955 &crc_win_y_start_fops);
3956 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3957 &crc_win_x_end_fops);
3958 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3959 &crc_win_y_end_fops);
3960 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3961 &crc_win_update_fops);
3962 debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc,
3963 &crc_poly_mode_fops);
3964 dput(dir);
3965 #endif
3966 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3967 crtc, &amdgpu_current_bpc_fops);
3968 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3969 crtc, &amdgpu_current_colorspace_fops);
3970 }
3971
3972 /*
3973 * Writes DTN log state to the user supplied buffer.
3974 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3975 */
dtn_log_read(struct file * f,char __user * buf,size_t size,loff_t * pos)3976 static ssize_t dtn_log_read(
3977 struct file *f,
3978 char __user *buf,
3979 size_t size,
3980 loff_t *pos)
3981 {
3982 struct amdgpu_device *adev = file_inode(f)->i_private;
3983 struct dc *dc = adev->dm.dc;
3984 struct dc_log_buffer_ctx log_ctx = { 0 };
3985 ssize_t result = 0;
3986
3987 if (!buf || !size)
3988 return -EINVAL;
3989
3990 if (!dc->hwss.log_hw_state)
3991 return 0;
3992
3993 dc->hwss.log_hw_state(dc, &log_ctx);
3994
3995 if (*pos < log_ctx.pos) {
3996 size_t to_copy = log_ctx.pos - *pos;
3997
3998 to_copy = min(to_copy, size);
3999
4000 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
4001 *pos += to_copy;
4002 result = to_copy;
4003 }
4004 }
4005
4006 kfree(log_ctx.buf);
4007
4008 return result;
4009 }
4010
4011 /*
4012 * Writes DTN log state to dmesg when triggered via a write.
4013 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
4014 */
dtn_log_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)4015 static ssize_t dtn_log_write(
4016 struct file *f,
4017 const char __user *buf,
4018 size_t size,
4019 loff_t *pos)
4020 {
4021 struct amdgpu_device *adev = file_inode(f)->i_private;
4022 struct dc *dc = adev->dm.dc;
4023
4024 /* Write triggers log output via dmesg. */
4025 if (size == 0)
4026 return 0;
4027
4028 if (dc->hwss.log_hw_state)
4029 dc->hwss.log_hw_state(dc, NULL);
4030
4031 return size;
4032 }
4033
mst_topo_show(struct seq_file * m,void * unused)4034 static int mst_topo_show(struct seq_file *m, void *unused)
4035 {
4036 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4037 struct drm_device *dev = adev_to_drm(adev);
4038 struct drm_connector *connector;
4039 struct drm_connector_list_iter conn_iter;
4040 struct amdgpu_dm_connector *aconnector;
4041
4042 drm_connector_list_iter_begin(dev, &conn_iter);
4043 drm_for_each_connector_iter(connector, &conn_iter) {
4044 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
4045 continue;
4046
4047 aconnector = to_amdgpu_dm_connector(connector);
4048
4049 /* Ensure we're only dumping the topology of a root mst node */
4050 if (!aconnector->mst_mgr.mst_state)
4051 continue;
4052
4053 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
4054 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
4055 }
4056 drm_connector_list_iter_end(&conn_iter);
4057
4058 return 0;
4059 }
4060
4061 /*
4062 * Sets trigger hpd for MST topologies.
4063 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
4064 * All topologies will be disconnected if val of 0 is set .
4065 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4066 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4067 */
trigger_hpd_mst_set(void * data,u64 val)4068 static int trigger_hpd_mst_set(void *data, u64 val)
4069 {
4070 struct amdgpu_device *adev = data;
4071 struct drm_device *dev = adev_to_drm(adev);
4072 struct drm_connector_list_iter iter;
4073 struct amdgpu_dm_connector *aconnector;
4074 struct drm_connector *connector;
4075 struct dc_link *link = NULL;
4076 int ret;
4077
4078 if (val == 1) {
4079 drm_connector_list_iter_begin(dev, &iter);
4080 drm_for_each_connector_iter(connector, &iter) {
4081 aconnector = to_amdgpu_dm_connector(connector);
4082 if (aconnector->dc_link->type == dc_connection_mst_branch &&
4083 aconnector->mst_mgr.aux) {
4084 mutex_lock(&adev->dm.dc_lock);
4085 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4086 mutex_unlock(&adev->dm.dc_lock);
4087
4088 if (!ret)
4089 DRM_ERROR("DM_MST: Failed to detect dc link!");
4090
4091 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
4092 if (ret < 0)
4093 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
4094 }
4095 }
4096 } else if (val == 0) {
4097 drm_connector_list_iter_begin(dev, &iter);
4098 drm_for_each_connector_iter(connector, &iter) {
4099 aconnector = to_amdgpu_dm_connector(connector);
4100 if (!aconnector->dc_link)
4101 continue;
4102
4103 if (!aconnector->mst_root)
4104 continue;
4105
4106 link = aconnector->dc_link;
4107 dc_link_dp_receiver_power_ctrl(link, false);
4108 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
4109 link->mst_stream_alloc_table.stream_count = 0;
4110 memset(link->mst_stream_alloc_table.stream_allocations, 0,
4111 sizeof(link->mst_stream_alloc_table.stream_allocations));
4112 }
4113 } else {
4114 return 0;
4115 }
4116 drm_kms_helper_hotplug_event(dev);
4117
4118 return 0;
4119 }
4120
4121 /*
4122 * The interface doesn't need get function, so it will return the
4123 * value of zero
4124 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4125 */
trigger_hpd_mst_get(void * data,u64 * val)4126 static int trigger_hpd_mst_get(void *data, u64 *val)
4127 {
4128 *val = 0;
4129 return 0;
4130 }
4131
4132 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
4133 trigger_hpd_mst_set, "%llu\n");
4134
4135
4136 /*
4137 * Sets the force_timing_sync debug option from the given string.
4138 * All connected displays will be force synchronized immediately.
4139 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4140 */
force_timing_sync_set(void * data,u64 val)4141 static int force_timing_sync_set(void *data, u64 val)
4142 {
4143 struct amdgpu_device *adev = data;
4144
4145 adev->dm.force_timing_sync = (bool)val;
4146
4147 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
4148
4149 return 0;
4150 }
4151
4152 /*
4153 * Gets the force_timing_sync debug option value into the given buffer.
4154 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4155 */
force_timing_sync_get(void * data,u64 * val)4156 static int force_timing_sync_get(void *data, u64 *val)
4157 {
4158 struct amdgpu_device *adev = data;
4159
4160 *val = adev->dm.force_timing_sync;
4161
4162 return 0;
4163 }
4164
4165 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
4166 force_timing_sync_set, "%llu\n");
4167
4168
4169 /*
4170 * Disables all HPD and HPD RX interrupt handling in the
4171 * driver when set to 1. Default is 0.
4172 */
disable_hpd_set(void * data,u64 val)4173 static int disable_hpd_set(void *data, u64 val)
4174 {
4175 struct amdgpu_device *adev = data;
4176
4177 adev->dm.disable_hpd_irq = (bool)val;
4178
4179 return 0;
4180 }
4181
4182
4183 /*
4184 * Returns 1 if HPD and HPRX interrupt handling is disabled,
4185 * 0 otherwise.
4186 */
disable_hpd_get(void * data,u64 * val)4187 static int disable_hpd_get(void *data, u64 *val)
4188 {
4189 struct amdgpu_device *adev = data;
4190
4191 *val = adev->dm.disable_hpd_irq;
4192
4193 return 0;
4194 }
4195
4196 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
4197 disable_hpd_set, "%llu\n");
4198
4199 /*
4200 * Prints hardware capabilities. These are used for IGT testing.
4201 */
capabilities_show(struct seq_file * m,void * unused)4202 static int capabilities_show(struct seq_file *m, void *unused)
4203 {
4204 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4205 struct dc *dc = adev->dm.dc;
4206 bool mall_supported = dc->caps.mall_size_total;
4207 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
4208 unsigned int mall_in_use = false;
4209 unsigned int subvp_in_use = false;
4210
4211 struct hubbub *hubbub = dc->res_pool->hubbub;
4212
4213 if (hubbub && hubbub->funcs->get_mall_en)
4214 hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
4215
4216 if (dc->cap_funcs.get_subvp_en)
4217 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
4218
4219 seq_printf(m, "mall supported: %s, enabled: %s\n",
4220 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
4221 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
4222 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
4223
4224 return 0;
4225 }
4226
4227 DEFINE_SHOW_ATTRIBUTE(capabilities);
4228
4229 /*
4230 * Temporary w/a to force sst sequence in M42D DP2 mst receiver
4231 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
4232 */
dp_force_sst_set(void * data,u64 val)4233 static int dp_force_sst_set(void *data, u64 val)
4234 {
4235 struct amdgpu_device *adev = data;
4236
4237 adev->dm.dc->debug.set_mst_en_for_sst = val;
4238
4239 return 0;
4240 }
4241
dp_force_sst_get(void * data,u64 * val)4242 static int dp_force_sst_get(void *data, u64 *val)
4243 {
4244 struct amdgpu_device *adev = data;
4245
4246 *val = adev->dm.dc->debug.set_mst_en_for_sst;
4247
4248 return 0;
4249 }
4250 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
4251 dp_force_sst_set, "%llu\n");
4252
4253 /*
4254 * Force DP2 sequence without VESA certified cable.
4255 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
4256 */
dp_ignore_cable_id_set(void * data,u64 val)4257 static int dp_ignore_cable_id_set(void *data, u64 val)
4258 {
4259 struct amdgpu_device *adev = data;
4260
4261 adev->dm.dc->debug.ignore_cable_id = val;
4262
4263 return 0;
4264 }
4265
dp_ignore_cable_id_get(void * data,u64 * val)4266 static int dp_ignore_cable_id_get(void *data, u64 *val)
4267 {
4268 struct amdgpu_device *adev = data;
4269
4270 *val = adev->dm.dc->debug.ignore_cable_id;
4271
4272 return 0;
4273 }
4274 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
4275 dp_ignore_cable_id_set, "%llu\n");
4276
4277 /*
4278 * Sets the DC visual confirm debug option from the given string.
4279 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
4280 */
visual_confirm_set(void * data,u64 val)4281 static int visual_confirm_set(void *data, u64 val)
4282 {
4283 struct amdgpu_device *adev = data;
4284
4285 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
4286
4287 return 0;
4288 }
4289
4290 /*
4291 * Reads the DC visual confirm debug option value into the given buffer.
4292 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
4293 */
visual_confirm_get(void * data,u64 * val)4294 static int visual_confirm_get(void *data, u64 *val)
4295 {
4296 struct amdgpu_device *adev = data;
4297
4298 *val = adev->dm.dc->debug.visual_confirm;
4299
4300 return 0;
4301 }
4302
4303 DEFINE_SHOW_ATTRIBUTE(mst_topo);
4304 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
4305 visual_confirm_set, "%llu\n");
4306
4307
4308 /*
4309 * Sets the DC skip_detection_link_training debug option from the given string.
4310 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4311 */
skip_detection_link_training_set(void * data,u64 val)4312 static int skip_detection_link_training_set(void *data, u64 val)
4313 {
4314 struct amdgpu_device *adev = data;
4315
4316 if (val == 0)
4317 adev->dm.dc->debug.skip_detection_link_training = false;
4318 else
4319 adev->dm.dc->debug.skip_detection_link_training = true;
4320
4321 return 0;
4322 }
4323
4324 /*
4325 * Reads the DC skip_detection_link_training debug option value into the given buffer.
4326 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4327 */
skip_detection_link_training_get(void * data,u64 * val)4328 static int skip_detection_link_training_get(void *data, u64 *val)
4329 {
4330 struct amdgpu_device *adev = data;
4331
4332 *val = adev->dm.dc->debug.skip_detection_link_training;
4333
4334 return 0;
4335 }
4336
4337 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4338 skip_detection_link_training_get,
4339 skip_detection_link_training_set, "%llu\n");
4340
4341 /*
4342 * Dumps the DCC_EN bit for each pipe.
4343 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4344 */
dcc_en_bits_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4345 static ssize_t dcc_en_bits_read(
4346 struct file *f,
4347 char __user *buf,
4348 size_t size,
4349 loff_t *pos)
4350 {
4351 struct amdgpu_device *adev = file_inode(f)->i_private;
4352 struct dc *dc = adev->dm.dc;
4353 char *rd_buf = NULL;
4354 const uint32_t rd_buf_size = 32;
4355 uint32_t result = 0;
4356 int offset = 0;
4357 int num_pipes = dc->res_pool->pipe_count;
4358 int *dcc_en_bits;
4359 int i, r;
4360
4361 dcc_en_bits = kzalloc_objs(int, num_pipes);
4362 if (!dcc_en_bits)
4363 return -ENOMEM;
4364
4365 if (!dc->hwss.get_dcc_en_bits) {
4366 kfree(dcc_en_bits);
4367 return 0;
4368 }
4369
4370 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4371
4372 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4373 if (!rd_buf) {
4374 kfree(dcc_en_bits);
4375 return -ENOMEM;
4376 }
4377
4378 for (i = 0; i < num_pipes; i++)
4379 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
4380 "%d ", dcc_en_bits[i]);
4381 rd_buf[strlen(rd_buf)] = '\n';
4382
4383 kfree(dcc_en_bits);
4384
4385 while (size) {
4386 if (*pos >= rd_buf_size)
4387 break;
4388 r = put_user(*(rd_buf + result), buf);
4389 if (r) {
4390 kfree(rd_buf);
4391 return r; /* r = -EFAULT */
4392 }
4393 buf += 1;
4394 size -= 1;
4395 *pos += 1;
4396 result += 1;
4397 }
4398
4399 kfree(rd_buf);
4400 return result;
4401 }
4402
dtn_debugfs_init(struct amdgpu_device * adev)4403 void dtn_debugfs_init(struct amdgpu_device *adev)
4404 {
4405 static const struct file_operations dtn_log_fops = {
4406 .owner = THIS_MODULE,
4407 .read = dtn_log_read,
4408 .write = dtn_log_write,
4409 .llseek = default_llseek
4410 };
4411 static const struct file_operations dcc_en_bits_fops = {
4412 .owner = THIS_MODULE,
4413 .read = dcc_en_bits_read,
4414 .llseek = default_llseek
4415 };
4416
4417 struct drm_minor *minor = adev_to_drm(adev)->primary;
4418 struct dentry *root = minor->debugfs_root;
4419
4420 debugfs_create_file("amdgpu_mst_topology", 0444, root,
4421 adev, &mst_topo_fops);
4422 debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4423 adev, &capabilities_fops);
4424 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4425 &dtn_log_fops);
4426 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4427 &dp_set_mst_en_for_sst_ops);
4428 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4429 &dp_ignore_cable_id_ops);
4430
4431 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4432 &visual_confirm_fops);
4433
4434 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4435 &skip_detection_link_training_fops);
4436
4437 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4438 adev, &dmub_tracebuffer_fops);
4439
4440 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4441 adev, &dmub_fw_state_fops);
4442
4443 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4444 adev, &force_timing_sync_ops);
4445
4446 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4447 adev, &dmub_trace_mask_fops);
4448
4449 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4450 adev, &dmcub_trace_event_state_fops);
4451
4452 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4453 adev, &trigger_hpd_mst_ops);
4454
4455 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4456 &dcc_en_bits_fops);
4457
4458 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4459 &disable_hpd_ops);
4460
4461 if (adev->dm.dc->caps.ips_support) {
4462 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
4463 &ips_status_fops);
4464
4465 debugfs_create_file_unsafe("amdgpu_dm_ips_residency_cntl", 0644, root, adev,
4466 &ips_residency_cntl_fops);
4467
4468 debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev,
4469 &ips_residency_fops);
4470 }
4471 }
4472