| /linux/drivers/ntb/hw/intel/ |
| H A D | ntb_hw_gen3.c | 155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); in gen3_setup_b2b_mw()
166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); in gen3_setup_b2b_mw()
493 iowrite64(addr, mmio + xlat_reg); in intel_ntb3_mw_set_trans()
496 iowrite64(0, mmio + xlat_reg); in intel_ntb3_mw_set_trans()
503 iowrite64(limit, mmio + limit_reg); in intel_ntb3_mw_set_trans()
506 iowrite64(base, mmio + limit_reg); in intel_ntb3_mw_set_trans()
507 iowrite64(0, mmio + xlat_reg); in intel_ntb3_mw_set_trans()
524 iowrite64(limit, mmio + limit_reg); in intel_ntb3_mw_set_trans()
[all …]
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| H A D | ntb_hw_gen4.c | 119 iowrite64(bar_addr, mmio + GEN4_IM23XLMT_OFFSET); in gen4_setup_b2b_mw()
124 iowrite64(bar_addr, mmio + GEN4_IM45XLMT_OFFSET); in gen4_setup_b2b_mw()
129 iowrite64(0, mmio + GEN4_IM23XBASE_OFFSET); in gen4_setup_b2b_mw()
130 iowrite64(0, mmio + GEN4_IM45XBASE_OFFSET); in gen4_setup_b2b_mw()
404 iowrite64(addr, mmio + xlat_reg); in intel_ntb4_mw_set_trans()
407 iowrite64(0, mmio + xlat_reg); in intel_ntb4_mw_set_trans()
414 iowrite64(limit, mmio + limit_reg); in intel_ntb4_mw_set_trans()
417 iowrite64(base, mmio + limit_reg); in intel_ntb4_mw_set_trans()
418 iowrite64(0, mmio + xlat_reg); in intel_ntb4_mw_set_trans()
429 iowrite64(base, mmio + limit_reg); in intel_ntb4_mw_set_trans()
[all …]
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| H A D | ntb_hw_gen1.c | 893 iowrite64(addr, mmio + xlat_reg); in intel_ntb_mw_set_trans()
896 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
901 iowrite64(limit, mmio + limit_reg); in intel_ntb_mw_set_trans()
904 iowrite64(base, mmio + limit_reg); in intel_ntb_mw_set_trans()
905 iowrite64(0, mmio + xlat_reg); in intel_ntb_mw_set_trans()
1405 iowrite64(bar_addr, mmio + XEON_SBAR0BASE_OFFSET); in xeon_setup_b2b_mw()
1413 iowrite64(bar_addr, mmio + XEON_SBAR23BASE_OFFSET); in xeon_setup_b2b_mw()
1420 iowrite64(bar_addr, mmio + XEON_SBAR45BASE_OFFSET); in xeon_setup_b2b_mw()
1440 iowrite64(bar_addr, mmio + XEON_SBAR23LMT_OFFSET); in xeon_setup_b2b_mw()
1447 iowrite64(bar_addr, mmio + XEON_SBAR45LMT_OFFSET); in xeon_setup_b2b_mw()
[all …]
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| H A D | ntb_hw_gen3.h | 101 iowrite64(bits, mmio); in gen3_db_iowrite()
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_mmio.c | 193 iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base); in ipc_mmio_config()
194 iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end); in ipc_mmio_config()
196 iowrite64(ipc_mmio->context_info_addr, in ipc_mmio_config()
206 iowrite64(addr, ipc_mmio->base + ipc_mmio->offset.psi_address); in ipc_mmio_set_psi_addr_and_size()
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| /linux/arch/alpha/include/asm/ |
| H A D | io.h | 158 REMAP2(u64, iowrite64, /**/) in REMAP1()
283 extern void iowrite64(u64, void __iomem *);
415 extern inline void iowrite64(u64 b, void __iomem *addr) in iowrite64() function
418 IO_CONCAT(__IO_PREFIX, iowrite64)(b, addr); in iowrite64()
435 #define iowrite64 iowrite64 macro
546 #define iowrite64be(v,p) iowrite64(swab64(v), (p))
640 #define iowrite64 iowrite64 macro
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| H A D | io_trivial.h | 54 IO_CONCAT(__IO_PREFIX,iowrite64)(u64 b, void __iomem *a) in IO_CONCAT() argument
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| /linux/include/linux/ |
| H A D | io-64-nonatomic-lo-hi.h | 111 #ifndef iowrite64
114 #define iowrite64 __iowrite64_lo_hi macro
116 #define iowrite64 iowrite64_lo_hi macro
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| H A D | io-64-nonatomic-hi-lo.h | 111 #ifndef iowrite64
114 #define iowrite64 __iowrite64_hi_lo macro
116 #define iowrite64 iowrite64_hi_lo macro
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| H A D | vfio_pci_core.h | 212 #ifdef iowrite64
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| /linux/drivers/ntb/hw/mscc/ |
| H A D | ntb_hw_switchtec.c | 232 iowrite64(sndev->self_partition, &ctl->bar_entry[bar].xlate_addr); in switchtec_ntb_mw_clr_direct()
239 iowrite64(0, &ctl->lut_entry[peer_lut_index(sndev, idx)]); in switchtec_ntb_mw_clr_lut()
257 iowrite64(sndev->self_partition | addr, in switchtec_ntb_mw_set_direct()
266 iowrite64((NTB_CTRL_LUT_EN | (sndev->self_partition << 1) | addr), in switchtec_ntb_mw_set_lut()
477 iowrite64(sndev->db_valid_mask << sndev->db_peer_shift, in crosslink_init_dbmsgs()
639 iowrite64(db_bits << sndev->db_shift, &sndev->mmio_self_dbmsg->idb); in switchtec_ntb_db_clear()
655 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); in switchtec_ntb_db_set_mask()
673 iowrite64(~sndev->db_mask, &sndev->mmio_self_dbmsg->idb_mask); in switchtec_ntb_db_clear_mask()
718 iowrite64(db_bits << sndev->db_peer_shift, in switchtec_ntb_peer_db_set()
931 iowrite64((NTB_CTRL_LUT_EN | (partition << 1) | addr), in config_rsvd_lut_win()
[all …]
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| /linux/drivers/gpu/drm/tilcdc/ |
| H A D | tilcdc_regs.h | 125 #if defined(iowrite64) && !defined(iowrite64_is_nonatomic) in tilcdc_write64()
126 iowrite64(data, addr); in tilcdc_write64()
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| /linux/arch/alpha/kernel/ |
| H A D | io.c | 71 void iowrite64(u64 b, void __iomem *addr) in iowrite64() function
74 IO_CONCAT(__IO_PREFIX,iowrite64)(b, addr); in iowrite64()
84 EXPORT_SYMBOL(iowrite64);
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| /linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | 705 #if defined(CONFIG_64BIT) && defined(iowrite64)
718 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
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| /linux/arch/parisc/lib/ |
| H A D | iomap.c | 409 void iowrite64(u64 datum, void __iomem *addr) in iowrite64() function
541 EXPORT_SYMBOL(iowrite64);
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| /linux/drivers/dma/idxd/ |
| H A D | perfmon.c | 338 iowrite64(cntr_cfg, CNTRCFG_REG(idxd, cntr)); in perfmon_pmu_event_start()
363 iowrite64(cntr_cfg, CNTRCFG_REG(idxd, cntr)); in perfmon_pmu_event_stop()
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| H A D | irq.c | 462 iowrite64(idxd->sw_err.bits[0] & IDXD_SWERR_ACK, in idxd_misc_thread()
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| /linux/drivers/dma/ |
| H A D | fsldma.h | 244 #define fsl_iowrite64(v, p) iowrite64(v, p)
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| /linux/drivers/vfio/pci/ |
| H A D | vfio_pci_rdwr.c | 25 #define vfio_iowrite64 iowrite64
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| /linux/drivers/crypto/caam/ |
| H A D | regs.h | 149 iowrite64(data, reg); in wr_reg64()
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| /linux/drivers/dma/dw-axi-dmac/ |
| H A D | dw-axi-dmac-platform.c | 68 iowrite64(val, chip->regs + reg); in axi_dma_iowrite64()
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