1dc0514f5SM Chetan Kumar // SPDX-License-Identifier: GPL-2.0-only
2dc0514f5SM Chetan Kumar /*
3dc0514f5SM Chetan Kumar * Copyright (C) 2020-21 Intel Corporation.
4dc0514f5SM Chetan Kumar */
5dc0514f5SM Chetan Kumar
6dc0514f5SM Chetan Kumar #include <linux/delay.h>
7dc0514f5SM Chetan Kumar #include <linux/device.h>
8dc0514f5SM Chetan Kumar #include <linux/io.h>
9dc0514f5SM Chetan Kumar #include <linux/io-64-nonatomic-lo-hi.h>
10dc0514f5SM Chetan Kumar #include <linux/slab.h>
11dc0514f5SM Chetan Kumar
12dc0514f5SM Chetan Kumar #include "iosm_ipc_mmio.h"
13*1f52d7b6SM Chetan Kumar #include "iosm_ipc_mux.h"
14dc0514f5SM Chetan Kumar
15dc0514f5SM Chetan Kumar /* Definition of MMIO offsets
16dc0514f5SM Chetan Kumar * note that MMIO_CI offsets are relative to end of chip info structure
17dc0514f5SM Chetan Kumar */
18dc0514f5SM Chetan Kumar
19dc0514f5SM Chetan Kumar /* MMIO chip info size in bytes */
20dc0514f5SM Chetan Kumar #define MMIO_CHIP_INFO_SIZE 60
21dc0514f5SM Chetan Kumar
22dc0514f5SM Chetan Kumar /* CP execution stage */
23dc0514f5SM Chetan Kumar #define MMIO_OFFSET_EXECUTION_STAGE 0x00
24dc0514f5SM Chetan Kumar
25dc0514f5SM Chetan Kumar /* Boot ROM Chip Info struct */
26dc0514f5SM Chetan Kumar #define MMIO_OFFSET_CHIP_INFO 0x04
27dc0514f5SM Chetan Kumar
28dc0514f5SM Chetan Kumar #define MMIO_OFFSET_ROM_EXIT_CODE 0x40
29dc0514f5SM Chetan Kumar
30dc0514f5SM Chetan Kumar #define MMIO_OFFSET_PSI_ADDRESS 0x54
31dc0514f5SM Chetan Kumar
32dc0514f5SM Chetan Kumar #define MMIO_OFFSET_PSI_SIZE 0x5C
33dc0514f5SM Chetan Kumar
34dc0514f5SM Chetan Kumar #define MMIO_OFFSET_IPC_STATUS 0x60
35dc0514f5SM Chetan Kumar
36dc0514f5SM Chetan Kumar #define MMIO_OFFSET_CONTEXT_INFO 0x64
37dc0514f5SM Chetan Kumar
38dc0514f5SM Chetan Kumar #define MMIO_OFFSET_BASE_ADDR 0x6C
39dc0514f5SM Chetan Kumar
40dc0514f5SM Chetan Kumar #define MMIO_OFFSET_END_ADDR 0x74
41dc0514f5SM Chetan Kumar
42dc0514f5SM Chetan Kumar #define MMIO_OFFSET_CP_VERSION 0xF0
43dc0514f5SM Chetan Kumar
44dc0514f5SM Chetan Kumar #define MMIO_OFFSET_CP_CAPABILITIES 0xF4
45dc0514f5SM Chetan Kumar
46dc0514f5SM Chetan Kumar /* Timeout in 50 msec to wait for the modem boot code to write a valid
47dc0514f5SM Chetan Kumar * execution stage into mmio area
48dc0514f5SM Chetan Kumar */
49dc0514f5SM Chetan Kumar #define IPC_MMIO_EXEC_STAGE_TIMEOUT 50
50dc0514f5SM Chetan Kumar
51dc0514f5SM Chetan Kumar /* check if exec stage has one of the valid values */
ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage)52dc0514f5SM Chetan Kumar static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage)
53dc0514f5SM Chetan Kumar {
54dc0514f5SM Chetan Kumar switch (stage) {
55dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_BOOT:
56dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_PSI:
57dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_EBL:
58dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_RUN:
59dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_CRASH:
60dc0514f5SM Chetan Kumar case IPC_MEM_EXEC_STAGE_CD_READY:
61dc0514f5SM Chetan Kumar return true;
62dc0514f5SM Chetan Kumar default:
63dc0514f5SM Chetan Kumar return false;
64dc0514f5SM Chetan Kumar }
65dc0514f5SM Chetan Kumar }
66dc0514f5SM Chetan Kumar
ipc_mmio_update_cp_capability(struct iosm_mmio * ipc_mmio)67dc0514f5SM Chetan Kumar void ipc_mmio_update_cp_capability(struct iosm_mmio *ipc_mmio)
68dc0514f5SM Chetan Kumar {
69dc0514f5SM Chetan Kumar u32 cp_cap;
70dc0514f5SM Chetan Kumar unsigned int ver;
71dc0514f5SM Chetan Kumar
72dc0514f5SM Chetan Kumar ver = ipc_mmio_get_cp_version(ipc_mmio);
73b539c44dSAndy Shevchenko cp_cap = ioread32(ipc_mmio->base + ipc_mmio->offset.cp_capability);
74dc0514f5SM Chetan Kumar
75*1f52d7b6SM Chetan Kumar ipc_mmio->mux_protocol = ((ver >= IOSM_CP_VERSION) && (cp_cap &
76*1f52d7b6SM Chetan Kumar (UL_AGGR | DL_AGGR))) ? MUX_AGGREGATION
77*1f52d7b6SM Chetan Kumar : MUX_LITE;
78dc0514f5SM Chetan Kumar
79dc0514f5SM Chetan Kumar ipc_mmio->has_ul_flow_credit =
80dc0514f5SM Chetan Kumar (ver >= IOSM_CP_VERSION) && (cp_cap & UL_FLOW_CREDIT);
81dc0514f5SM Chetan Kumar }
82dc0514f5SM Chetan Kumar
ipc_mmio_init(void __iomem * mmio,struct device * dev)83dc0514f5SM Chetan Kumar struct iosm_mmio *ipc_mmio_init(void __iomem *mmio, struct device *dev)
84dc0514f5SM Chetan Kumar {
85dc0514f5SM Chetan Kumar struct iosm_mmio *ipc_mmio = kzalloc(sizeof(*ipc_mmio), GFP_KERNEL);
86dc0514f5SM Chetan Kumar int retries = IPC_MMIO_EXEC_STAGE_TIMEOUT;
87dc0514f5SM Chetan Kumar enum ipc_mem_exec_stage stage;
88dc0514f5SM Chetan Kumar
89dc0514f5SM Chetan Kumar if (!ipc_mmio)
90dc0514f5SM Chetan Kumar return NULL;
91dc0514f5SM Chetan Kumar
92dc0514f5SM Chetan Kumar ipc_mmio->dev = dev;
93dc0514f5SM Chetan Kumar
94dc0514f5SM Chetan Kumar ipc_mmio->base = mmio;
95dc0514f5SM Chetan Kumar
96dc0514f5SM Chetan Kumar ipc_mmio->offset.exec_stage = MMIO_OFFSET_EXECUTION_STAGE;
97dc0514f5SM Chetan Kumar
98dc0514f5SM Chetan Kumar /* Check for a valid execution stage to make sure that the boot code
99dc0514f5SM Chetan Kumar * has correctly initialized the MMIO area.
100dc0514f5SM Chetan Kumar */
101dc0514f5SM Chetan Kumar do {
102dc0514f5SM Chetan Kumar stage = ipc_mmio_get_exec_stage(ipc_mmio);
103dc0514f5SM Chetan Kumar if (ipc_mmio_is_valid_exec_stage(stage))
104dc0514f5SM Chetan Kumar break;
105dc0514f5SM Chetan Kumar
106dc0514f5SM Chetan Kumar msleep(20);
107dc0514f5SM Chetan Kumar } while (retries-- > 0);
108dc0514f5SM Chetan Kumar
109dc0514f5SM Chetan Kumar if (!retries) {
110dc0514f5SM Chetan Kumar dev_err(ipc_mmio->dev, "invalid exec stage %X", stage);
111dc0514f5SM Chetan Kumar goto init_fail;
112dc0514f5SM Chetan Kumar }
113dc0514f5SM Chetan Kumar
114dc0514f5SM Chetan Kumar ipc_mmio->offset.chip_info = MMIO_OFFSET_CHIP_INFO;
115dc0514f5SM Chetan Kumar
116dc0514f5SM Chetan Kumar /* read chip info size and version from chip info structure */
117dc0514f5SM Chetan Kumar ipc_mmio->chip_info_version =
118dc0514f5SM Chetan Kumar ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info);
119dc0514f5SM Chetan Kumar
120dc0514f5SM Chetan Kumar /* Increment of 2 is needed as the size value in the chip info
121dc0514f5SM Chetan Kumar * excludes the version and size field, which are always present
122dc0514f5SM Chetan Kumar */
123dc0514f5SM Chetan Kumar ipc_mmio->chip_info_size =
124dc0514f5SM Chetan Kumar ioread8(ipc_mmio->base + ipc_mmio->offset.chip_info + 1) + 2;
125dc0514f5SM Chetan Kumar
126dc0514f5SM Chetan Kumar if (ipc_mmio->chip_info_size != MMIO_CHIP_INFO_SIZE) {
127dc0514f5SM Chetan Kumar dev_err(ipc_mmio->dev, "Unexpected Chip Info");
128dc0514f5SM Chetan Kumar goto init_fail;
129dc0514f5SM Chetan Kumar }
130dc0514f5SM Chetan Kumar
131dc0514f5SM Chetan Kumar ipc_mmio->offset.rom_exit_code = MMIO_OFFSET_ROM_EXIT_CODE;
132dc0514f5SM Chetan Kumar
133dc0514f5SM Chetan Kumar ipc_mmio->offset.psi_address = MMIO_OFFSET_PSI_ADDRESS;
134dc0514f5SM Chetan Kumar ipc_mmio->offset.psi_size = MMIO_OFFSET_PSI_SIZE;
135dc0514f5SM Chetan Kumar ipc_mmio->offset.ipc_status = MMIO_OFFSET_IPC_STATUS;
136dc0514f5SM Chetan Kumar ipc_mmio->offset.context_info = MMIO_OFFSET_CONTEXT_INFO;
137dc0514f5SM Chetan Kumar ipc_mmio->offset.ap_win_base = MMIO_OFFSET_BASE_ADDR;
138dc0514f5SM Chetan Kumar ipc_mmio->offset.ap_win_end = MMIO_OFFSET_END_ADDR;
139dc0514f5SM Chetan Kumar
140dc0514f5SM Chetan Kumar ipc_mmio->offset.cp_version = MMIO_OFFSET_CP_VERSION;
141dc0514f5SM Chetan Kumar ipc_mmio->offset.cp_capability = MMIO_OFFSET_CP_CAPABILITIES;
142dc0514f5SM Chetan Kumar
143dc0514f5SM Chetan Kumar return ipc_mmio;
144dc0514f5SM Chetan Kumar
145dc0514f5SM Chetan Kumar init_fail:
146dc0514f5SM Chetan Kumar kfree(ipc_mmio);
147dc0514f5SM Chetan Kumar return NULL;
148dc0514f5SM Chetan Kumar }
149dc0514f5SM Chetan Kumar
ipc_mmio_get_exec_stage(struct iosm_mmio * ipc_mmio)150dc0514f5SM Chetan Kumar enum ipc_mem_exec_stage ipc_mmio_get_exec_stage(struct iosm_mmio *ipc_mmio)
151dc0514f5SM Chetan Kumar {
152dc0514f5SM Chetan Kumar if (!ipc_mmio)
153dc0514f5SM Chetan Kumar return IPC_MEM_EXEC_STAGE_INVALID;
154dc0514f5SM Chetan Kumar
155b539c44dSAndy Shevchenko return (enum ipc_mem_exec_stage)ioread32(ipc_mmio->base +
156dc0514f5SM Chetan Kumar ipc_mmio->offset.exec_stage);
157dc0514f5SM Chetan Kumar }
158dc0514f5SM Chetan Kumar
ipc_mmio_copy_chip_info(struct iosm_mmio * ipc_mmio,void * dest,size_t size)159dc0514f5SM Chetan Kumar void ipc_mmio_copy_chip_info(struct iosm_mmio *ipc_mmio, void *dest,
160dc0514f5SM Chetan Kumar size_t size)
161dc0514f5SM Chetan Kumar {
162dc0514f5SM Chetan Kumar if (ipc_mmio && dest)
163dc0514f5SM Chetan Kumar memcpy_fromio(dest, ipc_mmio->base + ipc_mmio->offset.chip_info,
164dc0514f5SM Chetan Kumar size);
165dc0514f5SM Chetan Kumar }
166dc0514f5SM Chetan Kumar
ipc_mmio_get_ipc_state(struct iosm_mmio * ipc_mmio)167dc0514f5SM Chetan Kumar enum ipc_mem_device_ipc_state ipc_mmio_get_ipc_state(struct iosm_mmio *ipc_mmio)
168dc0514f5SM Chetan Kumar {
169dc0514f5SM Chetan Kumar if (!ipc_mmio)
170dc0514f5SM Chetan Kumar return IPC_MEM_DEVICE_IPC_INVALID;
171dc0514f5SM Chetan Kumar
172b539c44dSAndy Shevchenko return (enum ipc_mem_device_ipc_state)ioread32(ipc_mmio->base +
173b539c44dSAndy Shevchenko ipc_mmio->offset.ipc_status);
174dc0514f5SM Chetan Kumar }
175dc0514f5SM Chetan Kumar
ipc_mmio_get_rom_exit_code(struct iosm_mmio * ipc_mmio)176dc0514f5SM Chetan Kumar enum rom_exit_code ipc_mmio_get_rom_exit_code(struct iosm_mmio *ipc_mmio)
177dc0514f5SM Chetan Kumar {
178dc0514f5SM Chetan Kumar if (!ipc_mmio)
179dc0514f5SM Chetan Kumar return IMEM_ROM_EXIT_FAIL;
180dc0514f5SM Chetan Kumar
181b539c44dSAndy Shevchenko return (enum rom_exit_code)ioread32(ipc_mmio->base +
182dc0514f5SM Chetan Kumar ipc_mmio->offset.rom_exit_code);
183dc0514f5SM Chetan Kumar }
184dc0514f5SM Chetan Kumar
ipc_mmio_config(struct iosm_mmio * ipc_mmio)185dc0514f5SM Chetan Kumar void ipc_mmio_config(struct iosm_mmio *ipc_mmio)
186dc0514f5SM Chetan Kumar {
187dc0514f5SM Chetan Kumar if (!ipc_mmio)
188dc0514f5SM Chetan Kumar return;
189dc0514f5SM Chetan Kumar
190dc0514f5SM Chetan Kumar /* AP memory window (full window is open and active so that modem checks
191dc0514f5SM Chetan Kumar * each AP address) 0 means don't check on modem side.
192dc0514f5SM Chetan Kumar */
1931d99411fSAndy Shevchenko iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_base);
1941d99411fSAndy Shevchenko iowrite64(0, ipc_mmio->base + ipc_mmio->offset.ap_win_end);
195dc0514f5SM Chetan Kumar
1961d99411fSAndy Shevchenko iowrite64(ipc_mmio->context_info_addr,
197dc0514f5SM Chetan Kumar ipc_mmio->base + ipc_mmio->offset.context_info);
198dc0514f5SM Chetan Kumar }
199dc0514f5SM Chetan Kumar
ipc_mmio_set_psi_addr_and_size(struct iosm_mmio * ipc_mmio,dma_addr_t addr,u32 size)200dc0514f5SM Chetan Kumar void ipc_mmio_set_psi_addr_and_size(struct iosm_mmio *ipc_mmio, dma_addr_t addr,
201dc0514f5SM Chetan Kumar u32 size)
202dc0514f5SM Chetan Kumar {
203dc0514f5SM Chetan Kumar if (!ipc_mmio)
204dc0514f5SM Chetan Kumar return;
205dc0514f5SM Chetan Kumar
2061d99411fSAndy Shevchenko iowrite64(addr, ipc_mmio->base + ipc_mmio->offset.psi_address);
207b539c44dSAndy Shevchenko iowrite32(size, ipc_mmio->base + ipc_mmio->offset.psi_size);
208dc0514f5SM Chetan Kumar }
209dc0514f5SM Chetan Kumar
ipc_mmio_set_contex_info_addr(struct iosm_mmio * ipc_mmio,phys_addr_t addr)210dc0514f5SM Chetan Kumar void ipc_mmio_set_contex_info_addr(struct iosm_mmio *ipc_mmio, phys_addr_t addr)
211dc0514f5SM Chetan Kumar {
212dc0514f5SM Chetan Kumar if (!ipc_mmio)
213dc0514f5SM Chetan Kumar return;
214dc0514f5SM Chetan Kumar
215dc0514f5SM Chetan Kumar /* store context_info address. This will be stored in the mmio area
216dc0514f5SM Chetan Kumar * during IPC_MEM_DEVICE_IPC_INIT state via ipc_mmio_config()
217dc0514f5SM Chetan Kumar */
218dc0514f5SM Chetan Kumar ipc_mmio->context_info_addr = addr;
219dc0514f5SM Chetan Kumar }
220dc0514f5SM Chetan Kumar
ipc_mmio_get_cp_version(struct iosm_mmio * ipc_mmio)221dc0514f5SM Chetan Kumar int ipc_mmio_get_cp_version(struct iosm_mmio *ipc_mmio)
222dc0514f5SM Chetan Kumar {
223b539c44dSAndy Shevchenko if (ipc_mmio)
224b539c44dSAndy Shevchenko return ioread32(ipc_mmio->base + ipc_mmio->offset.cp_version);
225b539c44dSAndy Shevchenko
226b539c44dSAndy Shevchenko return -EFAULT;
227dc0514f5SM Chetan Kumar }
228