1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */
3
4 #ifndef _IONIC_IF_H_
5 #define _IONIC_IF_H_
6
7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
8 #define IONIC_DEV_INFO_VERSION 1
9 #define IONIC_IFNAMSIZ 16
10
11 /*
12 * enum ionic_cmd_opcode - Device commands
13 */
14 enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17 /* Device commands */
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24 /* Port commands */
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31 /* LIF commands */
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37 IONIC_CMD_LIF_SETPHC = 25,
38
39 IONIC_CMD_RX_MODE_SET = 30,
40 IONIC_CMD_RX_FILTER_ADD = 31,
41 IONIC_CMD_RX_FILTER_DEL = 32,
42
43 /* Queue commands */
44 IONIC_CMD_Q_IDENTIFY = 39,
45 IONIC_CMD_Q_INIT = 40,
46 IONIC_CMD_Q_CONTROL = 41,
47
48 /* RDMA commands */
49 IONIC_CMD_RDMA_RESET_LIF = 50,
50 IONIC_CMD_RDMA_CREATE_EQ = 51,
51 IONIC_CMD_RDMA_CREATE_CQ = 52,
52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
53
54 /* SR/IOV commands */
55 IONIC_CMD_VF_GETATTR = 60,
56 IONIC_CMD_VF_SETATTR = 61,
57 IONIC_CMD_VF_CTRL = 62,
58
59 /* CMB command */
60 IONIC_CMD_DISCOVER_CMB = 80,
61
62 /* QoS commands */
63 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
64 IONIC_CMD_QOS_CLASS_INIT = 241,
65 IONIC_CMD_QOS_CLASS_RESET = 242,
66 IONIC_CMD_QOS_CLASS_UPDATE = 243,
67 IONIC_CMD_QOS_CLEAR_STATS = 244,
68 IONIC_CMD_QOS_RESET = 245,
69
70 /* Firmware commands */
71 IONIC_CMD_FW_DOWNLOAD = 252,
72 IONIC_CMD_FW_CONTROL = 253,
73 IONIC_CMD_FW_DOWNLOAD_V1 = 254,
74 IONIC_CMD_FW_CONTROL_V1 = 255,
75 };
76
77 /*
78 * enum ionic_status_code - Device command return codes
79 */
80 enum ionic_status_code {
81 IONIC_RC_SUCCESS = 0, /* Success */
82 IONIC_RC_EVERSION = 1, /* Incorrect version for request */
83 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
84 IONIC_RC_EIO = 3, /* I/O error */
85 IONIC_RC_EPERM = 4, /* Permission denied */
86 IONIC_RC_EQID = 5, /* Bad qid */
87 IONIC_RC_EQTYPE = 6, /* Bad qtype */
88 IONIC_RC_ENOENT = 7, /* No such element */
89 IONIC_RC_EINTR = 8, /* operation interrupted */
90 IONIC_RC_EAGAIN = 9, /* Try again */
91 IONIC_RC_ENOMEM = 10, /* Out of memory */
92 IONIC_RC_EFAULT = 11, /* Bad address */
93 IONIC_RC_EBUSY = 12, /* Device or resource busy */
94 IONIC_RC_EEXIST = 13, /* object already exists */
95 IONIC_RC_EINVAL = 14, /* Invalid argument */
96 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
97 IONIC_RC_ERANGE = 16, /* Parameter out of range */
98 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
99 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
100 IONIC_RC_ENOSUPP = 19, /* Operation not supported */
101 IONIC_RC_ERROR = 29, /* Generic error */
102 IONIC_RC_ERDMA = 30, /* Generic RDMA error */
103 IONIC_RC_EVFID = 31, /* VF ID does not exist */
104 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */
105 };
106
107 enum ionic_notifyq_opcode {
108 IONIC_EVENT_LINK_CHANGE = 1,
109 IONIC_EVENT_RESET = 2,
110 IONIC_EVENT_HEARTBEAT = 3,
111 IONIC_EVENT_LOG = 4,
112 IONIC_EVENT_XCVR = 5,
113 };
114
115 /**
116 * struct ionic_admin_cmd - General admin command format
117 * @opcode: Opcode for the command
118 * @rsvd: reserved byte(s)
119 * @lif_index: LIF index
120 * @cmd_data: Opcode-specific command bytes
121 */
122 struct ionic_admin_cmd {
123 u8 opcode;
124 u8 rsvd;
125 __le16 lif_index;
126 u8 cmd_data[60];
127 };
128
129 /**
130 * struct ionic_admin_comp - General admin command completion format
131 * @status: Status of the command (enum ionic_status_code)
132 * @rsvd: reserved byte(s)
133 * @comp_index: Index in the descriptor ring for which this is the completion
134 * @cmd_data: Command-specific bytes
135 * @color: Color bit (Always 0 for commands issued to the
136 * Device Cmd Registers)
137 */
138 struct ionic_admin_comp {
139 u8 status;
140 u8 rsvd;
141 __le16 comp_index;
142 u8 cmd_data[11];
143 u8 color;
144 #define IONIC_COMP_COLOR_MASK 0x80
145 };
146
color_match(u8 color,u8 done_color)147 static inline u8 color_match(u8 color, u8 done_color)
148 {
149 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
150 }
151
152 /**
153 * struct ionic_nop_cmd - NOP command
154 * @opcode: opcode
155 * @rsvd: reserved byte(s)
156 */
157 struct ionic_nop_cmd {
158 u8 opcode;
159 u8 rsvd[63];
160 };
161
162 /**
163 * struct ionic_nop_comp - NOP command completion
164 * @status: Status of the command (enum ionic_status_code)
165 * @rsvd: reserved byte(s)
166 */
167 struct ionic_nop_comp {
168 u8 status;
169 u8 rsvd[15];
170 };
171
172 /**
173 * struct ionic_dev_init_cmd - Device init command
174 * @opcode: opcode
175 * @type: Device type
176 * @rsvd: reserved byte(s)
177 */
178 struct ionic_dev_init_cmd {
179 u8 opcode;
180 u8 type;
181 u8 rsvd[62];
182 };
183
184 /**
185 * struct ionic_dev_init_comp - Device init command completion
186 * @status: Status of the command (enum ionic_status_code)
187 * @rsvd: reserved byte(s)
188 */
189 struct ionic_dev_init_comp {
190 u8 status;
191 u8 rsvd[15];
192 };
193
194 /**
195 * struct ionic_dev_reset_cmd - Device reset command
196 * @opcode: opcode
197 * @rsvd: reserved byte(s)
198 */
199 struct ionic_dev_reset_cmd {
200 u8 opcode;
201 u8 rsvd[63];
202 };
203
204 /**
205 * struct ionic_dev_reset_comp - Reset command completion
206 * @status: Status of the command (enum ionic_status_code)
207 * @rsvd: reserved byte(s)
208 */
209 struct ionic_dev_reset_comp {
210 u8 status;
211 u8 rsvd[15];
212 };
213
214 #define IONIC_IDENTITY_VERSION_1 1
215 #define IONIC_DEV_IDENTITY_VERSION_2 2
216
217 /**
218 * struct ionic_dev_identify_cmd - Driver/device identify command
219 * @opcode: opcode
220 * @ver: Highest version of identify supported by driver
221 * @rsvd: reserved byte(s)
222 */
223 struct ionic_dev_identify_cmd {
224 u8 opcode;
225 u8 ver;
226 u8 rsvd[62];
227 };
228
229 /**
230 * struct ionic_dev_identify_comp - Driver/device identify command completion
231 * @status: Status of the command (enum ionic_status_code)
232 * @ver: Version of identify returned by device
233 * @rsvd: reserved byte(s)
234 */
235 struct ionic_dev_identify_comp {
236 u8 status;
237 u8 ver;
238 u8 rsvd[14];
239 };
240
241 enum ionic_os_type {
242 IONIC_OS_TYPE_LINUX = 1,
243 IONIC_OS_TYPE_WIN = 2,
244 IONIC_OS_TYPE_DPDK = 3,
245 IONIC_OS_TYPE_FREEBSD = 4,
246 IONIC_OS_TYPE_IPXE = 5,
247 IONIC_OS_TYPE_ESXI = 6,
248 };
249
250 /**
251 * union ionic_drv_identity - driver identity information
252 * @os_type: OS type (see enum ionic_os_type)
253 * @os_dist: OS distribution, numeric format
254 * @os_dist_str: OS distribution, string format
255 * @kernel_ver: Kernel version, numeric format
256 * @kernel_ver_str: Kernel version, string format
257 * @driver_ver_str: Driver version, string format
258 * @words: word access to struct contents
259 */
260 union ionic_drv_identity {
261 struct {
262 __le32 os_type;
263 __le32 os_dist;
264 char os_dist_str[128];
265 __le32 kernel_ver;
266 char kernel_ver_str[32];
267 char driver_ver_str[32];
268 };
269 __le32 words[478];
270 };
271
272 /**
273 * enum ionic_dev_capability - Device capabilities
274 * @IONIC_DEV_CAP_VF_CTRL: Device supports VF ctrl operations
275 * @IONIC_DEV_CAP_DISC_CMB: Device supports CMB discovery operations
276 * @IONIC_DEV_CAP_EXTRA_STATS: Device supports extra stats schema
277 */
278 enum ionic_dev_capability {
279 IONIC_DEV_CAP_VF_CTRL = BIT(0),
280 IONIC_DEV_CAP_DISC_CMB = BIT(1),
281 IONIC_DEV_CAP_EXTRA_STATS = BIT(4),
282 };
283
284 /**
285 * union ionic_dev_identity - device identity information
286 * @version: Version of device identify
287 * @type: Identify type (0 for now)
288 * @rsvd: reserved byte(s)
289 * @nports: Number of ports provisioned
290 * @rsvd2: reserved byte(s)
291 * @nlifs: Number of LIFs provisioned
292 * @nintrs: Number of interrupts provisioned
293 * @ndbpgs_per_lif: Number of doorbell pages per LIF
294 * @intr_coal_mult: Interrupt coalescing multiplication factor
295 * Scale user-supplied interrupt coalescing
296 * value in usecs to device units using:
297 * device units = usecs * mult / div
298 * @intr_coal_div: Interrupt coalescing division factor
299 * Scale user-supplied interrupt coalescing
300 * value in usecs to device units using:
301 * device units = usecs * mult / div
302 * @eq_count: Number of shared event queues
303 * @hwstamp_mask: Bitmask for subtraction of hardware tick values.
304 * @hwstamp_mult: Hardware tick to nanosecond multiplier.
305 * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two).
306 * @capabilities: Device capabilities
307 * @words: word access to struct contents
308 */
309 union ionic_dev_identity {
310 struct {
311 u8 version;
312 u8 type;
313 u8 rsvd[2];
314 u8 nports;
315 u8 rsvd2[3];
316 __le32 nlifs;
317 __le32 nintrs;
318 __le32 ndbpgs_per_lif;
319 __le32 intr_coal_mult;
320 __le32 intr_coal_div;
321 __le32 eq_count;
322 __le64 hwstamp_mask;
323 __le32 hwstamp_mult;
324 __le32 hwstamp_shift;
325 __le64 capabilities;
326 };
327 __le32 words[478];
328 };
329
330 enum ionic_lif_type {
331 IONIC_LIF_TYPE_CLASSIC = 0,
332 IONIC_LIF_TYPE_MACVLAN = 1,
333 IONIC_LIF_TYPE_NETQUEUE = 2,
334 };
335
336 /**
337 * struct ionic_lif_identify_cmd - LIF identify command
338 * @opcode: opcode
339 * @type: LIF type (enum ionic_lif_type)
340 * @ver: Version of identify returned by device
341 * @rsvd: reserved byte(s)
342 */
343 struct ionic_lif_identify_cmd {
344 u8 opcode;
345 u8 type;
346 u8 ver;
347 u8 rsvd[61];
348 };
349
350 /**
351 * struct ionic_lif_identify_comp - LIF identify command completion
352 * @status: Status of the command (enum ionic_status_code)
353 * @ver: Version of identify returned by device
354 * @rsvd2: reserved byte(s)
355 */
356 struct ionic_lif_identify_comp {
357 u8 status;
358 u8 ver;
359 u8 rsvd2[14];
360 };
361
362 /**
363 * enum ionic_lif_capability - LIF capabilities
364 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet
365 * @IONIC_LIF_CAP_RDMA: LIF supports RDMA
366 */
367 enum ionic_lif_capability {
368 IONIC_LIF_CAP_ETH = BIT(0),
369 IONIC_LIF_CAP_RDMA = BIT(1),
370 };
371
372 /**
373 * enum ionic_logical_qtype - Logical Queue Types
374 * @IONIC_QTYPE_ADMINQ: Administrative Queue
375 * @IONIC_QTYPE_NOTIFYQ: Notify Queue
376 * @IONIC_QTYPE_RXQ: Receive Queue
377 * @IONIC_QTYPE_TXQ: Transmit Queue
378 * @IONIC_QTYPE_EQ: Event Queue
379 * @IONIC_QTYPE_MAX: Max queue type supported
380 */
381 enum ionic_logical_qtype {
382 IONIC_QTYPE_ADMINQ = 0,
383 IONIC_QTYPE_NOTIFYQ = 1,
384 IONIC_QTYPE_RXQ = 2,
385 IONIC_QTYPE_TXQ = 3,
386 IONIC_QTYPE_EQ = 4,
387 IONIC_QTYPE_MAX = 16,
388 };
389
390 /**
391 * enum ionic_q_feature - Common Features for most queue types
392 *
393 * Common features use bits 0-15. Per-queue-type features use higher bits.
394 *
395 * @IONIC_QIDENT_F_CQ: Queue has completion ring
396 * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring
397 * @IONIC_QIDENT_F_EQ: Queue can use event queue
398 * @IONIC_QIDENT_F_CMB: Queue is in cmb bar
399 * @IONIC_Q_F_2X_DESC: Double main descriptor size
400 * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size
401 * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size
402 * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size
403 * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size
404 * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size
405 * @IONIC_QIDENT_F_EXPDB: Queue supports express doorbell
406 */
407 enum ionic_q_feature {
408 IONIC_QIDENT_F_CQ = BIT_ULL(0),
409 IONIC_QIDENT_F_SG = BIT_ULL(1),
410 IONIC_QIDENT_F_EQ = BIT_ULL(2),
411 IONIC_QIDENT_F_CMB = BIT_ULL(3),
412 IONIC_Q_F_2X_DESC = BIT_ULL(4),
413 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5),
414 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6),
415 IONIC_Q_F_4X_DESC = BIT_ULL(7),
416 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8),
417 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9),
418 IONIC_QIDENT_F_EXPDB = BIT_ULL(10),
419 };
420
421 /**
422 * enum ionic_rxq_feature - RXQ-specific Features
423 *
424 * Per-queue-type features use bits 16 and higher.
425 *
426 * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping
427 */
428 enum ionic_rxq_feature {
429 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16),
430 };
431
432 /**
433 * enum ionic_txq_feature - TXQ-specific Features
434 *
435 * Per-queue-type features use bits 16 and higher.
436 *
437 * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping
438 */
439 enum ionic_txq_feature {
440 IONIC_TXQ_F_HWSTAMP = BIT(16),
441 };
442
443 /**
444 * enum ionic_hwstamp_bits - Hardware timestamp decoding bits
445 * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value
446 * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset
447 * from the base cq descriptor.
448 */
449 enum ionic_hwstamp_bits {
450 IONIC_HWSTAMP_INVALID = ~0ull,
451 IONIC_HWSTAMP_CQ_NEGOFFSET = 8,
452 };
453
454 /**
455 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
456 * @qtype: Hardware Queue Type
457 * @rsvd: reserved byte(s)
458 * @qid_count: Number of Queue IDs of the logical type
459 * @qid_base: Minimum Queue ID of the logical type
460 */
461 struct ionic_lif_logical_qtype {
462 u8 qtype;
463 u8 rsvd[3];
464 __le32 qid_count;
465 __le32 qid_base;
466 };
467
468 /**
469 * enum ionic_lif_state - LIF state
470 * @IONIC_LIF_DISABLE: LIF disabled
471 * @IONIC_LIF_ENABLE: LIF enabled
472 * @IONIC_LIF_QUIESCE: LIF Quiesced
473 */
474 enum ionic_lif_state {
475 IONIC_LIF_QUIESCE = 0,
476 IONIC_LIF_ENABLE = 1,
477 IONIC_LIF_DISABLE = 2,
478 };
479
480 /**
481 * union ionic_lif_config - LIF configuration
482 * @state: LIF state (enum ionic_lif_state)
483 * @rsvd: reserved byte(s)
484 * @name: LIF name
485 * @mtu: MTU
486 * @mac: Station MAC address
487 * @vlan: Default Vlan ID
488 * @features: Features (enum ionic_eth_hw_features)
489 * @queue_count: Queue counts per queue-type
490 * @words: word access to struct contents
491 */
492 union ionic_lif_config {
493 struct {
494 u8 state;
495 u8 rsvd[3];
496 char name[IONIC_IFNAMSIZ];
497 __le32 mtu;
498 u8 mac[6];
499 __le16 vlan;
500 __le64 features;
501 __le32 queue_count[IONIC_QTYPE_MAX];
502 } __packed;
503 __le32 words[64];
504 };
505
506 /**
507 * enum ionic_lif_rdma_cap_stats - LIF stat type
508 * @IONIC_LIF_RDMA_STAT_GLOBAL: Global stats
509 * @IONIC_LIF_RDMA_STAT_QP: Queue pair stats
510 */
511 enum ionic_lif_rdma_cap_stats {
512 IONIC_LIF_RDMA_STAT_GLOBAL = BIT(0),
513 IONIC_LIF_RDMA_STAT_QP = BIT(1),
514 };
515
516 /**
517 * struct ionic_lif_identity - LIF identity information (type-specific)
518 *
519 * @capabilities: LIF capabilities
520 *
521 * @eth: Ethernet identify structure
522 * @eth.version: Ethernet identify structure version
523 * @eth.rsvd: reserved byte(s)
524 * @eth.max_ucast_filters: Number of perfect unicast addresses supported
525 * @eth.max_mcast_filters: Number of perfect multicast addresses supported
526 * @eth.min_frame_size: Minimum size of frames to be sent
527 * @eth.max_frame_size: Maximum size of frames to be sent
528 * @eth.rsvd2: reserved byte(s)
529 * @eth.hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode)
530 * @eth.hwstamp_rx_filters: Bitmask of enum ionic_pkt_class
531 * @eth.rsvd3: reserved byte(s)
532 * @eth.config: LIF config struct with features, mtu, mac, q counts
533 *
534 * @rdma: RDMA identify structure
535 * @rdma.version: RDMA capability version
536 * @rdma.qp_opcodes: Number of RDMA queue pair opcodes supported
537 * @rdma.admin_opcodes: Number of RDMA admin opcodes supported
538 * @rdma.minor_version: RDMA capability minor version
539 * @rdma.npts_per_lif: Page table size per LIF
540 * @rdma.nmrs_per_lif: Number of memory regions per LIF
541 * @rdma.nahs_per_lif: Number of address handles per LIF
542 * @rdma.max_stride: Max work request stride
543 * @rdma.cl_stride: Cache line stride
544 * @rdma.pte_stride: Page table entry stride
545 * @rdma.rrq_stride: Remote RQ work request stride
546 * @rdma.rsq_stride: Remote SQ work request stride
547 * @rdma.dcqcn_profiles: Number of DCQCN profiles
548 * @rdma.udma_shift: Log2 number of queues per queue group
549 * @rdma.rsvd_dimensions: Reserved byte
550 * @rdma.page_size_cap: Supported page sizes
551 * @rdma.aq_qtype: RDMA Admin Qtype
552 * @rdma.sq_qtype: RDMA Send Qtype
553 * @rdma.rq_qtype: RDMA Receive Qtype
554 * @rdma.cq_qtype: RDMA Completion Qtype
555 * @rdma.eq_qtype: RDMA Event Qtype
556 * @rdma.stats_type: Supported statistics type
557 * (enum ionic_lif_rdma_cap_stats)
558 * @rdma.rsvd: Reserved byte
559 * @rdma.rcq_sign_bit: RCQ sign bit
560 * @rdma.rsvd1: Reserved byte(s)
561 * @words: word access to struct contents
562 */
563 union ionic_lif_identity {
564 struct {
565 __le64 capabilities;
566
567 struct {
568 u8 version;
569 u8 rsvd[3];
570 __le32 max_ucast_filters;
571 __le32 max_mcast_filters;
572 __le16 rss_ind_tbl_sz;
573 __le32 min_frame_size;
574 __le32 max_frame_size;
575 u8 rsvd2[2];
576 __le64 hwstamp_tx_modes;
577 __le64 hwstamp_rx_filters;
578 u8 rsvd3[88];
579 union ionic_lif_config config;
580 } __packed eth;
581
582 struct {
583 u8 version;
584 u8 qp_opcodes;
585 u8 admin_opcodes;
586 u8 minor_version;
587 __le32 npts_per_lif;
588 __le32 nmrs_per_lif;
589 __le32 nahs_per_lif;
590 u8 max_stride;
591 u8 cl_stride;
592 u8 pte_stride;
593 u8 rrq_stride;
594 u8 rsq_stride;
595 u8 dcqcn_profiles;
596 u8 udma_shift;
597 u8 rsvd_dimensions;
598 __le64 page_size_cap;
599 struct ionic_lif_logical_qtype aq_qtype;
600 struct ionic_lif_logical_qtype sq_qtype;
601 struct ionic_lif_logical_qtype rq_qtype;
602 struct ionic_lif_logical_qtype cq_qtype;
603 struct ionic_lif_logical_qtype eq_qtype;
604 __le16 stats_type;
605 u8 rsvd;
606 u8 rcq_sign_bit;
607 u8 rsvd1[160];
608 } __packed rdma;
609 } __packed;
610 __le32 words[478];
611 };
612
613 /**
614 * struct ionic_lif_init_cmd - LIF init command
615 * @opcode: Opcode
616 * @type: LIF type (enum ionic_lif_type)
617 * @index: LIF index
618 * @rsvd: reserved byte(s)
619 * @info_pa: Destination address for LIF info (struct ionic_lif_info)
620 * @rsvd2: reserved byte(s)
621 */
622 struct ionic_lif_init_cmd {
623 u8 opcode;
624 u8 type;
625 __le16 index;
626 __le32 rsvd;
627 __le64 info_pa;
628 u8 rsvd2[48];
629 };
630
631 /**
632 * struct ionic_lif_init_comp - LIF init command completion
633 * @status: Status of the command (enum ionic_status_code)
634 * @rsvd: reserved byte(s)
635 * @hw_index: Hardware index of the initialized LIF
636 * @rsvd2: reserved byte(s)
637 */
638 struct ionic_lif_init_comp {
639 u8 status;
640 u8 rsvd;
641 __le16 hw_index;
642 u8 rsvd2[12];
643 };
644
645 /**
646 * struct ionic_q_identify_cmd - queue identify command
647 * @opcode: opcode
648 * @rsvd: reserved byte(s)
649 * @lif_type: LIF type (enum ionic_lif_type)
650 * @type: Logical queue type (enum ionic_logical_qtype)
651 * @ver: Highest queue type version that the driver supports
652 * @rsvd2: reserved byte(s)
653 */
654 struct ionic_q_identify_cmd {
655 u8 opcode;
656 u8 rsvd;
657 __le16 lif_type;
658 u8 type;
659 u8 ver;
660 u8 rsvd2[58];
661 };
662
663 /**
664 * struct ionic_q_identify_comp - queue identify command completion
665 * @status: Status of the command (enum ionic_status_code)
666 * @rsvd: reserved byte(s)
667 * @comp_index: Index in the descriptor ring for which this is the completion
668 * @ver: Queue type version that can be used with FW
669 * @rsvd2: reserved byte(s)
670 */
671 struct ionic_q_identify_comp {
672 u8 status;
673 u8 rsvd;
674 __le16 comp_index;
675 u8 ver;
676 u8 rsvd2[11];
677 };
678
679 /**
680 * union ionic_q_identity - queue identity information
681 * @version: Queue type version that can be used with FW
682 * @supported: Bitfield of queue versions, first bit = ver 0
683 * @rsvd: reserved byte(s)
684 * @features: Queue features (enum ionic_q_feature, etc)
685 * @desc_sz: Descriptor size
686 * @comp_sz: Completion descriptor size
687 * @sg_desc_sz: Scatter/Gather descriptor size
688 * @max_sg_elems: Maximum number of Scatter/Gather elements
689 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor
690 * @words: word access to struct contents
691 */
692 union ionic_q_identity {
693 struct {
694 u8 version;
695 u8 supported;
696 u8 rsvd[6];
697 __le64 features;
698 __le16 desc_sz;
699 __le16 comp_sz;
700 __le16 sg_desc_sz;
701 __le16 max_sg_elems;
702 __le16 sg_desc_stride;
703 };
704 __le32 words[478];
705 };
706
707 /**
708 * struct ionic_q_init_cmd - Queue init command
709 * @opcode: opcode
710 * @rsvd: reserved byte(s)
711 * @type: Logical queue type
712 * @ver: Queue type version
713 * @rsvd1: reserved byte(s)
714 * @lif_index: LIF index
715 * @index: (LIF, qtype) relative admin queue index
716 * @intr_index: Interrupt control register index, or Event queue index
717 * @pid: Process ID
718 * @flags:
719 * IRQ: Interrupt requested on completion
720 * ENA: Enable the queue. If ENA=0 the queue is initialized
721 * but remains disabled, to be later enabled with the
722 * Queue Enable command. If ENA=1, then queue is
723 * initialized and then enabled.
724 * SG: Enable Scatter-Gather on the queue.
725 * in number of descs. The actual ring size is
726 * (1 << ring_size). For example, to
727 * select a ring size of 64 descriptors write
728 * ring_size = 6. The minimum ring_size value is 2
729 * for a ring size of 4 descriptors. The maximum
730 * ring_size value is 16 for a ring size of 64k
731 * descriptors. Values of ring_size <2 and >16 are
732 * reserved.
733 * EQ: Enable the Event Queue
734 * @cos: Class of service for this queue
735 * @ring_size: Queue ring size, encoded as a log2(size)
736 * @ring_base: Queue ring base address
737 * @cq_ring_base: Completion queue ring base address
738 * @sg_ring_base: Scatter/Gather ring base address
739 * @rsvd2: reserved byte(s)
740 * @features: Mask of queue features to enable, if not in the flags above.
741 */
742 struct ionic_q_init_cmd {
743 u8 opcode;
744 u8 rsvd;
745 __le16 lif_index;
746 u8 type;
747 u8 ver;
748 u8 rsvd1[2];
749 __le32 index;
750 __le16 pid;
751 __le16 intr_index;
752 __le16 flags;
753 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
754 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
755 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
756 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
757 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */
758 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
759 u8 cos;
760 u8 ring_size;
761 __le64 ring_base;
762 __le64 cq_ring_base;
763 __le64 sg_ring_base;
764 u8 rsvd2[12];
765 __le64 features;
766 } __packed;
767
768 /**
769 * struct ionic_q_init_comp - Queue init command completion
770 * @status: Status of the command (enum ionic_status_code)
771 * @rsvd: reserved byte(s)
772 * @comp_index: Index in the descriptor ring for which this is the completion
773 * @hw_index: Hardware Queue ID
774 * @hw_type: Hardware Queue type
775 * @rsvd2: reserved byte(s)
776 * @color: Color
777 */
778 struct ionic_q_init_comp {
779 u8 status;
780 u8 rsvd;
781 __le16 comp_index;
782 __le32 hw_index;
783 u8 hw_type;
784 u8 rsvd2[6];
785 u8 color;
786 };
787
788 /* the device's internal addressing uses up to 52 bits */
789 #define IONIC_ADDR_LEN 52
790 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
791
792 enum ionic_txq_desc_opcode {
793 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
794 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
795 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
796 IONIC_TXQ_DESC_OPCODE_TSO = 3,
797 };
798
799 /**
800 * struct ionic_txq_desc - Ethernet Tx queue descriptor format
801 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
802 *
803 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
804 * Non-offload send. No segmentation,
805 * fragmentation or checksum calc/insertion is
806 * performed by device; packet is prepared
807 * to send by software stack and requires
808 * no further manipulation from device.
809 *
810 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
811 * Offload 16-bit L4 checksum
812 * calculation/insertion. The device will
813 * calculate the L4 checksum value and
814 * insert the result in the packet's L4
815 * header checksum field. The L4 checksum
816 * is calculated starting at @csum_start bytes
817 * into the packet to the end of the packet.
818 * The checksum insertion position is given
819 * in @csum_offset, which is the offset from
820 * @csum_start to the checksum field in the L4
821 * header. This feature is only applicable to
822 * protocols such as TCP, UDP and ICMP where a
823 * standard (i.e. the 'IP-style' checksum)
824 * one's complement 16-bit checksum is used,
825 * using an IP pseudo-header to seed the
826 * calculation. Software will preload the L4
827 * checksum field with the IP pseudo-header
828 * checksum.
829 *
830 * For tunnel encapsulation, @csum_start and
831 * @csum_offset refer to the inner L4
832 * header. Supported tunnels encapsulations
833 * are: IPIP, GRE, and UDP. If the @encap
834 * is clear, no further processing by the
835 * device is required; software will
836 * calculate the outer header checksums. If
837 * the @encap is set, the device will
838 * offload the outer header checksums using
839 * LCO (local checksum offload) (see
840 * Documentation/networking/checksum-offloads.rst
841 * for more info).
842 *
843 * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
844 * Offload 16-bit checksum computation to hardware.
845 * If @csum_l3 is set then the packet's L3 checksum is
846 * updated. Similarly, if @csum_l4 is set the L4
847 * checksum is updated. If @encap is set then encap header
848 * checksums are also updated.
849 *
850 * IONIC_TXQ_DESC_OPCODE_TSO:
851 * Device performs TCP segmentation offload
852 * (TSO). @hdr_len is the number of bytes
853 * to the end of TCP header (the offset to
854 * the TCP payload). @mss is the desired
855 * MSS, the TCP payload length for each
856 * segment. The device will calculate/
857 * insert IP (IPv4 only) and TCP checksums
858 * for each segment. In the first data
859 * buffer containing the header template,
860 * the driver will set IPv4 checksum to 0
861 * and preload TCP checksum with the IP
862 * pseudo header calculated with IP length = 0.
863 *
864 * Supported tunnel encapsulations are IPIP,
865 * layer-3 GRE, and UDP. @hdr_len includes
866 * both outer and inner headers. The driver
867 * will set IPv4 checksum to zero and
868 * preload TCP checksum with IP pseudo
869 * header on the inner header.
870 *
871 * TCP ECN offload is supported. The device
872 * will set CWR flag in the first segment if
873 * CWR is set in the template header, and
874 * clear CWR in remaining segments.
875 * flags:
876 * vlan:
877 * Insert an L2 VLAN header using @vlan_tci
878 * encap:
879 * Calculate encap header checksum
880 * csum_l3:
881 * Compute L3 header checksum
882 * csum_l4:
883 * Compute L4 header checksum
884 * tso_sot:
885 * TSO start
886 * tso_eot:
887 * TSO end
888 * num_sg_elems: Number of scatter-gather elements in SG
889 * descriptor
890 * addr: First data buffer's DMA address
891 * (Subsequent data buffers are on txq_sg_desc)
892 * @len: First data buffer's length, in bytes
893 * @vlan_tci: VLAN tag to insert in the packet (if requested
894 * by @V-bit). Includes .1p and .1q tags
895 * @hword0: half word padding
896 * @hdr_len: Length of packet headers, including
897 * encapsulating outer header, if applicable
898 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
899 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for
900 * all other modes. For
901 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
902 * of headers up to inner-most L4 header. For
903 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
904 * inner-most L4 payload, so inclusive of
905 * inner-most L4 header.
906 * @hword1: half word padding
907 * @mss: Desired MSS value for TSO; only applicable for
908 * IONIC_TXQ_DESC_OPCODE_TSO
909 * @csum_start: Offset from packet to first byte checked in L4 checksum
910 * @csum_offset: Offset from csum_start to L4 checksum field
911 * @hword2: half word padding
912 */
913 struct ionic_txq_desc {
914 __le64 cmd;
915 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf
916 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4
917 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf
918 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0
919 #define IONIC_TXQ_DESC_NSGE_MASK 0xf
920 #define IONIC_TXQ_DESC_NSGE_SHIFT 8
921 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
922 #define IONIC_TXQ_DESC_ADDR_SHIFT 12
923
924 /* common flags */
925 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1
926 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
927
928 /* flags for csum_hw opcode */
929 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
930 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
931
932 /* flags for tso opcode */
933 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
934 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
935
936 __le16 len;
937 union {
938 __le16 vlan_tci;
939 __le16 hword0;
940 };
941 union {
942 __le16 csum_start;
943 __le16 hdr_len;
944 __le16 hword1;
945 };
946 union {
947 __le16 csum_offset;
948 __le16 mss;
949 __le16 hword2;
950 };
951 };
952
encode_txq_desc_cmd(u8 opcode,u8 flags,u8 nsge,u64 addr)953 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
954 u8 nsge, u64 addr)
955 {
956 u64 cmd;
957
958 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
959 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
960 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
961 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
962
963 return cmd;
964 };
965
decode_txq_desc_cmd(u64 cmd,u8 * opcode,u8 * flags,u8 * nsge,u64 * addr)966 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
967 u8 *nsge, u64 *addr)
968 {
969 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
970 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
971 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
972 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
973 };
974
975 /**
976 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element
977 * @addr: DMA address of SG element data buffer
978 * @len: Length of SG element data buffer, in bytes
979 * @rsvd: reserved byte(s)
980 */
981 struct ionic_txq_sg_elem {
982 __le64 addr;
983 __le16 len;
984 __le16 rsvd[3];
985 };
986
987 /**
988 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
989 * @elems: Scatter-gather elements
990 */
991 struct ionic_txq_sg_desc {
992 #define IONIC_TX_MAX_SG_ELEMS 8
993 #define IONIC_TX_SG_DESC_STRIDE 8
994 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
995 };
996
997 struct ionic_txq_sg_desc_v1 {
998 #define IONIC_TX_MAX_SG_ELEMS_V1 15
999 #define IONIC_TX_SG_DESC_STRIDE_V1 16
1000 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
1001 };
1002
1003 /**
1004 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
1005 * @status: Status of the command (enum ionic_status_code)
1006 * @rsvd: reserved byte(s)
1007 * @comp_index: Index in the descriptor ring for which this is the completion
1008 * @rsvd2: reserved byte(s)
1009 * @color: Color bit
1010 */
1011 struct ionic_txq_comp {
1012 u8 status;
1013 u8 rsvd;
1014 __le16 comp_index;
1015 u8 rsvd2[11];
1016 u8 color;
1017 };
1018
1019 enum ionic_rxq_desc_opcode {
1020 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
1021 IONIC_RXQ_DESC_OPCODE_SG = 1,
1022 };
1023
1024 /**
1025 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
1026 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
1027 *
1028 * IONIC_RXQ_DESC_OPCODE_SIMPLE:
1029 * Receive full packet into data buffer
1030 * starting at @addr. Results of
1031 * receive, including actual bytes received,
1032 * are recorded in Rx completion descriptor.
1033 *
1034 * @rsvd: reserved byte(s)
1035 * @len: Data buffer's length, in bytes
1036 * @addr: Data buffer's DMA address
1037 */
1038 struct ionic_rxq_desc {
1039 u8 opcode;
1040 u8 rsvd[5];
1041 __le16 len;
1042 __le64 addr;
1043 };
1044
1045 /**
1046 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
1047 * @addr: DMA address of SG element data buffer
1048 * @len: Length of SG element data buffer, in bytes
1049 * @rsvd: reserved byte(s)
1050 */
1051 struct ionic_rxq_sg_elem {
1052 __le64 addr;
1053 __le16 len;
1054 __le16 rsvd[3];
1055 };
1056
1057 /**
1058 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
1059 * @elems: Scatter-gather elements
1060 */
1061 struct ionic_rxq_sg_desc {
1062 #define IONIC_RX_MAX_SG_ELEMS 8
1063 #define IONIC_RX_SG_DESC_STRIDE 8
1064 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
1065 };
1066
1067 /**
1068 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
1069 * @status: Status of the command (enum ionic_status_code)
1070 * @num_sg_elems: Number of SG elements used by this descriptor
1071 * @comp_index: Index in the descriptor ring for which this is the completion
1072 * @rss_hash: 32-bit RSS hash
1073 * @csum: 16-bit sum of the packet's L2 payload
1074 * If the packet's L2 payload is odd length, an extra
1075 * zero-value byte is included in the @csum calculation but
1076 * not included in @len.
1077 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
1078 * set. Includes .1p and .1q tags.
1079 * @len: Received packet length, in bytes. Excludes FCS.
1080 * @csum_calc L2 payload checksum is computed or not
1081 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:
1082 *
1083 * IONIC_RXQ_COMP_CSUM_F_TCP_OK:
1084 * The TCP checksum calculated by the device
1085 * matched the checksum in the receive packet's
1086 * TCP header.
1087 *
1088 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
1089 * The TCP checksum calculated by the device did
1090 * not match the checksum in the receive packet's
1091 * TCP header.
1092 *
1093 * IONIC_RXQ_COMP_CSUM_F_UDP_OK:
1094 * The UDP checksum calculated by the device
1095 * matched the checksum in the receive packet's
1096 * UDP header
1097 *
1098 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
1099 * The UDP checksum calculated by the device did
1100 * not match the checksum in the receive packet's
1101 * UDP header.
1102 *
1103 * IONIC_RXQ_COMP_CSUM_F_IP_OK:
1104 * The IPv4 checksum calculated by the device
1105 * matched the checksum in the receive packet's
1106 * first IPv4 header. If the receive packet
1107 * contains both a tunnel IPv4 header and a
1108 * transport IPv4 header, the device validates the
1109 * checksum for both IPv4 headers.
1110 *
1111 * IONIC_RXQ_COMP_CSUM_F_IP_BAD:
1112 * The IPv4 checksum calculated by the device did
1113 * not match the checksum in the receive packet's
1114 * first IPv4 header. If the receive packet
1115 * contains both a tunnel IPv4 header and a
1116 * transport IPv4 header, the device validates the
1117 * checksum for both IP headers.
1118 *
1119 * IONIC_RXQ_COMP_CSUM_F_VLAN:
1120 * The VLAN header was stripped and placed in @vlan_tci.
1121 *
1122 * IONIC_RXQ_COMP_CSUM_F_CALC:
1123 * The checksum was calculated by the device.
1124 *
1125 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
1126 */
1127 struct ionic_rxq_comp {
1128 u8 status;
1129 u8 num_sg_elems;
1130 __le16 comp_index;
1131 __le32 rss_hash;
1132 __le16 csum;
1133 __le16 vlan_tci;
1134 __le16 len;
1135 u8 csum_flags;
1136 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
1137 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
1138 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
1139 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
1140 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
1141 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
1142 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
1143 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
1144 u8 pkt_type_color;
1145 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
1146 };
1147
1148 enum ionic_pkt_type {
1149 IONIC_PKT_TYPE_NON_IP = 0x00,
1150 IONIC_PKT_TYPE_IPV4 = 0x01,
1151 IONIC_PKT_TYPE_IPV4_TCP = 0x03,
1152 IONIC_PKT_TYPE_IPV4_UDP = 0x05,
1153 IONIC_PKT_TYPE_IPV6 = 0x08,
1154 IONIC_PKT_TYPE_IPV6_TCP = 0x18,
1155 IONIC_PKT_TYPE_IPV6_UDP = 0x28,
1156 /* below types are only used if encap offloads are enabled on lif */
1157 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
1158 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
1159 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
1160 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
1161 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
1162 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
1163 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1164 };
1165
1166 enum ionic_eth_hw_features {
1167 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1168 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1169 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1170 IONIC_ETH_HW_RX_HASH = BIT(3),
1171 IONIC_ETH_HW_RX_CSUM = BIT(4),
1172 IONIC_ETH_HW_TX_SG = BIT(5),
1173 IONIC_ETH_HW_RX_SG = BIT(6),
1174 IONIC_ETH_HW_TX_CSUM = BIT(7),
1175 IONIC_ETH_HW_TSO = BIT(8),
1176 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1177 IONIC_ETH_HW_TSO_ECN = BIT(10),
1178 IONIC_ETH_HW_TSO_GRE = BIT(11),
1179 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1180 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1181 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1182 IONIC_ETH_HW_TSO_UDP = BIT(15),
1183 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1184 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1185 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1186 IONIC_ETH_HW_TSO_GENEVE = BIT(19),
1187 IONIC_ETH_HW_TIMESTAMP = BIT(20),
1188 IONIC_ETH_HW_RDMA_TIMESTAMP = BIT(21),
1189 };
1190
1191 /**
1192 * enum ionic_pkt_class - Packet classification mask.
1193 *
1194 * Used with rx steering filter, packets indicated by the mask can be steered
1195 * toward a specific receive queue.
1196 *
1197 * @IONIC_PKT_CLS_NTP_ALL: All NTP packets.
1198 * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync
1199 * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request
1200 * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets
1201 * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync
1202 * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request
1203 * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets
1204 * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync
1205 * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request
1206 * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets
1207 * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync
1208 * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request
1209 * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets
1210 * @IONIC_PKT_CLS_PTP_SYNC: PTP sync
1211 * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request
1212 * @IONIC_PKT_CLS_PTP_ALL: PTP all packets
1213 */
1214 enum ionic_pkt_class {
1215 IONIC_PKT_CLS_NTP_ALL = BIT(0),
1216
1217 IONIC_PKT_CLS_PTP1_SYNC = BIT(1),
1218 IONIC_PKT_CLS_PTP1_DREQ = BIT(2),
1219 IONIC_PKT_CLS_PTP1_ALL = BIT(3) |
1220 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ,
1221
1222 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4),
1223 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5),
1224 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) |
1225 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ,
1226
1227 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7),
1228 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8),
1229 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) |
1230 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ,
1231
1232 IONIC_PKT_CLS_PTP2_SYNC =
1233 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC,
1234 IONIC_PKT_CLS_PTP2_DREQ =
1235 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ,
1236 IONIC_PKT_CLS_PTP2_ALL =
1237 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL,
1238
1239 IONIC_PKT_CLS_PTP_SYNC =
1240 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC,
1241 IONIC_PKT_CLS_PTP_DREQ =
1242 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ,
1243 IONIC_PKT_CLS_PTP_ALL =
1244 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL,
1245 };
1246
1247 /**
1248 * struct ionic_q_control_cmd - Queue control command
1249 * @opcode: opcode
1250 * @type: Queue type
1251 * @lif_index: LIF index
1252 * @index: Queue index
1253 * @oper: Operation (enum ionic_q_control_oper)
1254 * @rsvd: reserved byte(s)
1255 */
1256 struct ionic_q_control_cmd {
1257 u8 opcode;
1258 u8 type;
1259 __le16 lif_index;
1260 __le32 index;
1261 u8 oper;
1262 u8 rsvd[55];
1263 };
1264
1265 typedef struct ionic_admin_comp ionic_q_control_comp;
1266
1267 enum ionic_q_control_oper {
1268 IONIC_Q_DISABLE = 0,
1269 IONIC_Q_ENABLE = 1,
1270 IONIC_Q_HANG_RESET = 2,
1271 };
1272
1273 /**
1274 * enum ionic_phy_type - Physical connection type
1275 * @IONIC_PHY_TYPE_NONE: No PHY installed
1276 * @IONIC_PHY_TYPE_COPPER: Copper PHY
1277 * @IONIC_PHY_TYPE_FIBER: Fiber PHY
1278 */
1279 enum ionic_phy_type {
1280 IONIC_PHY_TYPE_NONE = 0,
1281 IONIC_PHY_TYPE_COPPER = 1,
1282 IONIC_PHY_TYPE_FIBER = 2,
1283 };
1284
1285 /**
1286 * enum ionic_xcvr_state - Transceiver status
1287 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed
1288 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted
1289 * @IONIC_XCVR_STATE_PENDING: Transceiver pending
1290 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read
1291 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
1292 */
1293 enum ionic_xcvr_state {
1294 IONIC_XCVR_STATE_REMOVED = 0,
1295 IONIC_XCVR_STATE_INSERTED = 1,
1296 IONIC_XCVR_STATE_PENDING = 2,
1297 IONIC_XCVR_STATE_SPROM_READ = 3,
1298 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1299 };
1300
1301 /*
1302 * enum ionic_xcvr_pid - Supported link modes
1303 */
1304 enum ionic_xcvr_pid {
1305 IONIC_XCVR_PID_UNKNOWN = 0,
1306
1307 /* CU */
1308 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1309 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1310 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1311 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1312 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1313 IONIC_XCVR_PID_QSFP_50G_CR2_FC = 6,
1314 IONIC_XCVR_PID_QSFP_50G_CR2 = 7,
1315 IONIC_XCVR_PID_QSFP_200G_CR4 = 8,
1316 IONIC_XCVR_PID_QSFP_400G_CR4 = 9,
1317 /* Fiber */
1318 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1319 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1320 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1321 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1322 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1323 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1324 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1325 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1326 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1327 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1328 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1329 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1330 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1331 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1332 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1333 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1334 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1335 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1336 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1337 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1338 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1339 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1340 IONIC_XCVR_PID_SFP_10GBASE_T = 72,
1341 IONIC_XCVR_PID_SFP_1000BASE_T = 73,
1342 IONIC_XCVR_PID_QSFP_200G_AOC = 74,
1343 IONIC_XCVR_PID_QSFP_200G_FR4 = 75,
1344 IONIC_XCVR_PID_QSFP_200G_DR4 = 76,
1345 IONIC_XCVR_PID_QSFP_200G_SR4 = 77,
1346 IONIC_XCVR_PID_QSFP_200G_ACC = 78,
1347 IONIC_XCVR_PID_QSFP_400G_FR4 = 79,
1348 IONIC_XCVR_PID_QSFP_400G_DR4 = 80,
1349 IONIC_XCVR_PID_QSFP_400G_SR4 = 81,
1350 IONIC_XCVR_PID_QSFP_400G_VR4 = 82,
1351 IONIC_XCVR_PID_QSFP_400G_AOC = 83,
1352 IONIC_XCVR_PID_QSFP_400G_AEC = 84,
1353 IONIC_XCVR_PID_QSFP_200G_AEC = 85,
1354 IONIC_XCVR_PID_QSFP_400G_LPO = 86,
1355 IONIC_XCVR_PID_QSFP_100G_FR4 = 87,
1356 IONIC_XCVR_PID_QSFP_100G_DR4 = 88,
1357 };
1358
1359 /**
1360 * enum ionic_port_type - Port types
1361 * @IONIC_PORT_TYPE_NONE: Port type not configured
1362 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband)
1363 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band)
1364 */
1365 enum ionic_port_type {
1366 IONIC_PORT_TYPE_NONE = 0,
1367 IONIC_PORT_TYPE_ETH = 1,
1368 IONIC_PORT_TYPE_MGMT = 2,
1369 };
1370
1371 /**
1372 * enum ionic_port_admin_state - Port config state
1373 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured
1374 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled
1375 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
1376 */
1377 enum ionic_port_admin_state {
1378 IONIC_PORT_ADMIN_STATE_NONE = 0,
1379 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1380 IONIC_PORT_ADMIN_STATE_UP = 2,
1381 };
1382
1383 /**
1384 * enum ionic_port_oper_status - Port operational status
1385 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled
1386 * @IONIC_PORT_OPER_STATUS_UP: Port link status up
1387 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
1388 */
1389 enum ionic_port_oper_status {
1390 IONIC_PORT_OPER_STATUS_NONE = 0,
1391 IONIC_PORT_OPER_STATUS_UP = 1,
1392 IONIC_PORT_OPER_STATUS_DOWN = 2,
1393 };
1394
1395 /**
1396 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
1397 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled
1398 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC
1399 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC
1400 */
1401 enum ionic_port_fec_type {
1402 IONIC_PORT_FEC_TYPE_NONE = 0,
1403 IONIC_PORT_FEC_TYPE_FC = 1,
1404 IONIC_PORT_FEC_TYPE_RS = 2,
1405 };
1406
1407 /**
1408 * enum ionic_port_pause_type - Ethernet pause (flow control) modes
1409 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause
1410 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause
1411 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control
1412 */
1413 enum ionic_port_pause_type {
1414 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1415 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1416 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1417 };
1418
1419 /**
1420 * enum ionic_port_loopback_mode - Loopback modes
1421 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback
1422 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback
1423 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback
1424 */
1425 enum ionic_port_loopback_mode {
1426 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1427 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1428 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1429 };
1430
1431 /**
1432 * struct ionic_xcvr_status - Transceiver Status information
1433 * @state: Transceiver status (enum ionic_xcvr_state)
1434 * @phy: Physical connection type (enum ionic_phy_type)
1435 * @pid: Transceiver link mode (enum ionic_xcvr_pid)
1436 * @sprom: Transceiver sprom contents
1437 */
1438 struct ionic_xcvr_status {
1439 u8 state;
1440 u8 phy;
1441 __le16 pid;
1442 u8 sprom[256];
1443 };
1444
1445 /**
1446 * union ionic_port_config - Port configuration
1447 * @speed: port speed (in Mbps)
1448 * @mtu: mtu
1449 * @state: port admin state (enum ionic_port_admin_state)
1450 * @an_enable: autoneg enable
1451 * @fec_type: fec type (enum ionic_port_fec_type)
1452 * @pause_type: pause type (enum ionic_port_pause_type)
1453 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)
1454 * @words: word access to struct contents
1455 */
1456 union ionic_port_config {
1457 struct {
1458 #define IONIC_SPEED_400G 400000 /* 400G in Mbps */
1459 #define IONIC_SPEED_200G 200000 /* 200G in Mbps */
1460 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */
1461 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */
1462 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */
1463 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */
1464 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */
1465 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */
1466 __le32 speed;
1467 __le32 mtu;
1468 u8 state;
1469 u8 an_enable;
1470 u8 fec_type;
1471 #define IONIC_PAUSE_TYPE_MASK 0x0f
1472 #define IONIC_PAUSE_FLAGS_MASK 0xf0
1473 #define IONIC_PAUSE_F_TX 0x10
1474 #define IONIC_PAUSE_F_RX 0x20
1475 u8 pause_type;
1476 u8 loopback_mode;
1477 };
1478 __le32 words[64];
1479 };
1480
1481 /**
1482 * struct ionic_port_status - Port Status information
1483 * @status: link status (enum ionic_port_oper_status)
1484 * @id: port id
1485 * @speed: link speed (in Mbps)
1486 * @link_down_count: number of times link went from up to down
1487 * @fec_type: fec type (enum ionic_port_fec_type)
1488 * @rsvd: reserved byte(s)
1489 * @xcvr: transceiver status
1490 */
1491 struct ionic_port_status {
1492 __le32 id;
1493 __le32 speed;
1494 u8 status;
1495 __le16 link_down_count;
1496 u8 fec_type;
1497 u8 rsvd[48];
1498 struct ionic_xcvr_status xcvr;
1499 } __packed;
1500
1501 /**
1502 * struct ionic_port_identify_cmd - Port identify command
1503 * @opcode: opcode
1504 * @index: port index
1505 * @ver: Highest version of identify supported by driver
1506 * @rsvd: reserved byte(s)
1507 */
1508 struct ionic_port_identify_cmd {
1509 u8 opcode;
1510 u8 index;
1511 u8 ver;
1512 u8 rsvd[61];
1513 };
1514
1515 /**
1516 * struct ionic_port_identify_comp - Port identify command completion
1517 * @status: Status of the command (enum ionic_status_code)
1518 * @ver: Version of identify returned by device
1519 * @rsvd: reserved byte(s)
1520 */
1521 struct ionic_port_identify_comp {
1522 u8 status;
1523 u8 ver;
1524 u8 rsvd[14];
1525 };
1526
1527 /**
1528 * struct ionic_port_init_cmd - Port initialization command
1529 * @opcode: opcode
1530 * @index: port index
1531 * @rsvd: reserved byte(s)
1532 * @info_pa: destination address for port info (struct ionic_port_info)
1533 * @rsvd2: reserved byte(s)
1534 */
1535 struct ionic_port_init_cmd {
1536 u8 opcode;
1537 u8 index;
1538 u8 rsvd[6];
1539 __le64 info_pa;
1540 u8 rsvd2[48];
1541 };
1542
1543 /**
1544 * struct ionic_port_init_comp - Port initialization command completion
1545 * @status: Status of the command (enum ionic_status_code)
1546 * @rsvd: reserved byte(s)
1547 */
1548 struct ionic_port_init_comp {
1549 u8 status;
1550 u8 rsvd[15];
1551 };
1552
1553 /**
1554 * struct ionic_port_reset_cmd - Port reset command
1555 * @opcode: opcode
1556 * @index: port index
1557 * @rsvd: reserved byte(s)
1558 */
1559 struct ionic_port_reset_cmd {
1560 u8 opcode;
1561 u8 index;
1562 u8 rsvd[62];
1563 };
1564
1565 /**
1566 * struct ionic_port_reset_comp - Port reset command completion
1567 * @status: Status of the command (enum ionic_status_code)
1568 * @rsvd: reserved byte(s)
1569 */
1570 struct ionic_port_reset_comp {
1571 u8 status;
1572 u8 rsvd[15];
1573 };
1574
1575 /**
1576 * enum ionic_stats_ctl_cmd - List of commands for stats control
1577 * @IONIC_STATS_CTL_RESET: Reset statistics
1578 */
1579 enum ionic_stats_ctl_cmd {
1580 IONIC_STATS_CTL_RESET = 0,
1581 };
1582
1583 /**
1584 * enum ionic_txstamp_mode - List of TX Timestamping Modes
1585 * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping.
1586 * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping.
1587 * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets.
1588 * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp.
1589 */
1590 enum ionic_txstamp_mode {
1591 IONIC_TXSTAMP_OFF = 0,
1592 IONIC_TXSTAMP_ON = 1,
1593 IONIC_TXSTAMP_ONESTEP_SYNC = 2,
1594 IONIC_TXSTAMP_ONESTEP_P2P = 3,
1595 };
1596
1597 /**
1598 * enum ionic_port_attr - List of device attributes
1599 * @IONIC_PORT_ATTR_STATE: Port state attribute
1600 * @IONIC_PORT_ATTR_SPEED: Port speed attribute
1601 * @IONIC_PORT_ATTR_MTU: Port MTU attribute
1602 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute
1603 * @IONIC_PORT_ATTR_FEC: Port FEC attribute
1604 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute
1605 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute
1606 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
1607 */
1608 enum ionic_port_attr {
1609 IONIC_PORT_ATTR_STATE = 0,
1610 IONIC_PORT_ATTR_SPEED = 1,
1611 IONIC_PORT_ATTR_MTU = 2,
1612 IONIC_PORT_ATTR_AUTONEG = 3,
1613 IONIC_PORT_ATTR_FEC = 4,
1614 IONIC_PORT_ATTR_PAUSE = 5,
1615 IONIC_PORT_ATTR_LOOPBACK = 6,
1616 IONIC_PORT_ATTR_STATS_CTRL = 7,
1617 };
1618
1619 /**
1620 * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1621 * @opcode: Opcode
1622 * @index: Port index
1623 * @attr: Attribute type (enum ionic_port_attr)
1624 * @rsvd: reserved byte(s)
1625 * @state: Port state
1626 * @speed: Port speed
1627 * @mtu: Port MTU
1628 * @an_enable: Port autonegotiation setting
1629 * @fec_type: Port FEC type setting
1630 * @pause_type: Port pause type setting
1631 * @loopback_mode: Port loopback mode
1632 * @stats_ctl: Port stats setting
1633 * @rsvd2: reserved byte(s)
1634 */
1635 struct ionic_port_setattr_cmd {
1636 u8 opcode;
1637 u8 index;
1638 u8 attr;
1639 u8 rsvd;
1640 union {
1641 u8 state;
1642 __le32 speed;
1643 __le32 mtu;
1644 u8 an_enable;
1645 u8 fec_type;
1646 u8 pause_type;
1647 u8 loopback_mode;
1648 u8 stats_ctl;
1649 u8 rsvd2[60];
1650 };
1651 };
1652
1653 /**
1654 * struct ionic_port_setattr_comp - Port set attr command completion
1655 * @status: Status of the command (enum ionic_status_code)
1656 * @rsvd: reserved byte(s)
1657 * @color: Color bit
1658 */
1659 struct ionic_port_setattr_comp {
1660 u8 status;
1661 u8 rsvd[14];
1662 u8 color;
1663 };
1664
1665 /**
1666 * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1667 * @opcode: Opcode
1668 * @index: port index
1669 * @attr: Attribute type (enum ionic_port_attr)
1670 * @rsvd: reserved byte(s)
1671 */
1672 struct ionic_port_getattr_cmd {
1673 u8 opcode;
1674 u8 index;
1675 u8 attr;
1676 u8 rsvd[61];
1677 };
1678
1679 /**
1680 * struct ionic_port_getattr_comp - Port get attr command completion
1681 * @status: Status of the command (enum ionic_status_code)
1682 * @rsvd: reserved byte(s)
1683 * @state: Port state
1684 * @speed: Port speed
1685 * @mtu: Port MTU
1686 * @an_enable: Port autonegotiation setting
1687 * @fec_type: Port FEC type setting
1688 * @pause_type: Port pause type setting
1689 * @loopback_mode: Port loopback mode
1690 * @rsvd2: reserved byte(s)
1691 * @color: Color bit
1692 */
1693 struct ionic_port_getattr_comp {
1694 u8 status;
1695 u8 rsvd[3];
1696 union {
1697 u8 state;
1698 __le32 speed;
1699 __le32 mtu;
1700 u8 an_enable;
1701 u8 fec_type;
1702 u8 pause_type;
1703 u8 loopback_mode;
1704 u8 rsvd2[11];
1705 } __packed;
1706 u8 color;
1707 };
1708
1709 /**
1710 * struct ionic_lif_status - LIF status register
1711 * @eid: most recent NotifyQ event id
1712 * @port_num: port the LIF is connected to
1713 * @rsvd: reserved byte(s)
1714 * @link_status: port status (enum ionic_port_oper_status)
1715 * @link_speed: speed of link in Mbps
1716 * @link_down_count: number of times link went from up to down
1717 * @rsvd2: reserved byte(s)
1718 */
1719 struct ionic_lif_status {
1720 __le64 eid;
1721 u8 port_num;
1722 u8 rsvd;
1723 __le16 link_status;
1724 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
1725 __le16 link_down_count;
1726 u8 rsvd2[46];
1727 };
1728
1729 /**
1730 * struct ionic_lif_reset_cmd - LIF reset command
1731 * @opcode: opcode
1732 * @rsvd: reserved byte(s)
1733 * @index: LIF index
1734 * @rsvd2: reserved byte(s)
1735 */
1736 struct ionic_lif_reset_cmd {
1737 u8 opcode;
1738 u8 rsvd;
1739 __le16 index;
1740 __le32 rsvd2[15];
1741 };
1742
1743 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1744
1745 enum ionic_dev_state {
1746 IONIC_DEV_DISABLE = 0,
1747 IONIC_DEV_ENABLE = 1,
1748 IONIC_DEV_HANG_RESET = 2,
1749 };
1750
1751 /**
1752 * enum ionic_dev_attr - List of device attributes
1753 * @IONIC_DEV_ATTR_STATE: Device state attribute
1754 * @IONIC_DEV_ATTR_NAME: Device name attribute
1755 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes
1756 */
1757 enum ionic_dev_attr {
1758 IONIC_DEV_ATTR_STATE = 0,
1759 IONIC_DEV_ATTR_NAME = 1,
1760 IONIC_DEV_ATTR_FEATURES = 2,
1761 };
1762
1763 /**
1764 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1765 * @opcode: Opcode
1766 * @attr: Attribute type (enum ionic_dev_attr)
1767 * @rsvd: reserved byte(s)
1768 * @state: Device state (enum ionic_dev_state)
1769 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
1770 * @features: Device features
1771 * @rsvd2: reserved byte(s)
1772 */
1773 struct ionic_dev_setattr_cmd {
1774 u8 opcode;
1775 u8 attr;
1776 __le16 rsvd;
1777 union {
1778 u8 state;
1779 char name[IONIC_IFNAMSIZ];
1780 __le64 features;
1781 u8 rsvd2[60];
1782 } __packed;
1783 };
1784
1785 /**
1786 * struct ionic_dev_setattr_comp - Device set attr command completion
1787 * @status: Status of the command (enum ionic_status_code)
1788 * @rsvd: reserved byte(s)
1789 * @features: Device features
1790 * @rsvd2: reserved byte(s)
1791 * @color: Color bit
1792 */
1793 struct ionic_dev_setattr_comp {
1794 u8 status;
1795 u8 rsvd[3];
1796 union {
1797 __le64 features;
1798 u8 rsvd2[11];
1799 } __packed;
1800 u8 color;
1801 };
1802
1803 /**
1804 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1805 * @opcode: opcode
1806 * @attr: Attribute type (enum ionic_dev_attr)
1807 * @rsvd: reserved byte(s)
1808 */
1809 struct ionic_dev_getattr_cmd {
1810 u8 opcode;
1811 u8 attr;
1812 u8 rsvd[62];
1813 };
1814
1815 /**
1816 * struct ionic_dev_getattr_comp - Device set attr command completion
1817 * @status: Status of the command (enum ionic_status_code)
1818 * @rsvd: reserved byte(s)
1819 * @features: Device features
1820 * @rsvd2: reserved byte(s)
1821 * @color: Color bit
1822 */
1823 struct ionic_dev_getattr_comp {
1824 u8 status;
1825 u8 rsvd[3];
1826 union {
1827 __le64 features;
1828 u8 rsvd2[11];
1829 } __packed;
1830 u8 color;
1831 };
1832
1833 /*
1834 * RSS parameters
1835 */
1836 #define IONIC_RSS_HASH_KEY_SIZE 40
1837
1838 enum ionic_rss_hash_types {
1839 IONIC_RSS_TYPE_IPV4 = BIT(0),
1840 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1841 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1842 IONIC_RSS_TYPE_IPV6 = BIT(3),
1843 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1844 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1845 };
1846
1847 /**
1848 * enum ionic_lif_attr - List of LIF attributes
1849 * @IONIC_LIF_ATTR_STATE: LIF state attribute
1850 * @IONIC_LIF_ATTR_NAME: LIF name attribute
1851 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute
1852 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute
1853 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute
1854 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute
1855 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute
1856 * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode
1857 * @IONIC_LIF_ATTR_MAX: maximum attribute value
1858 */
1859 enum ionic_lif_attr {
1860 IONIC_LIF_ATTR_STATE = 0,
1861 IONIC_LIF_ATTR_NAME = 1,
1862 IONIC_LIF_ATTR_MTU = 2,
1863 IONIC_LIF_ATTR_MAC = 3,
1864 IONIC_LIF_ATTR_FEATURES = 4,
1865 IONIC_LIF_ATTR_RSS = 5,
1866 IONIC_LIF_ATTR_STATS_CTRL = 6,
1867 IONIC_LIF_ATTR_TXSTAMP = 7,
1868 IONIC_LIF_ATTR_MAX = 255,
1869 };
1870
1871 /**
1872 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1873 * @opcode: Opcode
1874 * @attr: Attribute type (enum ionic_lif_attr)
1875 * @index: LIF index
1876 * @state: LIF state (enum ionic_lif_state)
1877 * @name: The netdev name string, 0 terminated
1878 * @mtu: Mtu
1879 * @mac: Station mac
1880 * @features: Features (enum ionic_eth_hw_features)
1881 * @rss: RSS properties
1882 * @rss.types: The hash types to enable (see rss_hash_types)
1883 * @rss.key: The hash secret key
1884 * @rss.rsvd: reserved byte(s)
1885 * @rss.addr: Address for the indirection table shared memory
1886 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)
1887 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode)
1888 * @rsvd: reserved byte(s)
1889 */
1890 struct ionic_lif_setattr_cmd {
1891 u8 opcode;
1892 u8 attr;
1893 __le16 index;
1894 union {
1895 u8 state;
1896 char name[IONIC_IFNAMSIZ];
1897 __le32 mtu;
1898 u8 mac[6];
1899 __le64 features;
1900 struct {
1901 __le16 types;
1902 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1903 u8 rsvd[6];
1904 __le64 addr;
1905 } rss;
1906 u8 stats_ctl;
1907 __le16 txstamp_mode;
1908 u8 rsvd[60];
1909 } __packed;
1910 };
1911
1912 /**
1913 * struct ionic_lif_setattr_comp - LIF set attr command completion
1914 * @status: Status of the command (enum ionic_status_code)
1915 * @rsvd: reserved byte(s)
1916 * @comp_index: Index in the descriptor ring for which this is the completion
1917 * @features: features (enum ionic_eth_hw_features)
1918 * @rsvd2: reserved byte(s)
1919 * @color: Color bit
1920 */
1921 struct ionic_lif_setattr_comp {
1922 u8 status;
1923 u8 rsvd;
1924 __le16 comp_index;
1925 union {
1926 __le64 features;
1927 u8 rsvd2[11];
1928 } __packed;
1929 u8 color;
1930 };
1931
1932 /**
1933 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1934 * @opcode: Opcode
1935 * @attr: Attribute type (enum ionic_lif_attr)
1936 * @index: LIF index
1937 * @rsvd: reserved byte(s)
1938 */
1939 struct ionic_lif_getattr_cmd {
1940 u8 opcode;
1941 u8 attr;
1942 __le16 index;
1943 u8 rsvd[60];
1944 };
1945
1946 /**
1947 * struct ionic_lif_getattr_comp - LIF get attr command completion
1948 * @status: Status of the command (enum ionic_status_code)
1949 * @rsvd: reserved byte(s)
1950 * @comp_index: Index in the descriptor ring for which this is the completion
1951 * @state: LIF state (enum ionic_lif_state)
1952 * @mtu: Mtu
1953 * @mac: Station mac
1954 * @features: Features (enum ionic_eth_hw_features)
1955 * @txstamp_mode: TX Timestamping Mode (enum ionic_txstamp_mode)
1956 * @rsvd2: reserved byte(s)
1957 * @color: Color bit
1958 */
1959 struct ionic_lif_getattr_comp {
1960 u8 status;
1961 u8 rsvd;
1962 __le16 comp_index;
1963 union {
1964 u8 state;
1965 __le32 mtu;
1966 u8 mac[6];
1967 __le64 features;
1968 __le16 txstamp_mode;
1969 u8 rsvd2[11];
1970 } __packed;
1971 u8 color;
1972 };
1973
1974 /**
1975 * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock
1976 * @opcode: Opcode
1977 * @rsvd1: reserved byte(s)
1978 * @lif_index: LIF index
1979 * @rsvd2: reserved byte(s)
1980 * @tick: Hardware stamp tick of an instant in time.
1981 * @nsec: Nanosecond stamp of the same instant.
1982 * @frac: Fractional nanoseconds at the same instant.
1983 * @mult: Cycle to nanosecond multiplier.
1984 * @shift: Cycle to nanosecond divisor (power of two).
1985 * @rsvd3: reserved byte(s)
1986 */
1987 struct ionic_lif_setphc_cmd {
1988 u8 opcode;
1989 u8 rsvd1;
1990 __le16 lif_index;
1991 u8 rsvd2[4];
1992 __le64 tick;
1993 __le64 nsec;
1994 __le64 frac;
1995 __le32 mult;
1996 __le32 shift;
1997 u8 rsvd3[24];
1998 };
1999
2000 enum ionic_rx_mode {
2001 IONIC_RX_MODE_F_UNICAST = BIT(0),
2002 IONIC_RX_MODE_F_MULTICAST = BIT(1),
2003 IONIC_RX_MODE_F_BROADCAST = BIT(2),
2004 IONIC_RX_MODE_F_PROMISC = BIT(3),
2005 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
2006 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
2007 };
2008
2009 /**
2010 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
2011 * @opcode: opcode
2012 * @rsvd: reserved byte(s)
2013 * @lif_index: LIF index
2014 * @rx_mode: Rx mode flags:
2015 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
2016 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
2017 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
2018 * IONIC_RX_MODE_F_PROMISC: Accept any packets
2019 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
2020 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
2021 * @rsvd2: reserved byte(s)
2022 */
2023 struct ionic_rx_mode_set_cmd {
2024 u8 opcode;
2025 u8 rsvd;
2026 __le16 lif_index;
2027 __le16 rx_mode;
2028 __le16 rsvd2[29];
2029 };
2030
2031 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
2032
2033 enum ionic_rx_filter_match_type {
2034 IONIC_RX_FILTER_MATCH_VLAN = 0x0,
2035 IONIC_RX_FILTER_MATCH_MAC = 0x1,
2036 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2,
2037 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10,
2038 };
2039
2040 /**
2041 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
2042 * @opcode: opcode
2043 * @qtype: Queue type
2044 * @lif_index: LIF index
2045 * @qid: Queue ID
2046 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
2047 * @vlan: VLAN filter
2048 * @vlan.vlan: VLAN ID
2049 * @mac: MAC filter
2050 * @mac.addr: MAC address (network-byte order)
2051 * @mac_vlan: MACVLAN filter
2052 * @mac_vlan.vlan: VLAN ID
2053 * @mac_vlan.addr: MAC address (network-byte order)
2054 * @pkt_class: Packet classification filter
2055 * @rsvd: reserved byte(s)
2056 */
2057 struct ionic_rx_filter_add_cmd {
2058 u8 opcode;
2059 u8 qtype;
2060 __le16 lif_index;
2061 __le32 qid;
2062 __le16 match;
2063 union {
2064 struct {
2065 __le16 vlan;
2066 } vlan;
2067 struct {
2068 u8 addr[6];
2069 } mac;
2070 struct {
2071 __le16 vlan;
2072 u8 addr[6];
2073 } mac_vlan;
2074 __le64 pkt_class;
2075 u8 rsvd[54];
2076 } __packed;
2077 };
2078
2079 /**
2080 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
2081 * @status: Status of the command (enum ionic_status_code)
2082 * @rsvd: reserved byte(s)
2083 * @comp_index: Index in the descriptor ring for which this is the completion
2084 * @filter_id: Filter ID
2085 * @rsvd2: reserved byte(s)
2086 * @color: Color bit
2087 */
2088 struct ionic_rx_filter_add_comp {
2089 u8 status;
2090 u8 rsvd;
2091 __le16 comp_index;
2092 __le32 filter_id;
2093 u8 rsvd2[7];
2094 u8 color;
2095 };
2096
2097 /**
2098 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
2099 * @opcode: opcode
2100 * @rsvd: reserved byte(s)
2101 * @lif_index: LIF index
2102 * @filter_id: Filter ID
2103 * @rsvd2: reserved byte(s)
2104 */
2105 struct ionic_rx_filter_del_cmd {
2106 u8 opcode;
2107 u8 rsvd;
2108 __le16 lif_index;
2109 __le32 filter_id;
2110 u8 rsvd2[56];
2111 };
2112
2113 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
2114
2115 enum ionic_vf_attr {
2116 IONIC_VF_ATTR_SPOOFCHK = 1,
2117 IONIC_VF_ATTR_TRUST = 2,
2118 IONIC_VF_ATTR_MAC = 3,
2119 IONIC_VF_ATTR_LINKSTATE = 4,
2120 IONIC_VF_ATTR_VLAN = 5,
2121 IONIC_VF_ATTR_RATE = 6,
2122 IONIC_VF_ATTR_STATSADDR = 7,
2123 };
2124
2125 /**
2126 * enum ionic_vf_link_status - Virtual Function link status
2127 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink
2128 * @IONIC_VF_LINK_STATUS_UP: Link always up
2129 * @IONIC_VF_LINK_STATUS_DOWN: Link always down
2130 */
2131 enum ionic_vf_link_status {
2132 IONIC_VF_LINK_STATUS_AUTO = 0,
2133 IONIC_VF_LINK_STATUS_UP = 1,
2134 IONIC_VF_LINK_STATUS_DOWN = 2,
2135 };
2136
2137 /**
2138 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
2139 * @opcode: Opcode
2140 * @attr: Attribute type (enum ionic_vf_attr)
2141 * @vf_index: VF index
2142 * @macaddr: mac address
2143 * @vlanid: vlan ID
2144 * @maxrate: max Tx rate in Mbps
2145 * @spoofchk: enable address spoof checking
2146 * @trust: enable VF trust
2147 * @linkstate: set link up or down
2148 * @stats_pa: set DMA address for VF stats
2149 * @pad: reserved byte(s)
2150 */
2151 struct ionic_vf_setattr_cmd {
2152 u8 opcode;
2153 u8 attr;
2154 __le16 vf_index;
2155 union {
2156 u8 macaddr[6];
2157 __le16 vlanid;
2158 __le32 maxrate;
2159 u8 spoofchk;
2160 u8 trust;
2161 u8 linkstate;
2162 __le64 stats_pa;
2163 u8 pad[60];
2164 } __packed;
2165 };
2166
2167 struct ionic_vf_setattr_comp {
2168 u8 status;
2169 u8 attr;
2170 __le16 vf_index;
2171 __le16 comp_index;
2172 u8 rsvd[9];
2173 u8 color;
2174 };
2175
2176 /**
2177 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
2178 * @opcode: Opcode
2179 * @attr: Attribute type (enum ionic_vf_attr)
2180 * @vf_index: VF index
2181 * @rsvd: reserved byte(s)
2182 */
2183 struct ionic_vf_getattr_cmd {
2184 u8 opcode;
2185 u8 attr;
2186 __le16 vf_index;
2187 u8 rsvd[60];
2188 };
2189
2190 struct ionic_vf_getattr_comp {
2191 u8 status;
2192 u8 attr;
2193 __le16 vf_index;
2194 union {
2195 u8 macaddr[6];
2196 __le16 vlanid;
2197 __le32 maxrate;
2198 u8 spoofchk;
2199 u8 trust;
2200 u8 linkstate;
2201 __le64 stats_pa;
2202 u8 pad[11];
2203 } __packed;
2204 u8 color;
2205 };
2206
2207 enum ionic_vf_ctrl_opcode {
2208 IONIC_VF_CTRL_START_ALL = 0,
2209 IONIC_VF_CTRL_START = 1,
2210 };
2211
2212 /**
2213 * struct ionic_vf_ctrl_cmd - VF control command
2214 * @opcode: Opcode for the command
2215 * @ctrl_opcode: VF control operation type
2216 * @vf_index: VF Index. It is unused if op START_ALL is used.
2217 */
2218 struct ionic_vf_ctrl_cmd {
2219 u8 opcode;
2220 u8 ctrl_opcode;
2221 __le16 vf_index;
2222 /* private: */
2223 u8 rsvd1[60];
2224 };
2225
2226 /**
2227 * struct ionic_vf_ctrl_comp - VF_CTRL command completion.
2228 * @status: Status of the command (enum ionic_status_code)
2229 */
2230 struct ionic_vf_ctrl_comp {
2231 u8 status;
2232 /* private: */
2233 u8 rsvd[15];
2234 };
2235
2236 /**
2237 * struct ionic_discover_cmb_cmd - CMB discovery command
2238 * @opcode: Opcode for the command
2239 * @rsvd: Reserved bytes
2240 */
2241 struct ionic_discover_cmb_cmd {
2242 u8 opcode;
2243 u8 rsvd[63];
2244 };
2245
2246 /**
2247 * struct ionic_discover_cmb_comp - CMB discover command completion.
2248 * @status: Status of the command (enum ionic_status_code)
2249 * @rsvd: Reserved bytes
2250 */
2251 struct ionic_discover_cmb_comp {
2252 u8 status;
2253 u8 rsvd[15];
2254 };
2255
2256 #define IONIC_MAX_CMB_REGIONS 16
2257 #define IONIC_CMB_SHIFT_64K 16
2258
2259 enum ionic_cmb_type {
2260 IONIC_CMB_TYPE_DEVMEM = 0,
2261 IONIC_CMB_TYPE_EXPDB64 = 1,
2262 IONIC_CMB_TYPE_EXPDB128 = 2,
2263 IONIC_CMB_TYPE_EXPDB256 = 3,
2264 IONIC_CMB_TYPE_EXPDB512 = 4,
2265 };
2266
2267 /**
2268 * union ionic_cmb_region - Configuration for CMB region
2269 * @bar_num: CMB mapping number from FW
2270 * @cmb_type: Type of CMB this region describes (enum ionic_cmb_type)
2271 * @rsvd: Reserved
2272 * @offset: Offset within BAR in 64KB pages
2273 * @length: Length of the CMB region
2274 * @words: 32-bit words for direct access to the entire region
2275 */
2276 union ionic_cmb_region {
2277 struct {
2278 u8 bar_num;
2279 u8 cmb_type;
2280 u8 rsvd[6];
2281 __le32 offset;
2282 __le32 length;
2283 } __packed;
2284 __le32 words[4];
2285 };
2286
2287 /**
2288 * union ionic_discover_cmb_identity - CMB layout identity structure
2289 * @num_regions: Number of CMB regions, up to 16
2290 * @flags: Feature and capability bits (0 for express
2291 * doorbell, 1 for 4K alignment indicator,
2292 * 31-24 for version information)
2293 * @region: CMB mappings region, entry 0 for regular
2294 * mapping, entries 1-7 for WQE sizes 64,
2295 * 128, 256, 512, 1024, 2048 and 4096 bytes
2296 * @words: Full union buffer size
2297 */
2298 union ionic_discover_cmb_identity {
2299 struct {
2300 __le32 num_regions;
2301 #define IONIC_CMB_FLAG_EXPDB BIT(0)
2302 #define IONIC_CMB_FLAG_4KALIGN BIT(1)
2303 #define IONIC_CMB_FLAG_VERSION 0xff000000
2304 __le32 flags;
2305 union ionic_cmb_region region[IONIC_MAX_CMB_REGIONS];
2306 };
2307 __le32 words[478];
2308 };
2309
2310 /**
2311 * struct ionic_qos_identify_cmd - QoS identify command
2312 * @opcode: opcode
2313 * @ver: Highest version of identify supported by driver
2314 * @rsvd: reserved byte(s)
2315 */
2316 struct ionic_qos_identify_cmd {
2317 u8 opcode;
2318 u8 ver;
2319 u8 rsvd[62];
2320 };
2321
2322 /**
2323 * struct ionic_qos_identify_comp - QoS identify command completion
2324 * @status: Status of the command (enum ionic_status_code)
2325 * @ver: Version of identify returned by device
2326 * @rsvd: reserved byte(s)
2327 */
2328 struct ionic_qos_identify_comp {
2329 u8 status;
2330 u8 ver;
2331 u8 rsvd[14];
2332 };
2333
2334 #define IONIC_QOS_TC_MAX 8
2335 #define IONIC_QOS_ALL_TC 0xFF
2336 /* Capri max supported, should be renamed. */
2337 #define IONIC_QOS_CLASS_MAX 7
2338 #define IONIC_QOS_PCP_MAX 8
2339 #define IONIC_QOS_CLASS_NAME_SZ 32
2340 #define IONIC_QOS_DSCP_MAX 64
2341 #define IONIC_QOS_ALL_PCP 0xFF
2342 #define IONIC_DSCP_BLOCK_SIZE 8
2343
2344 /*
2345 * enum ionic_qos_class
2346 */
2347 enum ionic_qos_class {
2348 IONIC_QOS_CLASS_DEFAULT = 0,
2349 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
2350 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
2351 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
2352 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
2353 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
2354 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
2355 };
2356
2357 /**
2358 * enum ionic_qos_class_type - Traffic classification criteria
2359 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS
2360 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP
2361 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP
2362 */
2363 enum ionic_qos_class_type {
2364 IONIC_QOS_CLASS_TYPE_NONE = 0,
2365 IONIC_QOS_CLASS_TYPE_PCP = 1,
2366 IONIC_QOS_CLASS_TYPE_DSCP = 2,
2367 };
2368
2369 /**
2370 * enum ionic_qos_sched_type - QoS class scheduling type
2371 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority
2372 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin
2373 */
2374 enum ionic_qos_sched_type {
2375 IONIC_QOS_SCHED_TYPE_STRICT = 0,
2376 IONIC_QOS_SCHED_TYPE_DWRR = 1,
2377 };
2378
2379 /**
2380 * union ionic_qos_config - QoS configuration structure
2381 * @flags: Configuration flags
2382 * IONIC_QOS_CONFIG_F_ENABLE enable
2383 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop
2384 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
2385 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
2386 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update
2387 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type)
2388 * @class_type: QoS class type (enum ionic_qos_class_type)
2389 * @pause_type: QoS pause type (enum ionic_qos_pause_type)
2390 * @name: QoS class name
2391 * @mtu: MTU of the class
2392 * @pfc_cos: Priority-Flow Control class of service
2393 * @dwrr_weight: QoS class scheduling weight
2394 * @strict_rlmt: Rate limit for strict priority scheduling
2395 * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP)
2396 * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP)
2397 * @dot1q_pcp: Dot1q pcp value
2398 * @ndscp: Number of valid dscp values in the ip_dscp field
2399 * @ip_dscp: IP dscp values
2400 * @words: word access to struct contents
2401 */
2402 union ionic_qos_config {
2403 struct {
2404 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
2405 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
2406 /* Used to rewrite PCP or DSCP value. */
2407 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
2408 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
2409 /* Non-disruptive TC update */
2410 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
2411 u8 flags;
2412 u8 sched_type;
2413 u8 class_type;
2414 u8 pause_type;
2415 char name[IONIC_QOS_CLASS_NAME_SZ];
2416 __le32 mtu;
2417 /* flow control */
2418 u8 pfc_cos;
2419 /* scheduler */
2420 union {
2421 u8 dwrr_weight;
2422 __le64 strict_rlmt;
2423 };
2424 /* marking */
2425 /* Used to rewrite PCP or DSCP value. */
2426 union {
2427 u8 rw_dot1q_pcp;
2428 u8 rw_ip_dscp;
2429 };
2430 /* classification */
2431 union {
2432 u8 dot1q_pcp;
2433 struct {
2434 u8 ndscp;
2435 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
2436 };
2437 };
2438 };
2439 __le32 words[64];
2440 };
2441
2442 /**
2443 * union ionic_qos_identity - QoS identity structure
2444 * @version: Version of the identify structure
2445 * @type: QoS system type
2446 * @rsvd: reserved byte(s)
2447 * @config: Current configuration of classes
2448 * @words: word access to struct contents
2449 */
2450 union ionic_qos_identity {
2451 struct {
2452 u8 version;
2453 u8 type;
2454 u8 rsvd[62];
2455 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2456 };
2457 __le32 words[478];
2458 };
2459
2460 /**
2461 * struct ionic_qos_init_cmd - QoS config init command
2462 * @opcode: Opcode
2463 * @group: QoS class id
2464 * @rsvd: reserved byte(s)
2465 * @info_pa: destination address for qos info
2466 * @rsvd1: reserved byte(s)
2467 */
2468 struct ionic_qos_init_cmd {
2469 u8 opcode;
2470 u8 group;
2471 u8 rsvd[6];
2472 __le64 info_pa;
2473 u8 rsvd1[48];
2474 };
2475
2476 typedef struct ionic_admin_comp ionic_qos_init_comp;
2477
2478 /**
2479 * struct ionic_qos_reset_cmd - QoS config reset command
2480 * @opcode: Opcode
2481 * @group: QoS class id
2482 * @rsvd: reserved byte(s)
2483 */
2484 struct ionic_qos_reset_cmd {
2485 u8 opcode;
2486 u8 group;
2487 u8 rsvd[62];
2488 };
2489
2490 /**
2491 * struct ionic_qos_clear_stats_cmd - Qos config reset command
2492 * @opcode: Opcode
2493 * @group_bitmap: bitmap of groups to be cleared
2494 * @rsvd: reserved byte(s)
2495 */
2496 struct ionic_qos_clear_stats_cmd {
2497 u8 opcode;
2498 u8 group_bitmap;
2499 u8 rsvd[62];
2500 };
2501
2502 typedef struct ionic_admin_comp ionic_qos_reset_comp;
2503
2504 /**
2505 * struct ionic_fw_download_cmd - Firmware download command
2506 * @opcode: opcode
2507 * @rsvd: reserved byte(s)
2508 * @addr: dma address of the firmware buffer
2509 * @offset: offset of the firmware buffer within the full image
2510 * @length: number of valid bytes in the firmware buffer
2511 */
2512 struct ionic_fw_download_cmd {
2513 u8 opcode;
2514 u8 rsvd[3];
2515 __le32 offset;
2516 __le64 addr;
2517 __le32 length;
2518 };
2519
2520 typedef struct ionic_admin_comp ionic_fw_download_comp;
2521
2522 /**
2523 * enum ionic_fw_control_oper - FW control operations
2524 * @IONIC_FW_RESET: Reset firmware
2525 * @IONIC_FW_INSTALL: Install firmware
2526 * @IONIC_FW_ACTIVATE: Activate firmware
2527 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously
2528 * @IONIC_FW_INSTALL_STATUS: Firmware installation status
2529 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously
2530 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status
2531 * @IONIC_FW_UPDATE_CLEANUP: Clean up after an interrupted fw update
2532 */
2533 enum ionic_fw_control_oper {
2534 IONIC_FW_RESET = 0,
2535 IONIC_FW_INSTALL = 1,
2536 IONIC_FW_ACTIVATE = 2,
2537 IONIC_FW_INSTALL_ASYNC = 3,
2538 IONIC_FW_INSTALL_STATUS = 4,
2539 IONIC_FW_ACTIVATE_ASYNC = 5,
2540 IONIC_FW_ACTIVATE_STATUS = 6,
2541 IONIC_FW_UPDATE_CLEANUP = 7,
2542 };
2543
2544 /**
2545 * struct ionic_fw_control_cmd - Firmware control command
2546 * @opcode: opcode
2547 * @rsvd: reserved byte(s)
2548 * @oper: firmware control operation (enum ionic_fw_control_oper)
2549 * @slot: slot to activate
2550 * @rsvd1: reserved byte(s)
2551 */
2552 struct ionic_fw_control_cmd {
2553 u8 opcode;
2554 u8 rsvd[3];
2555 u8 oper;
2556 u8 slot;
2557 u8 rsvd1[58];
2558 };
2559
2560 /**
2561 * struct ionic_fw_control_comp - Firmware control copletion
2562 * @status: Status of the command (enum ionic_status_code)
2563 * @rsvd: reserved byte(s)
2564 * @comp_index: Index in the descriptor ring for which this is the completion
2565 * @slot: Slot where the firmware was installed
2566 * @rsvd1: reserved byte(s)
2567 * @color: Color bit
2568 */
2569 struct ionic_fw_control_comp {
2570 u8 status;
2571 u8 rsvd;
2572 __le16 comp_index;
2573 u8 slot;
2574 u8 rsvd1[10];
2575 u8 color;
2576 };
2577
2578 /******************************************************************
2579 ******************* RDMA Commands ********************************
2580 ******************************************************************/
2581
2582 /**
2583 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
2584 * @opcode: opcode
2585 * @rsvd: reserved byte(s)
2586 * @lif_index: LIF index
2587 * @rsvd2: reserved byte(s)
2588 *
2589 * There is no RDMA specific dev command completion struct. Completion uses
2590 * the common struct ionic_admin_comp. Only the status is indicated.
2591 * Nonzero status means the LIF does not support RDMA.
2592 **/
2593 struct ionic_rdma_reset_cmd {
2594 u8 opcode;
2595 u8 rsvd;
2596 __le16 lif_index;
2597 u8 rsvd2[60];
2598 };
2599
2600 /**
2601 * struct ionic_rdma_queue_cmd - Create RDMA Queue command
2602 * @opcode: opcode, 52, 53
2603 * @rsvd: reserved byte(s)
2604 * @lif_index: LIF index
2605 * @qid_ver: (qid | (RDMA version << 24))
2606 * @cid: intr, eq_id, or cq_id
2607 * @dbid: doorbell page id
2608 * @depth_log2: log base two of queue depth
2609 * @stride_log2: log base two of queue stride
2610 * @dma_addr: address of the queue memory
2611 * @rsvd2: reserved byte(s)
2612 *
2613 * The same command struct is used to create an RDMA event queue, completion
2614 * queue, or RDMA admin queue. The cid is an interrupt number for an event
2615 * queue, an event queue id for a completion queue, or a completion queue id
2616 * for an RDMA admin queue.
2617 *
2618 * The queue created via a dev command must be contiguous in dma space.
2619 *
2620 * The dev commands are intended only to be used during driver initialization,
2621 * to create queues supporting the RDMA admin queue. Other queues, and other
2622 * types of RDMA resources like memory regions, will be created and registered
2623 * via the RDMA admin queue, and will support a more complete interface
2624 * providing scatter gather lists for larger, scattered queue buffers and
2625 * memory registration.
2626 *
2627 * There is no RDMA specific dev command completion struct. Completion uses
2628 * the common struct ionic_admin_comp. Only the status is indicated.
2629 **/
2630 struct ionic_rdma_queue_cmd {
2631 u8 opcode;
2632 u8 rsvd;
2633 __le16 lif_index;
2634 __le32 qid_ver;
2635 __le32 cid;
2636 __le16 dbid;
2637 u8 depth_log2;
2638 u8 stride_log2;
2639 __le64 dma_addr;
2640 u8 rsvd2[40];
2641 };
2642
2643 /******************************************************************
2644 ******************* Notify Events ********************************
2645 ******************************************************************/
2646
2647 /**
2648 * struct ionic_notifyq_event - Generic event reporting structure
2649 * @eid: event number
2650 * @ecode: event code
2651 * @data: unspecified data about the event
2652 *
2653 * This is the generic event report struct from which the other
2654 * actual events will be formed.
2655 */
2656 struct ionic_notifyq_event {
2657 __le64 eid;
2658 __le16 ecode;
2659 u8 data[54];
2660 };
2661
2662 /**
2663 * struct ionic_link_change_event - Link change event notification
2664 * @eid: event number
2665 * @ecode: event code = IONIC_EVENT_LINK_CHANGE
2666 * @link_status: link up/down, with error bits (enum ionic_port_status)
2667 * @link_speed: speed of the network link
2668 * @rsvd: reserved byte(s)
2669 *
2670 * Sent when the network link state changes between UP and DOWN
2671 */
2672 struct ionic_link_change_event {
2673 __le64 eid;
2674 __le16 ecode;
2675 __le16 link_status;
2676 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
2677 u8 rsvd[48];
2678 };
2679
2680 /**
2681 * struct ionic_reset_event - Reset event notification
2682 * @eid: event number
2683 * @ecode: event code = IONIC_EVENT_RESET
2684 * @reset_code: reset type
2685 * @state: 0=pending, 1=complete, 2=error
2686 * @rsvd: reserved byte(s)
2687 *
2688 * Sent when the NIC or some subsystem is going to be or
2689 * has been reset.
2690 */
2691 struct ionic_reset_event {
2692 __le64 eid;
2693 __le16 ecode;
2694 u8 reset_code;
2695 u8 state;
2696 u8 rsvd[52];
2697 };
2698
2699 /**
2700 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
2701 * @eid: event number
2702 * @ecode: event code = IONIC_EVENT_HEARTBEAT
2703 * @rsvd: reserved byte(s)
2704 */
2705 struct ionic_heartbeat_event {
2706 __le64 eid;
2707 __le16 ecode;
2708 u8 rsvd[54];
2709 };
2710
2711 /**
2712 * struct ionic_log_event - Sent to notify the driver of an internal error
2713 * @eid: event number
2714 * @ecode: event code = IONIC_EVENT_LOG
2715 * @data: log data
2716 */
2717 struct ionic_log_event {
2718 __le64 eid;
2719 __le16 ecode;
2720 u8 data[54];
2721 };
2722
2723 /**
2724 * struct ionic_xcvr_event - Transceiver change event
2725 * @eid: event number
2726 * @ecode: event code = IONIC_EVENT_XCVR
2727 * @rsvd: reserved byte(s)
2728 */
2729 struct ionic_xcvr_event {
2730 __le64 eid;
2731 __le16 ecode;
2732 u8 rsvd[54];
2733 };
2734
2735 /*
2736 * struct ionic_port_stats - Port statistics structure
2737 */
2738 struct ionic_port_stats {
2739 __le64 frames_rx_ok;
2740 __le64 frames_rx_all;
2741 __le64 frames_rx_bad_fcs;
2742 __le64 frames_rx_bad_all;
2743 __le64 octets_rx_ok;
2744 __le64 octets_rx_all;
2745 __le64 frames_rx_unicast;
2746 __le64 frames_rx_multicast;
2747 __le64 frames_rx_broadcast;
2748 __le64 frames_rx_pause;
2749 __le64 frames_rx_bad_length;
2750 __le64 frames_rx_undersized;
2751 __le64 frames_rx_oversized;
2752 __le64 frames_rx_fragments;
2753 __le64 frames_rx_jabber;
2754 __le64 frames_rx_pripause;
2755 __le64 frames_rx_stomped_crc;
2756 __le64 frames_rx_too_long;
2757 __le64 frames_rx_vlan_good;
2758 __le64 frames_rx_dropped;
2759 __le64 frames_rx_less_than_64b;
2760 __le64 frames_rx_64b;
2761 __le64 frames_rx_65b_127b;
2762 __le64 frames_rx_128b_255b;
2763 __le64 frames_rx_256b_511b;
2764 __le64 frames_rx_512b_1023b;
2765 __le64 frames_rx_1024b_1518b;
2766 __le64 frames_rx_1519b_2047b;
2767 __le64 frames_rx_2048b_4095b;
2768 __le64 frames_rx_4096b_8191b;
2769 __le64 frames_rx_8192b_9215b;
2770 __le64 frames_rx_other;
2771 __le64 frames_tx_ok;
2772 __le64 frames_tx_all;
2773 __le64 frames_tx_bad;
2774 __le64 octets_tx_ok;
2775 __le64 octets_tx_total;
2776 __le64 frames_tx_unicast;
2777 __le64 frames_tx_multicast;
2778 __le64 frames_tx_broadcast;
2779 __le64 frames_tx_pause;
2780 __le64 frames_tx_pripause;
2781 __le64 frames_tx_vlan;
2782 __le64 frames_tx_less_than_64b;
2783 __le64 frames_tx_64b;
2784 __le64 frames_tx_65b_127b;
2785 __le64 frames_tx_128b_255b;
2786 __le64 frames_tx_256b_511b;
2787 __le64 frames_tx_512b_1023b;
2788 __le64 frames_tx_1024b_1518b;
2789 __le64 frames_tx_1519b_2047b;
2790 __le64 frames_tx_2048b_4095b;
2791 __le64 frames_tx_4096b_8191b;
2792 __le64 frames_tx_8192b_9215b;
2793 __le64 frames_tx_other;
2794 __le64 frames_tx_pri_0;
2795 __le64 frames_tx_pri_1;
2796 __le64 frames_tx_pri_2;
2797 __le64 frames_tx_pri_3;
2798 __le64 frames_tx_pri_4;
2799 __le64 frames_tx_pri_5;
2800 __le64 frames_tx_pri_6;
2801 __le64 frames_tx_pri_7;
2802 __le64 frames_rx_pri_0;
2803 __le64 frames_rx_pri_1;
2804 __le64 frames_rx_pri_2;
2805 __le64 frames_rx_pri_3;
2806 __le64 frames_rx_pri_4;
2807 __le64 frames_rx_pri_5;
2808 __le64 frames_rx_pri_6;
2809 __le64 frames_rx_pri_7;
2810 __le64 tx_pripause_0_1us_count;
2811 __le64 tx_pripause_1_1us_count;
2812 __le64 tx_pripause_2_1us_count;
2813 __le64 tx_pripause_3_1us_count;
2814 __le64 tx_pripause_4_1us_count;
2815 __le64 tx_pripause_5_1us_count;
2816 __le64 tx_pripause_6_1us_count;
2817 __le64 tx_pripause_7_1us_count;
2818 __le64 rx_pripause_0_1us_count;
2819 __le64 rx_pripause_1_1us_count;
2820 __le64 rx_pripause_2_1us_count;
2821 __le64 rx_pripause_3_1us_count;
2822 __le64 rx_pripause_4_1us_count;
2823 __le64 rx_pripause_5_1us_count;
2824 __le64 rx_pripause_6_1us_count;
2825 __le64 rx_pripause_7_1us_count;
2826 __le64 rx_pause_1us_count;
2827 __le64 frames_tx_truncated;
2828 };
2829
2830 struct ionic_mgmt_port_stats {
2831 __le64 frames_rx_ok;
2832 __le64 frames_rx_all;
2833 __le64 frames_rx_bad_fcs;
2834 __le64 frames_rx_bad_all;
2835 __le64 octets_rx_ok;
2836 __le64 octets_rx_all;
2837 __le64 frames_rx_unicast;
2838 __le64 frames_rx_multicast;
2839 __le64 frames_rx_broadcast;
2840 __le64 frames_rx_pause;
2841 __le64 frames_rx_bad_length;
2842 __le64 frames_rx_undersized;
2843 __le64 frames_rx_oversized;
2844 __le64 frames_rx_fragments;
2845 __le64 frames_rx_jabber;
2846 __le64 frames_rx_64b;
2847 __le64 frames_rx_65b_127b;
2848 __le64 frames_rx_128b_255b;
2849 __le64 frames_rx_256b_511b;
2850 __le64 frames_rx_512b_1023b;
2851 __le64 frames_rx_1024b_1518b;
2852 __le64 frames_rx_gt_1518b;
2853 __le64 frames_rx_fifo_full;
2854 __le64 frames_tx_ok;
2855 __le64 frames_tx_all;
2856 __le64 frames_tx_bad;
2857 __le64 octets_tx_ok;
2858 __le64 octets_tx_total;
2859 __le64 frames_tx_unicast;
2860 __le64 frames_tx_multicast;
2861 __le64 frames_tx_broadcast;
2862 __le64 frames_tx_pause;
2863 };
2864
2865 struct ionic_port_extra_stats {
2866 __le64 rsfec_correctable_blocks;
2867 __le64 rsfec_uncorrectable_blocks;
2868 __le64 fec_corrected_bits_total;
2869 __le64 rx_bits_phy;
2870 __le64 fec_codeword_error_bin[16];
2871 };
2872
2873 /**
2874 * struct ionic_port_identity - port identity structure
2875 * @version: identity structure version
2876 * @type: type of port (enum ionic_port_type)
2877 * @num_lanes: number of lanes for the port
2878 * @autoneg: autoneg supported
2879 * @min_frame_size: minimum frame size supported
2880 * @max_frame_size: maximum frame size supported
2881 * @fec_type: supported fec types
2882 * @pause_type: supported pause types
2883 * @loopback_mode: supported loopback mode
2884 * @speeds: supported speeds
2885 * @rsvd2: reserved byte(s)
2886 * @config: current port configuration
2887 * @words: word access to struct contents
2888 */
2889 union ionic_port_identity {
2890 struct {
2891 u8 version;
2892 u8 type;
2893 u8 num_lanes;
2894 u8 autoneg;
2895 __le32 min_frame_size;
2896 __le32 max_frame_size;
2897 u8 fec_type[4];
2898 u8 pause_type[2];
2899 u8 loopback_mode[2];
2900 __le32 speeds[16];
2901 u8 rsvd2[44];
2902 union ionic_port_config config;
2903 };
2904 __le32 words[478];
2905 };
2906
2907 /**
2908 * struct ionic_port_info - port info structure
2909 * @config: Port configuration data
2910 * @status: Port status data
2911 * @stats: Port statistics data
2912 * @mgmt_stats: Port management statistics data
2913 * @sprom_epage: Extended Transceiver sprom
2914 * @sprom_page1: Extended Transceiver sprom, page 1
2915 * @sprom_page2: Extended Transceiver sprom, page 2
2916 * @sprom_page17: Extended Transceiver sprom, page 17
2917 * @rsvd: reserved byte(s)
2918 * @extra_stats: Extra port statistics data
2919 */
2920 struct ionic_port_info {
2921 union ionic_port_config config;
2922 struct ionic_port_status status;
2923 union {
2924 struct ionic_port_stats stats;
2925 struct ionic_mgmt_port_stats mgmt_stats;
2926 };
2927 union {
2928 u8 sprom_epage[384];
2929 struct {
2930 u8 sprom_page1[128];
2931 u8 sprom_page2[128];
2932 u8 sprom_page17[128];
2933 };
2934 };
2935 u8 rsvd[376];
2936 struct ionic_port_extra_stats extra_stats;
2937 };
2938
2939 /*
2940 * struct ionic_lif_stats - LIF statistics structure
2941 */
2942 struct ionic_lif_stats {
2943 /* RX */
2944 __le64 rx_ucast_bytes;
2945 __le64 rx_ucast_packets;
2946 __le64 rx_mcast_bytes;
2947 __le64 rx_mcast_packets;
2948 __le64 rx_bcast_bytes;
2949 __le64 rx_bcast_packets;
2950 __le64 rsvd0;
2951 __le64 rsvd1;
2952 /* RX drops */
2953 __le64 rx_ucast_drop_bytes;
2954 __le64 rx_ucast_drop_packets;
2955 __le64 rx_mcast_drop_bytes;
2956 __le64 rx_mcast_drop_packets;
2957 __le64 rx_bcast_drop_bytes;
2958 __le64 rx_bcast_drop_packets;
2959 __le64 rx_dma_error;
2960 __le64 rsvd2;
2961 /* TX */
2962 __le64 tx_ucast_bytes;
2963 __le64 tx_ucast_packets;
2964 __le64 tx_mcast_bytes;
2965 __le64 tx_mcast_packets;
2966 __le64 tx_bcast_bytes;
2967 __le64 tx_bcast_packets;
2968 __le64 rsvd3;
2969 __le64 rsvd4;
2970 /* TX drops */
2971 __le64 tx_ucast_drop_bytes;
2972 __le64 tx_ucast_drop_packets;
2973 __le64 tx_mcast_drop_bytes;
2974 __le64 tx_mcast_drop_packets;
2975 __le64 tx_bcast_drop_bytes;
2976 __le64 tx_bcast_drop_packets;
2977 __le64 tx_dma_error;
2978 __le64 rsvd5;
2979 /* Rx Queue/Ring drops */
2980 __le64 rx_queue_disabled;
2981 __le64 rx_queue_empty;
2982 __le64 rx_queue_error;
2983 __le64 rx_desc_fetch_error;
2984 __le64 rx_desc_data_error;
2985 __le64 rsvd6;
2986 __le64 rsvd7;
2987 __le64 rsvd8;
2988 /* Tx Queue/Ring drops */
2989 __le64 tx_queue_disabled;
2990 __le64 tx_queue_error;
2991 __le64 tx_desc_fetch_error;
2992 __le64 tx_desc_data_error;
2993 __le64 tx_queue_empty;
2994 __le64 rsvd10;
2995 __le64 rsvd11;
2996 __le64 rsvd12;
2997
2998 /* RDMA/ROCE TX */
2999 __le64 tx_rdma_ucast_bytes;
3000 __le64 tx_rdma_ucast_packets;
3001 __le64 tx_rdma_mcast_bytes;
3002 __le64 tx_rdma_mcast_packets;
3003 __le64 tx_rdma_cnp_packets;
3004 __le64 rsvd13;
3005 __le64 rsvd14;
3006 __le64 rsvd15;
3007
3008 /* RDMA/ROCE RX */
3009 __le64 rx_rdma_ucast_bytes;
3010 __le64 rx_rdma_ucast_packets;
3011 __le64 rx_rdma_mcast_bytes;
3012 __le64 rx_rdma_mcast_packets;
3013 __le64 rx_rdma_cnp_packets;
3014 __le64 rx_rdma_ecn_packets;
3015 __le64 rsvd16;
3016 __le64 rsvd17;
3017
3018 __le64 rsvd18;
3019 __le64 rsvd19;
3020 __le64 rsvd20;
3021 __le64 rsvd21;
3022 __le64 rsvd22;
3023 __le64 rsvd23;
3024 __le64 rsvd24;
3025 __le64 rsvd25;
3026
3027 __le64 rsvd26;
3028 __le64 rsvd27;
3029 __le64 rsvd28;
3030 __le64 rsvd29;
3031 __le64 rsvd30;
3032 __le64 rsvd31;
3033 __le64 rsvd32;
3034 __le64 rsvd33;
3035
3036 __le64 rsvd34;
3037 __le64 rsvd35;
3038 __le64 rsvd36;
3039 __le64 rsvd37;
3040 __le64 rsvd38;
3041 __le64 rsvd39;
3042 __le64 rsvd40;
3043 __le64 rsvd41;
3044
3045 __le64 rsvd42;
3046 __le64 rsvd43;
3047 __le64 rsvd44;
3048 __le64 rsvd45;
3049 __le64 rsvd46;
3050 __le64 rsvd47;
3051 __le64 rsvd48;
3052 __le64 rsvd49;
3053
3054 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
3055 __le64 rdma_req_rx_pkt_seq_err;
3056 __le64 rdma_req_rx_rnr_retry_err;
3057 __le64 rdma_req_rx_remote_access_err;
3058 __le64 rdma_req_rx_remote_inv_req_err;
3059 __le64 rdma_req_rx_remote_oper_err;
3060 __le64 rdma_req_rx_implied_nak_seq_err;
3061 __le64 rdma_req_rx_cqe_err;
3062 __le64 rdma_req_rx_cqe_flush_err;
3063
3064 __le64 rdma_req_rx_dup_responses;
3065 __le64 rdma_req_rx_invalid_packets;
3066 __le64 rdma_req_tx_local_access_err;
3067 __le64 rdma_req_tx_local_oper_err;
3068 __le64 rdma_req_tx_memory_mgmt_err;
3069 __le64 rsvd52;
3070 __le64 rsvd53;
3071 __le64 rsvd54;
3072
3073 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
3074 __le64 rdma_resp_rx_dup_requests;
3075 __le64 rdma_resp_rx_out_of_buffer;
3076 __le64 rdma_resp_rx_out_of_seq_pkts;
3077 __le64 rdma_resp_rx_cqe_err;
3078 __le64 rdma_resp_rx_cqe_flush_err;
3079 __le64 rdma_resp_rx_local_len_err;
3080 __le64 rdma_resp_rx_inv_request_err;
3081 __le64 rdma_resp_rx_local_qp_oper_err;
3082
3083 __le64 rdma_resp_rx_out_of_atomic_resource;
3084 __le64 rdma_resp_tx_pkt_seq_err;
3085 __le64 rdma_resp_tx_remote_inv_req_err;
3086 __le64 rdma_resp_tx_remote_access_err;
3087 __le64 rdma_resp_tx_remote_oper_err;
3088 __le64 rdma_resp_tx_rnr_retry_err;
3089 __le64 rsvd57;
3090 __le64 rsvd58;
3091 };
3092
3093 /**
3094 * struct ionic_lif_info - LIF info structure
3095 * @config: LIF configuration structure
3096 * @status: LIF status structure
3097 * @stats: LIF statistics structure
3098 */
3099 struct ionic_lif_info {
3100 union ionic_lif_config config;
3101 struct ionic_lif_status status;
3102 struct ionic_lif_stats stats;
3103 };
3104
3105 union ionic_dev_cmd {
3106 u32 words[16];
3107 struct ionic_admin_cmd cmd;
3108 struct ionic_nop_cmd nop;
3109
3110 struct ionic_dev_identify_cmd identify;
3111 struct ionic_dev_init_cmd init;
3112 struct ionic_dev_reset_cmd reset;
3113 struct ionic_dev_getattr_cmd getattr;
3114 struct ionic_dev_setattr_cmd setattr;
3115
3116 struct ionic_port_identify_cmd port_identify;
3117 struct ionic_port_init_cmd port_init;
3118 struct ionic_port_reset_cmd port_reset;
3119 struct ionic_port_getattr_cmd port_getattr;
3120 struct ionic_port_setattr_cmd port_setattr;
3121
3122 struct ionic_vf_setattr_cmd vf_setattr;
3123 struct ionic_vf_getattr_cmd vf_getattr;
3124 struct ionic_vf_ctrl_cmd vf_ctrl;
3125
3126 struct ionic_discover_cmb_cmd discover_cmb;
3127
3128 struct ionic_lif_identify_cmd lif_identify;
3129 struct ionic_lif_init_cmd lif_init;
3130 struct ionic_lif_reset_cmd lif_reset;
3131
3132 struct ionic_qos_identify_cmd qos_identify;
3133 struct ionic_qos_init_cmd qos_init;
3134 struct ionic_qos_reset_cmd qos_reset;
3135 struct ionic_qos_clear_stats_cmd qos_clear_stats;
3136
3137 struct ionic_q_identify_cmd q_identify;
3138 struct ionic_q_init_cmd q_init;
3139 struct ionic_q_control_cmd q_control;
3140
3141 struct ionic_fw_download_cmd fw_download;
3142 struct ionic_fw_control_cmd fw_control;
3143 };
3144
3145 union ionic_dev_cmd_comp {
3146 u32 words[4];
3147 u8 status;
3148 struct ionic_admin_comp comp;
3149 struct ionic_nop_comp nop;
3150
3151 struct ionic_dev_identify_comp identify;
3152 struct ionic_dev_init_comp init;
3153 struct ionic_dev_reset_comp reset;
3154 struct ionic_dev_getattr_comp getattr;
3155 struct ionic_dev_setattr_comp setattr;
3156
3157 struct ionic_port_identify_comp port_identify;
3158 struct ionic_port_init_comp port_init;
3159 struct ionic_port_reset_comp port_reset;
3160 struct ionic_port_getattr_comp port_getattr;
3161 struct ionic_port_setattr_comp port_setattr;
3162
3163 struct ionic_vf_setattr_comp vf_setattr;
3164 struct ionic_vf_getattr_comp vf_getattr;
3165 struct ionic_vf_ctrl_comp vf_ctrl;
3166
3167 struct ionic_discover_cmb_comp discover_cmb;
3168
3169 struct ionic_lif_identify_comp lif_identify;
3170 struct ionic_lif_init_comp lif_init;
3171 ionic_lif_reset_comp lif_reset;
3172
3173 struct ionic_qos_identify_comp qos_identify;
3174 ionic_qos_init_comp qos_init;
3175 ionic_qos_reset_comp qos_reset;
3176
3177 struct ionic_q_identify_comp q_identify;
3178 struct ionic_q_init_comp q_init;
3179
3180 ionic_fw_download_comp fw_download;
3181 struct ionic_fw_control_comp fw_control;
3182 };
3183
3184 /**
3185 * struct ionic_hwstamp_regs - Hardware current timestamp registers
3186 * @tick_low: Low 32 bits of hardware timestamp
3187 * @tick_high: High 32 bits of hardware timestamp
3188 */
3189 struct ionic_hwstamp_regs {
3190 u32 tick_low;
3191 u32 tick_high;
3192 };
3193
3194 /**
3195 * union ionic_dev_info_regs - Device info register format (read-only)
3196 * @signature: Signature value of 0x44455649 ('DEVI')
3197 * @version: Current version of info
3198 * @asic_type: Asic type
3199 * @asic_rev: Asic revision
3200 * @fw_status: Firmware status
3201 * bit 0 - 1 = fw running
3202 * bit 4-7 - 4 bit generation number, changes on fw restart
3203 * @fw_heartbeat: Firmware heartbeat counter
3204 * @serial_num: Serial number
3205 * @rsvd_pad1024: reserved byte(s)
3206 * @fw_version: Firmware version
3207 * @hwstamp: Hardware current timestamp registers
3208 * @words: word access to struct contents
3209 */
3210 union ionic_dev_info_regs {
3211 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
3212 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
3213 struct {
3214 u32 signature;
3215 u8 version;
3216 u8 asic_type;
3217 u8 asic_rev;
3218 #define IONIC_FW_STS_F_RUNNING 0x01
3219 #define IONIC_FW_STS_F_GENERATION 0xF0
3220 u8 fw_status;
3221 u32 fw_heartbeat;
3222 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
3223 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
3224 u8 rsvd_pad1024[948];
3225 struct ionic_hwstamp_regs hwstamp;
3226 };
3227 u32 words[512];
3228 };
3229
3230 /**
3231 * union ionic_dev_cmd_regs - Device command register format (read-write)
3232 * @doorbell: Device Cmd Doorbell, write-only
3233 * Write a 1 to signal device to process cmd,
3234 * poll done for completion.
3235 * @done: Done indicator, bit 0 == 1 when command is complete
3236 * @cmd: Opcode-specific command bytes
3237 * @comp: Opcode-specific response bytes
3238 * @rsvd: reserved byte(s)
3239 * @data: Opcode-specific side-data
3240 * @words: word access to struct contents
3241 */
3242 union ionic_dev_cmd_regs {
3243 struct {
3244 u32 doorbell;
3245 u32 done;
3246 union ionic_dev_cmd cmd;
3247 union ionic_dev_cmd_comp comp;
3248 u8 rsvd[48];
3249 u32 data[478];
3250 } __packed;
3251 u32 words[512];
3252 };
3253
3254 /**
3255 * union ionic_dev_regs - Device register format for bar 0 page 0
3256 * @info: Device info registers
3257 * @devcmd: Device command registers
3258 * @words: word access to struct contents
3259 */
3260 union ionic_dev_regs {
3261 struct {
3262 union ionic_dev_info_regs info;
3263 union ionic_dev_cmd_regs devcmd;
3264 } __packed;
3265 __le32 words[1024];
3266 };
3267
3268 union ionic_adminq_cmd {
3269 struct ionic_admin_cmd cmd;
3270 struct ionic_nop_cmd nop;
3271 struct ionic_q_identify_cmd q_identify;
3272 struct ionic_q_init_cmd q_init;
3273 struct ionic_q_control_cmd q_control;
3274 struct ionic_lif_setattr_cmd lif_setattr;
3275 struct ionic_lif_getattr_cmd lif_getattr;
3276 struct ionic_lif_setphc_cmd lif_setphc;
3277 struct ionic_rx_mode_set_cmd rx_mode_set;
3278 struct ionic_rx_filter_add_cmd rx_filter_add;
3279 struct ionic_rx_filter_del_cmd rx_filter_del;
3280 struct ionic_rdma_reset_cmd rdma_reset;
3281 struct ionic_rdma_queue_cmd rdma_queue;
3282 struct ionic_fw_download_cmd fw_download;
3283 struct ionic_fw_control_cmd fw_control;
3284 };
3285
3286 union ionic_adminq_comp {
3287 struct ionic_admin_comp comp;
3288 struct ionic_nop_comp nop;
3289 struct ionic_q_identify_comp q_identify;
3290 struct ionic_q_init_comp q_init;
3291 struct ionic_lif_setattr_comp lif_setattr;
3292 struct ionic_lif_getattr_comp lif_getattr;
3293 struct ionic_admin_comp lif_setphc;
3294 struct ionic_rx_filter_add_comp rx_filter_add;
3295 struct ionic_fw_control_comp fw_control;
3296 };
3297
3298 #define IONIC_BARS_MAX 6
3299 #define IONIC_PCI_BAR_DBELL 1
3300 #define IONIC_PCI_BAR_CMB 2
3301
3302 #define IONIC_BAR0_SIZE 0x8000
3303 #define IONIC_BAR2_SIZE 0x800000
3304
3305 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
3306 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
3307 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
3308 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
3309 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
3310
3311 /* BAR2 */
3312 #define IONIC_BAR2_CMB_ENTRY_SIZE 0x800000
3313 #define IONIC_DEV_CMD_DONE 0x00000001
3314
3315 #define IONIC_ASIC_TYPE_NONE 0
3316 #define IONIC_ASIC_TYPE_CAPRI 1
3317 #define IONIC_ASIC_TYPE_ELBA 2
3318 #define IONIC_ASIC_TYPE_GIGLIO 3
3319 #define IONIC_ASIC_TYPE_SALINA 4
3320
3321 /**
3322 * struct ionic_doorbell - Doorbell register layout
3323 * @p_index: Producer index
3324 * @ring: Selects the specific ring of the queue to update
3325 * Type-specific meaning:
3326 * ring=0: Default producer/consumer queue
3327 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
3328 * send events to EQs when armed. EQs send
3329 * interrupts when armed.
3330 * @qid_lo: Queue destination for the producer index and flags (low bits)
3331 * @qid_hi: Queue destination for the producer index and flags (high bits)
3332 * @rsvd2: reserved byte(s)
3333 */
3334 struct ionic_doorbell {
3335 __le16 p_index;
3336 u8 ring;
3337 u8 qid_lo;
3338 __le16 qid_hi;
3339 u16 rsvd2;
3340 };
3341
3342 struct ionic_intr_status {
3343 u32 status[2];
3344 };
3345
3346 struct ionic_notifyq_cmd {
3347 __le32 data; /* Not used but needed for qcq structure */
3348 };
3349
3350 union ionic_notifyq_comp {
3351 struct ionic_notifyq_event event;
3352 struct ionic_link_change_event link_change;
3353 struct ionic_reset_event reset;
3354 struct ionic_heartbeat_event heartbeat;
3355 struct ionic_log_event log;
3356 };
3357
3358 /* Deprecate */
3359 struct ionic_identity {
3360 union ionic_drv_identity drv;
3361 union ionic_dev_identity dev;
3362 union ionic_lif_identity lif;
3363 union ionic_port_identity port;
3364 union ionic_qos_identity qos;
3365 union ionic_q_identity txq;
3366 union ionic_discover_cmb_identity cmb_layout;
3367 };
3368
3369 #endif /* _IONIC_IF_H_ */
3370