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Searched refs:iobase (Results 1 – 25 of 136) sorted by relevance

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/linux/drivers/rtc/
H A Drtc-asm9260.c108 void __iomem *iobase; member
120 isr = ioread32(priv->iobase + HW_CIIR); in asm9260_rtc_irq()
126 iowrite32(0, priv->iobase + HW_CIIR); in asm9260_rtc_irq()
141 ctime0 = ioread32(priv->iobase + HW_CTIME0); in asm9260_rtc_read_time()
142 ctime1 = ioread32(priv->iobase + HW_CTIME1); in asm9260_rtc_read_time()
143 ctime2 = ioread32(priv->iobase + HW_CTIME2); in asm9260_rtc_read_time()
145 if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) { in asm9260_rtc_read_time()
150 ctime0 = ioread32(priv->iobase + HW_CTIME0); in asm9260_rtc_read_time()
151 ctime1 = ioread32(priv->iobase + HW_CTIME1); in asm9260_rtc_read_time()
152 ctime2 = ioread32(priv->iobase + HW_CTIME2); in asm9260_rtc_read_time()
[all …]
/linux/drivers/irqchip/
H A Dirq-sa11x0.c28 static void __iomem *iobase; variable
38 reg = readl_relaxed(iobase + ICMR); in sa1100_mask_irq()
40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
47 reg = readl_relaxed(iobase + ICMR); in sa1100_unmask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
93 st->icmr = readl_relaxed(iobase + ICMR); in sa1100irq_suspend()
94 st->iclr = readl_relaxed(iobase + ICLR); in sa1100irq_suspend()
95 st->iccr = readl_relaxed(iobase + ICCR); in sa1100irq_suspend()
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend()
110 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume()
[all …]
/linux/drivers/comedi/drivers/
H A Dni_daq_700.c84 outb(s->state & 0xff, dev->iobase + DIO_W); in daq700_dio_insn_bits()
88 val |= inb(dev->iobase + DIO_R) << 8; in daq700_dio_insn_bits()
119 status = inb(dev->iobase + STA_R2); in daq700_ai_eoc()
122 status = inb(dev->iobase + STA_R1); in daq700_ai_eoc()
148 outb(r3_bits | (range & 0x03), dev->iobase + CMD_R3); in daq700_ai_rinsn()
152 outb(chan | 0x80, dev->iobase + CMD_R1); in daq700_ai_rinsn()
159 outb(0x00, dev->iobase + CMD_R2); /* enable ADC conversions */ in daq700_ai_rinsn()
160 outb(0x30, dev->iobase + CMO_R); /* mode 0 out0 L, from H */ in daq700_ai_rinsn()
161 outb(0x00, dev->iobase + ADCLEAR_R); /* clear the ADC FIFO */ in daq700_ai_rinsn()
163 inw(dev->iobase + ADFIFO_R); in daq700_ai_rinsn()
[all …]
H A Ddmm32at.c166 outb(DMM32AT_FIFO_CTRL_FIFORST, dev->iobase + DMM32AT_FIFO_CTRL_REG); in dmm32at_ai_set_chanspec()
170 dev->iobase + DMM32AT_FIFO_CTRL_REG); in dmm32at_ai_set_chanspec()
172 outb(chan, dev->iobase + DMM32AT_AI_LO_CHAN_REG); in dmm32at_ai_set_chanspec()
173 outb(last_chan, dev->iobase + DMM32AT_AI_HI_CHAN_REG); in dmm32at_ai_set_chanspec()
174 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AI_CFG_REG); in dmm32at_ai_set_chanspec()
182 val = inb(dev->iobase + DMM32AT_AI_LSB_REG); in dmm32at_ai_get_sample()
183 val |= (inb(dev->iobase + DMM32AT_AI_MSB_REG) << 8); in dmm32at_ai_get_sample()
196 status = inb(dev->iobase + context); in dmm32at_ai_status()
219 outb(0xff, dev->iobase + DMM32AT_AI_START_CONV_REG); in dmm32at_ai_insn_read()
344 outb(0, dev->iobase + DMM32AT_CTRDIO_CFG_REG); in dmm32at_setaitimer()
[all …]
H A Ddt2817.c65 outb(oe, dev->iobase + DT2817_CR); in dt2817_dio_insn_config()
75 unsigned long iobase = dev->iobase + DT2817_DATA; in dt2817_dio_insn_bits() local
82 outb(s->state & 0xff, iobase + 0); in dt2817_dio_insn_bits()
84 outb((s->state >> 8) & 0xff, iobase + 1); in dt2817_dio_insn_bits()
86 outb((s->state >> 16) & 0xff, iobase + 2); in dt2817_dio_insn_bits()
88 outb((s->state >> 24) & 0xff, iobase + 3); in dt2817_dio_insn_bits()
91 val = inb(iobase + 0); in dt2817_dio_insn_bits()
92 val |= (inb(iobase + 1) << 8); in dt2817_dio_insn_bits()
93 val |= (inb(iobase + 2) << 16); in dt2817_dio_insn_bits()
94 val |= (inb(iobase + 3) << 24); in dt2817_dio_insn_bits()
[all …]
H A Daddi_watchdog.c18 unsigned long iobase; member
44 outl(reload, spriv->iobase + ADDI_TCW_RELOAD_REG); in addi_watchdog_insn_config()
57 outl(spriv->wdog_ctrl, spriv->iobase + ADDI_TCW_CTRL_REG); in addi_watchdog_insn_config()
71 data[i] = inl(spriv->iobase + ADDI_TCW_STATUS_REG); in addi_watchdog_insn_read()
92 spriv->iobase + ADDI_TCW_CTRL_REG); in addi_watchdog_insn_write()
98 void addi_watchdog_reset(unsigned long iobase) in addi_watchdog_reset() argument
100 outl(0x0, iobase + ADDI_TCW_CTRL_REG); in addi_watchdog_reset()
101 outl(0x0, iobase + ADDI_TCW_RELOAD_REG); in addi_watchdog_reset()
105 int addi_watchdog_init(struct comedi_subdevice *s, unsigned long iobase) in addi_watchdog_init() argument
113 spriv->iobase = iobase; in addi_watchdog_init()
H A Dmultiq3.c82 dev->iobase + MULTIQ3_CTRL_REG); in multiq3_set_ctrl()
92 status = inw(dev->iobase + MULTIQ3_STATUS_REG); in multiq3_ai_status()
116 outw(0, dev->iobase + MULTIQ3_AI_CONV_REG); in multiq3_ai_insn_read()
124 val = inb(dev->iobase + MULTIQ3_AI_REG) << 8; in multiq3_ai_insn_read()
125 val |= inb(dev->iobase + MULTIQ3_AI_REG); in multiq3_ai_insn_read()
148 outw(val, dev->iobase + MULTIQ3_AO_REG); in multiq3_ao_insn_write()
160 data[1] = inw(dev->iobase + MULTIQ3_DI_REG); in multiq3_di_insn_bits()
171 outw(s->state, dev->iobase + MULTIQ3_DO_REG); in multiq3_do_insn_bits()
193 outb(MULTIQ3_BP_RESET, dev->iobase + MULTIQ3_ENC_CTRL_REG); in multiq3_encoder_insn_read()
196 outb(MULTIQ3_TRSFRCNTR_OL, dev->iobase + MULTIQ3_ENC_CTRL_REG); in multiq3_encoder_insn_read()
[all …]
H A Ddas08.c161 status = inb(dev->iobase + DAS08_STATUS_REG); in das08_ai_eoc()
182 inb(dev->iobase + DAS08_AI_LSB_REG); in das08_ai_insn_read()
183 inb(dev->iobase + DAS08_AI_MSB_REG); in das08_ai_insn_read()
190 outb(devpriv->do_mux_bits, dev->iobase + DAS08_CONTROL_REG); in das08_ai_insn_read()
197 dev->iobase + DAS08_GAIN_REG); in das08_ai_insn_read()
203 if (inb(dev->iobase + DAS08_AI_MSB_REG) & 0x80) in das08_ai_insn_read()
207 outb_p(0, dev->iobase + DAS08_AI_TRIG_REG); in das08_ai_insn_read()
213 msb = inb(dev->iobase + DAS08_AI_MSB_REG); in das08_ai_insn_read()
214 lsb = inb(dev->iobase + DAS08_AI_LSB_REG); in das08_ai_insn_read()
254 data[1] = DAS08_STATUS_DI(inb(dev->iobase + DAS08_STATUS_REG)); in das08_di_insn_bits()
[all …]
H A Dpcl724.c98 unsigned long iobase) in pcl724_8255mapped_io() argument
100 int movport = I8255_SIZE * (iobase >> 12); in pcl724_8255mapped_io()
102 iobase &= 0x0fff; in pcl724_8255mapped_io()
104 outb(port + movport, iobase); in pcl724_8255mapped_io()
106 outb(data, iobase + 1); in pcl724_8255mapped_io()
109 return inb(iobase + 1); in pcl724_8255mapped_io()
117 unsigned long iobase; in pcl724_attach() local
146 iobase = dev->iobase + (i * 0x1000); in pcl724_attach()
148 iobase); in pcl724_attach()
H A Dcomedi_parport.c77 outb(s->state, dev->iobase + PARPORT_DATA_REG); in parport_data_reg_insn_bits()
79 data[1] = inb(dev->iobase + PARPORT_DATA_REG); in parport_data_reg_insn_bits()
96 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); in parport_data_reg_insn_config()
101 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); in parport_data_reg_insn_config()
111 data[1] = inb(dev->iobase + PARPORT_STATUS_REG) >> 3; in parport_status_reg_insn_bits()
124 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); in parport_ctrl_reg_insn_bits()
127 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); in parport_ctrl_reg_insn_bits()
188 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); in parport_intr_cmd()
190 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); in parport_intr_cmd()
200 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); in parport_intr_cancel()
[all …]
H A Dii_pci20kc.c148 void __iomem *iobase = ii20k_module_iobase(dev, s); in ii20k_ao_insn_write() local
160 writeb(val & 0xff, iobase + II20K_AO_LSB_REG(chan)); in ii20k_ao_insn_write()
161 writeb((val >> 8) & 0xff, iobase + II20K_AO_MSB_REG(chan)); in ii20k_ao_insn_write()
162 writeb(0x00, iobase + II20K_AO_STRB_REG(chan)); in ii20k_ao_insn_write()
173 void __iomem *iobase = ii20k_module_iobase(dev, s); in ii20k_ai_eoc() local
176 status = readb(iobase + II20K_AI_STATUS_REG); in ii20k_ai_eoc()
186 void __iomem *iobase = ii20k_module_iobase(dev, s); in ii20k_ai_setup() local
192 writeb(II20K_AI_CONF_ENA, iobase + II20K_AI_CONF_REG); in ii20k_ai_setup()
195 writeb(0, iobase + II20K_AI_STATUS_CMD_REG); in ii20k_ai_setup()
199 writeb(val, iobase + II20K_AI_OPT_REG); in ii20k_ai_setup()
[all …]
H A Ds526.c179 outw((val >> 16) & 0xffff, dev->iobase + S526_GPCT_MSB_REG(chan)); in s526_gpct_write()
180 outw(val & 0xffff, dev->iobase + S526_GPCT_LSB_REG(chan)); in s526_gpct_write()
189 val = inw(dev->iobase + S526_GPCT_LSB_REG(chan)) & 0xffff; in s526_gpct_read()
190 val |= (inw(dev->iobase + S526_GPCT_MSB_REG(chan)) & 0xff) << 16; in s526_gpct_read()
235 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
242 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
276 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
284 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
291 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
294 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
[all …]
H A Dni_at_ao.c121 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_select_reg_group()
141 dev->iobase + ATAO_AO_REG(chan)); in atao_ao_insn_write()
157 outw(s->state, dev->iobase + ATAO_DIO_REG); in atao_dio_insn_bits()
159 data[1] = inw(dev->iobase + ATAO_DIO_REG); in atao_dio_insn_bits()
192 outw(devpriv->cfg3, dev->iobase + ATAO_CFG3_REG); in atao_dio_insn_config()
248 outw(bits, dev->iobase + ATAO_CFG2_REG); in atao_calib_insn_write()
250 dev->iobase + ATAO_CFG2_REG); in atao_calib_insn_write()
254 outw(ATAO_CFG2_CALLD(chan), dev->iobase + ATAO_CFG2_REG); in atao_calib_insn_write()
255 outw(ATAO_CFG2_CALLD_NOP, dev->iobase + ATAO_CFG2_REG); in atao_calib_insn_write()
270 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1_REG); in atao_reset()
[all …]
H A Dfl512.c58 outb(chan, dev->iobase + FL512_AI_MUX_REG); in fl512_ai_insn_read()
61 outb(0, dev->iobase + FL512_AI_START_CONV_REG); in fl512_ai_insn_read()
66 val = inb(dev->iobase + FL512_AI_LSB_REG); in fl512_ai_insn_read()
67 val |= (inb(dev->iobase + FL512_AI_MSB_REG) << 8); in fl512_ai_insn_read()
89 outb(val & 0x0ff, dev->iobase + FL512_AO_DATA_REG(chan)); in fl512_ao_insn_write()
90 outb((val >> 8) & 0xf, dev->iobase + FL512_AO_DATA_REG(chan)); in fl512_ao_insn_write()
91 inb(dev->iobase + FL512_AO_TRIG_REG(chan)); in fl512_ao_insn_write()
101 unsigned int iobase = it->options[0]; in fl512_attach() local
108 ret = comedi_check_request_region(dev, iobase, 0x10, in fl512_attach()
H A D8255.c50 unsigned int iobase; in dev_8255_attach() local
55 iobase = it->options[i]; in dev_8255_attach()
56 if (!iobase) in dev_8255_attach()
70 iobase = it->options[i]; in dev_8255_attach()
80 ret = __comedi_check_request_region(dev, iobase, I8255_SIZE, in dev_8255_attach()
84 ret = subdev_8255_io_init(dev, s, iobase); in dev_8255_attach()
90 release_region(iobase, I8255_SIZE); in dev_8255_attach()
H A Drti800.c140 status = inb(dev->iobase + RTI800_CSR); in rti800_ai_eoc()
142 outb(0, dev->iobase + RTI800_CLRFLAGS); in rti800_ai_eoc()
162 inb(dev->iobase + RTI800_ADCHI); in rti800_ai_insn_read()
163 outb(0, dev->iobase + RTI800_CLRFLAGS); in rti800_ai_insn_read()
168 outb(devpriv->muxgain_bits, dev->iobase + RTI800_MUXGAIN); in rti800_ai_insn_read()
185 outb(0, dev->iobase + RTI800_CONVERT); in rti800_ai_insn_read()
191 val = inb(dev->iobase + RTI800_ADCLO); in rti800_ai_insn_read()
192 val |= (inb(dev->iobase + RTI800_ADCHI) & 0xf) << 8; in rti800_ai_insn_read()
222 outb(val & 0xff, dev->iobase + reg_lo); in rti800_ao_insn_write()
223 outb((val >> 8) & 0xff, dev->iobase + reg_hi); in rti800_ao_insn_write()
[all …]
H A Ddt2814.c56 status = inb(dev->iobase + DT2814_CSR); in dt2814_ai_notbusy()
80 inb(dev->iobase + DT2814_DATA); in dt2814_ai_clear()
81 inb(dev->iobase + DT2814_DATA); in dt2814_ai_clear()
93 status = inb(dev->iobase + DT2814_CSR); in dt2814_ai_eoc()
111 outb(chan, dev->iobase + DT2814_CSR); in dt2814_ai_insn_read()
117 hi = inb(dev->iobase + DT2814_DATA); in dt2814_ai_insn_read()
118 lo = inb(dev->iobase + DT2814_DATA); in dt2814_ai_insn_read()
213 outb(chan | DT2814_ENB | (trigvar << 5), dev->iobase + DT2814_CSR); in dt2814_ai_cmd()
225 status = inb(dev->iobase + DT2814_CSR); in dt2814_ai_cancel()
234 outb(status & DT2814_CHANMASK, dev->iobase + DT2814_CSR); in dt2814_ai_cancel()
[all …]
H A Ddt282x.c447 dev->iobase + DT2821_SUPCSR_REG); in dt282x_ao_dma_interrupt()
467 dev->iobase + DT2821_SUPCSR_REG); in dt282x_ai_dma_interrupt()
506 adcsr = inw(dev->iobase + DT2821_ADCSR_REG); in dt282x_interrupt()
507 dacsr = inw(dev->iobase + DT2821_DACSR_REG); in dt282x_interrupt()
508 supcsr = inw(dev->iobase + DT2821_SUPCSR_REG); in dt282x_interrupt()
543 dev->iobase + DT2821_CHANCSR_REG); in dt282x_load_changain()
551 dev->iobase + DT2821_ADCSR_REG); in dt282x_load_changain()
553 outw(DT2821_CHANCSR_NUMB(n), dev->iobase + DT2821_CHANCSR_REG); in dt282x_load_changain()
563 status = inw(dev->iobase + DT2821_ADCSR_REG); in dt282x_ai_timeout()
597 outw(devpriv->adcsr, dev->iobase + DT2821_ADCSR_REG); in dt282x_ai_insn_read()
[all …]
H A Ddas1800.c343 insw(dev->iobase + DAS1800_FIFO, devpriv->fifo_buf, nsamples); in das1800_handle_fifo_half_full()
353 while (inb(dev->iobase + DAS1800_STATUS) & FNE) { in das1800_handle_fifo_not_empty()
354 dpnt = inw(dev->iobase + DAS1800_FIFO); in das1800_handle_fifo_not_empty()
414 outb(CLEAR_INTR_MASK & ~DMATC, dev->iobase + DAS1800_STATUS); in das1800_handle_dma()
430 outb(0x0, dev->iobase + DAS1800_STATUS); in das1800_ai_cancel()
431 outb(0x0, dev->iobase + DAS1800_CONTROL_B); in das1800_ai_cancel()
432 outb(0x0, dev->iobase + DAS1800_CONTROL_A); in das1800_ai_cancel()
451 unsigned int status = inb(dev->iobase + DAS1800_STATUS); in das1800_ai_handler()
454 outb(ADC, dev->iobase + DAS1800_SELECT); in das1800_ai_handler()
467 outb(CLEAR_INTR_MASK & ~OVF, dev->iobase + DAS1800_STATUS); in das1800_ai_handler()
[all …]
H A Ddas16m1.c114 outb(i, dev->iobase + DAS16M1_Q_ADDR_REG); in das16m1_ai_set_queue()
116 dev->iobase + DAS16M1_Q_REG); in das16m1_ai_set_queue()
284 outb(byte, dev->iobase + DAS16M1_CS_REG); in das16m1_ai_cmd()
287 outb(0, dev->iobase + DAS16M1_CLR_INTR_REG); in das16m1_ai_cmd()
290 outb(devpriv->intr_ctrl, dev->iobase + DAS16M1_INTR_CTRL_REG); in das16m1_ai_cmd()
303 outb(devpriv->intr_ctrl, dev->iobase + DAS16M1_INTR_CTRL_REG); in das16m1_ai_cancel()
315 status = inb(dev->iobase + DAS16M1_CS_REG); in das16m1_ai_eoc()
335 outb(0, dev->iobase + DAS16M1_CLR_INTR_REG); in das16m1_ai_insn_read()
337 outb(0, dev->iobase + DAS16M1_AI_REG); in das16m1_ai_insn_read()
343 val = inw(dev->iobase + DAS16M1_AI_REG); in das16m1_ai_insn_read()
[all …]
/linux/drivers/char/tpm/
H A Dtpm_tis_synquacer.c28 void __iomem *iobase; member
44 *result++ = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
47 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
48 result[0] = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
51 result[3] = ioread8(phy->iobase + addr + 3); in tpm_tis_synquacer_read_bytes()
52 result[2] = ioread8(phy->iobase + addr + 2); in tpm_tis_synquacer_read_bytes()
53 result[1] = ioread8(phy->iobase + addr + 1); in tpm_tis_synquacer_read_bytes()
54 result[0] = ioread8(phy->iobase + addr); in tpm_tis_synquacer_read_bytes()
69 iowrite8(*value++, phy->iobase + addr); in tpm_tis_synquacer_write_bytes()
78 iowrite8(value[3], phy->iobase + addr + 3); in tpm_tis_synquacer_write_bytes()
[all …]
H A Dtpm_tis.c43 void __iomem *iobase; member
56 static inline void tpm_tis_flush(void __iomem *iobase) in tpm_tis_flush() argument
58 ioread8(iobase + TPM_ACCESS(0)); in tpm_tis_flush()
61 #define tpm_tis_flush(iobase) do { } while (0) argument
71 static inline void tpm_tis_iowrite8(u8 b, void __iomem *iobase, u32 addr) in tpm_tis_iowrite8() argument
73 iowrite8(b, iobase + addr); in tpm_tis_iowrite8()
74 tpm_tis_flush(iobase); in tpm_tis_iowrite8()
84 static inline void tpm_tis_iowrite32(u32 b, void __iomem *iobase, u32 addr) in tpm_tis_iowrite32() argument
86 iowrite32(b, iobase + addr); in tpm_tis_iowrite32()
87 tpm_tis_flush(iobase); in tpm_tis_iowrite32()
[all …]
H A Dtpm_atmel.c23 void __iomem *iobase; member
105 status = ioread8(priv->iobase + 1); in tpm_atml_recv()
110 *buf++ = ioread8(priv->iobase); in tpm_atml_recv()
121 status = ioread8(priv->iobase + 1); in tpm_atml_recv()
132 status = ioread8(priv->iobase + 1); in tpm_atml_recv()
137 *buf++ = ioread8(priv->iobase); in tpm_atml_recv()
141 status = ioread8(priv->iobase + 1); in tpm_atml_recv()
160 iowrite8(buf[i], priv->iobase); in tpm_atml_send()
170 iowrite8(ATML_STATUS_ABORT, priv->iobase + 1); in tpm_atml_cancel()
177 return ioread8(priv->iobase + 1); in tpm_atml_status()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-hisi.c91 void __iomem *iobase; member
115 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
120 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
125 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
130 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
138 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE); in hisi_i2c_handle_errors()
159 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
163 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL); in hisi_i2c_start_xfer()
165 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
168 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR); in hisi_i2c_start_xfer()
[all …]
/linux/sound/pci/
H A Dals4000.c96 unsigned long iobase; member
176 static inline void snd_als4k_iobase_writeb(unsigned long iobase, in snd_als4k_iobase_writeb() argument
180 outb(val, iobase + reg); in snd_als4k_iobase_writeb()
183 static inline void snd_als4k_iobase_writel(unsigned long iobase, in snd_als4k_iobase_writel() argument
187 outl(val, iobase + reg); in snd_als4k_iobase_writel()
190 static inline u8 snd_als4k_iobase_readb(unsigned long iobase, in snd_als4k_iobase_readb() argument
193 return inb(iobase + reg); in snd_als4k_iobase_readb()
196 static inline u32 snd_als4k_iobase_readl(unsigned long iobase, in snd_als4k_iobase_readl() argument
199 return inl(iobase + reg); in snd_als4k_iobase_readl()
202 static inline void snd_als4k_gcr_write_addr(unsigned long iobase, in snd_als4k_gcr_write_addr() argument
217 snd_als4k_gcr_read_addr(unsigned long iobase,enum als4k_gcr_t reg) snd_als4k_gcr_read_addr() argument
678 snd_als4000_set_addr(unsigned long iobase,unsigned int sb_io,unsigned int mpu_io,unsigned int opl_io,unsigned int game_io) snd_als4000_set_addr() argument
807 unsigned long iobase; __snd_card_als4000_probe() local
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