1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/string_helpers.h>
28 #include <linux/uaccess.h>
29 #include <media/cec-notifier.h>
30
31 #include "dc.h"
32 #include "amdgpu.h"
33 #include "amdgpu_dm.h"
34 #include "amdgpu_dm_debugfs.h"
35 #include "amdgpu_dm_replay.h"
36 #include "amdgpu_dm_psr.h"
37 #include "dm_helpers.h"
38 #include "dmub/dmub_srv.h"
39 #include "resource.h"
40 #include "dsc.h"
41 #include "link_hwss.h"
42 #include "dc/dc_dmub_srv.h"
43 #include "link/protocols/link_dp_capability.h"
44 #include "inc/hw/dchubbub.h"
45
46 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
47 #include "amdgpu_dm_psr.h"
48 #endif
49
50 #define MULTIPLIER_TO_LR 270000
51 struct dmub_debugfs_trace_header {
52 uint32_t entry_count;
53 uint32_t reserved[3];
54 };
55
56 struct dmub_debugfs_trace_entry {
57 uint32_t trace_code;
58 uint32_t tick_count;
59 uint32_t param0;
60 uint32_t param1;
61 };
62
63 static const char *const mst_progress_status[] = {
64 "probe",
65 "remote_edid",
66 "allocate_new_payload",
67 "clear_allocated_payload",
68 };
69
70 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
71 *
72 * Function takes in attributes passed to debugfs write entry
73 * and writes into param array.
74 * The user passes max_param_num to identify maximum number of
75 * parameters that could be parsed.
76 *
77 */
parse_write_buffer_into_params(char * wr_buf,uint32_t wr_buf_size,long * param,const char __user * buf,int max_param_num,uint8_t * param_nums)78 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
79 long *param, const char __user *buf,
80 int max_param_num,
81 uint8_t *param_nums)
82 {
83 char *wr_buf_ptr = NULL;
84 uint32_t wr_buf_count = 0;
85 int r;
86 char *sub_str = NULL;
87 const char delimiter[3] = {' ', '\n', '\0'};
88 uint8_t param_index = 0;
89
90 *param_nums = 0;
91
92 wr_buf_ptr = wr_buf;
93
94 /* r is bytes not be copied */
95 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
96 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
97 return -EFAULT;
98 }
99
100 /* check number of parameters. isspace could not differ space and\n */
101 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
102 /* skip space*/
103 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
104 wr_buf_ptr++;
105 wr_buf_count++;
106 }
107
108 if (wr_buf_count == wr_buf_size)
109 break;
110
111 /* skip non-space*/
112 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
113 wr_buf_ptr++;
114 wr_buf_count++;
115 }
116
117 (*param_nums)++;
118
119 if (wr_buf_count == wr_buf_size)
120 break;
121 }
122
123 if (*param_nums > max_param_num)
124 *param_nums = max_param_num;
125
126 wr_buf_ptr = wr_buf; /* reset buf pointer */
127 wr_buf_count = 0; /* number of char already checked */
128
129 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
130 wr_buf_ptr++;
131 wr_buf_count++;
132 }
133
134 while (param_index < *param_nums) {
135 /* after strsep, wr_buf_ptr will be moved to after space */
136 sub_str = strsep(&wr_buf_ptr, delimiter);
137
138 r = kstrtol(sub_str, 16, &(param[param_index]));
139
140 if (r)
141 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
142
143 param_index++;
144 }
145
146 return 0;
147 }
148
149 /* function description
150 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
151 *
152 * valid lane count value: 1, 2, 4
153 * valid link rate value:
154 * 06h = 1.62Gbps per lane
155 * 0Ah = 2.7Gbps per lane
156 * 0Ch = 3.24Gbps per lane
157 * 14h = 5.4Gbps per lane
158 * 1Eh = 8.1Gbps per lane
159 *
160 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
161 *
162 * --- to get dp configuration
163 *
164 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
165 *
166 * It will list current, verified, reported, preferred dp configuration.
167 * current -- for current video mode
168 * verified --- maximum configuration which pass link training
169 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
170 * preferred --- user force settings
171 *
172 * --- set (or force) dp configuration
173 *
174 * echo <lane_count> <link_rate> > link_settings
175 *
176 * for example, to force to 2 lane, 2.7GHz,
177 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
178 *
179 * spread_spectrum could not be changed dynamically.
180 *
181 * in case invalid lane count, link rate are force, no hw programming will be
182 * done. please check link settings after force operation to see if HW get
183 * programming.
184 *
185 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
186 *
187 * check current and preferred settings.
188 *
189 */
dp_link_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)190 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
191 size_t size, loff_t *pos)
192 {
193 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
194 struct dc_link *link = connector->dc_link;
195 char *rd_buf = NULL;
196 char *rd_buf_ptr = NULL;
197 const uint32_t rd_buf_size = 100;
198 uint32_t result = 0;
199 int r;
200
201 if (*pos & 3 || size & 3)
202 return -EINVAL;
203
204 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
205 if (!rd_buf)
206 return 0;
207
208 rd_buf_ptr = rd_buf;
209
210 rd_buf_ptr += scnprintf(rd_buf_ptr, rd_buf_size - (rd_buf_ptr - rd_buf),
211 "Current: %d 0x%x %d ",
212 link->cur_link_settings.lane_count,
213 link->cur_link_settings.link_rate,
214 link->cur_link_settings.link_spread);
215
216 rd_buf_ptr += scnprintf(rd_buf_ptr, rd_buf_size - (rd_buf_ptr - rd_buf),
217 "Verified: %d 0x%x %d ",
218 link->verified_link_cap.lane_count,
219 link->verified_link_cap.link_rate,
220 link->verified_link_cap.link_spread);
221
222 rd_buf_ptr += scnprintf(rd_buf_ptr, rd_buf_size - (rd_buf_ptr - rd_buf),
223 "Reported: %d 0x%x %d ",
224 link->reported_link_cap.lane_count,
225 link->reported_link_cap.link_rate,
226 link->reported_link_cap.link_spread);
227
228 rd_buf_ptr += scnprintf(rd_buf_ptr, rd_buf_size - (rd_buf_ptr - rd_buf),
229 "Preferred: %d 0x%x %d\n",
230 link->preferred_link_setting.lane_count,
231 link->preferred_link_setting.link_rate,
232 link->preferred_link_setting.link_spread);
233
234 while (size) {
235 if (*pos >= rd_buf_size)
236 break;
237
238 r = put_user(*(rd_buf + result), buf);
239 if (r) {
240 kfree(rd_buf);
241 return r; /* r = -EFAULT */
242 }
243
244 buf += 1;
245 size -= 1;
246 *pos += 1;
247 result += 1;
248 }
249
250 kfree(rd_buf);
251 return result;
252 }
253
dp_link_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)254 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
255 size_t size, loff_t *pos)
256 {
257 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
258 struct dc_link *link = connector->dc_link;
259 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
260 struct dc *dc = (struct dc *)link->dc;
261 struct dc_link_settings prefer_link_settings = {0};
262 char *wr_buf = NULL;
263 const uint32_t wr_buf_size = 40;
264 /* 0: lane_count; 1: link_rate */
265 int max_param_num = 2;
266 uint8_t param_nums = 0;
267 long param[2];
268 bool valid_input = true;
269
270 if (size == 0)
271 return -EINVAL;
272
273 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
274 if (!wr_buf)
275 return -ENOSPC;
276
277 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
278 (long *)param, buf,
279 max_param_num,
280 ¶m_nums)) {
281 kfree(wr_buf);
282 return -EINVAL;
283 }
284
285 if (param_nums <= 0) {
286 kfree(wr_buf);
287 DRM_DEBUG_DRIVER("user data not be read\n");
288 return -EINVAL;
289 }
290
291 switch (param[0]) {
292 case LANE_COUNT_ONE:
293 case LANE_COUNT_TWO:
294 case LANE_COUNT_FOUR:
295 break;
296 default:
297 valid_input = false;
298 break;
299 }
300
301 switch (param[1]) {
302 case LINK_RATE_LOW:
303 case LINK_RATE_RATE_2:
304 case LINK_RATE_RATE_3:
305 case LINK_RATE_HIGH:
306 case LINK_RATE_RBR2:
307 case LINK_RATE_RATE_6:
308 case LINK_RATE_HIGH2:
309 case LINK_RATE_HIGH3:
310 case LINK_RATE_UHBR10:
311 case LINK_RATE_UHBR13_5:
312 case LINK_RATE_UHBR20:
313 break;
314 default:
315 valid_input = false;
316 break;
317 }
318
319 if (!valid_input) {
320 kfree(wr_buf);
321 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
322 mutex_lock(&adev->dm.dc_lock);
323 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
324 mutex_unlock(&adev->dm.dc_lock);
325 return size;
326 }
327
328 /* save user force lane_count, link_rate to preferred settings
329 * spread spectrum will not be changed
330 */
331 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
332 prefer_link_settings.use_link_rate_set = false;
333 prefer_link_settings.lane_count = param[0];
334 prefer_link_settings.link_rate = param[1];
335
336 mutex_lock(&adev->dm.dc_lock);
337 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false);
338 mutex_unlock(&adev->dm.dc_lock);
339
340 kfree(wr_buf);
341 return size;
342 }
343
dp_mst_is_end_device(struct amdgpu_dm_connector * aconnector)344 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
345 {
346 bool is_end_device = false;
347 struct drm_dp_mst_topology_mgr *mgr = NULL;
348 struct drm_dp_mst_port *port = NULL;
349
350 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
351 mgr = &aconnector->mst_root->mst_mgr;
352 port = aconnector->mst_output_port;
353
354 drm_modeset_lock(&mgr->base.lock, NULL);
355 if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
356 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
357 is_end_device = true;
358 drm_modeset_unlock(&mgr->base.lock);
359 }
360
361 return is_end_device;
362 }
363
364 /* Change MST link setting
365 *
366 * valid lane count value: 1, 2, 4
367 * valid link rate value:
368 * 06h = 1.62Gbps per lane
369 * 0Ah = 2.7Gbps per lane
370 * 0Ch = 3.24Gbps per lane
371 * 14h = 5.4Gbps per lane
372 * 1Eh = 8.1Gbps per lane
373 * 3E8h = 10.0Gbps per lane
374 * 546h = 13.5Gbps per lane
375 * 7D0h = 20.0Gbps per lane
376 *
377 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
378 *
379 * for example, to force to 2 lane, 10.0GHz,
380 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
381 *
382 * Valid input will trigger hotplug event to get new link setting applied
383 * Invalid input will trigger training setting reset
384 *
385 * The usage can be referred to link_settings entry
386 *
387 */
dp_mst_link_setting(struct file * f,const char __user * buf,size_t size,loff_t * pos)388 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
389 size_t size, loff_t *pos)
390 {
391 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
392 struct dc_link *link = aconnector->dc_link;
393 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
394 struct dc *dc = (struct dc *)link->dc;
395 struct dc_link_settings prefer_link_settings = {0};
396 char *wr_buf = NULL;
397 const uint32_t wr_buf_size = 40;
398 /* 0: lane_count; 1: link_rate */
399 int max_param_num = 2;
400 uint8_t param_nums = 0;
401 long param[2];
402 bool valid_input = true;
403
404 if (!dp_mst_is_end_device(aconnector))
405 return -EINVAL;
406
407 if (size == 0)
408 return -EINVAL;
409
410 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
411 if (!wr_buf)
412 return -ENOSPC;
413
414 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
415 (long *)param, buf,
416 max_param_num,
417 ¶m_nums)) {
418 kfree(wr_buf);
419 return -EINVAL;
420 }
421
422 if (param_nums <= 0) {
423 kfree(wr_buf);
424 DRM_DEBUG_DRIVER("user data not be read\n");
425 return -EINVAL;
426 }
427
428 switch (param[0]) {
429 case LANE_COUNT_ONE:
430 case LANE_COUNT_TWO:
431 case LANE_COUNT_FOUR:
432 break;
433 default:
434 valid_input = false;
435 break;
436 }
437
438 switch (param[1]) {
439 case LINK_RATE_LOW:
440 case LINK_RATE_HIGH:
441 case LINK_RATE_RBR2:
442 case LINK_RATE_HIGH2:
443 case LINK_RATE_HIGH3:
444 case LINK_RATE_UHBR10:
445 case LINK_RATE_UHBR13_5:
446 case LINK_RATE_UHBR20:
447 break;
448 default:
449 valid_input = false;
450 break;
451 }
452
453 if (!valid_input) {
454 kfree(wr_buf);
455 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
456 mutex_lock(&adev->dm.dc_lock);
457 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
458 mutex_unlock(&adev->dm.dc_lock);
459 return -EINVAL;
460 }
461
462 /* save user force lane_count, link_rate to preferred settings
463 * spread spectrum will not be changed
464 */
465 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
466 prefer_link_settings.use_link_rate_set = false;
467 prefer_link_settings.lane_count = param[0];
468 prefer_link_settings.link_rate = param[1];
469
470 /* skip immediate retrain, and train to new link setting after hotplug event triggered */
471 mutex_lock(&adev->dm.dc_lock);
472 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
473 mutex_unlock(&adev->dm.dc_lock);
474
475 mutex_lock(&aconnector->base.dev->mode_config.mutex);
476 aconnector->base.force = DRM_FORCE_OFF;
477 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
478 drm_kms_helper_hotplug_event(aconnector->base.dev);
479
480 msleep(100);
481
482 mutex_lock(&aconnector->base.dev->mode_config.mutex);
483 aconnector->base.force = DRM_FORCE_UNSPECIFIED;
484 mutex_unlock(&aconnector->base.dev->mode_config.mutex);
485 drm_kms_helper_hotplug_event(aconnector->base.dev);
486
487 kfree(wr_buf);
488 return size;
489 }
490
491 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
492 * post-cursor2 (defined by VESA DP specification)
493 *
494 * valid values
495 * voltage swing: 0,1,2,3
496 * pre-emphasis : 0,1,2,3
497 * post cursor2 : 0,1,2,3
498 *
499 *
500 * how to use this debugfs
501 *
502 * debugfs is located at /sys/kernel/debug/dri/0/DP-x
503 *
504 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
505 *
506 * To figure out which DP-x is the display for DP to be check,
507 * cd DP-x
508 * ls -ll
509 * There should be debugfs file, like link_settings, phy_settings.
510 * cat link_settings
511 * from lane_count, link_rate to figure which DP-x is for display to be worked
512 * on
513 *
514 * To get current DP PHY settings,
515 * cat phy_settings
516 *
517 * To change DP PHY settings,
518 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
519 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
520 * 0,
521 * echo 2 3 0 > phy_settings
522 *
523 * To check if change be applied, get current phy settings by
524 * cat phy_settings
525 *
526 * In case invalid values are set by user, like
527 * echo 1 4 0 > phy_settings
528 *
529 * HW will NOT be programmed by these settings.
530 * cat phy_settings will show the previous valid settings.
531 */
dp_phy_settings_read(struct file * f,char __user * buf,size_t size,loff_t * pos)532 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
533 size_t size, loff_t *pos)
534 {
535 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
536 struct dc_link *link = connector->dc_link;
537 char *rd_buf = NULL;
538 const uint32_t rd_buf_size = 20;
539 uint32_t result = 0;
540 int r;
541
542 if (*pos & 3 || size & 3)
543 return -EINVAL;
544
545 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
546 if (!rd_buf)
547 return -EINVAL;
548
549 snprintf(rd_buf, rd_buf_size, " %d %d %d\n",
550 link->cur_lane_setting[0].VOLTAGE_SWING,
551 link->cur_lane_setting[0].PRE_EMPHASIS,
552 link->cur_lane_setting[0].POST_CURSOR2);
553
554 while (size) {
555 if (*pos >= rd_buf_size)
556 break;
557
558 r = put_user((*(rd_buf + result)), buf);
559 if (r) {
560 kfree(rd_buf);
561 return r; /* r = -EFAULT */
562 }
563
564 buf += 1;
565 size -= 1;
566 *pos += 1;
567 result += 1;
568 }
569
570 kfree(rd_buf);
571 return result;
572 }
573
dp_lttpr_status_show(struct seq_file * m,void * unused)574 static int dp_lttpr_status_show(struct seq_file *m, void *unused)
575 {
576 struct drm_connector *connector = m->private;
577 struct amdgpu_dm_connector *aconnector =
578 to_amdgpu_dm_connector(connector);
579 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
580
581 if (connector->status != connector_status_connected)
582 return -ENODEV;
583
584 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n",
585 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt),
586 caps.phy_repeater_cnt);
587
588 seq_puts(m, "phy repeater mode: ");
589
590 switch (caps.mode) {
591 case DP_PHY_REPEATER_MODE_TRANSPARENT:
592 seq_puts(m, "transparent");
593 break;
594 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
595 seq_puts(m, "non-transparent");
596 break;
597 case 0x00:
598 seq_puts(m, "non lttpr");
599 break;
600 default:
601 seq_printf(m, "read error (raw: 0x%x)", caps.mode);
602 break;
603 }
604
605 seq_putc(m, '\n');
606 return 0;
607 }
608
dp_phy_settings_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)609 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
610 size_t size, loff_t *pos)
611 {
612 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
613 struct dc_link *link = connector->dc_link;
614 struct dc *dc = (struct dc *)link->dc;
615 char *wr_buf = NULL;
616 uint32_t wr_buf_size = 40;
617 long param[3];
618 bool use_prefer_link_setting;
619 struct link_training_settings link_lane_settings = {0};
620 int max_param_num = 3;
621 uint8_t param_nums = 0;
622 int r = 0;
623
624
625 if (size == 0)
626 return -EINVAL;
627
628 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
629 if (!wr_buf)
630 return -ENOSPC;
631
632 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
633 (long *)param, buf,
634 max_param_num,
635 ¶m_nums)) {
636 kfree(wr_buf);
637 return -EINVAL;
638 }
639
640 if (param_nums <= 0) {
641 kfree(wr_buf);
642 DRM_DEBUG_DRIVER("user data not be read\n");
643 return -EINVAL;
644 }
645
646 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
647 (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
648 (param[2] > POST_CURSOR2_MAX_LEVEL)) {
649 kfree(wr_buf);
650 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
651 return size;
652 }
653
654 /* get link settings: lane count, link rate */
655 use_prefer_link_setting =
656 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
657 (link->test_pattern_enabled));
658
659 memset(&link_lane_settings, 0, sizeof(link_lane_settings));
660
661 if (use_prefer_link_setting) {
662 link_lane_settings.link_settings.lane_count =
663 link->preferred_link_setting.lane_count;
664 link_lane_settings.link_settings.link_rate =
665 link->preferred_link_setting.link_rate;
666 link_lane_settings.link_settings.link_spread =
667 link->preferred_link_setting.link_spread;
668 } else {
669 link_lane_settings.link_settings.lane_count =
670 link->cur_link_settings.lane_count;
671 link_lane_settings.link_settings.link_rate =
672 link->cur_link_settings.link_rate;
673 link_lane_settings.link_settings.link_spread =
674 link->cur_link_settings.link_spread;
675 }
676
677 /* apply phy settings from user */
678 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
679 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
680 (enum dc_voltage_swing) (param[0]);
681 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
682 (enum dc_pre_emphasis) (param[1]);
683 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
684 (enum dc_post_cursor2) (param[2]);
685 }
686
687 /* program ASIC registers and DPCD registers */
688 dc_link_set_drive_settings(dc, &link_lane_settings, link);
689
690 kfree(wr_buf);
691 return size;
692 }
693
694 /* function description
695 *
696 * set PHY layer or Link layer test pattern
697 * PHY test pattern is used for PHY SI check.
698 * Link layer test will not affect PHY SI.
699 *
700 * Reset Test Pattern:
701 * 0 = DP_TEST_PATTERN_VIDEO_MODE
702 *
703 * PHY test pattern supported:
704 * 1 = DP_TEST_PATTERN_D102
705 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
706 * 3 = DP_TEST_PATTERN_PRBS7
707 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
708 * 5 = DP_TEST_PATTERN_CP2520_1
709 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
710 * 7 = DP_TEST_PATTERN_CP2520_3
711 *
712 * DP PHY Link Training Patterns
713 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
714 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
715 * a = DP_TEST_PATTERN_TRAINING_PATTERN3
716 * b = DP_TEST_PATTERN_TRAINING_PATTERN4
717 *
718 * DP Link Layer Test pattern
719 * c = DP_TEST_PATTERN_COLOR_SQUARES
720 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
721 * e = DP_TEST_PATTERN_VERTICAL_BARS
722 * f = DP_TEST_PATTERN_HORIZONTAL_BARS
723 * 10= DP_TEST_PATTERN_COLOR_RAMP
724 *
725 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
726 *
727 * --- set test pattern
728 * echo <test pattern #> > test_pattern
729 *
730 * If test pattern # is not supported, NO HW programming will be done.
731 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
732 * for the user pattern. input 10 bytes data are separated by space
733 *
734 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
735 *
736 * --- reset test pattern
737 * echo 0 > test_pattern
738 *
739 * --- HPD detection is disabled when set PHY test pattern
740 *
741 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
742 * is disable. User could unplug DP display from DP connected and plug scope to
743 * check test pattern PHY SI.
744 * If there is need unplug scope and plug DP display back, do steps below:
745 * echo 0 > phy_test_pattern
746 * unplug scope
747 * plug DP display.
748 *
749 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
750 * driver could detect "unplug scope" and "plug DP display"
751 */
dp_phy_test_pattern_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)752 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
753 size_t size, loff_t *pos)
754 {
755 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
756 struct dc_link *link = connector->dc_link;
757 char *wr_buf = NULL;
758 uint32_t wr_buf_size = 100;
759 long param[11] = {0x0};
760 int max_param_num = 11;
761 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
762 bool disable_hpd = false;
763 bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID;
764 bool valid_test_pattern = false;
765 uint8_t param_nums = 0;
766 /* init with default 80bit custom pattern */
767 uint8_t custom_pattern[10] = {
768 0x1f, 0x7c, 0xf0, 0xc1, 0x07,
769 0x1f, 0x7c, 0xf0, 0xc1, 0x07
770 };
771 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
772 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
773 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
774 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
775 struct link_training_settings link_training_settings = {0};
776 int i;
777
778 if (size == 0)
779 return -EINVAL;
780
781 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
782 if (!wr_buf)
783 return -ENOSPC;
784
785 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
786 (long *)param, buf,
787 max_param_num,
788 ¶m_nums)) {
789 kfree(wr_buf);
790 return -EINVAL;
791 }
792
793 if (param_nums <= 0) {
794 kfree(wr_buf);
795 DRM_DEBUG_DRIVER("user data not be read\n");
796 return -EINVAL;
797 }
798
799
800 test_pattern = param[0];
801
802 switch (test_pattern) {
803 case DP_TEST_PATTERN_VIDEO_MODE:
804 case DP_TEST_PATTERN_COLOR_SQUARES:
805 case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
806 case DP_TEST_PATTERN_VERTICAL_BARS:
807 case DP_TEST_PATTERN_HORIZONTAL_BARS:
808 case DP_TEST_PATTERN_COLOR_RAMP:
809 valid_test_pattern = true;
810 break;
811
812 case DP_TEST_PATTERN_D102:
813 case DP_TEST_PATTERN_SYMBOL_ERROR:
814 case DP_TEST_PATTERN_PRBS7:
815 case DP_TEST_PATTERN_80BIT_CUSTOM:
816 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
817 case DP_TEST_PATTERN_TRAINING_PATTERN4:
818 disable_hpd = true;
819 valid_test_pattern = true;
820 break;
821
822 default:
823 valid_test_pattern = false;
824 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
825 break;
826 }
827
828 if (!valid_test_pattern) {
829 kfree(wr_buf);
830 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
831 return size;
832 }
833
834 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
835 for (i = 0; i < 10; i++) {
836 if ((uint8_t) param[i + 1] != 0x0)
837 break;
838 }
839
840 if (i < 10) {
841 /* not use default value */
842 for (i = 0; i < 10; i++)
843 custom_pattern[i] = (uint8_t) param[i + 1];
844 }
845 }
846
847 /* Usage: set DP physical test pattern using debugfs with normal DP
848 * panel. Then plug out DP panel and connect a scope to measure
849 * For normal video mode and test pattern generated from CRCT,
850 * they are visibile to user. So do not disable HPD.
851 * Video Mode is also set to clear the test pattern, so enable HPD
852 * because it might have been disabled after a test pattern was set.
853 * AUX depends on HPD * sequence dependent, do not move!
854 */
855 if (supports_hpd && !disable_hpd)
856 dc_link_enable_hpd(link);
857
858 prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
859 prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
860 prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
861
862 cur_link_settings.lane_count = link->cur_link_settings.lane_count;
863 cur_link_settings.link_rate = link->cur_link_settings.link_rate;
864 cur_link_settings.link_spread = link->cur_link_settings.link_spread;
865
866 link_training_settings.link_settings = cur_link_settings;
867
868
869 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
870 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
871 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN &&
872 (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
873 prefer_link_settings.link_rate != cur_link_settings.link_rate))
874 link_training_settings.link_settings = prefer_link_settings;
875 }
876
877 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
878 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
879
880 dc_link_dp_set_test_pattern(
881 link,
882 test_pattern,
883 DP_TEST_PATTERN_COLOR_SPACE_RGB,
884 &link_training_settings,
885 custom_pattern,
886 10);
887
888 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
889 * Then plug out DP panel and connect a scope to measure DP PHY signal.
890 * Need disable interrupt to avoid SW driver disable DP output. This is
891 * done after the test pattern is set.
892 */
893 if (valid_test_pattern && supports_hpd && disable_hpd)
894 dc_link_disable_hpd(link);
895
896 kfree(wr_buf);
897
898 return size;
899 }
900
901 /*
902 * Returns the DMCUB tracebuffer contents.
903 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
904 */
dmub_tracebuffer_show(struct seq_file * m,void * data)905 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
906 {
907 struct amdgpu_device *adev = m->private;
908 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
909 struct dmub_fw_meta_info *fw_meta_info = NULL;
910 struct dmub_debugfs_trace_entry *entries;
911 uint8_t *tbuf_base;
912 uint32_t tbuf_size, max_entries, num_entries, first_entry, i;
913
914 if (!fb_info)
915 return 0;
916
917 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
918 if (!tbuf_base)
919 return 0;
920
921 if (adev->dm.dmub_srv)
922 fw_meta_info = &adev->dm.dmub_srv->meta_info;
923
924 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size :
925 DMUB_TRACE_BUFFER_SIZE;
926 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
927 sizeof(struct dmub_debugfs_trace_entry);
928
929 num_entries =
930 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
931
932 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that
933 * entries are being overwritten.
934 */
935 if (num_entries > max_entries)
936 seq_printf(m, "...\n");
937
938 first_entry = num_entries % max_entries;
939 num_entries = min(num_entries, max_entries);
940
941 entries = (struct dmub_debugfs_trace_entry
942 *)(tbuf_base +
943 sizeof(struct dmub_debugfs_trace_header));
944
945 /* To print entries chronologically, start from the first entry till the
946 * top of buffer, then from base of buffer to first entry.
947 */
948 for (i = first_entry; i < num_entries; ++i) {
949 struct dmub_debugfs_trace_entry *entry = &entries[i];
950
951 seq_printf(m,
952 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
953 entry->trace_code, entry->tick_count, entry->param0,
954 entry->param1);
955 }
956 for (i = 0; i < first_entry; ++i) {
957 struct dmub_debugfs_trace_entry *entry = &entries[i];
958
959 seq_printf(m,
960 "trace_code=%u tick_count=%u param0=%u param1=%u\n",
961 entry->trace_code, entry->tick_count, entry->param0,
962 entry->param1);
963 }
964
965 return 0;
966 }
967
968 /*
969 * Returns the DMCUB firmware state contents.
970 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
971 */
dmub_fw_state_show(struct seq_file * m,void * data)972 static int dmub_fw_state_show(struct seq_file *m, void *data)
973 {
974 struct amdgpu_device *adev = m->private;
975 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
976 uint8_t *state_base;
977 uint32_t state_size;
978
979 if (!fb_info)
980 return 0;
981
982 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
983 if (!state_base)
984 return 0;
985
986 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
987
988 return seq_write(m, state_base, state_size);
989 }
990
991 /* replay_capability_show() - show eDP panel replay capability
992 *
993 * The read function: replay_capability_show
994 * Shows if sink and driver has Replay capability or not.
995 *
996 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
997 *
998 * Expected output:
999 * "Sink support: no\n" - if panel doesn't support Replay
1000 * "Sink support: yes\n" - if panel supports Replay
1001 * "Driver support: no\n" - if driver doesn't support Replay
1002 * "Driver support: yes\n" - if driver supports Replay
1003 */
replay_capability_show(struct seq_file * m,void * data)1004 static int replay_capability_show(struct seq_file *m, void *data)
1005 {
1006 struct drm_connector *connector = m->private;
1007 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1008 struct dc_link *link = aconnector->dc_link;
1009 bool sink_support_replay = false;
1010 bool driver_support_replay = false;
1011
1012 if (!link)
1013 return -ENODEV;
1014
1015 if (link->type == dc_connection_none)
1016 return -ENODEV;
1017
1018 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1019 return -ENODEV;
1020
1021 /* If Replay is already set to support, skip the checks */
1022 if (link->replay_settings.config.replay_supported) {
1023 sink_support_replay = true;
1024 driver_support_replay = true;
1025 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
1026 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1027 } else {
1028 struct dc *dc = link->ctx->dc;
1029
1030 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1031 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1032 driver_support_replay =
1033 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1034 }
1035
1036 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
1037 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
1038 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
1039
1040 return 0;
1041 }
1042
1043 /* psr_capability_show() - show eDP panel PSR capability
1044 *
1045 * The read function: sink_psr_capability_show
1046 * Shows if sink has PSR capability or not.
1047 * If yes - the PSR version is appended
1048 *
1049 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1050 *
1051 * Expected output:
1052 * "Sink support: no\n" - if panel doesn't support PSR
1053 * "Sink support: yes [0x01]\n" - if panel supports PSR1
1054 * "Driver support: no\n" - if driver doesn't support PSR
1055 * "Driver support: yes [0x01]\n" - if driver supports PSR1
1056 */
psr_capability_show(struct seq_file * m,void * data)1057 static int psr_capability_show(struct seq_file *m, void *data)
1058 {
1059 struct drm_connector *connector = m->private;
1060 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1061 struct dc_link *link = aconnector->dc_link;
1062
1063 if (!link)
1064 return -ENODEV;
1065
1066 if (link->type == dc_connection_none)
1067 return -ENODEV;
1068
1069 if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1070 return -ENODEV;
1071
1072 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0));
1073 if (link->dpcd_caps.psr_info.psr_version)
1074 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1075 seq_puts(m, "\n");
1076
1077 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled));
1078 if (link->psr_settings.psr_version)
1079 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
1080 seq_putc(m, '\n');
1081
1082 return 0;
1083 }
1084
1085 /*
1086 * Returns the current bpc for the crtc.
1087 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1088 */
amdgpu_current_bpc_show(struct seq_file * m,void * data)1089 static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1090 {
1091 struct drm_crtc *crtc = m->private;
1092 struct drm_device *dev = crtc->dev;
1093 struct dm_crtc_state *dm_crtc_state = NULL;
1094 int res = -ENODEV;
1095 unsigned int bpc;
1096
1097 mutex_lock(&dev->mode_config.mutex);
1098 drm_modeset_lock(&crtc->mutex, NULL);
1099 if (crtc->state == NULL)
1100 goto unlock;
1101
1102 dm_crtc_state = to_dm_crtc_state(crtc->state);
1103 if (dm_crtc_state->stream == NULL)
1104 goto unlock;
1105
1106 switch (dm_crtc_state->stream->timing.display_color_depth) {
1107 case COLOR_DEPTH_666:
1108 bpc = 6;
1109 break;
1110 case COLOR_DEPTH_888:
1111 bpc = 8;
1112 break;
1113 case COLOR_DEPTH_101010:
1114 bpc = 10;
1115 break;
1116 case COLOR_DEPTH_121212:
1117 bpc = 12;
1118 break;
1119 case COLOR_DEPTH_161616:
1120 bpc = 16;
1121 break;
1122 default:
1123 goto unlock;
1124 }
1125
1126 seq_printf(m, "Current: %u\n", bpc);
1127 res = 0;
1128
1129 unlock:
1130 drm_modeset_unlock(&crtc->mutex);
1131 mutex_unlock(&dev->mode_config.mutex);
1132
1133 return res;
1134 }
1135 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1136
1137 /*
1138 * Returns the current colorspace for the crtc.
1139 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1140 */
amdgpu_current_colorspace_show(struct seq_file * m,void * data)1141 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1142 {
1143 struct drm_crtc *crtc = m->private;
1144 struct drm_device *dev = crtc->dev;
1145 struct dm_crtc_state *dm_crtc_state = NULL;
1146 int res = -ENODEV;
1147
1148 mutex_lock(&dev->mode_config.mutex);
1149 drm_modeset_lock(&crtc->mutex, NULL);
1150 if (crtc->state == NULL)
1151 goto unlock;
1152
1153 dm_crtc_state = to_dm_crtc_state(crtc->state);
1154 if (dm_crtc_state->stream == NULL)
1155 goto unlock;
1156
1157 switch (dm_crtc_state->stream->output_color_space) {
1158 case COLOR_SPACE_SRGB:
1159 seq_puts(m, "sRGB");
1160 break;
1161 case COLOR_SPACE_YCBCR601:
1162 case COLOR_SPACE_YCBCR601_LIMITED:
1163 seq_puts(m, "BT601_YCC");
1164 break;
1165 case COLOR_SPACE_YCBCR709:
1166 case COLOR_SPACE_YCBCR709_LIMITED:
1167 seq_puts(m, "BT709_YCC");
1168 break;
1169 case COLOR_SPACE_ADOBERGB:
1170 seq_puts(m, "opRGB");
1171 break;
1172 case COLOR_SPACE_2020_RGB_FULLRANGE:
1173 seq_puts(m, "BT2020_RGB");
1174 break;
1175 case COLOR_SPACE_2020_YCBCR_LIMITED:
1176 seq_puts(m, "BT2020_YCC");
1177 break;
1178 default:
1179 goto unlock;
1180 }
1181 res = 0;
1182
1183 unlock:
1184 drm_modeset_unlock(&crtc->mutex);
1185 mutex_unlock(&dev->mode_config.mutex);
1186
1187 return res;
1188 }
1189 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1190
1191
1192 /*
1193 * Example usage:
1194 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1195 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1196 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1197 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1198 */
dp_dsc_passthrough_set(struct file * f,const char __user * buf,size_t size,loff_t * pos)1199 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1200 size_t size, loff_t *pos)
1201 {
1202 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1203 char *wr_buf = NULL;
1204 uint32_t wr_buf_size = 42;
1205 int max_param_num = 1;
1206 long param;
1207 uint8_t param_nums = 0;
1208
1209 if (size == 0)
1210 return -EINVAL;
1211
1212 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1213
1214 if (!wr_buf) {
1215 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1216 return -ENOSPC;
1217 }
1218
1219 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1220 ¶m, buf,
1221 max_param_num,
1222 ¶m_nums)) {
1223 kfree(wr_buf);
1224 return -EINVAL;
1225 }
1226
1227 aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1228
1229 kfree(wr_buf);
1230 return 0;
1231 }
1232
1233 /*
1234 * Returns the HDCP capability of the Display (1.4 for now).
1235 *
1236 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1237 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1238 *
1239 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1240 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1241 */
hdcp_sink_capability_show(struct seq_file * m,void * data)1242 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1243 {
1244 struct drm_connector *connector = m->private;
1245 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1246 bool hdcp_cap, hdcp2_cap;
1247
1248 if (connector->status != connector_status_connected)
1249 return -ENODEV;
1250
1251 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
1252
1253 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1254 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
1255
1256
1257 if (hdcp_cap)
1258 seq_printf(m, "%s ", "HDCP1.4");
1259 if (hdcp2_cap)
1260 seq_printf(m, "%s ", "HDCP2.2");
1261
1262 if (!hdcp_cap && !hdcp2_cap)
1263 seq_printf(m, "%s ", "None");
1264
1265 seq_putc(m, '\n');
1266
1267 return 0;
1268 }
1269
1270 /*
1271 * Returns whether the connected display is internal and not hotpluggable.
1272 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1273 */
internal_display_show(struct seq_file * m,void * data)1274 static int internal_display_show(struct seq_file *m, void *data)
1275 {
1276 struct drm_connector *connector = m->private;
1277 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1278 struct dc_link *link = aconnector->dc_link;
1279
1280 seq_printf(m, "Internal: %u\n", link->is_internal_display);
1281
1282 return 0;
1283 }
1284
1285 /*
1286 * Returns the number of segments used if ODM Combine mode is enabled.
1287 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1288 */
odm_combine_segments_show(struct seq_file * m,void * unused)1289 static int odm_combine_segments_show(struct seq_file *m, void *unused)
1290 {
1291 struct drm_connector *connector = m->private;
1292 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1293 struct dc_link *link = aconnector->dc_link;
1294 struct pipe_ctx *pipe_ctx = NULL;
1295 int i, segments = -EOPNOTSUPP;
1296
1297 for (i = 0; i < MAX_PIPES; i++) {
1298 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1299 if (pipe_ctx->stream &&
1300 pipe_ctx->stream->link == link)
1301 break;
1302 }
1303
1304 if (connector->status != connector_status_connected)
1305 return -ENODEV;
1306
1307 if (pipe_ctx && pipe_ctx->stream_res.tg &&
1308 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1309 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1310
1311 seq_printf(m, "%d\n", segments);
1312 return 0;
1313 }
1314
1315 /* function description
1316 *
1317 * generic SDP message access for testing
1318 *
1319 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1320 *
1321 * SDP header
1322 * Hb0 : Secondary-Data Packet ID
1323 * Hb1 : Secondary-Data Packet type
1324 * Hb2 : Secondary-Data-packet-specific header, Byte 0
1325 * Hb3 : Secondary-Data-packet-specific header, Byte 1
1326 *
1327 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1328 */
dp_sdp_message_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1329 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1330 size_t size, loff_t *pos)
1331 {
1332 int r;
1333 uint8_t data[36] = {0};
1334 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1335 struct dm_crtc_state *acrtc_state;
1336 uint32_t write_size = 36;
1337
1338 if (connector->base.status != connector_status_connected)
1339 return -ENODEV;
1340
1341 if (size == 0)
1342 return 0;
1343
1344 if (!connector->base.state || !connector->base.state->crtc)
1345 return -ENODEV;
1346
1347 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1348
1349 write_size = min_t(size_t, size, sizeof(data));
1350
1351 r = copy_from_user(data, buf, write_size);
1352
1353 write_size -= r;
1354
1355 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1356
1357 return write_size;
1358 }
1359
1360 /* function: Read link's DSC & FEC capabilities
1361 *
1362 *
1363 * Access it with the following command (you need to specify
1364 * connector like DP-1):
1365 *
1366 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1367 *
1368 */
dp_dsc_fec_support_show(struct seq_file * m,void * data)1369 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1370 {
1371 struct drm_connector *connector = m->private;
1372 struct drm_modeset_acquire_ctx ctx;
1373 struct drm_device *dev = connector->dev;
1374 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1375 int ret = 0;
1376 bool try_again = false;
1377 bool is_fec_supported = false;
1378 bool is_dsc_supported = false;
1379 struct dpcd_caps dpcd_caps;
1380
1381 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1382 do {
1383 try_again = false;
1384 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1385 if (ret) {
1386 if (ret == -EDEADLK) {
1387 ret = drm_modeset_backoff(&ctx);
1388 if (!ret) {
1389 try_again = true;
1390 continue;
1391 }
1392 }
1393 break;
1394 }
1395 if (connector->status != connector_status_connected) {
1396 ret = -ENODEV;
1397 break;
1398 }
1399 dpcd_caps = aconnector->dc_link->dpcd_caps;
1400 if (aconnector->mst_output_port) {
1401 /* aconnector sets dsc_aux during get_modes call
1402 * if MST connector has it means it can either
1403 * enable DSC on the sink device or on MST branch
1404 * its connected to.
1405 */
1406 if (aconnector->dsc_aux) {
1407 is_fec_supported = true;
1408 is_dsc_supported = true;
1409 }
1410 } else {
1411 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1412 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1413 }
1414 } while (try_again);
1415
1416 drm_modeset_drop_locks(&ctx);
1417 drm_modeset_acquire_fini(&ctx);
1418
1419 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported));
1420 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported));
1421
1422 return ret;
1423 }
1424
1425 /* function: Trigger virtual HPD redetection on connector
1426 *
1427 * This function will perform link rediscovery, link disable
1428 * and enable, and dm connector state update.
1429 *
1430 * Retrigger HPD on an existing connector by echoing 1 into
1431 * its respectful "trigger_hotplug" debugfs entry:
1432 *
1433 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1434 *
1435 * This function can perform HPD unplug:
1436 *
1437 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1438 *
1439 */
trigger_hotplug(struct file * f,const char __user * buf,size_t size,loff_t * pos)1440 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1441 size_t size, loff_t *pos)
1442 {
1443 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1444 struct drm_connector *connector = &aconnector->base;
1445 struct dc_link *link = NULL;
1446 struct drm_device *dev = connector->dev;
1447 struct amdgpu_device *adev = drm_to_adev(dev);
1448 enum dc_connection_type new_connection_type = dc_connection_none;
1449 char *wr_buf = NULL;
1450 uint32_t wr_buf_size = 42;
1451 int max_param_num = 1;
1452 long param[1] = {0};
1453 uint8_t param_nums = 0;
1454 bool ret = false;
1455
1456 if (!aconnector->dc_link)
1457 return -EINVAL;
1458
1459 if (size == 0)
1460 return -EINVAL;
1461
1462 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1463
1464 if (!wr_buf) {
1465 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1466 return -ENOSPC;
1467 }
1468
1469 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1470 (long *)param, buf,
1471 max_param_num,
1472 ¶m_nums)) {
1473 kfree(wr_buf);
1474 return -EINVAL;
1475 }
1476
1477 kfree(wr_buf);
1478
1479 if (param_nums <= 0) {
1480 DRM_DEBUG_DRIVER("user data not be read\n");
1481 return -EINVAL;
1482 }
1483
1484 mutex_lock(&aconnector->hpd_lock);
1485
1486 /* Don't support for mst end device*/
1487 if (aconnector->mst_root) {
1488 mutex_unlock(&aconnector->hpd_lock);
1489 return -EINVAL;
1490 }
1491
1492 if (param[0] == 1) {
1493
1494 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) &&
1495 new_connection_type != dc_connection_none)
1496 goto unlock;
1497
1498 mutex_lock(&adev->dm.dc_lock);
1499 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1500 mutex_unlock(&adev->dm.dc_lock);
1501
1502 if (!ret)
1503 goto unlock;
1504
1505 amdgpu_dm_update_connector_after_detect(aconnector);
1506
1507 drm_modeset_lock_all(dev);
1508 dm_restore_drm_connector_state(dev, connector);
1509 drm_modeset_unlock_all(dev);
1510
1511 drm_kms_helper_connector_hotplug_event(connector);
1512 } else if (param[0] == 0) {
1513 if (!aconnector->dc_link)
1514 goto unlock;
1515
1516 link = aconnector->dc_link;
1517
1518 if (link->local_sink) {
1519 dc_sink_release(link->local_sink);
1520 link->local_sink = NULL;
1521 }
1522
1523 link->dpcd_sink_count = 0;
1524 link->type = dc_connection_none;
1525 link->dongle_max_pix_clk = 0;
1526
1527 amdgpu_dm_update_connector_after_detect(aconnector);
1528
1529 /* If the aconnector is the root node in mst topology */
1530 if (aconnector->mst_mgr.mst_state == true)
1531 dc_link_reset_cur_dp_mst_topology(link);
1532
1533 drm_modeset_lock_all(dev);
1534 dm_restore_drm_connector_state(dev, connector);
1535 drm_modeset_unlock_all(dev);
1536
1537 drm_kms_helper_connector_hotplug_event(connector);
1538 }
1539
1540 unlock:
1541 mutex_unlock(&aconnector->hpd_lock);
1542
1543 return size;
1544 }
1545
1546 /* function: read DSC status on the connector
1547 *
1548 * The read function: dp_dsc_clock_en_read
1549 * returns current status of DSC clock on the connector.
1550 * The return is a boolean flag: 1 or 0.
1551 *
1552 * Access it with the following command (you need to specify
1553 * connector like DP-1):
1554 *
1555 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1556 *
1557 * Expected output:
1558 * 1 - means that DSC is currently enabled
1559 * 0 - means that DSC is disabled
1560 */
dp_dsc_clock_en_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1561 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1562 size_t size, loff_t *pos)
1563 {
1564 char *rd_buf = NULL;
1565 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1566 struct display_stream_compressor *dsc;
1567 struct dcn_dsc_state dsc_state = {0};
1568 const uint32_t rd_buf_size = 10;
1569 struct pipe_ctx *pipe_ctx;
1570 ssize_t result = 0;
1571 int i, r, str_len = 10;
1572
1573 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1574
1575 if (!rd_buf)
1576 return -ENOMEM;
1577
1578 for (i = 0; i < MAX_PIPES; i++) {
1579 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1580 if (pipe_ctx->stream &&
1581 pipe_ctx->stream->link == aconnector->dc_link &&
1582 pipe_ctx->stream->sink &&
1583 pipe_ctx->stream->sink == aconnector->dc_sink)
1584 break;
1585 }
1586
1587 dsc = pipe_ctx->stream_res.dsc;
1588 if (dsc)
1589 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1590
1591 snprintf(rd_buf, str_len,
1592 "%d\n",
1593 dsc_state.dsc_clock_en);
1594
1595 while (size) {
1596 if (*pos >= rd_buf_size)
1597 break;
1598
1599 r = put_user(*(rd_buf + result), buf);
1600 if (r) {
1601 kfree(rd_buf);
1602 return r; /* r = -EFAULT */
1603 }
1604
1605 buf += 1;
1606 size -= 1;
1607 *pos += 1;
1608 result += 1;
1609 }
1610
1611 kfree(rd_buf);
1612 return result;
1613 }
1614
1615 /* function: write force DSC on the connector
1616 *
1617 * The write function: dp_dsc_clock_en_write
1618 * enables to force DSC on the connector.
1619 * User can write to either force enable or force disable DSC
1620 * on the next modeset or set it to driver default
1621 *
1622 * Accepted inputs:
1623 * 0 - default DSC enablement policy
1624 * 1 - force enable DSC on the connector
1625 * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1626 *
1627 * Writing DSC settings is done with the following command:
1628 * - To force enable DSC (you need to specify
1629 * connector like DP-1):
1630 *
1631 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1632 *
1633 * - To return to default state set the flag to zero and
1634 * let driver deal with DSC automatically
1635 * (you need to specify connector like DP-1):
1636 *
1637 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1638 *
1639 */
dp_dsc_clock_en_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1640 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1641 size_t size, loff_t *pos)
1642 {
1643 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1644 struct drm_connector *connector = &aconnector->base;
1645 struct drm_device *dev = connector->dev;
1646 struct drm_crtc *crtc = NULL;
1647 struct dm_crtc_state *dm_crtc_state = NULL;
1648 struct pipe_ctx *pipe_ctx;
1649 int i;
1650 char *wr_buf = NULL;
1651 uint32_t wr_buf_size = 42;
1652 int max_param_num = 1;
1653 long param[1] = {0};
1654 uint8_t param_nums = 0;
1655
1656 if (size == 0)
1657 return -EINVAL;
1658
1659 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1660
1661 if (!wr_buf) {
1662 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1663 return -ENOSPC;
1664 }
1665
1666 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1667 (long *)param, buf,
1668 max_param_num,
1669 ¶m_nums)) {
1670 kfree(wr_buf);
1671 return -EINVAL;
1672 }
1673
1674 if (param_nums <= 0) {
1675 DRM_DEBUG_DRIVER("user data not be read\n");
1676 kfree(wr_buf);
1677 return -EINVAL;
1678 }
1679
1680 for (i = 0; i < MAX_PIPES; i++) {
1681 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1682 if (pipe_ctx->stream &&
1683 pipe_ctx->stream->link == aconnector->dc_link &&
1684 pipe_ctx->stream->sink &&
1685 pipe_ctx->stream->sink == aconnector->dc_sink)
1686 break;
1687 }
1688
1689 if (!pipe_ctx->stream)
1690 goto done;
1691
1692 // Get CRTC state
1693 mutex_lock(&dev->mode_config.mutex);
1694 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1695
1696 if (connector->state == NULL)
1697 goto unlock;
1698
1699 crtc = connector->state->crtc;
1700 if (crtc == NULL)
1701 goto unlock;
1702
1703 drm_modeset_lock(&crtc->mutex, NULL);
1704 if (crtc->state == NULL)
1705 goto unlock;
1706
1707 dm_crtc_state = to_dm_crtc_state(crtc->state);
1708 if (dm_crtc_state->stream == NULL)
1709 goto unlock;
1710
1711 if (param[0] == 1)
1712 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1713 else if (param[0] == 2)
1714 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1715 else
1716 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1717
1718 dm_crtc_state->dsc_force_changed = true;
1719
1720 unlock:
1721 if (crtc)
1722 drm_modeset_unlock(&crtc->mutex);
1723 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1724 mutex_unlock(&dev->mode_config.mutex);
1725
1726 done:
1727 kfree(wr_buf);
1728 return size;
1729 }
1730
1731 /* function: read DSC slice width parameter on the connector
1732 *
1733 * The read function: dp_dsc_slice_width_read
1734 * returns dsc slice width used in the current configuration
1735 * The return is an integer: 0 or other positive number
1736 *
1737 * Access the status with the following command:
1738 *
1739 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1740 *
1741 * 0 - means that DSC is disabled
1742 *
1743 * Any other number more than zero represents the
1744 * slice width currently used by DSC in pixels
1745 *
1746 */
dp_dsc_slice_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1747 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1748 size_t size, loff_t *pos)
1749 {
1750 char *rd_buf = NULL;
1751 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1752 struct display_stream_compressor *dsc;
1753 struct dcn_dsc_state dsc_state = {0};
1754 const uint32_t rd_buf_size = 100;
1755 struct pipe_ctx *pipe_ctx;
1756 ssize_t result = 0;
1757 int i, r, str_len = 30;
1758
1759 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1760
1761 if (!rd_buf)
1762 return -ENOMEM;
1763
1764 for (i = 0; i < MAX_PIPES; i++) {
1765 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1766 if (pipe_ctx->stream &&
1767 pipe_ctx->stream->link == aconnector->dc_link &&
1768 pipe_ctx->stream->sink &&
1769 pipe_ctx->stream->sink == aconnector->dc_sink)
1770 break;
1771 }
1772
1773 dsc = pipe_ctx->stream_res.dsc;
1774 if (dsc)
1775 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1776
1777 snprintf(rd_buf, str_len,
1778 "%d\n",
1779 dsc_state.dsc_slice_width);
1780
1781 while (size) {
1782 if (*pos >= rd_buf_size)
1783 break;
1784
1785 r = put_user(*(rd_buf + result), buf);
1786 if (r) {
1787 kfree(rd_buf);
1788 return r; /* r = -EFAULT */
1789 }
1790
1791 buf += 1;
1792 size -= 1;
1793 *pos += 1;
1794 result += 1;
1795 }
1796
1797 kfree(rd_buf);
1798 return result;
1799 }
1800
1801 /* function: write DSC slice width parameter
1802 *
1803 * The write function: dp_dsc_slice_width_write
1804 * overwrites automatically generated DSC configuration
1805 * of slice width.
1806 *
1807 * The user has to write the slice width divisible by the
1808 * picture width.
1809 *
1810 * Also the user has to write width in hexidecimal
1811 * rather than in decimal.
1812 *
1813 * Writing DSC settings is done with the following command:
1814 * - To force overwrite slice width: (example sets to 1920 pixels)
1815 *
1816 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1817 *
1818 * - To stop overwriting and let driver find the optimal size,
1819 * set the width to zero:
1820 *
1821 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1822 *
1823 */
dp_dsc_slice_width_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)1824 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1825 size_t size, loff_t *pos)
1826 {
1827 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1828 struct pipe_ctx *pipe_ctx;
1829 struct drm_connector *connector = &aconnector->base;
1830 struct drm_device *dev = connector->dev;
1831 struct drm_crtc *crtc = NULL;
1832 struct dm_crtc_state *dm_crtc_state = NULL;
1833 int i;
1834 char *wr_buf = NULL;
1835 uint32_t wr_buf_size = 42;
1836 int max_param_num = 1;
1837 long param[1] = {0};
1838 uint8_t param_nums = 0;
1839
1840 if (size == 0)
1841 return -EINVAL;
1842
1843 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1844
1845 if (!wr_buf) {
1846 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1847 return -ENOSPC;
1848 }
1849
1850 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1851 (long *)param, buf,
1852 max_param_num,
1853 ¶m_nums)) {
1854 kfree(wr_buf);
1855 return -EINVAL;
1856 }
1857
1858 if (param_nums <= 0) {
1859 DRM_DEBUG_DRIVER("user data not be read\n");
1860 kfree(wr_buf);
1861 return -EINVAL;
1862 }
1863
1864 for (i = 0; i < MAX_PIPES; i++) {
1865 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1866 if (pipe_ctx->stream &&
1867 pipe_ctx->stream->link == aconnector->dc_link &&
1868 pipe_ctx->stream->sink &&
1869 pipe_ctx->stream->sink == aconnector->dc_sink)
1870 break;
1871 }
1872
1873 if (!pipe_ctx->stream)
1874 goto done;
1875
1876 // Safely get CRTC state
1877 mutex_lock(&dev->mode_config.mutex);
1878 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1879
1880 if (connector->state == NULL)
1881 goto unlock;
1882
1883 crtc = connector->state->crtc;
1884 if (crtc == NULL)
1885 goto unlock;
1886
1887 drm_modeset_lock(&crtc->mutex, NULL);
1888 if (crtc->state == NULL)
1889 goto unlock;
1890
1891 dm_crtc_state = to_dm_crtc_state(crtc->state);
1892 if (dm_crtc_state->stream == NULL)
1893 goto unlock;
1894
1895 if (param[0] > 0)
1896 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1897 pipe_ctx->stream->timing.h_addressable,
1898 param[0]);
1899 else
1900 aconnector->dsc_settings.dsc_num_slices_h = 0;
1901
1902 dm_crtc_state->dsc_force_changed = true;
1903
1904 unlock:
1905 if (crtc)
1906 drm_modeset_unlock(&crtc->mutex);
1907 drm_modeset_unlock(&dev->mode_config.connection_mutex);
1908 mutex_unlock(&dev->mode_config.mutex);
1909
1910 done:
1911 kfree(wr_buf);
1912 return size;
1913 }
1914
1915 /* function: read DSC slice height parameter on the connector
1916 *
1917 * The read function: dp_dsc_slice_height_read
1918 * returns dsc slice height used in the current configuration
1919 * The return is an integer: 0 or other positive number
1920 *
1921 * Access the status with the following command:
1922 *
1923 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1924 *
1925 * 0 - means that DSC is disabled
1926 *
1927 * Any other number more than zero represents the
1928 * slice height currently used by DSC in pixels
1929 *
1930 */
dp_dsc_slice_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1931 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1932 size_t size, loff_t *pos)
1933 {
1934 char *rd_buf = NULL;
1935 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1936 struct display_stream_compressor *dsc;
1937 struct dcn_dsc_state dsc_state = {0};
1938 const uint32_t rd_buf_size = 100;
1939 struct pipe_ctx *pipe_ctx;
1940 ssize_t result = 0;
1941 int i, r, str_len = 30;
1942
1943 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1944
1945 if (!rd_buf)
1946 return -ENOMEM;
1947
1948 for (i = 0; i < MAX_PIPES; i++) {
1949 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1950 if (pipe_ctx->stream &&
1951 pipe_ctx->stream->link == aconnector->dc_link &&
1952 pipe_ctx->stream->sink &&
1953 pipe_ctx->stream->sink == aconnector->dc_sink)
1954 break;
1955 }
1956
1957 dsc = pipe_ctx->stream_res.dsc;
1958 if (dsc)
1959 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1960
1961 snprintf(rd_buf, str_len,
1962 "%d\n",
1963 dsc_state.dsc_slice_height);
1964
1965 while (size) {
1966 if (*pos >= rd_buf_size)
1967 break;
1968
1969 r = put_user(*(rd_buf + result), buf);
1970 if (r) {
1971 kfree(rd_buf);
1972 return r; /* r = -EFAULT */
1973 }
1974
1975 buf += 1;
1976 size -= 1;
1977 *pos += 1;
1978 result += 1;
1979 }
1980
1981 kfree(rd_buf);
1982 return result;
1983 }
1984
1985 /* function: write DSC slice height parameter
1986 *
1987 * The write function: dp_dsc_slice_height_write
1988 * overwrites automatically generated DSC configuration
1989 * of slice height.
1990 *
1991 * The user has to write the slice height divisible by the
1992 * picture height.
1993 *
1994 * Also the user has to write height in hexidecimal
1995 * rather than in decimal.
1996 *
1997 * Writing DSC settings is done with the following command:
1998 * - To force overwrite slice height (example sets to 128 pixels):
1999 *
2000 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2001 *
2002 * - To stop overwriting and let driver find the optimal size,
2003 * set the height to zero:
2004 *
2005 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2006 *
2007 */
dp_dsc_slice_height_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2008 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
2009 size_t size, loff_t *pos)
2010 {
2011 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2012 struct drm_connector *connector = &aconnector->base;
2013 struct drm_device *dev = connector->dev;
2014 struct drm_crtc *crtc = NULL;
2015 struct dm_crtc_state *dm_crtc_state = NULL;
2016 struct pipe_ctx *pipe_ctx;
2017 int i;
2018 char *wr_buf = NULL;
2019 uint32_t wr_buf_size = 42;
2020 int max_param_num = 1;
2021 uint8_t param_nums = 0;
2022 long param[1] = {0};
2023
2024 if (size == 0)
2025 return -EINVAL;
2026
2027 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2028
2029 if (!wr_buf) {
2030 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2031 return -ENOSPC;
2032 }
2033
2034 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2035 (long *)param, buf,
2036 max_param_num,
2037 ¶m_nums)) {
2038 kfree(wr_buf);
2039 return -EINVAL;
2040 }
2041
2042 if (param_nums <= 0) {
2043 DRM_DEBUG_DRIVER("user data not be read\n");
2044 kfree(wr_buf);
2045 return -EINVAL;
2046 }
2047
2048 for (i = 0; i < MAX_PIPES; i++) {
2049 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2050 if (pipe_ctx->stream &&
2051 pipe_ctx->stream->link == aconnector->dc_link &&
2052 pipe_ctx->stream->sink &&
2053 pipe_ctx->stream->sink == aconnector->dc_sink)
2054 break;
2055 }
2056
2057 if (!pipe_ctx->stream)
2058 goto done;
2059
2060 // Get CRTC state
2061 mutex_lock(&dev->mode_config.mutex);
2062 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2063
2064 if (connector->state == NULL)
2065 goto unlock;
2066
2067 crtc = connector->state->crtc;
2068 if (crtc == NULL)
2069 goto unlock;
2070
2071 drm_modeset_lock(&crtc->mutex, NULL);
2072 if (crtc->state == NULL)
2073 goto unlock;
2074
2075 dm_crtc_state = to_dm_crtc_state(crtc->state);
2076 if (dm_crtc_state->stream == NULL)
2077 goto unlock;
2078
2079 if (param[0] > 0)
2080 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2081 pipe_ctx->stream->timing.v_addressable,
2082 param[0]);
2083 else
2084 aconnector->dsc_settings.dsc_num_slices_v = 0;
2085
2086 dm_crtc_state->dsc_force_changed = true;
2087
2088 unlock:
2089 if (crtc)
2090 drm_modeset_unlock(&crtc->mutex);
2091 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2092 mutex_unlock(&dev->mode_config.mutex);
2093
2094 done:
2095 kfree(wr_buf);
2096 return size;
2097 }
2098
2099 /* function: read DSC target rate on the connector in bits per pixel
2100 *
2101 * The read function: dp_dsc_bits_per_pixel_read
2102 * returns target rate of compression in bits per pixel
2103 * The return is an integer: 0 or other positive integer
2104 *
2105 * Access it with the following command:
2106 *
2107 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2108 *
2109 * 0 - means that DSC is disabled
2110 */
dp_dsc_bits_per_pixel_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2111 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2112 size_t size, loff_t *pos)
2113 {
2114 char *rd_buf = NULL;
2115 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2116 struct display_stream_compressor *dsc;
2117 struct dcn_dsc_state dsc_state = {0};
2118 const uint32_t rd_buf_size = 100;
2119 struct pipe_ctx *pipe_ctx;
2120 ssize_t result = 0;
2121 int i, r, str_len = 30;
2122
2123 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2124
2125 if (!rd_buf)
2126 return -ENOMEM;
2127
2128 for (i = 0; i < MAX_PIPES; i++) {
2129 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2130 if (pipe_ctx->stream &&
2131 pipe_ctx->stream->link == aconnector->dc_link &&
2132 pipe_ctx->stream->sink &&
2133 pipe_ctx->stream->sink == aconnector->dc_sink)
2134 break;
2135 }
2136
2137 dsc = pipe_ctx->stream_res.dsc;
2138 if (dsc)
2139 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2140
2141 snprintf(rd_buf, str_len,
2142 "%d\n",
2143 dsc_state.dsc_bits_per_pixel);
2144
2145 while (size) {
2146 if (*pos >= rd_buf_size)
2147 break;
2148
2149 r = put_user(*(rd_buf + result), buf);
2150 if (r) {
2151 kfree(rd_buf);
2152 return r; /* r = -EFAULT */
2153 }
2154
2155 buf += 1;
2156 size -= 1;
2157 *pos += 1;
2158 result += 1;
2159 }
2160
2161 kfree(rd_buf);
2162 return result;
2163 }
2164
2165 /* function: write DSC target rate in bits per pixel
2166 *
2167 * The write function: dp_dsc_bits_per_pixel_write
2168 * overwrites automatically generated DSC configuration
2169 * of DSC target bit rate.
2170 *
2171 * Also the user has to write bpp in hexidecimal
2172 * rather than in decimal.
2173 *
2174 * Writing DSC settings is done with the following command:
2175 * - To force overwrite rate (example sets to 256 bpp x 1/16):
2176 *
2177 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2178 *
2179 * - To stop overwriting and let driver find the optimal rate,
2180 * set the rate to zero:
2181 *
2182 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2183 *
2184 */
dp_dsc_bits_per_pixel_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2185 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2186 size_t size, loff_t *pos)
2187 {
2188 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2189 struct drm_connector *connector = &aconnector->base;
2190 struct drm_device *dev = connector->dev;
2191 struct drm_crtc *crtc = NULL;
2192 struct dm_crtc_state *dm_crtc_state = NULL;
2193 struct pipe_ctx *pipe_ctx;
2194 int i;
2195 char *wr_buf = NULL;
2196 uint32_t wr_buf_size = 42;
2197 int max_param_num = 1;
2198 uint8_t param_nums = 0;
2199 long param[1] = {0};
2200
2201 if (size == 0)
2202 return -EINVAL;
2203
2204 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2205
2206 if (!wr_buf) {
2207 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2208 return -ENOSPC;
2209 }
2210
2211 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2212 (long *)param, buf,
2213 max_param_num,
2214 ¶m_nums)) {
2215 kfree(wr_buf);
2216 return -EINVAL;
2217 }
2218
2219 if (param_nums <= 0) {
2220 DRM_DEBUG_DRIVER("user data not be read\n");
2221 kfree(wr_buf);
2222 return -EINVAL;
2223 }
2224
2225 for (i = 0; i < MAX_PIPES; i++) {
2226 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2227 if (pipe_ctx->stream &&
2228 pipe_ctx->stream->link == aconnector->dc_link &&
2229 pipe_ctx->stream->sink &&
2230 pipe_ctx->stream->sink == aconnector->dc_sink)
2231 break;
2232 }
2233
2234 if (!pipe_ctx->stream)
2235 goto done;
2236
2237 // Get CRTC state
2238 mutex_lock(&dev->mode_config.mutex);
2239 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2240
2241 if (connector->state == NULL)
2242 goto unlock;
2243
2244 crtc = connector->state->crtc;
2245 if (crtc == NULL)
2246 goto unlock;
2247
2248 drm_modeset_lock(&crtc->mutex, NULL);
2249 if (crtc->state == NULL)
2250 goto unlock;
2251
2252 dm_crtc_state = to_dm_crtc_state(crtc->state);
2253 if (dm_crtc_state->stream == NULL)
2254 goto unlock;
2255
2256 aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2257
2258 dm_crtc_state->dsc_force_changed = true;
2259
2260 unlock:
2261 if (crtc)
2262 drm_modeset_unlock(&crtc->mutex);
2263 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2264 mutex_unlock(&dev->mode_config.mutex);
2265
2266 done:
2267 kfree(wr_buf);
2268 return size;
2269 }
2270
2271 /* function: read DSC picture width parameter on the connector
2272 *
2273 * The read function: dp_dsc_pic_width_read
2274 * returns dsc picture width used in the current configuration
2275 * It is the same as h_addressable of the current
2276 * display's timing
2277 * The return is an integer: 0 or other positive integer
2278 * If 0 then DSC is disabled.
2279 *
2280 * Access it with the following command:
2281 *
2282 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2283 *
2284 * 0 - means that DSC is disabled
2285 */
dp_dsc_pic_width_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2286 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2287 size_t size, loff_t *pos)
2288 {
2289 char *rd_buf = NULL;
2290 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2291 struct display_stream_compressor *dsc;
2292 struct dcn_dsc_state dsc_state = {0};
2293 const uint32_t rd_buf_size = 100;
2294 struct pipe_ctx *pipe_ctx;
2295 ssize_t result = 0;
2296 int i, r, str_len = 30;
2297
2298 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2299
2300 if (!rd_buf)
2301 return -ENOMEM;
2302
2303 for (i = 0; i < MAX_PIPES; i++) {
2304 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2305 if (pipe_ctx->stream &&
2306 pipe_ctx->stream->link == aconnector->dc_link &&
2307 pipe_ctx->stream->sink &&
2308 pipe_ctx->stream->sink == aconnector->dc_sink)
2309 break;
2310 }
2311
2312 dsc = pipe_ctx->stream_res.dsc;
2313 if (dsc)
2314 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2315
2316 snprintf(rd_buf, str_len,
2317 "%d\n",
2318 dsc_state.dsc_pic_width);
2319
2320 while (size) {
2321 if (*pos >= rd_buf_size)
2322 break;
2323
2324 r = put_user(*(rd_buf + result), buf);
2325 if (r) {
2326 kfree(rd_buf);
2327 return r; /* r = -EFAULT */
2328 }
2329
2330 buf += 1;
2331 size -= 1;
2332 *pos += 1;
2333 result += 1;
2334 }
2335
2336 kfree(rd_buf);
2337 return result;
2338 }
2339
dp_dsc_pic_height_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2340 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2341 size_t size, loff_t *pos)
2342 {
2343 char *rd_buf = NULL;
2344 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2345 struct display_stream_compressor *dsc;
2346 struct dcn_dsc_state dsc_state = {0};
2347 const uint32_t rd_buf_size = 100;
2348 struct pipe_ctx *pipe_ctx;
2349 ssize_t result = 0;
2350 int i, r, str_len = 30;
2351
2352 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2353
2354 if (!rd_buf)
2355 return -ENOMEM;
2356
2357 for (i = 0; i < MAX_PIPES; i++) {
2358 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2359 if (pipe_ctx->stream &&
2360 pipe_ctx->stream->link == aconnector->dc_link &&
2361 pipe_ctx->stream->sink &&
2362 pipe_ctx->stream->sink == aconnector->dc_sink)
2363 break;
2364 }
2365
2366 dsc = pipe_ctx->stream_res.dsc;
2367 if (dsc)
2368 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2369
2370 snprintf(rd_buf, str_len,
2371 "%d\n",
2372 dsc_state.dsc_pic_height);
2373
2374 while (size) {
2375 if (*pos >= rd_buf_size)
2376 break;
2377
2378 r = put_user(*(rd_buf + result), buf);
2379 if (r) {
2380 kfree(rd_buf);
2381 return r; /* r = -EFAULT */
2382 }
2383
2384 buf += 1;
2385 size -= 1;
2386 *pos += 1;
2387 result += 1;
2388 }
2389
2390 kfree(rd_buf);
2391 return result;
2392 }
2393
2394 /* function: read DSC chunk size parameter on the connector
2395 *
2396 * The read function: dp_dsc_chunk_size_read
2397 * returns dsc chunk size set in the current configuration
2398 * The value is calculated automatically by DSC code
2399 * and depends on slice parameters and bpp target rate
2400 * The return is an integer: 0 or other positive integer
2401 * If 0 then DSC is disabled.
2402 *
2403 * Access it with the following command:
2404 *
2405 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2406 *
2407 * 0 - means that DSC is disabled
2408 */
dp_dsc_chunk_size_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2409 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2410 size_t size, loff_t *pos)
2411 {
2412 char *rd_buf = NULL;
2413 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2414 struct display_stream_compressor *dsc;
2415 struct dcn_dsc_state dsc_state = {0};
2416 const uint32_t rd_buf_size = 100;
2417 struct pipe_ctx *pipe_ctx;
2418 ssize_t result = 0;
2419 int i, r, str_len = 30;
2420
2421 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2422
2423 if (!rd_buf)
2424 return -ENOMEM;
2425
2426 for (i = 0; i < MAX_PIPES; i++) {
2427 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2428 if (pipe_ctx->stream &&
2429 pipe_ctx->stream->link == aconnector->dc_link &&
2430 pipe_ctx->stream->sink &&
2431 pipe_ctx->stream->sink == aconnector->dc_sink)
2432 break;
2433 }
2434
2435 dsc = pipe_ctx->stream_res.dsc;
2436 if (dsc)
2437 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2438
2439 snprintf(rd_buf, str_len,
2440 "%d\n",
2441 dsc_state.dsc_chunk_size);
2442
2443 while (size) {
2444 if (*pos >= rd_buf_size)
2445 break;
2446
2447 r = put_user(*(rd_buf + result), buf);
2448 if (r) {
2449 kfree(rd_buf);
2450 return r; /* r = -EFAULT */
2451 }
2452
2453 buf += 1;
2454 size -= 1;
2455 *pos += 1;
2456 result += 1;
2457 }
2458
2459 kfree(rd_buf);
2460 return result;
2461 }
2462
2463 /* function: read DSC slice bpg offset on the connector
2464 *
2465 * The read function: dp_dsc_slice_bpg_offset_read
2466 * returns dsc bpg slice offset set in the current configuration
2467 * The value is calculated automatically by DSC code
2468 * and depends on slice parameters and bpp target rate
2469 * The return is an integer: 0 or other positive integer
2470 * If 0 then DSC is disabled.
2471 *
2472 * Access it with the following command:
2473 *
2474 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2475 *
2476 * 0 - means that DSC is disabled
2477 */
dp_dsc_slice_bpg_offset_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2478 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2479 size_t size, loff_t *pos)
2480 {
2481 char *rd_buf = NULL;
2482 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2483 struct display_stream_compressor *dsc;
2484 struct dcn_dsc_state dsc_state = {0};
2485 const uint32_t rd_buf_size = 100;
2486 struct pipe_ctx *pipe_ctx;
2487 ssize_t result = 0;
2488 int i, r, str_len = 30;
2489
2490 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2491
2492 if (!rd_buf)
2493 return -ENOMEM;
2494
2495 for (i = 0; i < MAX_PIPES; i++) {
2496 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2497 if (pipe_ctx->stream &&
2498 pipe_ctx->stream->link == aconnector->dc_link &&
2499 pipe_ctx->stream->sink &&
2500 pipe_ctx->stream->sink == aconnector->dc_sink)
2501 break;
2502 }
2503
2504 dsc = pipe_ctx->stream_res.dsc;
2505 if (dsc)
2506 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2507
2508 snprintf(rd_buf, str_len,
2509 "%d\n",
2510 dsc_state.dsc_slice_bpg_offset);
2511
2512 while (size) {
2513 if (*pos >= rd_buf_size)
2514 break;
2515
2516 r = put_user(*(rd_buf + result), buf);
2517 if (r) {
2518 kfree(rd_buf);
2519 return r; /* r = -EFAULT */
2520 }
2521
2522 buf += 1;
2523 size -= 1;
2524 *pos += 1;
2525 result += 1;
2526 }
2527
2528 kfree(rd_buf);
2529 return result;
2530 }
2531
2532
2533 /*
2534 * function description: Read max_requested_bpc property from the connector
2535 *
2536 * Access it with the following command:
2537 *
2538 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2539 *
2540 */
dp_max_bpc_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2541 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2542 size_t size, loff_t *pos)
2543 {
2544 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2545 struct drm_connector *connector = &aconnector->base;
2546 struct drm_device *dev = connector->dev;
2547 struct dm_connector_state *state;
2548 ssize_t result = 0;
2549 char *rd_buf = NULL;
2550 char *rd_buf_ptr = NULL;
2551 const uint32_t rd_buf_size = 10;
2552 int r;
2553
2554 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2555
2556 if (!rd_buf)
2557 return -ENOMEM;
2558
2559 mutex_lock(&dev->mode_config.mutex);
2560 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2561
2562 if (connector->state == NULL)
2563 goto unlock;
2564
2565 state = to_dm_connector_state(connector->state);
2566
2567 rd_buf_ptr = rd_buf;
2568 snprintf(rd_buf_ptr, rd_buf_size,
2569 "%u\n",
2570 state->base.max_requested_bpc);
2571
2572 while (size) {
2573 if (*pos >= rd_buf_size)
2574 break;
2575
2576 r = put_user(*(rd_buf + result), buf);
2577 if (r) {
2578 result = r; /* r = -EFAULT */
2579 goto unlock;
2580 }
2581 buf += 1;
2582 size -= 1;
2583 *pos += 1;
2584 result += 1;
2585 }
2586 unlock:
2587 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2588 mutex_unlock(&dev->mode_config.mutex);
2589 kfree(rd_buf);
2590 return result;
2591 }
2592
2593
2594 /*
2595 * function description: Set max_requested_bpc property on the connector
2596 *
2597 * This function will not force the input BPC on connector, it will only
2598 * change the max value. This is equivalent to setting max_bpc through
2599 * xrandr.
2600 *
2601 * The BPC value written must be >= 6 and <= 16. Values outside of this
2602 * range will result in errors.
2603 *
2604 * BPC values:
2605 * 0x6 - 6 BPC
2606 * 0x8 - 8 BPC
2607 * 0xa - 10 BPC
2608 * 0xc - 12 BPC
2609 * 0x10 - 16 BPC
2610 *
2611 * Write the max_bpc in the following way:
2612 *
2613 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2614 *
2615 */
dp_max_bpc_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2616 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2617 size_t size, loff_t *pos)
2618 {
2619 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2620 struct drm_connector *connector = &aconnector->base;
2621 struct dm_connector_state *state;
2622 struct drm_device *dev = connector->dev;
2623 char *wr_buf = NULL;
2624 uint32_t wr_buf_size = 42;
2625 int max_param_num = 1;
2626 long param[1] = {0};
2627 uint8_t param_nums = 0;
2628
2629 if (size == 0)
2630 return -EINVAL;
2631
2632 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2633
2634 if (!wr_buf) {
2635 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2636 return -ENOSPC;
2637 }
2638
2639 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2640 (long *)param, buf,
2641 max_param_num,
2642 ¶m_nums)) {
2643 kfree(wr_buf);
2644 return -EINVAL;
2645 }
2646
2647 if (param_nums <= 0) {
2648 DRM_DEBUG_DRIVER("user data not be read\n");
2649 kfree(wr_buf);
2650 return -EINVAL;
2651 }
2652
2653 if (param[0] < 6 || param[0] > 16) {
2654 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2655 kfree(wr_buf);
2656 return -EINVAL;
2657 }
2658
2659 mutex_lock(&dev->mode_config.mutex);
2660 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2661
2662 if (connector->state == NULL)
2663 goto unlock;
2664
2665 state = to_dm_connector_state(connector->state);
2666 state->base.max_requested_bpc = param[0];
2667 unlock:
2668 drm_modeset_unlock(&dev->mode_config.connection_mutex);
2669 mutex_unlock(&dev->mode_config.mutex);
2670
2671 kfree(wr_buf);
2672 return size;
2673 }
2674
2675 /*
2676 * IPS status. Read only.
2677 *
2678 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2679 */
ips_status_show(struct seq_file * m,void * unused)2680 static int ips_status_show(struct seq_file *m, void *unused)
2681 {
2682 struct amdgpu_device *adev = m->private;
2683 struct dc *dc = adev->dm.dc;
2684 struct dc_dmub_srv *dc_dmub_srv;
2685
2686 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips);
2687 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2688
2689 if (adev->dm.idle_workqueue) {
2690 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2691 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2692 }
2693
2694 dc_dmub_srv = dc->ctx->dmub_srv;
2695 if (dc_dmub_srv && dc_dmub_srv->dmub) {
2696 uint32_t rcg_count, ips1_count, ips2_count;
2697 volatile const struct dmub_shared_state_ips_fw *ips_fw =
2698 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2699 rcg_count = ips_fw->rcg_entry_count;
2700 ips1_count = ips_fw->ips1_entry_count;
2701 ips2_count = ips_fw->ips2_entry_count;
2702 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n",
2703 rcg_count,
2704 ips1_count,
2705 ips2_count);
2706 rcg_count = ips_fw->rcg_exit_count;
2707 ips1_count = ips_fw->ips1_exit_count;
2708 ips2_count = ips_fw->ips2_exit_count;
2709 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u\n",
2710 rcg_count,
2711 ips1_count,
2712 ips2_count);
2713 }
2714 return 0;
2715 }
2716
2717 /*
2718 * IPS residency information from DMUB service. Read only.
2719 *
2720 * For time-window (segment) measurement:
2721 * 1) echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2722 * 2) sleep <seconds>
2723 * 3) echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl
2724 * 4) cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency
2725 */
ips_residency_show(struct seq_file * m,void * unused)2726 static int ips_residency_show(struct seq_file *m, void *unused)
2727 {
2728 struct amdgpu_device *adev = m->private;
2729 struct dc *dc = adev->dm.dc;
2730 uint8_t panel_inst = 0;
2731 enum ips_residency_mode mode;
2732 struct dmub_ips_residency_info info;
2733
2734 mutex_lock(&adev->dm.dc_lock);
2735
2736 mode = IPS_RESIDENCY__IPS1_RCG;
2737 if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) {
2738 seq_printf(m, "ISP query failed\n");
2739 } else {
2740 unsigned int pct, frac;
2741 pct = info.residency_millipercent / 1000;
2742 frac = info.residency_millipercent % 1000;
2743
2744 seq_printf(m, "IPS residency: %u.%03u%% \n", pct, frac);
2745 seq_printf(m, " entry_counter: %u\n", info.entry_counter);
2746 seq_printf(m, " total_time_us: %llu\n",
2747 (unsigned long long)info.total_time_us);
2748 seq_printf(m, " total_inactive_time_us: %llu\n",
2749 (unsigned long long)info.total_inactive_time_us);
2750 }
2751 mutex_unlock(&adev->dm.dc_lock);
2752 return 0;
2753 }
2754
ips_residency_cntl_get(void * data,u64 * val)2755 static int ips_residency_cntl_get(void *data, u64 *val)
2756 {
2757 *val = 0;
2758 return 0;
2759 }
2760
ips_residency_cntl_set(void * data,u64 val)2761 static int ips_residency_cntl_set(void *data, u64 val)
2762 {
2763 struct amdgpu_device *adev = data;
2764 struct dc *dc = adev->dm.dc;
2765 uint8_t panel_inst = 0;
2766 int ret = 0;
2767
2768 mutex_lock(&adev->dm.dc_lock);
2769 if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val))
2770 ret = -EIO;
2771 mutex_unlock(&adev->dm.dc_lock);
2772
2773 return ret;
2774 }
2775
2776 /*
2777 * Backlight at this moment. Read only.
2778 * As written to display, taking ABM and backlight lut into account.
2779 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2780 *
2781 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2782 */
current_backlight_show(struct seq_file * m,void * unused)2783 static int current_backlight_show(struct seq_file *m, void *unused)
2784 {
2785 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2786 struct dc_link *link = aconnector->dc_link;
2787 unsigned int backlight;
2788
2789 backlight = dc_link_get_backlight_level(link);
2790 seq_printf(m, "0x%x\n", backlight);
2791
2792 return 0;
2793 }
2794
2795 /*
2796 * Backlight value that is being approached. Read only.
2797 * As written to display, taking ABM and backlight lut into account.
2798 * Ranges from 0x0 to 0x10000 (= 100% PWM)
2799 *
2800 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2801 */
target_backlight_show(struct seq_file * m,void * unused)2802 static int target_backlight_show(struct seq_file *m, void *unused)
2803 {
2804 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2805 struct dc_link *link = aconnector->dc_link;
2806 unsigned int backlight;
2807
2808 backlight = dc_link_get_target_backlight_pwm(link);
2809 seq_printf(m, "0x%x\n", backlight);
2810
2811 return 0;
2812 }
2813
2814 /*
2815 * function description: Determine if the connector is mst connector
2816 *
2817 * This function helps to determine whether a connector is a mst connector.
2818 * - "root" stands for the root connector of the topology
2819 * - "branch" stands for branch device of the topology
2820 * - "end" stands for leaf node connector of the topology
2821 * - "no" stands for the connector is not a device of a mst topology
2822 * Access it with the following command:
2823 *
2824 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2825 *
2826 */
dp_is_mst_connector_show(struct seq_file * m,void * unused)2827 static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2828 {
2829 struct drm_connector *connector = m->private;
2830 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2831 struct drm_dp_mst_topology_mgr *mgr = NULL;
2832 struct drm_dp_mst_port *port = NULL;
2833 char *role = NULL;
2834
2835 mutex_lock(&aconnector->hpd_lock);
2836
2837 if (aconnector->mst_mgr.mst_state) {
2838 role = "root";
2839 } else if (aconnector->mst_root &&
2840 aconnector->mst_root->mst_mgr.mst_state) {
2841
2842 role = "end";
2843
2844 mgr = &aconnector->mst_root->mst_mgr;
2845 port = aconnector->mst_output_port;
2846
2847 drm_modeset_lock(&mgr->base.lock, NULL);
2848 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2849 port->mcs)
2850 role = "branch";
2851 drm_modeset_unlock(&mgr->base.lock);
2852
2853 } else {
2854 role = "no";
2855 }
2856
2857 seq_printf(m, "%s\n", role);
2858
2859 mutex_unlock(&aconnector->hpd_lock);
2860
2861 return 0;
2862 }
2863
2864 /*
2865 * function description: Read out the mst progress status
2866 *
2867 * This function helps to determine the mst progress status of
2868 * a mst connector.
2869 *
2870 * Access it with the following command:
2871 *
2872 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2873 *
2874 */
dp_mst_progress_status_show(struct seq_file * m,void * unused)2875 static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2876 {
2877 struct drm_connector *connector = m->private;
2878 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2879 struct amdgpu_device *adev = drm_to_adev(connector->dev);
2880 int i;
2881
2882 mutex_lock(&aconnector->hpd_lock);
2883 mutex_lock(&adev->dm.dc_lock);
2884
2885 if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2886 seq_puts(m, "disabled\n");
2887 } else {
2888 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2889 seq_printf(m, "%s:%s\n",
2890 mst_progress_status[i],
2891 aconnector->mst_status & BIT(i) ? "done" : "not_done");
2892 }
2893
2894 mutex_unlock(&adev->dm.dc_lock);
2895 mutex_unlock(&aconnector->hpd_lock);
2896
2897 return 0;
2898 }
2899
2900 /*
2901 * Reports whether the connected display is a USB4 DPIA tunneled display
2902 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2903 */
is_dpia_link_show(struct seq_file * m,void * data)2904 static int is_dpia_link_show(struct seq_file *m, void *data)
2905 {
2906 struct drm_connector *connector = m->private;
2907 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2908 struct dc_link *link = aconnector->dc_link;
2909
2910 if (connector->status != connector_status_connected)
2911 return -ENODEV;
2912
2913 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2914 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2915
2916 return 0;
2917 }
2918
2919 /**
2920 * hdmi_cec_state_show - Read out the HDMI-CEC feature status
2921 * @m: sequence file.
2922 * @data: unused.
2923 *
2924 * Return 0 on success
2925 */
hdmi_cec_state_show(struct seq_file * m,void * data)2926 static int hdmi_cec_state_show(struct seq_file *m, void *data)
2927 {
2928 struct drm_connector *connector = m->private;
2929 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2930
2931 seq_printf(m, "%s:%d\n", connector->name, connector->base.id);
2932 seq_printf(m, "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0);
2933
2934 return 0;
2935 }
2936
2937 /**
2938 * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side
2939 * @f: file structure.
2940 * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.
2941 * @size: size of buffer from userpsace.
2942 * @pos: unused.
2943 *
2944 * Return size on success, error code on failure
2945 */
hdmi_cec_state_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2946 static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,
2947 size_t size, loff_t *pos)
2948 {
2949 int ret;
2950 bool enable;
2951 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2952 struct drm_device *ddev = aconnector->base.dev;
2953
2954 if (size == 0)
2955 return -EINVAL;
2956
2957 ret = kstrtobool_from_user(buf, size, &enable);
2958 if (ret) {
2959 drm_dbg_driver(ddev, "invalid user data !\n");
2960 return ret;
2961 }
2962
2963 if (enable) {
2964 if (aconnector->notifier)
2965 return -EINVAL;
2966 ret = amdgpu_dm_initialize_hdmi_connector(aconnector);
2967 if (ret)
2968 return ret;
2969 amdgpu_dm_hdmi_cec_set_edid(aconnector);
2970 } else {
2971 if (!aconnector->notifier)
2972 return -EINVAL;
2973 cec_notifier_conn_unregister(aconnector->notifier);
2974 aconnector->notifier = NULL;
2975 }
2976
2977 return size;
2978 }
2979
2980 /**
2981 * hdmi_automation_enable - Enable/Disable HDMI automation feature
2982 * @f: file structure.
2983 * @buf: userspace buffer. set to '1' to enable; '0' to disable automation feature.
2984 * @size: size of buffer from userpsace.
2985 * @pos: unused.
2986 *
2987 * Return size on success, error code on failure
2988 */
hdmi_automation_enable(struct file * f,const char __user * buf,size_t size,loff_t * pos)2989 static ssize_t hdmi_automation_enable(struct file *f, const char __user *buf,
2990 size_t size, loff_t *pos)
2991 {
2992 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2993 char *wr_buf = NULL;
2994 const uint32_t wr_buf_size = 40;
2995 int max_param_num = 1;
2996 uint8_t param_nums = 0;
2997 long param[2];
2998 bool hdmi_comp_auto;
2999
3000 if (size == 0)
3001 return -EINVAL;
3002
3003 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3004 if (!wr_buf)
3005 return -ENOSPC;
3006
3007 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3008 (long *)param, buf,
3009 max_param_num,
3010 ¶m_nums)) {
3011 kfree(wr_buf);
3012 return -EINVAL;
3013 }
3014
3015 if (param_nums <= 0) {
3016 kfree(wr_buf);
3017 DRM_DEBUG_DRIVER("user data not be read\n");
3018 return -EINVAL;
3019 }
3020
3021 switch (param[0]) {
3022 case 0:
3023 hdmi_comp_auto = false;
3024 break;
3025 case 1:
3026 default:
3027 hdmi_comp_auto = true;
3028 break;
3029 }
3030
3031 /* Persist setting across sink re-detection/hotplug. */
3032 aconnector->hdmi_comp_auto = hdmi_comp_auto;
3033
3034 kfree(wr_buf);
3035 return size;
3036 }
3037
3038 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
3039 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
3040 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
3041 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
3042 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
3043 DEFINE_SHOW_ATTRIBUTE(internal_display);
3044 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
3045 DEFINE_SHOW_ATTRIBUTE(replay_capability);
3046 DEFINE_SHOW_ATTRIBUTE(psr_capability);
3047 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
3048 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
3049 DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
3050 DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);
3051
3052 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
3053 .owner = THIS_MODULE,
3054 .read = dp_dsc_clock_en_read,
3055 .write = dp_dsc_clock_en_write,
3056 .llseek = default_llseek
3057 };
3058
3059 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
3060 .owner = THIS_MODULE,
3061 .read = dp_dsc_slice_width_read,
3062 .write = dp_dsc_slice_width_write,
3063 .llseek = default_llseek
3064 };
3065
3066 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
3067 .owner = THIS_MODULE,
3068 .read = dp_dsc_slice_height_read,
3069 .write = dp_dsc_slice_height_write,
3070 .llseek = default_llseek
3071 };
3072
3073 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
3074 .owner = THIS_MODULE,
3075 .read = dp_dsc_bits_per_pixel_read,
3076 .write = dp_dsc_bits_per_pixel_write,
3077 .llseek = default_llseek
3078 };
3079
3080 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
3081 .owner = THIS_MODULE,
3082 .read = dp_dsc_pic_width_read,
3083 .llseek = default_llseek
3084 };
3085
3086 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
3087 .owner = THIS_MODULE,
3088 .read = dp_dsc_pic_height_read,
3089 .llseek = default_llseek
3090 };
3091
3092 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
3093 .owner = THIS_MODULE,
3094 .read = dp_dsc_chunk_size_read,
3095 .llseek = default_llseek
3096 };
3097
3098 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
3099 .owner = THIS_MODULE,
3100 .read = dp_dsc_slice_bpg_offset_read,
3101 .llseek = default_llseek
3102 };
3103
3104 static const struct file_operations trigger_hotplug_debugfs_fops = {
3105 .owner = THIS_MODULE,
3106 .write = trigger_hotplug,
3107 .llseek = default_llseek
3108 };
3109
3110 static const struct file_operations dp_link_settings_debugfs_fops = {
3111 .owner = THIS_MODULE,
3112 .read = dp_link_settings_read,
3113 .write = dp_link_settings_write,
3114 .llseek = default_llseek
3115 };
3116
3117 static const struct file_operations dp_phy_settings_debugfs_fop = {
3118 .owner = THIS_MODULE,
3119 .read = dp_phy_settings_read,
3120 .write = dp_phy_settings_write,
3121 .llseek = default_llseek
3122 };
3123
3124 static const struct file_operations dp_phy_test_pattern_fops = {
3125 .owner = THIS_MODULE,
3126 .write = dp_phy_test_pattern_debugfs_write,
3127 .llseek = default_llseek
3128 };
3129
3130 static const struct file_operations sdp_message_fops = {
3131 .owner = THIS_MODULE,
3132 .write = dp_sdp_message_debugfs_write,
3133 .llseek = default_llseek
3134 };
3135
3136 static const struct file_operations dp_max_bpc_debugfs_fops = {
3137 .owner = THIS_MODULE,
3138 .read = dp_max_bpc_read,
3139 .write = dp_max_bpc_write,
3140 .llseek = default_llseek
3141 };
3142
3143 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
3144 .owner = THIS_MODULE,
3145 .write = dp_dsc_passthrough_set,
3146 .llseek = default_llseek
3147 };
3148
3149 static const struct file_operations dp_mst_link_settings_debugfs_fops = {
3150 .owner = THIS_MODULE,
3151 .write = dp_mst_link_setting,
3152 .llseek = default_llseek
3153 };
3154
3155 static const struct file_operations hdmi_automation_debugfs_fops = {
3156 .owner = THIS_MODULE,
3157 .write = hdmi_automation_enable,
3158 .llseek = default_llseek
3159 };
3160
3161 static const struct {
3162 char *name;
3163 const struct file_operations *fops;
3164 } dp_debugfs_entries[] = {
3165 {"link_settings", &dp_link_settings_debugfs_fops},
3166 {"phy_settings", &dp_phy_settings_debugfs_fop},
3167 {"lttpr_status", &dp_lttpr_status_fops},
3168 {"test_pattern", &dp_phy_test_pattern_fops},
3169 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3170 {"sdp_message", &sdp_message_fops},
3171 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
3172 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
3173 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
3174 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
3175 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
3176 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
3177 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
3178 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
3179 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
3180 {"max_bpc", &dp_max_bpc_debugfs_fops},
3181 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
3182 {"is_mst_connector", &dp_is_mst_connector_fops},
3183 {"mst_progress_status", &dp_mst_progress_status_fops},
3184 {"is_dpia_link", &is_dpia_link_fops},
3185 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
3186 };
3187
3188 static const struct {
3189 char *name;
3190 const struct file_operations *fops;
3191 } hdmi_debugfs_entries[] = {
3192 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
3193 {"hdmi_cec_state", &hdmi_cec_state_fops},
3194 {"hdmi_automation", &hdmi_automation_debugfs_fops}
3195 };
3196
3197 /*
3198 * Force a specific pixel encoding for the given connector, overriding the
3199 * encoding that stream validation would otherwise pick. The value is an
3200 * enum dc_pixel_encoding:
3201 *
3202 * 0 - PIXEL_ENCODING_UNDEFINED (no override, default)
3203 * 1 - PIXEL_ENCODING_RGB
3204 * 2 - PIXEL_ENCODING_YCBCR422
3205 * 3 - PIXEL_ENCODING_YCBCR444
3206 * 4 - PIXEL_ENCODING_YCBCR420
3207 */
force_yuv_pixel_format_set(void * data,u64 val)3208 static int force_yuv_pixel_format_set(void *data, u64 val)
3209 {
3210 struct amdgpu_dm_connector *connector = data;
3211
3212 if (val >= PIXEL_ENCODING_COUNT)
3213 return -EINVAL;
3214
3215 connector->force_yuv_pixel_format = (uint8_t)val;
3216
3217 return 0;
3218 }
3219
3220 /*
3221 * Read back the pixel encoding currently forced on the given connector.
3222 */
force_yuv_pixel_format_get(void * data,u64 * val)3223 static int force_yuv_pixel_format_get(void *data, u64 *val)
3224 {
3225 struct amdgpu_dm_connector *connector = data;
3226
3227 *val = connector->force_yuv_pixel_format;
3228
3229 return 0;
3230 }
3231
3232 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv_pixel_format_fops, force_yuv_pixel_format_get,
3233 force_yuv_pixel_format_set, "%llu\n");
3234
3235 /*
3236 * Read Replay state
3237 */
replay_get_state(void * data,u64 * val)3238 static int replay_get_state(void *data, u64 *val)
3239 {
3240 struct amdgpu_dm_connector *connector = data;
3241 struct dc_link *link = connector->dc_link;
3242 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3243 struct dc *dc = adev->dm.dc;
3244 uint64_t state = REPLAY_STATE_INVALID;
3245 bool reallow_idle = false;
3246
3247 mutex_lock(&adev->dm.dc_lock);
3248
3249 if (dc->idle_optimizations_allowed) {
3250 dc_allow_idle_optimizations(dc, false);
3251 reallow_idle = true;
3252 }
3253
3254 dc_link_get_replay_state(link, &state);
3255
3256 if (reallow_idle)
3257 dc_allow_idle_optimizations(dc, true);
3258
3259 mutex_unlock(&adev->dm.dc_lock);
3260
3261 *val = state;
3262
3263 return 0;
3264 }
3265
3266 /*
3267 * Start / Stop capture Replay residency
3268 */
replay_set_residency(void * data,u64 val)3269 static int replay_set_residency(void *data, u64 val)
3270 {
3271 struct amdgpu_dm_connector *connector = data;
3272 struct dc_link *link = connector->dc_link;
3273 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3274 struct dc *dc = adev->dm.dc;
3275 bool is_start = (val != 0);
3276 u32 residency = 0;
3277 bool reallow_idle = false;
3278
3279 mutex_lock(&adev->dm.dc_lock);
3280
3281 if (dc->idle_optimizations_allowed) {
3282 dc_allow_idle_optimizations(dc, false);
3283 reallow_idle = true;
3284 }
3285
3286 link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
3287
3288 if (reallow_idle)
3289 dc_allow_idle_optimizations(dc, true);
3290
3291 mutex_unlock(&adev->dm.dc_lock);
3292
3293 return 0;
3294 }
3295
3296 /*
3297 * Read Replay residency
3298 */
replay_get_residency(void * data,u64 * val)3299 static int replay_get_residency(void *data, u64 *val)
3300 {
3301 struct amdgpu_dm_connector *connector = data;
3302 struct dc_link *link = connector->dc_link;
3303 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3304 struct dc *dc = adev->dm.dc;
3305 u32 residency = 0;
3306 bool reallow_idle = false;
3307
3308 mutex_lock(&adev->dm.dc_lock);
3309
3310 if (dc->idle_optimizations_allowed) {
3311 dc_allow_idle_optimizations(dc, false);
3312 reallow_idle = true;
3313 }
3314
3315 link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
3316
3317 if (reallow_idle)
3318 dc_allow_idle_optimizations(dc, true);
3319
3320 mutex_unlock(&adev->dm.dc_lock);
3321
3322 *val = (u64)residency;
3323
3324 return 0;
3325 }
3326
3327 /*
3328 * Read PSR state
3329 */
psr_get(void * data,u64 * val)3330 static int psr_get(void *data, u64 *val)
3331 {
3332 struct amdgpu_dm_connector *connector = data;
3333 struct dc_link *link = connector->dc_link;
3334 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3335 struct dc *dc = adev->dm.dc;
3336 enum dc_psr_state state = PSR_STATE0;
3337 bool reallow_idle = false;
3338
3339 mutex_lock(&adev->dm.dc_lock);
3340
3341 if (dc->idle_optimizations_allowed) {
3342 dc_allow_idle_optimizations(dc, false);
3343 reallow_idle = true;
3344 }
3345
3346 dc_link_get_psr_state(link, &state);
3347
3348 if (reallow_idle)
3349 dc_allow_idle_optimizations(dc, true);
3350
3351 mutex_unlock(&adev->dm.dc_lock);
3352
3353 *val = state;
3354
3355 return 0;
3356 }
3357
3358 /*
3359 * Read PSR state residency
3360 */
psr_read_residency(void * data,u64 * val)3361 static int psr_read_residency(void *data, u64 *val)
3362 {
3363 struct amdgpu_dm_connector *connector = data;
3364 struct dc_link *link = connector->dc_link;
3365 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3366 struct dc *dc = adev->dm.dc;
3367 u32 residency = 0;
3368 bool reallow_idle = false;
3369
3370 mutex_lock(&adev->dm.dc_lock);
3371
3372 if (dc->idle_optimizations_allowed) {
3373 dc_allow_idle_optimizations(dc, false);
3374 reallow_idle = true;
3375 }
3376
3377 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3378
3379 if (reallow_idle)
3380 dc_allow_idle_optimizations(dc, true);
3381
3382 mutex_unlock(&adev->dm.dc_lock);
3383
3384 *val = (u64)residency;
3385
3386 return 0;
3387 }
3388
3389 /* read allow_edp_hotplug_detection */
allow_edp_hotplug_detection_get(void * data,u64 * val)3390 static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3391 {
3392 struct amdgpu_dm_connector *aconnector = data;
3393 struct drm_connector *connector = &aconnector->base;
3394 struct drm_device *dev = connector->dev;
3395 struct amdgpu_device *adev = drm_to_adev(dev);
3396
3397 *val = adev->dm.dc->config.allow_edp_hotplug_detection;
3398
3399 return 0;
3400 }
3401
3402 /* set allow_edp_hotplug_detection */
allow_edp_hotplug_detection_set(void * data,u64 val)3403 static int allow_edp_hotplug_detection_set(void *data, u64 val)
3404 {
3405 struct amdgpu_dm_connector *aconnector = data;
3406 struct drm_connector *connector = &aconnector->base;
3407 struct drm_device *dev = connector->dev;
3408 struct amdgpu_device *adev = drm_to_adev(dev);
3409
3410 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3411
3412 return 0;
3413 }
3414
3415 /* check if kernel disallow eDP enter psr state
3416 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3417 * 0: allow edp enter psr; 1: disallow
3418 */
disallow_edp_enter_psr_get(void * data,u64 * val)3419 static int disallow_edp_enter_psr_get(void *data, u64 *val)
3420 {
3421 struct amdgpu_dm_connector *aconnector = data;
3422
3423 *val = (u64) aconnector->disallow_edp_enter_psr;
3424 return 0;
3425 }
3426
3427 /* set kernel disallow eDP enter psr state
3428 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3429 * 0: allow edp enter psr; 1: disallow
3430 *
3431 * usage: test app read crc from PSR eDP rx.
3432 *
3433 * during kernel boot up, kernel write dpcd 0x170 = 5.
3434 * this notify eDP rx psr enable and let rx check crc.
3435 * rx fw will start checking crc for rx internal logic.
3436 * crc read count within dpcd 0x246 is not updated and
3437 * value is 0. when eDP tx driver wants to read rx crc
3438 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3439 * timeout.
3440 *
3441 * to avoid this, we add this debugfs to let test app to disbable
3442 * rx crc checking for rx internal logic. then test app can read
3443 * non-zero crc read count.
3444 *
3445 * expected app sequence is as below:
3446 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3447 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3448 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3449 * without dpcd 0x170 = 5.
3450 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3451 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3452 * this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3453 */
disallow_edp_enter_psr_set(void * data,u64 val)3454 static int disallow_edp_enter_psr_set(void *data, u64 val)
3455 {
3456 struct amdgpu_dm_connector *aconnector = data;
3457 struct dc_link *link = aconnector->dc_link;
3458
3459 aconnector->disallow_edp_enter_psr = (val != 0);
3460
3461 /* eDP PSR enable / disable is happened during mode change in power module.
3462 * Only psr_settings.psr_version is used to decide whether PSR is enabled or not.
3463 * So here we only update psr_version based on debugfs setting.
3464 * If disallow_edp_enter_psr is true, set psr_version to unsupported;
3465 * if disallow_edp_enter_psr is false, set psr_version based on sink capability.
3466 */
3467 if (aconnector->disallow_edp_enter_psr)
3468 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
3469 else if (aconnector->psr_caps.psr_version == 1)
3470 link->psr_settings.psr_version = DC_PSR_VERSION_1;
3471 else if (aconnector->psr_caps.psr_version == 2)
3472 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
3473 return 0;
3474 }
3475
3476
3477 /* check if kernel disallow eDP enter replay state
3478 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3479 * 0: allow edp enter replay; 1: disallow
3480 */
disallow_edp_enter_replay_get(void * data,u64 * val)3481 static int disallow_edp_enter_replay_get(void *data, u64 *val)
3482 {
3483 struct amdgpu_dm_connector *aconnector = data;
3484
3485 *val = (u64) aconnector->disallow_edp_enter_replay;
3486 return 0;
3487 }
3488
3489 /* set kernel disallow eDP enter replay state
3490 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3491 * 0: allow edp enter replay; 1: disallow
3492 *
3493 * usage: test app read crc from PSR eDP rx.
3494 *
3495 * during kernel boot up, kernel write dpcd 0x37b to
3496 * notify eDP rx replay enable.
3497 * rx fw will start checking crc for rx internal logic.
3498 * crc read count within dpcd 0x246 is not updated and
3499 * value is 0. when eDP tx driver wants to read rx crc
3500 * from dpcd 0x246, 0x270, read count 0 lead tx driver
3501 * timeout.
3502 *
3503 * to avoid this, we add this debugfs to let test app to disbable
3504 * rx replay. then test app can read non-zero crc read count.
3505 *
3506 * expected app sequence is as below:
3507 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3508 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
3509 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3510 * without programming dpcd 0x37b.
3511 * 4. read crc from rx dpcd 0x270, 0x246, etc.
3512 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay.
3513 * this will let eDP back to normal with replay setup dpcd 0x37b.
3514 */
disallow_edp_enter_replay_set(void * data,u64 val)3515 static int disallow_edp_enter_replay_set(void *data, u64 val)
3516 {
3517 struct amdgpu_dm_connector *aconnector = data;
3518 struct dc_link *link = aconnector->dc_link;
3519
3520 aconnector->disallow_edp_enter_replay = (val != 0);
3521
3522 /* eDP replay enable / disable is happened during mode change in power module.
3523 * Only replay_settings.config.replay_supported is used to decide whether
3524 * replay is enabled or not. So here we only update replay_supported based on
3525 * debugfs setting.
3526 * If disallow_edp_enter_replay is true, set replay_supported to false.
3527 * if disallow_edp_enter_replay is false, set replay_supported back based on
3528 * sink replay capability.
3529 */
3530 if (aconnector->disallow_edp_enter_replay)
3531 link->replay_settings.config.replay_supported = false;
3532 else
3533 link->replay_settings.config.replay_supported =
3534 link->replay_settings.config.replay_cap_support;
3535 return 0;
3536 }
3537
3538
dmub_trace_mask_set(void * data,u64 val)3539 static int dmub_trace_mask_set(void *data, u64 val)
3540 {
3541 struct amdgpu_device *adev = data;
3542 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3543 enum dmub_gpint_command cmd;
3544 u64 mask = 0xffff;
3545 u8 shift = 0;
3546 u32 res;
3547 int i;
3548
3549 if (!srv->fw_version)
3550 return -EINVAL;
3551
3552 for (i = 0; i < 4; i++) {
3553 res = (val & mask) >> shift;
3554
3555 switch (i) {
3556 case 0:
3557 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3558 break;
3559 case 1:
3560 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3561 break;
3562 case 2:
3563 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3564 break;
3565 case 3:
3566 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3567 break;
3568 }
3569
3570 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT))
3571 return -EIO;
3572
3573 usleep_range(100, 1000);
3574
3575 mask <<= 16;
3576 shift += 16;
3577 }
3578
3579 return 0;
3580 }
3581
dmub_trace_mask_show(void * data,u64 * val)3582 static int dmub_trace_mask_show(void *data, u64 *val)
3583 {
3584 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3585 struct amdgpu_device *adev = data;
3586 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3587 u8 shift = 0;
3588 u64 raw = 0;
3589 u64 res = 0;
3590 int i = 0;
3591
3592 if (!srv->fw_version)
3593 return -EINVAL;
3594
3595 while (i < 4) {
3596 uint32_t response;
3597
3598 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3599 return -EIO;
3600
3601 raw = response;
3602 usleep_range(100, 1000);
3603
3604 cmd++;
3605 res |= (raw << shift);
3606 shift += 16;
3607 i++;
3608 }
3609
3610 *val = res;
3611
3612 return 0;
3613 }
3614
3615 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3616 dmub_trace_mask_set, "0x%llx\n");
3617
3618 /*
3619 * Set dmcub trace event IRQ enable or disable.
3620 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3621 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3622 */
dmcub_trace_event_state_set(void * data,u64 val)3623 static int dmcub_trace_event_state_set(void *data, u64 val)
3624 {
3625 struct amdgpu_device *adev = data;
3626
3627 if (val == 1 || val == 0) {
3628 dc_dmub_trace_event_control(adev->dm.dc, val);
3629 adev->dm.dmcub_trace_event_en = (bool)val;
3630 } else
3631 return 0;
3632
3633 return 0;
3634 }
3635
3636 /*
3637 * The interface doesn't need get function, so it will return the
3638 * value of zero
3639 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3640 */
dmcub_trace_event_state_get(void * data,u64 * val)3641 static int dmcub_trace_event_state_get(void *data, u64 *val)
3642 {
3643 struct amdgpu_device *adev = data;
3644
3645 *val = adev->dm.dmcub_trace_event_en;
3646 return 0;
3647 }
3648
3649 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3650 dmcub_trace_event_state_set, "%llu\n");
3651
3652 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3653 DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency,
3654 "%llu\n");
3655 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3656 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3657 "%llu\n");
3658
3659 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3660 allow_edp_hotplug_detection_get,
3661 allow_edp_hotplug_detection_set, "%llu\n");
3662
3663 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3664 disallow_edp_enter_psr_get,
3665 disallow_edp_enter_psr_set, "%llu\n");
3666
3667 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops,
3668 disallow_edp_enter_replay_get,
3669 disallow_edp_enter_replay_set, "%llu\n");
3670
3671 DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get,
3672 ips_residency_cntl_set, "%llu\n");
3673
3674 DEFINE_SHOW_ATTRIBUTE(current_backlight);
3675 DEFINE_SHOW_ATTRIBUTE(target_backlight);
3676 DEFINE_SHOW_ATTRIBUTE(ips_status);
3677 DEFINE_SHOW_ATTRIBUTE(ips_residency);
3678
3679 static const struct {
3680 char *name;
3681 const struct file_operations *fops;
3682 } connector_debugfs_entries[] = {
3683 {"force_yuv_pixel_format", &force_yuv_pixel_format_fops},
3684 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3685 {"internal_display", &internal_display_fops},
3686 {"odm_combine_segments", &odm_combine_segments_fops}
3687 };
3688
3689 /*
3690 * Returns supported customized link rates by this eDP panel.
3691 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3692 */
edp_ilr_show(struct seq_file * m,void * unused)3693 static int edp_ilr_show(struct seq_file *m, void *unused)
3694 {
3695 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3696 struct dc_link *link = aconnector->dc_link;
3697 uint8_t supported_link_rates[16];
3698 uint32_t link_rate_in_khz;
3699 uint32_t entry = 0;
3700 uint8_t dpcd_rev;
3701
3702 memset(supported_link_rates, 0, sizeof(supported_link_rates));
3703 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3704 supported_link_rates, sizeof(supported_link_rates));
3705
3706 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3707
3708 if (dpcd_rev >= DP_DPCD_REV_13 &&
3709 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3710
3711 for (entry = 0; entry < 16; entry += 2) {
3712 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3713 supported_link_rates[entry]) * 200;
3714 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3715 }
3716 } else {
3717 seq_puts(m, "ILR is not supported by this eDP panel.\n");
3718 }
3719
3720 return 0;
3721 }
3722
3723 /*
3724 * Set supported customized link rate to eDP panel.
3725 *
3726 * echo <lane_count> <link_rate option> > ilr_setting
3727 *
3728 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3729 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3730 * to set 4 lanes and 2.16 GHz
3731 */
edp_ilr_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)3732 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3733 size_t size, loff_t *pos)
3734 {
3735 struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3736 struct dc_link *link = connector->dc_link;
3737 struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
3738 struct dc *dc = (struct dc *)link->dc;
3739 struct dc_link_settings prefer_link_settings;
3740 char *wr_buf = NULL;
3741 const uint32_t wr_buf_size = 40;
3742 /* 0: lane_count; 1: link_rate */
3743 int max_param_num = 2;
3744 uint8_t param_nums = 0;
3745 long param[2];
3746 bool valid_input = true;
3747 uint8_t supported_link_rates[16] = {0};
3748 uint32_t entry = 0;
3749 uint32_t link_rate_in_khz = 0;
3750 uint8_t dpcd_rev = 0;
3751
3752 if (size == 0)
3753 return -EINVAL;
3754
3755 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3756 if (!wr_buf)
3757 return -ENOMEM;
3758
3759 if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3760 (long *)param, buf,
3761 max_param_num,
3762 ¶m_nums)) {
3763 kfree(wr_buf);
3764 return -EINVAL;
3765 }
3766
3767 if (param_nums <= 0) {
3768 kfree(wr_buf);
3769 return -EINVAL;
3770 }
3771
3772 switch (param[0]) {
3773 case LANE_COUNT_ONE:
3774 case LANE_COUNT_TWO:
3775 case LANE_COUNT_FOUR:
3776 break;
3777 default:
3778 valid_input = false;
3779 break;
3780 }
3781
3782 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3783 valid_input = false;
3784
3785 if (!valid_input) {
3786 kfree(wr_buf);
3787 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3788 prefer_link_settings.use_link_rate_set = false;
3789 mutex_lock(&adev->dm.dc_lock);
3790 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false);
3791 mutex_unlock(&adev->dm.dc_lock);
3792 return size;
3793 }
3794
3795 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
3796 supported_link_rates, sizeof(supported_link_rates)))
3797 return -EINVAL;
3798
3799 dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3800 if (dpcd_rev < DP_DPCD_REV_13 ||
3801 (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) {
3802 return size;
3803 }
3804
3805 entry = param[1] * 2;
3806 link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 +
3807 supported_link_rates[entry]) * 200;
3808
3809 /* save user force lane_count, link_rate to preferred settings
3810 * spread spectrum will not be changed
3811 */
3812 prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3813 prefer_link_settings.lane_count = param[0];
3814 prefer_link_settings.use_link_rate_set = true;
3815 prefer_link_settings.link_rate_set = param[1];
3816 prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR;
3817
3818 mutex_lock(&adev->dm.dc_lock);
3819 dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
3820 NULL, link, false);
3821 mutex_unlock(&adev->dm.dc_lock);
3822
3823 kfree(wr_buf);
3824 return size;
3825 }
3826
edp_ilr_open(struct inode * inode,struct file * file)3827 static int edp_ilr_open(struct inode *inode, struct file *file)
3828 {
3829 return single_open(file, edp_ilr_show, inode->i_private);
3830 }
3831
3832 static const struct file_operations edp_ilr_debugfs_fops = {
3833 .owner = THIS_MODULE,
3834 .open = edp_ilr_open,
3835 .read = seq_read,
3836 .llseek = seq_lseek,
3837 .release = single_release,
3838 .write = edp_ilr_write
3839 };
3840
connector_debugfs_init(struct amdgpu_dm_connector * connector)3841 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3842 {
3843 int i;
3844 struct dentry *dir = connector->base.debugfs_entry;
3845
3846 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3847 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3848 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3849 debugfs_create_file(dp_debugfs_entries[i].name,
3850 0644, dir, connector,
3851 dp_debugfs_entries[i].fops);
3852 }
3853 }
3854 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3855 debugfs_create_file("replay_capability", 0444, dir, connector,
3856 &replay_capability_fops);
3857 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3858 debugfs_create_file_unsafe("replay_residency", 0444, dir,
3859 connector, &replay_residency_fops);
3860 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
3861 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
3862 debugfs_create_file_unsafe("psr_residency", 0444, dir,
3863 connector, &psr_residency_fops);
3864 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3865 ¤t_backlight_fops);
3866 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3867 &target_backlight_fops);
3868 debugfs_create_file("ilr_setting", 0644, dir, connector,
3869 &edp_ilr_debugfs_fops);
3870 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3871 &allow_edp_hotplug_detection_fops);
3872 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3873 &disallow_edp_enter_psr_fops);
3874 debugfs_create_file("disallow_edp_enter_replay", 0644, dir, connector,
3875 &disallow_edp_enter_replay_fops);
3876 }
3877
3878 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3879 debugfs_create_file(connector_debugfs_entries[i].name,
3880 0644, dir, connector,
3881 connector_debugfs_entries[i].fops);
3882 }
3883
3884 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3885 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3886 debugfs_create_file(hdmi_debugfs_entries[i].name,
3887 0644, dir, connector,
3888 hdmi_debugfs_entries[i].fops);
3889 }
3890 }
3891 }
3892
3893 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3894 /*
3895 * Set crc window coordinate x start
3896 */
crc_win_x_start_set(void * data,u64 val)3897 static int crc_win_x_start_set(void *data, u64 val)
3898 {
3899 struct drm_crtc *crtc = data;
3900 struct drm_device *drm_dev = crtc->dev;
3901 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3902
3903 spin_lock_irq(&drm_dev->event_lock);
3904 acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
3905 acrtc->dm_irq_params.window_param[0].update_win = false;
3906 spin_unlock_irq(&drm_dev->event_lock);
3907
3908 return 0;
3909 }
3910
3911 /*
3912 * Get crc window coordinate x start
3913 */
crc_win_x_start_get(void * data,u64 * val)3914 static int crc_win_x_start_get(void *data, u64 *val)
3915 {
3916 struct drm_crtc *crtc = data;
3917 struct drm_device *drm_dev = crtc->dev;
3918 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3919
3920 spin_lock_irq(&drm_dev->event_lock);
3921 *val = acrtc->dm_irq_params.window_param[0].x_start;
3922 spin_unlock_irq(&drm_dev->event_lock);
3923
3924 return 0;
3925 }
3926
3927 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3928 crc_win_x_start_set, "%llu\n");
3929
3930
3931 /*
3932 * Set crc window coordinate y start
3933 */
crc_win_y_start_set(void * data,u64 val)3934 static int crc_win_y_start_set(void *data, u64 val)
3935 {
3936 struct drm_crtc *crtc = data;
3937 struct drm_device *drm_dev = crtc->dev;
3938 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3939
3940 spin_lock_irq(&drm_dev->event_lock);
3941 acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
3942 acrtc->dm_irq_params.window_param[0].update_win = false;
3943 spin_unlock_irq(&drm_dev->event_lock);
3944
3945 return 0;
3946 }
3947
3948 /*
3949 * Get crc window coordinate y start
3950 */
crc_win_y_start_get(void * data,u64 * val)3951 static int crc_win_y_start_get(void *data, u64 *val)
3952 {
3953 struct drm_crtc *crtc = data;
3954 struct drm_device *drm_dev = crtc->dev;
3955 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3956
3957 spin_lock_irq(&drm_dev->event_lock);
3958 *val = acrtc->dm_irq_params.window_param[0].y_start;
3959 spin_unlock_irq(&drm_dev->event_lock);
3960
3961 return 0;
3962 }
3963
3964 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3965 crc_win_y_start_set, "%llu\n");
3966
3967 /*
3968 * Set crc window coordinate x end
3969 */
crc_win_x_end_set(void * data,u64 val)3970 static int crc_win_x_end_set(void *data, u64 val)
3971 {
3972 struct drm_crtc *crtc = data;
3973 struct drm_device *drm_dev = crtc->dev;
3974 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3975
3976 spin_lock_irq(&drm_dev->event_lock);
3977 acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
3978 acrtc->dm_irq_params.window_param[0].update_win = false;
3979 spin_unlock_irq(&drm_dev->event_lock);
3980
3981 return 0;
3982 }
3983
3984 /*
3985 * Get crc window coordinate x end
3986 */
crc_win_x_end_get(void * data,u64 * val)3987 static int crc_win_x_end_get(void *data, u64 *val)
3988 {
3989 struct drm_crtc *crtc = data;
3990 struct drm_device *drm_dev = crtc->dev;
3991 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3992
3993 spin_lock_irq(&drm_dev->event_lock);
3994 *val = acrtc->dm_irq_params.window_param[0].x_end;
3995 spin_unlock_irq(&drm_dev->event_lock);
3996
3997 return 0;
3998 }
3999
4000 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
4001 crc_win_x_end_set, "%llu\n");
4002
4003 /*
4004 * Set crc window coordinate y end
4005 */
crc_win_y_end_set(void * data,u64 val)4006 static int crc_win_y_end_set(void *data, u64 val)
4007 {
4008 struct drm_crtc *crtc = data;
4009 struct drm_device *drm_dev = crtc->dev;
4010 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4011
4012 spin_lock_irq(&drm_dev->event_lock);
4013 acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
4014 acrtc->dm_irq_params.window_param[0].update_win = false;
4015 spin_unlock_irq(&drm_dev->event_lock);
4016
4017 return 0;
4018 }
4019
4020 /*
4021 * Get crc window coordinate y end
4022 */
crc_win_y_end_get(void * data,u64 * val)4023 static int crc_win_y_end_get(void *data, u64 *val)
4024 {
4025 struct drm_crtc *crtc = data;
4026 struct drm_device *drm_dev = crtc->dev;
4027 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4028
4029 spin_lock_irq(&drm_dev->event_lock);
4030 *val = acrtc->dm_irq_params.window_param[0].y_end;
4031 spin_unlock_irq(&drm_dev->event_lock);
4032
4033 return 0;
4034 }
4035
4036 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
4037 crc_win_y_end_set, "%llu\n");
4038 /*
4039 * Trigger to commit crc window
4040 */
crc_win_update_set(void * data,u64 val)4041 static int crc_win_update_set(void *data, u64 val)
4042 {
4043 struct drm_crtc *crtc = data;
4044 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4045 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
4046
4047 if (val) {
4048 mutex_lock(&adev->dm.dc_lock);
4049 /* PSR Replay may write to OTG CRC window control register,
4050 * so inactive it before starting secure_display by sending disable event.
4051 */
4052 amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, true,
4053 psr_event_crc_window_active, true);
4054 amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, true,
4055 replay_event_crc_window_active, true);
4056
4057 spin_lock_irq(&adev_to_drm(adev)->event_lock);
4058 acrtc->dm_irq_params.window_param[0].enable = true;
4059 acrtc->dm_irq_params.window_param[0].update_win = true;
4060 acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
4061 acrtc->dm_irq_params.crc_window_activated = true;
4062 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
4063 mutex_unlock(&adev->dm.dc_lock);
4064 } else {
4065 /* Clear disable events to allow PSR/Replay to active */
4066 mutex_lock(&adev->dm.dc_lock);
4067 amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, false,
4068 psr_event_crc_window_active, false);
4069 amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, false,
4070 replay_event_crc_window_active, false);
4071 mutex_unlock(&adev->dm.dc_lock);
4072 }
4073 return 0;
4074 }
4075
4076 /*
4077 * Get crc window update flag
4078 */
crc_win_update_get(void * data,u64 * val)4079 static int crc_win_update_get(void *data, u64 *val)
4080 {
4081 *val = 0;
4082 return 0;
4083 }
4084
4085 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
4086 crc_win_update_set, "%llu\n");
4087
4088 /*
4089 * Trigger to set crc polynomial mode
4090 * 0: 16-bit CRC, 1: 32-bit CRC
4091 * only accepts 0 or 1 for supported hwip versions
4092 */
crc_poly_mode_set(void * data,u64 val)4093 static int crc_poly_mode_set(void *data, u64 val)
4094 {
4095 struct drm_crtc *crtc = data;
4096 struct amdgpu_crtc *acrtc;
4097 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
4098
4099 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) &&
4100 (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) &&
4101 (val < 2)) {
4102 acrtc = to_amdgpu_crtc(crtc);
4103 mutex_lock(&adev->dm.dc_lock);
4104 spin_lock_irq(&adev_to_drm(adev)->event_lock);
4105 acrtc->dm_irq_params.crc_poly_mode = val;
4106 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
4107 mutex_unlock(&adev->dm.dc_lock);
4108 }
4109
4110 return 0;
4111 }
4112
4113 /*
4114 * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC)
4115 */
crc_poly_mode_get(void * data,u64 * val)4116 static int crc_poly_mode_get(void *data, u64 *val)
4117 {
4118 struct drm_crtc *crtc = data;
4119 struct drm_device *drm_dev = crtc->dev;
4120 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4121
4122 spin_lock_irq(&drm_dev->event_lock);
4123 *val = acrtc->dm_irq_params.crc_poly_mode;
4124 spin_unlock_irq(&drm_dev->event_lock);
4125
4126 return 0;
4127 }
4128
4129 DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get,
4130 crc_poly_mode_set, "%llu\n");
4131 #endif
crtc_debugfs_init(struct drm_crtc * crtc)4132 void crtc_debugfs_init(struct drm_crtc *crtc)
4133 {
4134 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
4135 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
4136
4137 if (!dir)
4138 return;
4139
4140 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
4141 &crc_win_x_start_fops);
4142 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
4143 &crc_win_y_start_fops);
4144 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
4145 &crc_win_x_end_fops);
4146 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
4147 &crc_win_y_end_fops);
4148 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
4149 &crc_win_update_fops);
4150 debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc,
4151 &crc_poly_mode_fops);
4152 dput(dir);
4153 #endif
4154 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
4155 crtc, &amdgpu_current_bpc_fops);
4156 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
4157 crtc, &amdgpu_current_colorspace_fops);
4158 }
4159
4160 /*
4161 * Writes DTN log state to the user supplied buffer.
4162 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
4163 */
dtn_log_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4164 static ssize_t dtn_log_read(
4165 struct file *f,
4166 char __user *buf,
4167 size_t size,
4168 loff_t *pos)
4169 {
4170 struct amdgpu_device *adev = file_inode(f)->i_private;
4171 struct dc *dc = adev->dm.dc;
4172 struct dc_log_buffer_ctx log_ctx = { 0 };
4173 ssize_t result = 0;
4174
4175 if (!buf || !size)
4176 return -EINVAL;
4177
4178 if (!dc->hwss.log_hw_state)
4179 return 0;
4180
4181 dc->hwss.log_hw_state(dc, &log_ctx);
4182
4183 if (*pos < log_ctx.pos) {
4184 size_t to_copy = log_ctx.pos - *pos;
4185
4186 to_copy = min(to_copy, size);
4187
4188 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
4189 *pos += to_copy;
4190 result = to_copy;
4191 }
4192 }
4193
4194 kfree(log_ctx.buf);
4195
4196 return result;
4197 }
4198
4199 /*
4200 * Writes DTN log state to dmesg when triggered via a write.
4201 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
4202 */
dtn_log_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)4203 static ssize_t dtn_log_write(
4204 struct file *f,
4205 const char __user *buf,
4206 size_t size,
4207 loff_t *pos)
4208 {
4209 struct amdgpu_device *adev = file_inode(f)->i_private;
4210 struct dc *dc = adev->dm.dc;
4211
4212 /* Write triggers log output via dmesg. */
4213 if (size == 0)
4214 return 0;
4215
4216 if (dc->hwss.log_hw_state)
4217 dc->hwss.log_hw_state(dc, NULL);
4218
4219 return size;
4220 }
4221
mst_topo_show(struct seq_file * m,void * unused)4222 static int mst_topo_show(struct seq_file *m, void *unused)
4223 {
4224 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4225 struct drm_device *dev = adev_to_drm(adev);
4226 struct drm_connector *connector;
4227 struct drm_connector_list_iter conn_iter;
4228 struct amdgpu_dm_connector *aconnector;
4229
4230 drm_connector_list_iter_begin(dev, &conn_iter);
4231 drm_for_each_connector_iter(connector, &conn_iter) {
4232 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
4233 continue;
4234
4235 aconnector = to_amdgpu_dm_connector(connector);
4236
4237 /* Ensure we're only dumping the topology of a root mst node */
4238 if (!aconnector->mst_mgr.mst_state)
4239 continue;
4240
4241 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
4242 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
4243 }
4244 drm_connector_list_iter_end(&conn_iter);
4245
4246 return 0;
4247 }
4248
4249 /*
4250 * Sets trigger hpd for MST topologies.
4251 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
4252 * All topologies will be disconnected if val of 0 is set .
4253 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4254 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4255 */
trigger_hpd_mst_set(void * data,u64 val)4256 static int trigger_hpd_mst_set(void *data, u64 val)
4257 {
4258 struct amdgpu_device *adev = data;
4259 struct drm_device *dev = adev_to_drm(adev);
4260 struct drm_connector_list_iter iter;
4261 struct amdgpu_dm_connector *aconnector;
4262 struct drm_connector *connector;
4263 struct dc_link *link = NULL;
4264 int ret;
4265
4266 if (val == 1) {
4267 drm_connector_list_iter_begin(dev, &iter);
4268 drm_for_each_connector_iter(connector, &iter) {
4269 aconnector = to_amdgpu_dm_connector(connector);
4270 if (aconnector->dc_link->type == dc_connection_mst_branch &&
4271 aconnector->mst_mgr.aux) {
4272 mutex_lock(&adev->dm.dc_lock);
4273 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
4274 mutex_unlock(&adev->dm.dc_lock);
4275
4276 if (!ret)
4277 DRM_ERROR("DM_MST: Failed to detect dc link!");
4278
4279 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
4280 if (ret < 0)
4281 DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
4282 }
4283 }
4284 } else if (val == 0) {
4285 drm_connector_list_iter_begin(dev, &iter);
4286 drm_for_each_connector_iter(connector, &iter) {
4287 aconnector = to_amdgpu_dm_connector(connector);
4288 if (!aconnector->dc_link)
4289 continue;
4290
4291 if (!aconnector->mst_root)
4292 continue;
4293
4294 link = aconnector->dc_link;
4295 dc_link_dp_receiver_power_ctrl(link, false);
4296 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false);
4297 link->mst_stream_alloc_table.stream_count = 0;
4298 memset(link->mst_stream_alloc_table.stream_allocations, 0,
4299 sizeof(link->mst_stream_alloc_table.stream_allocations));
4300 }
4301 } else {
4302 return 0;
4303 }
4304 drm_kms_helper_hotplug_event(dev);
4305
4306 return 0;
4307 }
4308
4309 /*
4310 * The interface doesn't need get function, so it will return the
4311 * value of zero
4312 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
4313 */
trigger_hpd_mst_get(void * data,u64 * val)4314 static int trigger_hpd_mst_get(void *data, u64 *val)
4315 {
4316 *val = 0;
4317 return 0;
4318 }
4319
4320 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
4321 trigger_hpd_mst_set, "%llu\n");
4322
4323
4324 /*
4325 * Sets the force_timing_sync debug option from the given string.
4326 * All connected displays will be force synchronized immediately.
4327 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4328 */
force_timing_sync_set(void * data,u64 val)4329 static int force_timing_sync_set(void *data, u64 val)
4330 {
4331 struct amdgpu_device *adev = data;
4332
4333 adev->dm.force_timing_sync = (bool)val;
4334
4335 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
4336
4337 return 0;
4338 }
4339
4340 /*
4341 * Gets the force_timing_sync debug option value into the given buffer.
4342 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
4343 */
force_timing_sync_get(void * data,u64 * val)4344 static int force_timing_sync_get(void *data, u64 *val)
4345 {
4346 struct amdgpu_device *adev = data;
4347
4348 *val = adev->dm.force_timing_sync;
4349
4350 return 0;
4351 }
4352
4353 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
4354 force_timing_sync_set, "%llu\n");
4355
4356
4357 /*
4358 * Disables all HPD and HPD RX interrupt handling in the
4359 * driver when set to 1. Default is 0.
4360 */
disable_hpd_set(void * data,u64 val)4361 static int disable_hpd_set(void *data, u64 val)
4362 {
4363 struct amdgpu_device *adev = data;
4364
4365 adev->dm.disable_hpd_irq = (bool)val;
4366
4367 return 0;
4368 }
4369
4370
4371 /*
4372 * Returns 1 if HPD and HPRX interrupt handling is disabled,
4373 * 0 otherwise.
4374 */
disable_hpd_get(void * data,u64 * val)4375 static int disable_hpd_get(void *data, u64 *val)
4376 {
4377 struct amdgpu_device *adev = data;
4378
4379 *val = adev->dm.disable_hpd_irq;
4380
4381 return 0;
4382 }
4383
4384 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
4385 disable_hpd_set, "%llu\n");
4386
4387 /*
4388 * Prints hardware capabilities. These are used for IGT testing.
4389 */
capabilities_show(struct seq_file * m,void * unused)4390 static int capabilities_show(struct seq_file *m, void *unused)
4391 {
4392 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4393 struct dc *dc = adev->dm.dc;
4394 bool mall_supported = dc->caps.mall_size_total;
4395 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
4396 unsigned int mall_in_use = false;
4397 unsigned int subvp_in_use = false;
4398
4399 struct hubbub *hubbub = dc->res_pool->hubbub;
4400
4401 if (hubbub && hubbub->funcs->get_mall_en)
4402 hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
4403
4404 if (dc->cap_funcs.get_subvp_en)
4405 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
4406
4407 seq_printf(m, "mall supported: %s, enabled: %s\n",
4408 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
4409 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n",
4410 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
4411
4412 return 0;
4413 }
4414
4415 DEFINE_SHOW_ATTRIBUTE(capabilities);
4416
4417 /*
4418 * Temporary w/a to force sst sequence in M42D DP2 mst receiver
4419 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
4420 */
dp_force_sst_set(void * data,u64 val)4421 static int dp_force_sst_set(void *data, u64 val)
4422 {
4423 struct amdgpu_device *adev = data;
4424
4425 adev->dm.dc->debug.set_mst_en_for_sst = val;
4426
4427 return 0;
4428 }
4429
dp_force_sst_get(void * data,u64 * val)4430 static int dp_force_sst_get(void *data, u64 *val)
4431 {
4432 struct amdgpu_device *adev = data;
4433
4434 *val = adev->dm.dc->debug.set_mst_en_for_sst;
4435
4436 return 0;
4437 }
4438 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
4439 dp_force_sst_set, "%llu\n");
4440
4441 /*
4442 * Force DP2 sequence without VESA certified cable.
4443 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
4444 */
dp_ignore_cable_id_set(void * data,u64 val)4445 static int dp_ignore_cable_id_set(void *data, u64 val)
4446 {
4447 struct amdgpu_device *adev = data;
4448
4449 adev->dm.dc->debug.ignore_cable_id = val;
4450
4451 return 0;
4452 }
4453
dp_ignore_cable_id_get(void * data,u64 * val)4454 static int dp_ignore_cable_id_get(void *data, u64 *val)
4455 {
4456 struct amdgpu_device *adev = data;
4457
4458 *val = adev->dm.dc->debug.ignore_cable_id;
4459
4460 return 0;
4461 }
4462 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
4463 dp_ignore_cable_id_set, "%llu\n");
4464
4465 /*
4466 * Sets the DC visual confirm debug option from the given string.
4467 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
4468 */
visual_confirm_set(void * data,u64 val)4469 static int visual_confirm_set(void *data, u64 val)
4470 {
4471 struct amdgpu_device *adev = data;
4472
4473 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
4474
4475 return 0;
4476 }
4477
4478 /*
4479 * Reads the DC visual confirm debug option value into the given buffer.
4480 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
4481 */
visual_confirm_get(void * data,u64 * val)4482 static int visual_confirm_get(void *data, u64 *val)
4483 {
4484 struct amdgpu_device *adev = data;
4485
4486 *val = adev->dm.dc->debug.visual_confirm;
4487
4488 return 0;
4489 }
4490
4491 DEFINE_SHOW_ATTRIBUTE(mst_topo);
4492 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
4493 visual_confirm_set, "%llu\n");
4494
4495
4496 /*
4497 * Sets the DC skip_detection_link_training debug option from the given string.
4498 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4499 */
skip_detection_link_training_set(void * data,u64 val)4500 static int skip_detection_link_training_set(void *data, u64 val)
4501 {
4502 struct amdgpu_device *adev = data;
4503
4504 if (val == 0)
4505 adev->dm.dc->debug.skip_detection_link_training = false;
4506 else
4507 adev->dm.dc->debug.skip_detection_link_training = true;
4508
4509 return 0;
4510 }
4511
4512 /*
4513 * Reads the DC skip_detection_link_training debug option value into the given buffer.
4514 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4515 */
skip_detection_link_training_get(void * data,u64 * val)4516 static int skip_detection_link_training_get(void *data, u64 *val)
4517 {
4518 struct amdgpu_device *adev = data;
4519
4520 *val = adev->dm.dc->debug.skip_detection_link_training;
4521
4522 return 0;
4523 }
4524
4525 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4526 skip_detection_link_training_get,
4527 skip_detection_link_training_set, "%llu\n");
4528
4529 /*
4530 * Dumps the DCC_EN bit for each pipe.
4531 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4532 */
dcc_en_bits_read(struct file * f,char __user * buf,size_t size,loff_t * pos)4533 static ssize_t dcc_en_bits_read(
4534 struct file *f,
4535 char __user *buf,
4536 size_t size,
4537 loff_t *pos)
4538 {
4539 struct amdgpu_device *adev = file_inode(f)->i_private;
4540 struct dc *dc = adev->dm.dc;
4541 char *rd_buf = NULL;
4542 const uint32_t rd_buf_size = 32;
4543 uint32_t result = 0;
4544 int offset = 0;
4545 int num_pipes = dc->res_pool->pipe_count;
4546 int *dcc_en_bits;
4547 int i, r;
4548
4549 dcc_en_bits = kzalloc_objs(int, num_pipes);
4550 if (!dcc_en_bits)
4551 return -ENOMEM;
4552
4553 if (!dc->hwss.get_dcc_en_bits) {
4554 kfree(dcc_en_bits);
4555 return 0;
4556 }
4557
4558 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4559
4560 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4561 if (!rd_buf) {
4562 kfree(dcc_en_bits);
4563 return -ENOMEM;
4564 }
4565
4566 for (i = 0; i < num_pipes; i++)
4567 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
4568 "%d ", dcc_en_bits[i]);
4569 rd_buf[strlen(rd_buf)] = '\n';
4570
4571 kfree(dcc_en_bits);
4572
4573 while (size) {
4574 if (*pos >= rd_buf_size)
4575 break;
4576 r = put_user(*(rd_buf + result), buf);
4577 if (r) {
4578 kfree(rd_buf);
4579 return r; /* r = -EFAULT */
4580 }
4581 buf += 1;
4582 size -= 1;
4583 *pos += 1;
4584 result += 1;
4585 }
4586
4587 kfree(rd_buf);
4588 return result;
4589 }
4590
dtn_debugfs_init(struct amdgpu_device * adev)4591 void dtn_debugfs_init(struct amdgpu_device *adev)
4592 {
4593 static const struct file_operations dtn_log_fops = {
4594 .owner = THIS_MODULE,
4595 .read = dtn_log_read,
4596 .write = dtn_log_write,
4597 .llseek = default_llseek
4598 };
4599 static const struct file_operations dcc_en_bits_fops = {
4600 .owner = THIS_MODULE,
4601 .read = dcc_en_bits_read,
4602 .llseek = default_llseek
4603 };
4604
4605 struct drm_minor *minor = adev_to_drm(adev)->primary;
4606 struct dentry *root = minor->debugfs_root;
4607
4608 debugfs_create_file("amdgpu_mst_topology", 0444, root,
4609 adev, &mst_topo_fops);
4610 debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4611 adev, &capabilities_fops);
4612 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4613 &dtn_log_fops);
4614 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4615 &dp_set_mst_en_for_sst_ops);
4616 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4617 &dp_ignore_cable_id_ops);
4618
4619 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
4620 &visual_confirm_fops);
4621
4622 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev,
4623 &skip_detection_link_training_fops);
4624
4625 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
4626 adev, &dmub_tracebuffer_fops);
4627
4628 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
4629 adev, &dmub_fw_state_fops);
4630
4631 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
4632 adev, &force_timing_sync_ops);
4633
4634 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root,
4635 adev, &dmub_trace_mask_fops);
4636
4637 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
4638 adev, &dmcub_trace_event_state_fops);
4639
4640 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
4641 adev, &trigger_hpd_mst_ops);
4642
4643 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
4644 &dcc_en_bits_fops);
4645
4646 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
4647 &disable_hpd_ops);
4648
4649 if (adev->dm.dc->caps.ips_support) {
4650 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev,
4651 &ips_status_fops);
4652
4653 debugfs_create_file_unsafe("amdgpu_dm_ips_residency_cntl", 0644, root, adev,
4654 &ips_residency_cntl_fops);
4655
4656 debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev,
4657 &ips_residency_fops);
4658 }
4659 }
4660