1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/debugfs.h> 26 #include <linux/firmware.h> 27 #include <drm/drm_vblank.h> 28 29 #include <drm/drm_file.h> 30 #include <drm/drm_print.h> 31 32 #include "intel_crtc.h" 33 #include "intel_de.h" 34 #include "intel_display_power_well.h" 35 #include "intel_display_regs.h" 36 #include "intel_display_rpm.h" 37 #include "intel_display_types.h" 38 #include "intel_display_utils.h" 39 #include "intel_dmc.h" 40 #include "intel_dmc_regs.h" 41 #include "intel_flipq.h" 42 43 /** 44 * DOC: DMC Firmware Support 45 * 46 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 47 * engine to save and restore the state of display engine when it enter into 48 * low-power state and comes back to normal. 49 */ 50 51 #define INTEL_DMC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git" 52 53 enum intel_dmc_id { 54 DMC_FW_MAIN = 0, 55 DMC_FW_PIPEA, 56 DMC_FW_PIPEB, 57 DMC_FW_PIPEC, 58 DMC_FW_PIPED, 59 DMC_FW_MAX 60 }; 61 62 struct intel_dmc { 63 struct intel_display *display; 64 struct work_struct work; 65 const char *fw_path; 66 u32 max_fw_size; /* bytes */ 67 u32 version; 68 struct { 69 u32 dc5_start; 70 u32 count; 71 } dc6_allowed; 72 struct dmc_fw_info { 73 u32 mmio_count; 74 i915_reg_t mmioaddr[20]; 75 u32 mmiodata[20]; 76 u32 dmc_offset; 77 u32 start_mmioaddr; 78 u32 dmc_fw_size; /*dwords */ 79 u32 *payload; 80 bool present; 81 } dmc_info[DMC_FW_MAX]; 82 }; 83 84 /* Note: This may be NULL. */ 85 static struct intel_dmc *display_to_dmc(struct intel_display *display) 86 { 87 return display->dmc.dmc; 88 } 89 90 static const char *dmc_firmware_param(struct intel_display *display) 91 { 92 const char *p = display->params.dmc_firmware_path; 93 94 return p && *p ? p : NULL; 95 } 96 97 static bool dmc_firmware_param_disabled(struct intel_display *display) 98 { 99 const char *p = dmc_firmware_param(display); 100 101 /* Magic path to indicate disabled */ 102 return p && !strcmp(p, "/dev/null"); 103 } 104 105 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 106 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 107 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 108 109 #define DMC_PATH(platform) \ 110 "i915/" __stringify(platform) "_dmc.bin" 111 112 /* 113 * New DMC additions should not use this. This is used solely to remain 114 * compatible with systems that have not yet updated DMC blobs to use 115 * unversioned file names. 116 */ 117 #define DMC_LEGACY_PATH(platform, major, minor) \ 118 "i915/" \ 119 __stringify(platform) "_dmc_ver" \ 120 __stringify(major) "_" \ 121 __stringify(minor) ".bin" 122 123 #define XE2LPD_DMC_MAX_FW_SIZE 0x8000 124 #define XELPDP_DMC_MAX_FW_SIZE 0x7000 125 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 126 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 127 128 #define XE3P_LPD_DMC_PATH DMC_PATH(xe3p_lpd) 129 MODULE_FIRMWARE(XE3P_LPD_DMC_PATH); 130 131 #define XE3LPD_3002_DMC_PATH DMC_PATH(xe3lpd_3002) 132 MODULE_FIRMWARE(XE3LPD_3002_DMC_PATH); 133 134 #define XE3LPD_DMC_PATH DMC_PATH(xe3lpd) 135 MODULE_FIRMWARE(XE3LPD_DMC_PATH); 136 137 #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) 138 MODULE_FIRMWARE(XE2LPD_DMC_PATH); 139 140 #define BMG_DMC_PATH DMC_PATH(bmg) 141 MODULE_FIRMWARE(BMG_DMC_PATH); 142 143 #define MTL_DMC_PATH DMC_PATH(mtl) 144 MODULE_FIRMWARE(MTL_DMC_PATH); 145 146 #define DG2_DMC_PATH DMC_LEGACY_PATH(dg2, 2, 08) 147 MODULE_FIRMWARE(DG2_DMC_PATH); 148 149 #define ADLP_DMC_PATH DMC_PATH(adlp) 150 #define ADLP_DMC_FALLBACK_PATH DMC_LEGACY_PATH(adlp, 2, 16) 151 MODULE_FIRMWARE(ADLP_DMC_PATH); 152 MODULE_FIRMWARE(ADLP_DMC_FALLBACK_PATH); 153 154 #define ADLS_DMC_PATH DMC_LEGACY_PATH(adls, 2, 01) 155 MODULE_FIRMWARE(ADLS_DMC_PATH); 156 157 #define DG1_DMC_PATH DMC_LEGACY_PATH(dg1, 2, 02) 158 MODULE_FIRMWARE(DG1_DMC_PATH); 159 160 #define RKL_DMC_PATH DMC_LEGACY_PATH(rkl, 2, 03) 161 MODULE_FIRMWARE(RKL_DMC_PATH); 162 163 #define TGL_DMC_PATH DMC_LEGACY_PATH(tgl, 2, 12) 164 MODULE_FIRMWARE(TGL_DMC_PATH); 165 166 #define ICL_DMC_PATH DMC_LEGACY_PATH(icl, 1, 09) 167 #define ICL_DMC_MAX_FW_SIZE 0x6000 168 MODULE_FIRMWARE(ICL_DMC_PATH); 169 170 #define GLK_DMC_PATH DMC_LEGACY_PATH(glk, 1, 04) 171 #define GLK_DMC_MAX_FW_SIZE 0x4000 172 MODULE_FIRMWARE(GLK_DMC_PATH); 173 174 #define KBL_DMC_PATH DMC_LEGACY_PATH(kbl, 1, 04) 175 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 176 MODULE_FIRMWARE(KBL_DMC_PATH); 177 178 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27) 179 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 180 MODULE_FIRMWARE(SKL_DMC_PATH); 181 182 #define BXT_DMC_PATH DMC_LEGACY_PATH(bxt, 1, 07) 183 #define BXT_DMC_MAX_FW_SIZE 0x3000 184 MODULE_FIRMWARE(BXT_DMC_PATH); 185 186 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) 187 { 188 const char *fw_path = NULL; 189 u32 max_fw_size = 0; 190 191 if (DISPLAY_VERx100(display) == 3500) { 192 fw_path = XE3P_LPD_DMC_PATH; 193 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 194 } else if (DISPLAY_VERx100(display) == 3002) { 195 fw_path = XE3LPD_3002_DMC_PATH; 196 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 197 } else if (DISPLAY_VERx100(display) == 3000) { 198 fw_path = XE3LPD_DMC_PATH; 199 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 200 } else if (DISPLAY_VERx100(display) == 2000) { 201 fw_path = XE2LPD_DMC_PATH; 202 max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; 203 } else if (DISPLAY_VERx100(display) == 1401) { 204 fw_path = BMG_DMC_PATH; 205 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 206 } else if (DISPLAY_VERx100(display) == 1400) { 207 fw_path = MTL_DMC_PATH; 208 max_fw_size = XELPDP_DMC_MAX_FW_SIZE; 209 } else if (display->platform.dg2) { 210 fw_path = DG2_DMC_PATH; 211 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 212 } else if (display->platform.alderlake_p) { 213 fw_path = ADLP_DMC_PATH; 214 max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 215 } else if (display->platform.alderlake_s) { 216 fw_path = ADLS_DMC_PATH; 217 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 218 } else if (display->platform.dg1) { 219 fw_path = DG1_DMC_PATH; 220 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 221 } else if (display->platform.rocketlake) { 222 fw_path = RKL_DMC_PATH; 223 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 224 } else if (display->platform.tigerlake) { 225 fw_path = TGL_DMC_PATH; 226 max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 227 } else if (DISPLAY_VER(display) == 11) { 228 fw_path = ICL_DMC_PATH; 229 max_fw_size = ICL_DMC_MAX_FW_SIZE; 230 } else if (display->platform.geminilake) { 231 fw_path = GLK_DMC_PATH; 232 max_fw_size = GLK_DMC_MAX_FW_SIZE; 233 } else if (display->platform.kabylake || 234 display->platform.coffeelake || 235 display->platform.cometlake) { 236 fw_path = KBL_DMC_PATH; 237 max_fw_size = KBL_DMC_MAX_FW_SIZE; 238 } else if (display->platform.skylake) { 239 fw_path = SKL_DMC_PATH; 240 max_fw_size = SKL_DMC_MAX_FW_SIZE; 241 } else if (display->platform.broxton) { 242 fw_path = BXT_DMC_PATH; 243 max_fw_size = BXT_DMC_MAX_FW_SIZE; 244 } 245 246 *size = max_fw_size; 247 248 return fw_path; 249 } 250 251 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 252 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 253 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 254 #define DMC_V1_MAX_MMIO_COUNT 8 255 #define DMC_V3_MAX_MMIO_COUNT 20 256 #define DMC_V1_MMIO_START_RANGE 0x80000 257 258 #define PIPE_TO_DMC_ID(pipe) (DMC_FW_PIPEA + ((pipe) - PIPE_A)) 259 260 struct intel_css_header { 261 /* 0x09 for DMC */ 262 u32 module_type; 263 264 /* Includes the DMC specific header in dwords */ 265 u32 header_len; 266 267 /* always value would be 0x10000 */ 268 u32 header_ver; 269 270 /* Not used */ 271 u32 module_id; 272 273 /* Not used */ 274 u32 module_vendor; 275 276 /* in YYYYMMDD format */ 277 u32 date; 278 279 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 280 u32 size; 281 282 /* Not used */ 283 u32 key_size; 284 285 /* Not used */ 286 u32 modulus_size; 287 288 /* Not used */ 289 u32 exponent_size; 290 291 /* Not used */ 292 u32 reserved1[12]; 293 294 /* Major Minor */ 295 u32 version; 296 297 /* Not used */ 298 u32 reserved2[8]; 299 300 /* Not used */ 301 u32 kernel_header_info; 302 } __packed; 303 304 struct intel_fw_info { 305 u8 reserved1; 306 307 /* reserved on package_header version 1, must be 0 on version 2 */ 308 u8 dmc_id; 309 310 /* Stepping (A, B, C, ..., *). * is a wildcard */ 311 char stepping; 312 313 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 314 char substepping; 315 316 u32 offset; 317 u32 reserved2; 318 } __packed; 319 320 struct intel_package_header { 321 /* DMC container header length in dwords */ 322 u8 header_len; 323 324 /* 0x01, 0x02 */ 325 u8 header_ver; 326 327 u8 reserved[10]; 328 329 /* Number of valid entries in the FWInfo array below */ 330 u32 num_entries; 331 } __packed; 332 333 struct intel_dmc_header_base { 334 /* always value would be 0x40403E3E */ 335 u32 signature; 336 337 /* DMC binary header length */ 338 u8 header_len; 339 340 /* 0x01 */ 341 u8 header_ver; 342 343 /* Reserved */ 344 u16 dmcc_ver; 345 346 /* Major, Minor */ 347 u32 project; 348 349 /* Firmware program size (excluding header) in dwords */ 350 u32 fw_size; 351 352 /* Major Minor version */ 353 u32 fw_version; 354 } __packed; 355 356 struct intel_dmc_header_v1 { 357 struct intel_dmc_header_base base; 358 359 /* Number of valid MMIO cycles present. */ 360 u32 mmio_count; 361 362 /* MMIO address */ 363 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 364 365 /* MMIO data */ 366 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 367 368 /* FW filename */ 369 char dfile[32]; 370 371 u32 reserved1[2]; 372 } __packed; 373 374 struct intel_dmc_header_v3 { 375 struct intel_dmc_header_base base; 376 377 /* DMC RAM start MMIO address */ 378 u32 start_mmioaddr; 379 380 u32 reserved[9]; 381 382 /* FW filename */ 383 char dfile[32]; 384 385 /* Number of valid MMIO cycles present. */ 386 u32 mmio_count; 387 388 /* MMIO address */ 389 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 390 391 /* MMIO data */ 392 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 393 } __packed; 394 395 struct stepping_info { 396 char stepping; 397 char substepping; 398 }; 399 400 #define for_each_dmc_id(__dmc_id) \ 401 for ((__dmc_id) = DMC_FW_MAIN; (__dmc_id) < DMC_FW_MAX; (__dmc_id)++) 402 403 static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) 404 { 405 return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; 406 } 407 408 static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) 409 { 410 struct intel_dmc *dmc = display_to_dmc(display); 411 412 return dmc && dmc->dmc_info[dmc_id].payload; 413 } 414 415 bool intel_dmc_has_payload(struct intel_display *display) 416 { 417 return has_dmc_id_fw(display, DMC_FW_MAIN); 418 } 419 420 static void initialize_stepping_info(struct intel_display *display, struct stepping_info *si) 421 { 422 const char *step_name = DISPLAY_RUNTIME_INFO(display)->step_name; 423 424 si->stepping = step_name[0] ?: '*'; 425 si->substepping = step_name[1] ?: '*'; 426 } 427 428 static void gen9_set_dc_state_debugmask(struct intel_display *display) 429 { 430 /* The below bit doesn't need to be cleared ever afterwards */ 431 intel_de_rmw(display, DC_STATE_DEBUG, 0, 432 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 433 intel_de_posting_read(display, DC_STATE_DEBUG); 434 } 435 436 static void disable_event_handler(struct intel_display *display, 437 i915_reg_t ctl_reg, i915_reg_t htp_reg) 438 { 439 intel_de_write(display, ctl_reg, 440 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 441 DMC_EVT_CTL_TYPE_EDGE_0_1) | 442 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 443 DMC_EVENT_FALSE)); 444 intel_de_write(display, htp_reg, 0); 445 } 446 447 static void disable_all_event_handlers(struct intel_display *display, 448 enum intel_dmc_id dmc_id) 449 { 450 int handler; 451 452 /* TODO: disable the event handlers on pre-GEN12 platforms as well */ 453 if (DISPLAY_VER(display) < 12) 454 return; 455 456 if (!has_dmc_id_fw(display, dmc_id)) 457 return; 458 459 for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) 460 disable_event_handler(display, 461 DMC_EVT_CTL(display, dmc_id, handler), 462 DMC_EVT_HTP(display, dmc_id, handler)); 463 } 464 465 static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 466 { 467 enum pipe pipe; 468 469 /* 470 * Wa_16015201720:adl-p,dg2 471 * The WA requires clock gating to be disabled all the time 472 * for pipe A and B. 473 * For pipe C and D clock gating needs to be disabled only 474 * during initializing the firmware. 475 */ 476 if (enable) 477 for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) 478 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 479 0, PIPEDMC_GATING_DIS); 480 else 481 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) 482 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 483 PIPEDMC_GATING_DIS, 0); 484 } 485 486 static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) 487 { 488 /* 489 * Wa_16015201720 490 * The WA requires clock gating to be disabled all the time 491 * for pipe A and B. 492 */ 493 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, 494 MTL_PIPEDMC_GATING_DIS(PIPE_A) | 495 MTL_PIPEDMC_GATING_DIS(PIPE_B)); 496 } 497 498 static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) 499 { 500 if (display->platform.meteorlake && enable) 501 mtl_pipedmc_clock_gating_wa(display); 502 else if (DISPLAY_VER(display) == 13) 503 adlp_pipedmc_clock_gating_wa(display, enable); 504 } 505 506 static u32 pipedmc_interrupt_mask(struct intel_display *display) 507 { 508 /* 509 * FIXME PIPEDMC_ERROR not enabled for now due to LNL pipe B 510 * triggering it during the first DC state transition. Figure 511 * out what is going on... 512 */ 513 return PIPEDMC_FLIPQ_PROG_DONE | 514 PIPEDMC_GTT_FAULT | 515 PIPEDMC_ATS_FAULT; 516 } 517 518 static u32 dmc_evt_ctl_disable(u32 dmc_evt_ctl) 519 { 520 /* 521 * DMC_EVT_CTL_ENABLE cannot be cleared once set. Always 522 * configure it based on the original event definition to 523 * avoid mismatches in assert_dmc_loaded(). 524 */ 525 return (dmc_evt_ctl & DMC_EVT_CTL_ENABLE) | 526 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, 527 DMC_EVT_CTL_TYPE_EDGE_0_1) | 528 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 529 DMC_EVENT_FALSE); 530 } 531 532 static bool is_dmc_evt_ctl_reg(struct intel_display *display, 533 enum intel_dmc_id dmc_id, i915_reg_t reg) 534 { 535 u32 offset = i915_mmio_reg_offset(reg); 536 u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); 537 u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 538 539 return offset >= start && offset < end; 540 } 541 542 static bool is_dmc_evt_htp_reg(struct intel_display *display, 543 enum intel_dmc_id dmc_id, i915_reg_t reg) 544 { 545 u32 offset = i915_mmio_reg_offset(reg); 546 u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); 547 u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); 548 549 return offset >= start && offset < end; 550 } 551 552 static bool is_event_handler(struct intel_display *display, 553 enum intel_dmc_id dmc_id, 554 unsigned int event_id, 555 i915_reg_t reg, u32 data) 556 { 557 return is_dmc_evt_ctl_reg(display, dmc_id, reg) && 558 REG_FIELD_GET(DMC_EVT_CTL_EVENT_ID_MASK, data) == event_id; 559 } 560 561 static bool fixup_dmc_evt(struct intel_display *display, 562 enum intel_dmc_id dmc_id, 563 i915_reg_t reg_ctl, u32 *data_ctl, 564 i915_reg_t reg_htp, u32 *data_htp) 565 { 566 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg_ctl)) 567 return false; 568 569 if (!is_dmc_evt_htp_reg(display, dmc_id, reg_htp)) 570 return false; 571 572 /* make sure reg_ctl and reg_htp are for the same event */ 573 if (i915_mmio_reg_offset(reg_ctl) - i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)) != 574 i915_mmio_reg_offset(reg_htp) - i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0))) 575 return false; 576 577 /* 578 * On ADL-S the HRR event handler is not restored after DC6. 579 * Clear it to zero from the beginning to avoid mismatches later. 580 */ 581 if (display->platform.alderlake_s && dmc_id == DMC_FW_MAIN && 582 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 583 *data_ctl = 0; 584 *data_htp = 0; 585 return true; 586 } 587 588 /* 589 * TGL/ADL-S DMC firmware incorrectly uses the undelayed vblank 590 * event for the HRR handler, when it should be using the delayed 591 * vblank event instead. Fixed firmware was never released 592 * so the Windows driver just hacks around it by overriding 593 * the event ID. Do the same. 594 */ 595 if ((display->platform.tigerlake || display->platform.alderlake_s) && 596 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_A, reg_ctl, *data_ctl)) { 597 *data_ctl &= ~DMC_EVT_CTL_EVENT_ID_MASK; 598 *data_ctl |= REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, 599 MAINDMC_EVENT_VBLANK_DELAYED_A); 600 return true; 601 } 602 603 return false; 604 } 605 606 static bool disable_dmc_evt(struct intel_display *display, 607 enum intel_dmc_id dmc_id, 608 i915_reg_t reg, u32 data) 609 { 610 if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) 611 return false; 612 613 /* keep all pipe DMC events disabled by default */ 614 if (dmc_id != DMC_FW_MAIN) 615 return true; 616 617 /* also disable the flip queue event on the main DMC on TGL */ 618 if (display->platform.tigerlake && 619 is_event_handler(display, dmc_id, MAINDMC_EVENT_CLK_MSEC, reg, data)) 620 return true; 621 622 /* also disable the HRR event on the main DMC on TGL/ADLS */ 623 if ((display->platform.tigerlake || display->platform.alderlake_s) && 624 is_event_handler(display, dmc_id, MAINDMC_EVENT_VBLANK_DELAYED_A, reg, data)) 625 return true; 626 627 return false; 628 } 629 630 static u32 dmc_mmiodata(struct intel_display *display, 631 struct intel_dmc *dmc, 632 enum intel_dmc_id dmc_id, int i) 633 { 634 if (disable_dmc_evt(display, dmc_id, 635 dmc->dmc_info[dmc_id].mmioaddr[i], 636 dmc->dmc_info[dmc_id].mmiodata[i])) 637 return dmc_evt_ctl_disable(dmc->dmc_info[dmc_id].mmiodata[i]); 638 else 639 return dmc->dmc_info[dmc_id].mmiodata[i]; 640 } 641 642 static void dmc_load_mmio(struct intel_display *display, enum intel_dmc_id dmc_id) 643 { 644 struct intel_dmc *dmc = display_to_dmc(display); 645 int i; 646 647 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 648 intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], 649 dmc_mmiodata(display, dmc, dmc_id, i)); 650 } 651 } 652 653 static void dmc_load_program(struct intel_display *display, enum intel_dmc_id dmc_id) 654 { 655 struct intel_dmc *dmc = display_to_dmc(display); 656 int i; 657 658 disable_all_event_handlers(display, dmc_id); 659 660 preempt_disable(); 661 662 for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { 663 intel_de_write_fw(display, 664 DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), 665 dmc->dmc_info[dmc_id].payload[i]); 666 } 667 668 preempt_enable(); 669 670 dmc_load_mmio(display, dmc_id); 671 } 672 673 static void assert_dmc_loaded(struct intel_display *display, 674 enum intel_dmc_id dmc_id) 675 { 676 struct intel_dmc *dmc = display_to_dmc(display); 677 u32 expected, found; 678 int i; 679 680 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 681 return; 682 683 found = intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, 0)); 684 expected = dmc->dmc_info[dmc_id].payload[0]; 685 686 drm_WARN(display->drm, found != expected, 687 "DMC %d program storage start incorrect (expected 0x%x, current 0x%x)\n", 688 dmc_id, expected, found); 689 690 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 691 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 692 693 found = intel_de_read(display, reg); 694 expected = dmc_mmiodata(display, dmc, dmc_id, i); 695 696 drm_WARN(display->drm, found != expected, 697 "DMC %d mmio[%d]/0x%x incorrect (expected 0x%x, current 0x%x)\n", 698 dmc_id, i, i915_mmio_reg_offset(reg), expected, found); 699 } 700 } 701 702 void assert_main_dmc_loaded(struct intel_display *display) 703 { 704 assert_dmc_loaded(display, DMC_FW_MAIN); 705 } 706 707 static bool need_pipedmc_load_program(struct intel_display *display) 708 { 709 /* On TGL/derivatives pipe DMC state is lost when PG1 is disabled */ 710 return DISPLAY_VER(display) == 12; 711 } 712 713 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe) 714 { 715 /* 716 * Xe3_LPD/Xe3p_LPD: 717 * - pipe A/B DMC doesn't need save/restore 718 * - pipe C/D DMC is in PG0, needs manual save/restore 719 */ 720 if (IS_DISPLAY_VER(display, 30, 35)) 721 return pipe >= PIPE_C; 722 723 /* 724 * FIXME LNL unclear, main DMC firmware has the pipe DMC A/B PG0 725 * save/restore, but so far unable to see the loss of pipe DMC state 726 * in action. Are we just failing to turn off PG0 due to some other 727 * SoC level stuff? 728 */ 729 if (DISPLAY_VER(display) == 20) 730 return false; 731 732 /* 733 * FIXME BMG untested, main DMC firmware has the 734 * pipe DMC A/B PG0 save/restore... 735 */ 736 if (display->platform.battlemage) 737 return false; 738 739 /* 740 * DG2: 741 * - Pipe DMCs presumably in PG0? 742 * - No DC6, and even DC9 doesn't seem to result 743 * in loss of DMC state for whatever reason 744 */ 745 if (display->platform.dg2) 746 return false; 747 748 /* 749 * ADL/MTL: 750 * - pipe A/B DMC is in PG0, saved/restored by the main DMC 751 * - pipe C/D DMC is in PG0, needs manual save/restore 752 */ 753 if (IS_DISPLAY_VER(display, 13, 14)) 754 return pipe >= PIPE_C; 755 756 return false; 757 } 758 759 static bool can_enable_pipedmc(const struct intel_crtc_state *crtc_state) 760 { 761 struct intel_display *display = to_intel_display(crtc_state); 762 763 /* 764 * On TGL/derivatives pipe DMC state is lost when PG1 is disabled. 765 * Do not even enable the pipe DMC when that can happen outside 766 * of driver control (PSR+DC5/6). 767 */ 768 if (DISPLAY_VER(display) == 12 && crtc_state->has_psr) 769 return false; 770 771 return true; 772 } 773 774 void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state) 775 { 776 struct intel_display *display = to_intel_display(crtc_state); 777 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 778 enum pipe pipe = crtc->pipe; 779 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 780 781 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 782 return; 783 784 if (!can_enable_pipedmc(crtc_state)) { 785 intel_dmc_disable_pipe(crtc_state); 786 return; 787 } 788 789 if (need_pipedmc_load_program(display)) 790 dmc_load_program(display, dmc_id); 791 else if (need_pipedmc_load_mmio(display, pipe)) 792 dmc_load_mmio(display, dmc_id); 793 794 assert_dmc_loaded(display, dmc_id); 795 796 if (DISPLAY_VER(display) >= 20) { 797 intel_flipq_reset(display, pipe); 798 799 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 800 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display)); 801 } 802 803 if (DISPLAY_VER(display) >= 14) 804 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); 805 else 806 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); 807 } 808 809 void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state) 810 { 811 struct intel_display *display = to_intel_display(crtc_state); 812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 813 enum pipe pipe = crtc->pipe; 814 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 815 816 if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) 817 return; 818 819 if (DISPLAY_VER(display) >= 14) 820 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); 821 else 822 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); 823 824 if (DISPLAY_VER(display) >= 20) { 825 intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~0); 826 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), pipedmc_interrupt_mask(display)); 827 828 intel_flipq_reset(display, pipe); 829 } 830 } 831 832 static void dmc_configure_event(struct intel_display *display, 833 enum intel_dmc_id dmc_id, 834 unsigned int event_id, 835 bool enable) 836 { 837 struct intel_dmc *dmc = display_to_dmc(display); 838 int num_handlers = 0; 839 int i; 840 841 for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { 842 i915_reg_t reg = dmc->dmc_info[dmc_id].mmioaddr[i]; 843 u32 data = dmc->dmc_info[dmc_id].mmiodata[i]; 844 845 if (!is_event_handler(display, dmc_id, event_id, reg, data)) 846 continue; 847 848 intel_de_write(display, reg, enable ? data : dmc_evt_ctl_disable(data)); 849 num_handlers++; 850 } 851 852 drm_WARN_ONCE(display->drm, num_handlers != 1, 853 "DMC %d has %d handlers for event 0x%x\n", 854 dmc_id, num_handlers, event_id); 855 } 856 857 void intel_dmc_configure_dc_balance_event(struct intel_display *display, 858 enum pipe pipe, bool enable) 859 { 860 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 861 862 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); 863 } 864 865 /** 866 * intel_dmc_block_pkgc() - block PKG C-state 867 * @display: display instance 868 * @pipe: pipe which register use to block 869 * @block: block/unblock 870 * 871 * This interface is target for Wa_16025596647 usage. I.e. to set/clear 872 * PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS bit in PIPEDMC_BLOCK_PKGC_SW register. 873 */ 874 void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, 875 bool block) 876 { 877 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), 878 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS, block ? 879 PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0); 880 } 881 882 /** 883 * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG 884 * C-state exit 885 * @display: display instance 886 * @pipe: pipe which register use to block 887 * @enable: enable/disable 888 * 889 * This interface is target for Wa_16025596647 usage. I.e. start the package C 890 * exit at the start of the undelayed vblank 891 */ 892 void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, 893 enum pipe pipe, bool enable) 894 { 895 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); 896 897 dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_VBLANK, enable); 898 } 899 900 /** 901 * intel_dmc_load_program() - write the firmware from memory to register. 902 * @display: display instance 903 * 904 * DMC firmware is read from a .bin file and kept in internal memory one time. 905 * Everytime display comes back from low power state this function is called to 906 * copy the firmware from internal memory to registers. 907 */ 908 void intel_dmc_load_program(struct intel_display *display) 909 { 910 struct i915_power_domains *power_domains = &display->power.domains; 911 enum intel_dmc_id dmc_id; 912 913 if (!intel_dmc_has_payload(display)) 914 return; 915 916 assert_display_rpm_held(display); 917 918 pipedmc_clock_gating_wa(display, true); 919 920 for_each_dmc_id(dmc_id) { 921 dmc_load_program(display, dmc_id); 922 assert_dmc_loaded(display, dmc_id); 923 } 924 925 if (DISPLAY_VER(display) >= 20) 926 intel_de_write(display, DMC_FQ_W2_PTS_CFG_SEL, 927 PIPE_D_DMC_W2_PTS_CONFIG_SELECT(PIPE_D) | 928 PIPE_C_DMC_W2_PTS_CONFIG_SELECT(PIPE_C) | 929 PIPE_B_DMC_W2_PTS_CONFIG_SELECT(PIPE_B) | 930 PIPE_A_DMC_W2_PTS_CONFIG_SELECT(PIPE_A)); 931 932 power_domains->dc_state = 0; 933 934 gen9_set_dc_state_debugmask(display); 935 936 pipedmc_clock_gating_wa(display, false); 937 } 938 939 /** 940 * intel_dmc_disable_program() - disable the firmware 941 * @display: display instance 942 * 943 * Disable all event handlers in the firmware, making sure the firmware is 944 * inactive after the display is uninitialized. 945 */ 946 void intel_dmc_disable_program(struct intel_display *display) 947 { 948 enum intel_dmc_id dmc_id; 949 950 if (!intel_dmc_has_payload(display)) 951 return; 952 953 pipedmc_clock_gating_wa(display, true); 954 955 for_each_dmc_id(dmc_id) 956 disable_all_event_handlers(display, dmc_id); 957 958 pipedmc_clock_gating_wa(display, false); 959 } 960 961 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 962 const struct stepping_info *si) 963 { 964 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 965 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 966 /* 967 * If we don't find a more specific one from above two checks, we 968 * then check for the generic one to be sure to work even with 969 * "broken firmware" 970 */ 971 (si->stepping == '*' && si->substepping == fw_info->substepping) || 972 (fw_info->stepping == '*' && fw_info->substepping == '*')) 973 return true; 974 975 return false; 976 } 977 978 /* 979 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 980 * already sanitized. 981 */ 982 static void dmc_set_fw_offset(struct intel_dmc *dmc, 983 const struct intel_fw_info *fw_info, 984 unsigned int num_entries, 985 const struct stepping_info *si, 986 u8 package_ver) 987 { 988 struct intel_display *display = dmc->display; 989 enum intel_dmc_id dmc_id; 990 unsigned int i; 991 992 for (i = 0; i < num_entries; i++) { 993 dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 994 995 if (!is_valid_dmc_id(dmc_id)) { 996 drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); 997 continue; 998 } 999 1000 /* More specific versions come first, so we don't even have to 1001 * check for the stepping since we already found a previous FW 1002 * for this id. 1003 */ 1004 if (dmc->dmc_info[dmc_id].present) 1005 continue; 1006 1007 if (fw_info_matches_stepping(&fw_info[i], si)) { 1008 dmc->dmc_info[dmc_id].present = true; 1009 dmc->dmc_info[dmc_id].dmc_offset = fw_info[i].offset; 1010 } 1011 } 1012 } 1013 1014 static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, 1015 const u32 *mmioaddr, u32 mmio_count, 1016 int header_ver, enum intel_dmc_id dmc_id) 1017 { 1018 struct intel_display *display = dmc->display; 1019 u32 start_range, end_range; 1020 int i; 1021 1022 if (header_ver == 1) { 1023 start_range = DMC_MMIO_START_RANGE; 1024 end_range = DMC_MMIO_END_RANGE; 1025 } else if (dmc_id == DMC_FW_MAIN) { 1026 start_range = TGL_MAIN_MMIO_START; 1027 end_range = TGL_MAIN_MMIO_END; 1028 } else if (DISPLAY_VER(display) >= 13) { 1029 start_range = ADLP_PIPE_MMIO_START; 1030 end_range = ADLP_PIPE_MMIO_END; 1031 } else if (DISPLAY_VER(display) >= 12) { 1032 start_range = TGL_PIPE_MMIO_START(dmc_id); 1033 end_range = TGL_PIPE_MMIO_END(dmc_id); 1034 } else { 1035 drm_warn(display->drm, "Unknown mmio range for sanity check"); 1036 return false; 1037 } 1038 1039 for (i = 0; i < mmio_count; i++) { 1040 if (mmioaddr[i] < start_range || mmioaddr[i] > end_range) 1041 return false; 1042 } 1043 1044 return true; 1045 } 1046 1047 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 1048 const struct intel_dmc_header_base *dmc_header, 1049 size_t rem_size, enum intel_dmc_id dmc_id) 1050 { 1051 struct intel_display *display = dmc->display; 1052 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 1053 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 1054 const u32 *mmioaddr, *mmiodata; 1055 u32 mmio_count, mmio_count_max, start_mmioaddr; 1056 u8 *payload; 1057 1058 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 1059 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 1060 1061 /* 1062 * Check if we can access common fields, we will checkc again below 1063 * after we have read the version 1064 */ 1065 if (rem_size < sizeof(struct intel_dmc_header_base)) 1066 goto error_truncated; 1067 1068 /* Cope with small differences between v1 and v3 */ 1069 if (dmc_header->header_ver == 3) { 1070 const struct intel_dmc_header_v3 *v3 = 1071 (const struct intel_dmc_header_v3 *)dmc_header; 1072 1073 if (rem_size < sizeof(struct intel_dmc_header_v3)) 1074 goto error_truncated; 1075 1076 mmioaddr = v3->mmioaddr; 1077 mmiodata = v3->mmiodata; 1078 mmio_count = v3->mmio_count; 1079 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 1080 /* header_len is in dwords */ 1081 header_len_bytes = dmc_header->header_len * 4; 1082 start_mmioaddr = v3->start_mmioaddr; 1083 dmc_header_size = sizeof(*v3); 1084 } else if (dmc_header->header_ver == 1) { 1085 const struct intel_dmc_header_v1 *v1 = 1086 (const struct intel_dmc_header_v1 *)dmc_header; 1087 1088 if (rem_size < sizeof(struct intel_dmc_header_v1)) 1089 goto error_truncated; 1090 1091 mmioaddr = v1->mmioaddr; 1092 mmiodata = v1->mmiodata; 1093 mmio_count = v1->mmio_count; 1094 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 1095 header_len_bytes = dmc_header->header_len; 1096 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 1097 dmc_header_size = sizeof(*v1); 1098 } else { 1099 drm_err(display->drm, "Unknown DMC fw header version: %u\n", 1100 dmc_header->header_ver); 1101 return 0; 1102 } 1103 1104 if (header_len_bytes != dmc_header_size) { 1105 drm_err(display->drm, "DMC firmware has wrong dmc header length " 1106 "(%u bytes)\n", header_len_bytes); 1107 return 0; 1108 } 1109 1110 /* Cache the dmc header info. */ 1111 if (mmio_count > mmio_count_max) { 1112 drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 1113 return 0; 1114 } 1115 1116 if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, 1117 dmc_header->header_ver, dmc_id)) { 1118 drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); 1119 return 0; 1120 } 1121 1122 drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); 1123 for (i = 0; i < mmio_count; i++) { 1124 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 1125 dmc_info->mmiodata[i] = mmiodata[i]; 1126 } 1127 1128 for (i = 0; i < mmio_count - 1; i++) { 1129 u32 orig_mmiodata[2] = { 1130 dmc_info->mmiodata[i], 1131 dmc_info->mmiodata[i+1], 1132 }; 1133 1134 if (!fixup_dmc_evt(display, dmc_id, 1135 dmc_info->mmioaddr[i], &dmc_info->mmiodata[i], 1136 dmc_info->mmioaddr[i+1], &dmc_info->mmiodata[i+1])) 1137 continue; 1138 1139 drm_dbg_kms(display->drm, 1140 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_CTL)\n", 1141 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), 1142 orig_mmiodata[0], dmc_info->mmiodata[i]); 1143 drm_dbg_kms(display->drm, 1144 " mmio[%d]: 0x%x = 0x%x->0x%x (EVT_HTP)\n", 1145 i+1, i915_mmio_reg_offset(dmc_info->mmioaddr[i+1]), 1146 orig_mmiodata[1], dmc_info->mmiodata[i+1]); 1147 } 1148 1149 for (i = 0; i < mmio_count; i++) { 1150 drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", 1151 i, i915_mmio_reg_offset(dmc_info->mmioaddr[i]), dmc_info->mmiodata[i], 1152 is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : 1153 is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", 1154 disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], 1155 dmc_info->mmiodata[i]) ? " (disabling)" : ""); 1156 } 1157 dmc_info->mmio_count = mmio_count; 1158 dmc_info->start_mmioaddr = start_mmioaddr; 1159 1160 rem_size -= header_len_bytes; 1161 1162 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 1163 payload_size = dmc_header->fw_size * 4; 1164 if (rem_size < payload_size) 1165 goto error_truncated; 1166 1167 if (payload_size > dmc->max_fw_size) { 1168 drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); 1169 return 0; 1170 } 1171 dmc_info->dmc_fw_size = dmc_header->fw_size; 1172 1173 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 1174 if (!dmc_info->payload) 1175 return 0; 1176 1177 payload = (u8 *)(dmc_header) + header_len_bytes; 1178 memcpy(dmc_info->payload, payload, payload_size); 1179 1180 return header_len_bytes + payload_size; 1181 1182 error_truncated: 1183 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1184 return 0; 1185 } 1186 1187 static u32 1188 parse_dmc_fw_package(struct intel_dmc *dmc, 1189 const struct intel_package_header *package_header, 1190 const struct stepping_info *si, 1191 size_t rem_size) 1192 { 1193 struct intel_display *display = dmc->display; 1194 u32 package_size = sizeof(struct intel_package_header); 1195 u32 num_entries, max_entries; 1196 const struct intel_fw_info *fw_info; 1197 1198 if (rem_size < package_size) 1199 goto error_truncated; 1200 1201 if (package_header->header_ver == 1) { 1202 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 1203 } else if (package_header->header_ver == 2) { 1204 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 1205 } else { 1206 drm_err(display->drm, "DMC firmware has unknown header version %u\n", 1207 package_header->header_ver); 1208 return 0; 1209 } 1210 1211 /* 1212 * We should always have space for max_entries, 1213 * even if not all are used 1214 */ 1215 package_size += max_entries * sizeof(struct intel_fw_info); 1216 if (rem_size < package_size) 1217 goto error_truncated; 1218 1219 if (package_header->header_len * 4 != package_size) { 1220 drm_err(display->drm, "DMC firmware has wrong package header length " 1221 "(%u bytes)\n", package_size); 1222 return 0; 1223 } 1224 1225 num_entries = package_header->num_entries; 1226 if (WARN_ON(num_entries > max_entries)) 1227 num_entries = max_entries; 1228 1229 fw_info = (const struct intel_fw_info *) 1230 ((u8 *)package_header + sizeof(*package_header)); 1231 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 1232 package_header->header_ver); 1233 1234 /* dmc_offset is in dwords */ 1235 return package_size; 1236 1237 error_truncated: 1238 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1239 return 0; 1240 } 1241 1242 /* Return number of bytes parsed or 0 on error */ 1243 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 1244 struct intel_css_header *css_header, 1245 size_t rem_size) 1246 { 1247 struct intel_display *display = dmc->display; 1248 1249 if (rem_size < sizeof(struct intel_css_header)) { 1250 drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); 1251 return 0; 1252 } 1253 1254 if (sizeof(struct intel_css_header) != 1255 (css_header->header_len * 4)) { 1256 drm_err(display->drm, "DMC firmware has wrong CSS header length " 1257 "(%u bytes)\n", 1258 (css_header->header_len * 4)); 1259 return 0; 1260 } 1261 1262 dmc->version = css_header->version; 1263 1264 return sizeof(struct intel_css_header); 1265 } 1266 1267 static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) 1268 { 1269 struct intel_display *display = dmc->display; 1270 struct intel_css_header *css_header; 1271 struct intel_package_header *package_header; 1272 struct intel_dmc_header_base *dmc_header; 1273 struct stepping_info si = {}; 1274 enum intel_dmc_id dmc_id; 1275 u32 readcount = 0; 1276 u32 r, offset; 1277 1278 if (!fw) 1279 return -EINVAL; 1280 1281 initialize_stepping_info(display, &si); 1282 1283 /* Extract CSS Header information */ 1284 css_header = (struct intel_css_header *)fw->data; 1285 r = parse_dmc_fw_css(dmc, css_header, fw->size); 1286 if (!r) 1287 return -EINVAL; 1288 1289 readcount += r; 1290 1291 /* Extract Package Header information */ 1292 package_header = (struct intel_package_header *)&fw->data[readcount]; 1293 r = parse_dmc_fw_package(dmc, package_header, &si, fw->size - readcount); 1294 if (!r) 1295 return -EINVAL; 1296 1297 readcount += r; 1298 1299 for_each_dmc_id(dmc_id) { 1300 if (!dmc->dmc_info[dmc_id].present) 1301 continue; 1302 1303 offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; 1304 if (offset > fw->size) { 1305 drm_err(display->drm, "Reading beyond the fw_size\n"); 1306 continue; 1307 } 1308 1309 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 1310 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); 1311 } 1312 1313 if (!intel_dmc_has_payload(display)) { 1314 drm_err(display->drm, "DMC firmware main program not found\n"); 1315 return -ENOENT; 1316 } 1317 1318 return 0; 1319 } 1320 1321 static void intel_dmc_runtime_pm_get(struct intel_display *display) 1322 { 1323 drm_WARN_ON(display->drm, display->dmc.wakeref); 1324 display->dmc.wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); 1325 } 1326 1327 static void intel_dmc_runtime_pm_put(struct intel_display *display) 1328 { 1329 struct ref_tracker *wakeref __maybe_unused = 1330 fetch_and_zero(&display->dmc.wakeref); 1331 1332 intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); 1333 } 1334 1335 static const char *dmc_fallback_path(struct intel_display *display) 1336 { 1337 if (display->platform.alderlake_p) 1338 return ADLP_DMC_FALLBACK_PATH; 1339 1340 return NULL; 1341 } 1342 1343 static void dmc_load_work_fn(struct work_struct *work) 1344 { 1345 struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); 1346 struct intel_display *display = dmc->display; 1347 const struct firmware *fw = NULL; 1348 const char *fallback_path; 1349 int err; 1350 1351 err = request_firmware(&fw, dmc->fw_path, display->drm->dev); 1352 1353 if (err == -ENOENT && !dmc_firmware_param(display)) { 1354 fallback_path = dmc_fallback_path(display); 1355 if (fallback_path) { 1356 drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", 1357 dmc->fw_path, fallback_path); 1358 err = request_firmware(&fw, fallback_path, display->drm->dev); 1359 if (err == 0) 1360 dmc->fw_path = fallback_path; 1361 } 1362 } 1363 1364 if (err) { 1365 drm_notice(display->drm, 1366 "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", 1367 dmc->fw_path, ERR_PTR(err)); 1368 drm_notice(display->drm, "DMC firmware homepage: %s", 1369 INTEL_DMC_FIRMWARE_URL); 1370 return; 1371 } 1372 1373 err = parse_dmc_fw(dmc, fw); 1374 if (err) { 1375 drm_notice(display->drm, 1376 "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", 1377 dmc->fw_path, ERR_PTR(err)); 1378 goto out; 1379 } 1380 1381 intel_dmc_load_program(display); 1382 intel_dmc_runtime_pm_put(display); 1383 1384 drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", 1385 dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), 1386 DMC_VERSION_MINOR(dmc->version)); 1387 1388 out: 1389 release_firmware(fw); 1390 } 1391 1392 /** 1393 * intel_dmc_init() - initialize the firmware loading. 1394 * @display: display instance 1395 * 1396 * This function is called at the time of loading the display driver to read 1397 * firmware from a .bin file and copied into a internal memory. 1398 */ 1399 void intel_dmc_init(struct intel_display *display) 1400 { 1401 struct intel_dmc *dmc; 1402 1403 if (!HAS_DMC(display)) 1404 return; 1405 1406 /* 1407 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 1408 * runtime-suspend. 1409 * 1410 * On error, we return with the rpm wakeref held to prevent runtime 1411 * suspend as runtime suspend *requires* a working DMC for whatever 1412 * reason. 1413 */ 1414 intel_dmc_runtime_pm_get(display); 1415 1416 dmc = kzalloc_obj(*dmc); 1417 if (!dmc) 1418 return; 1419 1420 dmc->display = display; 1421 1422 INIT_WORK(&dmc->work, dmc_load_work_fn); 1423 1424 dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); 1425 1426 if (dmc_firmware_param_disabled(display)) { 1427 drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); 1428 goto out; 1429 } 1430 1431 if (dmc_firmware_param(display)) 1432 dmc->fw_path = dmc_firmware_param(display); 1433 1434 if (!dmc->fw_path) { 1435 drm_dbg_kms(display->drm, 1436 "No known DMC firmware for platform, disabling runtime PM\n"); 1437 goto out; 1438 } 1439 1440 display->dmc.dmc = dmc; 1441 1442 drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); 1443 queue_work(display->wq.unordered, &dmc->work); 1444 1445 return; 1446 1447 out: 1448 kfree(dmc); 1449 } 1450 1451 /** 1452 * intel_dmc_suspend() - prepare DMC firmware before system suspend 1453 * @display: display instance 1454 * 1455 * Prepare the DMC firmware before entering system suspend. This includes 1456 * flushing pending work items and releasing any resources acquired during 1457 * init. 1458 */ 1459 void intel_dmc_suspend(struct intel_display *display) 1460 { 1461 struct intel_dmc *dmc = display_to_dmc(display); 1462 1463 if (!HAS_DMC(display)) 1464 return; 1465 1466 if (dmc) 1467 flush_work(&dmc->work); 1468 1469 /* Drop the reference held in case DMC isn't loaded. */ 1470 if (!intel_dmc_has_payload(display)) 1471 intel_dmc_runtime_pm_put(display); 1472 } 1473 1474 void intel_dmc_wait_fw_load(struct intel_display *display) 1475 { 1476 struct intel_dmc *dmc = display_to_dmc(display); 1477 1478 if (!HAS_DMC(display)) 1479 return; 1480 1481 if (dmc) 1482 flush_work(&dmc->work); 1483 } 1484 1485 /** 1486 * intel_dmc_resume() - init DMC firmware during system resume 1487 * @display: display instance 1488 * 1489 * Reinitialize the DMC firmware during system resume, reacquiring any 1490 * resources released in intel_dmc_suspend(). 1491 */ 1492 void intel_dmc_resume(struct intel_display *display) 1493 { 1494 if (!HAS_DMC(display)) 1495 return; 1496 1497 /* 1498 * Reacquire the reference to keep RPM disabled in case DMC isn't 1499 * loaded. 1500 */ 1501 if (!intel_dmc_has_payload(display)) 1502 intel_dmc_runtime_pm_get(display); 1503 } 1504 1505 /** 1506 * intel_dmc_fini() - unload the DMC firmware. 1507 * @display: display instance 1508 * 1509 * Firmmware unloading includes freeing the internal memory and reset the 1510 * firmware loading status. 1511 */ 1512 void intel_dmc_fini(struct intel_display *display) 1513 { 1514 struct intel_dmc *dmc = display_to_dmc(display); 1515 enum intel_dmc_id dmc_id; 1516 1517 if (!HAS_DMC(display)) 1518 return; 1519 1520 intel_dmc_suspend(display); 1521 drm_WARN_ON(display->drm, display->dmc.wakeref); 1522 1523 if (dmc) { 1524 for_each_dmc_id(dmc_id) 1525 kfree(dmc->dmc_info[dmc_id].payload); 1526 1527 kfree(dmc); 1528 display->dmc.dmc = NULL; 1529 } 1530 } 1531 1532 struct intel_dmc_snapshot { 1533 bool initialized; 1534 bool loaded; 1535 u32 version; 1536 }; 1537 1538 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display) 1539 { 1540 struct intel_dmc *dmc = display_to_dmc(display); 1541 struct intel_dmc_snapshot *snapshot; 1542 1543 if (!HAS_DMC(display)) 1544 return NULL; 1545 1546 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 1547 if (!snapshot) 1548 return NULL; 1549 1550 snapshot->initialized = dmc; 1551 snapshot->loaded = intel_dmc_has_payload(display); 1552 if (dmc) 1553 snapshot->version = dmc->version; 1554 1555 return snapshot; 1556 } 1557 1558 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p) 1559 { 1560 if (!snapshot) 1561 return; 1562 1563 drm_printf(p, "DMC initialized: %s\n", str_yes_no(snapshot->initialized)); 1564 drm_printf(p, "DMC loaded: %s\n", str_yes_no(snapshot->loaded)); 1565 if (snapshot->initialized) 1566 drm_printf(p, "DMC fw version: %d.%d\n", 1567 DMC_VERSION_MAJOR(snapshot->version), 1568 DMC_VERSION_MINOR(snapshot->version)); 1569 } 1570 1571 void intel_dmc_update_dc6_allowed_count(struct intel_display *display, 1572 bool start_tracking) 1573 { 1574 struct intel_dmc *dmc = display_to_dmc(display); 1575 u32 dc5_cur_count; 1576 1577 if (DISPLAY_VER(dmc->display) < 14) 1578 return; 1579 1580 dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT); 1581 1582 if (!start_tracking) 1583 dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start; 1584 1585 dmc->dc6_allowed.dc5_start = dc5_cur_count; 1586 } 1587 1588 static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count) 1589 { 1590 struct i915_power_domains *power_domains = &display->power.domains; 1591 struct intel_dmc *dmc = display_to_dmc(display); 1592 bool dc6_enabled; 1593 1594 if (DISPLAY_VER(display) < 14) 1595 return false; 1596 1597 mutex_lock(&power_domains->lock); 1598 dc6_enabled = power_domains->dc_state & DC_STATE_EN_UPTO_DC6; 1599 if (dc6_enabled) 1600 intel_dmc_update_dc6_allowed_count(display, false); 1601 1602 *count = dmc->dc6_allowed.count; 1603 mutex_unlock(&power_domains->lock); 1604 1605 return true; 1606 } 1607 1608 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 1609 { 1610 struct intel_display *display = m->private; 1611 struct intel_dmc *dmc = display_to_dmc(display); 1612 struct ref_tracker *wakeref; 1613 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 1614 u32 dc6_allowed_count; 1615 1616 if (!HAS_DMC(display)) 1617 return -ENODEV; 1618 1619 wakeref = intel_display_rpm_get(display); 1620 1621 seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); 1622 seq_printf(m, "fw loaded: %s\n", 1623 str_yes_no(intel_dmc_has_payload(display))); 1624 seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); 1625 seq_printf(m, "Pipe A fw needed: %s\n", 1626 str_yes_no(DISPLAY_VER(display) >= 12)); 1627 seq_printf(m, "Pipe A fw loaded: %s\n", 1628 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); 1629 seq_printf(m, "Pipe B fw needed: %s\n", 1630 str_yes_no(display->platform.alderlake_p || 1631 DISPLAY_VER(display) >= 14)); 1632 seq_printf(m, "Pipe B fw loaded: %s\n", 1633 str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); 1634 1635 if (!intel_dmc_has_payload(display)) 1636 goto out; 1637 1638 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 1639 DMC_VERSION_MINOR(dmc->version)); 1640 1641 if (DISPLAY_VER(display) >= 12) { 1642 i915_reg_t dc3co_reg; 1643 1644 if (display->platform.dgfx || DISPLAY_VER(display) >= 14) { 1645 dc3co_reg = DG1_DMC_DEBUG3; 1646 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 1647 } else { 1648 dc3co_reg = TGL_DMC_DEBUG3; 1649 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 1650 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 1651 } 1652 1653 seq_printf(m, "DC3CO count: %d\n", 1654 intel_de_read(display, dc3co_reg)); 1655 } else { 1656 dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT : 1657 SKL_DMC_DC3_DC5_COUNT; 1658 if (!display->platform.geminilake && !display->platform.broxton) 1659 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 1660 } 1661 1662 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); 1663 1664 if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count)) 1665 seq_printf(m, "DC5 -> DC6 allowed count: %d\n", 1666 dc6_allowed_count); 1667 else if (i915_mmio_reg_valid(dc6_reg)) 1668 seq_printf(m, "DC5 -> DC6 count: %d\n", 1669 intel_de_read(display, dc6_reg)); 1670 1671 seq_printf(m, "program base: 0x%08x\n", 1672 intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 1673 1674 out: 1675 seq_printf(m, "ssp base: 0x%08x\n", 1676 intel_de_read(display, DMC_SSP_BASE)); 1677 seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); 1678 1679 intel_display_rpm_put(display, wakeref); 1680 1681 return 0; 1682 } 1683 1684 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 1685 1686 void intel_dmc_debugfs_register(struct intel_display *display) 1687 { 1688 debugfs_create_file("i915_dmc_info", 0444, display->drm->debugfs_root, 1689 display, &intel_dmc_debugfs_status_fops); 1690 } 1691 1692 void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe) 1693 { 1694 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 1695 u32 tmp = 0, int_vector; 1696 1697 if (DISPLAY_VER(display) >= 20) { 1698 tmp = intel_de_read(display, PIPEDMC_INTERRUPT(pipe)); 1699 intel_de_write(display, PIPEDMC_INTERRUPT(pipe), tmp); 1700 1701 if (tmp & PIPEDMC_FLIPQ_PROG_DONE) { 1702 spin_lock(&display->drm->event_lock); 1703 1704 if (crtc->flipq_event) { 1705 /* 1706 * Update vblank counter/timestamp in case it 1707 * hasn't been done yet for this frame. 1708 */ 1709 drm_crtc_accurate_vblank_count(&crtc->base); 1710 1711 drm_crtc_send_vblank_event(&crtc->base, crtc->flipq_event); 1712 crtc->flipq_event = NULL; 1713 } 1714 1715 spin_unlock(&display->drm->event_lock); 1716 } 1717 1718 if (tmp & PIPEDMC_ATS_FAULT) 1719 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC ATS fault\n", 1720 crtc->base.base.id, crtc->base.name); 1721 if (tmp & PIPEDMC_GTT_FAULT) 1722 drm_err_ratelimited(display->drm, "[CRTC:%d:%s] PIPEDMC GTT fault\n", 1723 crtc->base.base.id, crtc->base.name); 1724 if (tmp & PIPEDMC_ERROR) 1725 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC error\n", 1726 crtc->base.base.id, crtc->base.name); 1727 } 1728 1729 int_vector = intel_de_read(display, PIPEDMC_STATUS(pipe)) & PIPEDMC_INT_VECTOR_MASK; 1730 if (tmp == 0 && int_vector != 0) 1731 drm_err(display->drm, "[CRTC:%d:%s] PIPEDMC interrupt vector 0x%x\n", 1732 crtc->base.base.id, crtc->base.name, int_vector); 1733 } 1734 1735 void intel_pipedmc_enable_event(struct intel_crtc *crtc, 1736 enum pipedmc_event_id event) 1737 { 1738 struct intel_display *display = to_intel_display(crtc); 1739 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1740 1741 dmc_configure_event(display, dmc_id, event, true); 1742 } 1743 1744 void intel_pipedmc_disable_event(struct intel_crtc *crtc, 1745 enum pipedmc_event_id event) 1746 { 1747 struct intel_display *display = to_intel_display(crtc); 1748 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1749 1750 dmc_configure_event(display, dmc_id, event, false); 1751 } 1752 1753 u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) 1754 { 1755 struct intel_display *display = to_intel_display(crtc); 1756 struct intel_dmc *dmc = display_to_dmc(display); 1757 enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(crtc->pipe); 1758 1759 return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; 1760 } 1761 1762 void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1763 { 1764 struct intel_display *display = to_intel_display(crtc); 1765 enum pipe pipe = crtc->pipe; 1766 1767 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 1768 PIPEDMC_ADAPTIVE_DCB_ENABLE); 1769 } 1770 1771 void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) 1772 { 1773 struct intel_display *display = to_intel_display(crtc); 1774 enum pipe pipe = crtc->pipe; 1775 1776 intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); 1777 } 1778