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Searched refs:inst_mask (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4_2.c160 uint32_t inst_mask) in sdma_v4_4_2_inst_init_golden_registers() argument
489 uint32_t inst_mask) in sdma_v4_4_2_inst_gfx_stop() argument
496 for_each_inst(i, inst_mask) { in sdma_v4_4_2_inst_gfx_stop()
532 uint32_t inst_mask) in sdma_v4_4_2_inst_rlc_stop() argument
546 uint32_t inst_mask) in sdma_v4_4_2_inst_page_stop() argument
551 for_each_inst(i, inst_mask) { in sdma_v4_4_2_inst_page_stop()
573 bool enable, uint32_t inst_mask) in sdma_v4_4_2_inst_ctx_switch_enable() argument
602 for_each_inst(i, inst_mask) { in sdma_v4_4_2_inst_ctx_switch_enable()
628 uint32_t inst_mask) in sdma_v4_4_2_inst_enable() argument
634 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); in sdma_v4_4_2_inst_enable()
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H A Dsdma_v7_1.c115 uint32_t inst_mask);
362 * @inst_mask: mask of dma engine instances to be disabled
367 uint32_t inst_mask) in sdma_v7_1_inst_gfx_stop() argument
372 for_each_inst(i, inst_mask) { in sdma_v7_1_inst_gfx_stop()
386 * @inst_mask: mask of dma engine instances to be disabled
391 uint32_t inst_mask) in sdma_v7_1_inst_rlc_stop() argument
401 * @inst_mask: mask of dma engine instances to be enabled
406 bool enable, uint32_t inst_mask) in sdma_v7_1_inst_ctx_switch_enable() argument
410 for_each_inst(i, inst_mask) { in sdma_v7_1_inst_ctx_switch_enable()
421 * @inst_mask
426 sdma_v7_1_inst_enable(struct amdgpu_device * adev,bool enable,uint32_t inst_mask) sdma_v7_1_inst_enable() argument
616 sdma_v7_1_inst_gfx_resume(struct amdgpu_device * adev,uint32_t inst_mask) sdma_v7_1_inst_gfx_resume() argument
640 sdma_v7_1_inst_rlc_resume(struct amdgpu_device * adev,uint32_t inst_mask) sdma_v7_1_inst_rlc_resume() argument
646 sdma_v7_1_inst_free_ucode_buffer(struct amdgpu_device * adev,uint32_t inst_mask) sdma_v7_1_inst_free_ucode_buffer() argument
667 sdma_v7_1_inst_load_microcode(struct amdgpu_device * adev,uint32_t inst_mask) sdma_v7_1_inst_load_microcode() argument
743 uint32_t inst_mask; sdma_v7_1_soft_reset() local
813 sdma_v7_1_inst_start(struct amdgpu_device * adev,uint32_t inst_mask) sdma_v7_1_inst_start() argument
1371 uint32_t inst_mask; sdma_v7_1_hw_init() local
1778 sdma_v7_1_xcp_resume(void * handle,uint32_t inst_mask) sdma_v7_1_xcp_resume() argument
1788 sdma_v7_1_xcp_suspend(void * handle,uint32_t inst_mask) sdma_v7_1_xcp_suspend() argument
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H A Dgfxhub_v1_2.c641 static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_resume() argument
651 gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, inst_mask); in gfxhub_v1_2_xcp_resume()
654 return gfxhub_v1_2_xcc_gart_enable(adev, inst_mask); in gfxhub_v1_2_xcp_resume()
659 static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_suspend() argument
664 gfxhub_v1_2_xcc_gart_disable(adev, inst_mask); in gfxhub_v1_2_xcp_suspend()
H A Dgfxhub_v12_1.c833 static int gfxhub_v12_1_xcp_resume(void *handle, uint32_t inst_mask) in gfxhub_v12_1_xcp_resume() argument
843 gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, inst_mask); in gfxhub_v12_1_xcp_resume()
846 return gfxhub_v12_1_xcc_gart_enable(adev, inst_mask); in gfxhub_v12_1_xcp_resume()
851 static int gfxhub_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) in gfxhub_v12_1_xcp_suspend() argument
856 gfxhub_v12_1_xcc_gart_disable(adev, inst_mask); in gfxhub_v12_1_xcp_suspend()
H A Dnbio_v7_9.c435 u32 inst_mask; in nbio_v7_9_init_registers() local
443 inst_mask = adev->aid_mask & ~1U; in nbio_v7_9_init_registers()
444 for_each_inst(i, inst_mask) { in nbio_v7_9_init_registers()
H A Damdgpu_discovery.c514 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_config_quirk()
844 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
846 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
850 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
852 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
912 adev->vcn.inst_mask &= ~BIT(inst); in amdgpu_discovery_read_from_harvest_table()
913 adev->jpeg.inst_mask &= ~BIT(inst); in amdgpu_discovery_read_from_harvest_table()
1203 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; in amdgpu_discovery_get_harvest_info()
1762 adev->vcn.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1763 adev->jpeg.inst_mask in amdgpu_discovery_reg_base_init()
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H A Dsdma_v5_0.c562 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask) in sdma_v5_0_gfx_stop() argument
567 for_each_inst(i, inst_mask) { in sdma_v5_0_gfx_stop()
659 uint32_t inst_mask; in sdma_v5_0_enable() local
661 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_0_enable()
663 sdma_v5_0_gfx_stop(adev, 1 << inst_mask); in sdma_v5_0_enable()
H A Dsdma_v5_2.c412 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask) in sdma_v5_2_gfx_stop() argument
417 for_each_inst(i, inst_mask) { in sdma_v5_2_gfx_stop()
508 uint32_t inst_mask; in sdma_v5_2_enable() local
510 inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); in sdma_v5_2_enable()
512 sdma_v5_2_gfx_stop(adev, inst_mask); in sdma_v5_2_enable()
H A Damdgpu.h1170 #define for_each_inst(i, inst_mask) \ argument
1171 for (i = ffs(inst_mask); i-- != 0; \
1172 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
H A Dgfx_v9_4_3.c4209 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_resume() argument
4218 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4223 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4231 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4241 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_suspend() argument
4246 for_each_inst(i, inst_mask) in gfx_v9_4_3_xcp_suspend()
H A Dgfx_v12_1.c4426 static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) in gfx_v12_1_xcp_resume() argument
4435 tmp_mask = inst_mask; in gfx_v12_1_xcp_resume()
4440 tmp_mask = inst_mask; in gfx_v12_1_xcp_resume()
4448 r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); in gfx_v12_1_xcp_resume()
4453 static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) in gfx_v12_1_xcp_suspend() argument
4458 for_each_inst(i, inst_mask) in gfx_v12_1_xcp_suspend()
/linux/drivers/perf/
H A Dnvidia_t410_c2c_pmu.c339 unsigned long *inst_mask; in nv_c2c_pmu_read_counter() local
351 inst_mask = c2c_pmu->peer_insts[filter_idx]; in nv_c2c_pmu_read_counter()
352 for_each_set_bit(inst_idx, inst_mask, c2c_pmu->data->nr_inst) { in nv_c2c_pmu_read_counter()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_8_ppt.c1620 u32 inst_mask; in smu_v15_0_8_get_xcp_metrics() local
1641 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); in smu_v15_0_8_get_xcp_metrics()
1643 for_each_inst(k, inst_mask) { in smu_v15_0_8_get_xcp_metrics()
1659 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); in smu_v15_0_8_get_xcp_metrics()
1661 for_each_inst(k, inst_mask) { in smu_v15_0_8_get_xcp_metrics()
/linux/drivers/gpu/drm/amd/pm/
H A Damdgpu_dpm.c778 int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask) in amdgpu_dpm_reset_sdma() argument
787 ret = smu_reset_sdma(smu, inst_mask); in amdgpu_dpm_reset_sdma()
793 int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask) in amdgpu_dpm_reset_vcn() argument
802 ret = smu_reset_vcn(smu, inst_mask); in amdgpu_dpm_reset_vcn()