1 /* Copyright 2012-17 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_DWBC_H__ 26 #define __DC_DWBC_H__ 27 28 #include "dal_types.h" 29 #include "dc_hw_types.h" 30 31 #define DWB_SW_V2 1 32 #define DWB_MCIF_BUF_COUNT 4 33 34 /* forward declaration of mcif_wb struct */ 35 struct mcif_wb; 36 37 38 enum dwb_sw_version { 39 dwb_ver_1_0 = 1, 40 dwb_ver_2_0 = 2, 41 }; 42 43 enum dwb_source { 44 dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */ 45 dwb_src_blnd, /* for DCE7x/9x */ 46 dwb_src_fmt, /* for DCE7x/9x */ 47 dwb_src_otg0 = 0x100, /* for DCN1.x/DCN2.x, register: mmDWB_SOURCE_SELECT */ 48 dwb_src_otg1, /* for DCN1.x/DCN2.x */ 49 dwb_src_otg2, /* for DCN1.x/DCN2.x */ 50 dwb_src_otg3, /* for DCN1.x/DCN2.x */ 51 }; 52 53 /* DCN1.x, DCN2.x support 2 pipes */ 54 enum dwb_pipe { 55 dwb_pipe0 = 0, 56 dwb_pipe1, 57 dwb_pipe_max_num, 58 }; 59 60 enum dwb_frame_capture_enable { 61 DWB_FRAME_CAPTURE_DISABLE = 0, 62 DWB_FRAME_CAPTURE_ENABLE = 1, 63 }; 64 65 enum wbscl_coef_filter_type_sel { 66 WBSCL_COEF_LUMA_VERT_FILTER = 0, 67 WBSCL_COEF_CHROMA_VERT_FILTER = 1, 68 WBSCL_COEF_LUMA_HORZ_FILTER = 2, 69 WBSCL_COEF_CHROMA_HORZ_FILTER = 3 70 }; 71 72 73 enum dwb_boundary_mode { 74 DWBSCL_BOUNDARY_MODE_EDGE = 0, 75 DWBSCL_BOUNDARY_MODE_BLACK = 1 76 }; 77 78 enum dwb_output_csc_mode { 79 DWB_OUTPUT_CSC_DISABLE = 0, 80 DWB_OUTPUT_CSC_COEF_A = 1, 81 DWB_OUTPUT_CSC_COEF_B = 2 82 }; 83 84 enum dwb_ogam_lut_mode { 85 DWB_OGAM_MODE_BYPASS, 86 DWB_OGAM_RAMA_LUT, 87 DWB_OGAM_RAMB_LUT 88 }; 89 90 enum dwb_color_volume { 91 DWB_SRGB_BT709 = 0, //SDR 92 DWB_PQ = 1, //HDR 93 DWB_HLG = 2, //HDR 94 }; 95 96 enum dwb_color_space { 97 DWB_SRGB = 0, //SDR 98 DWB_BT709 = 1, //SDR 99 DWB_BT2020 = 2, //HDR 100 }; 101 102 struct dwb_efc_hdr_metadata { 103 /*display chromaticities and white point in units of 0.00001 */ 104 unsigned int chromaticity_green_x; 105 unsigned int chromaticity_green_y; 106 unsigned int chromaticity_blue_x; 107 unsigned int chromaticity_blue_y; 108 unsigned int chromaticity_red_x; 109 unsigned int chromaticity_red_y; 110 unsigned int chromaticity_white_point_x; 111 unsigned int chromaticity_white_point_y; 112 113 /*in units of candelas per square meter */ 114 unsigned int min_luminance; 115 unsigned int max_luminance; 116 117 /*in units of nits */ 118 unsigned int maximum_content_light_level; 119 unsigned int maximum_frame_average_light_level; 120 }; 121 122 struct dwb_efc_display_settings { 123 unsigned int inputColorVolume; 124 unsigned int inputColorSpace; 125 unsigned int inputBitDepthMinus8; 126 struct dwb_efc_hdr_metadata hdr_metadata; 127 unsigned int dwbOutputBlack; // 0 - Normal, 1 - Output Black 128 }; 129 130 struct dwb_warmup_params { 131 bool warmup_en; /* false: normal mode, true: enable pattern generator */ 132 bool warmup_mode; /* false: 420, true: 444 */ 133 bool warmup_depth; /* false: 8bit, true: 10bit */ 134 int warmup_data; /* Data to be sent by pattern generator (same for each pixel component) */ 135 int warmup_width; /* Pattern width (pixels) */ 136 int warmup_height; /* Pattern height (lines) */ 137 }; 138 139 struct dwb_caps { 140 enum dce_version hw_version; /* DCN engine version. */ 141 enum dwb_sw_version sw_version; /* DWB sw implementation version. */ 142 unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */ 143 unsigned int adapter_id; 144 unsigned int num_pipes; /* number of DWB pipes */ 145 struct { 146 unsigned int support_dwb :1; 147 unsigned int support_ogam :1; 148 unsigned int support_wbscl :1; 149 unsigned int support_ocsc :1; 150 unsigned int support_stereo :1; 151 unsigned int support_4k_120p :1; 152 } caps; 153 unsigned int reserved2[10]; /* Reserved for future use, MUST BE 0. */ 154 }; 155 156 struct dwbc { 157 const struct dwbc_funcs *funcs; 158 struct dc_context *ctx; 159 int inst; 160 struct mcif_wb *mcif; 161 bool status; 162 int inputSrcSelect; 163 bool dwb_output_black; 164 enum dc_transfer_func_predefined tf; 165 enum dc_color_space output_color_space; 166 bool dwb_is_efc_transition; 167 bool dwb_is_drc; 168 int wb_src_plane_inst;/*hubp, mpcc, inst*/ 169 uint32_t mask_id; 170 int otg_inst; 171 bool mvc_cfg; 172 struct dc_dwb_params params; 173 }; 174 175 struct dwbc_funcs { 176 bool (*get_caps)( 177 struct dwbc *dwbc, 178 struct dwb_caps *caps); 179 180 bool (*enable)( 181 struct dwbc *dwbc, 182 struct dc_dwb_params *params); 183 184 bool (*disable)(struct dwbc *dwbc); 185 186 bool (*update)( 187 struct dwbc *dwbc, 188 struct dc_dwb_params *params); 189 190 bool (*is_enabled)( 191 struct dwbc *dwbc); 192 193 void (*set_fc_enable)( 194 struct dwbc *dwbc, 195 enum dwb_frame_capture_enable enable); 196 197 void (*dwb_set_scaler)( 198 struct dwbc *dwbc, 199 struct dc_dwb_params *params); 200 201 void (*set_stereo)( 202 struct dwbc *dwbc, 203 struct dwb_stereo_params *stereo_params); 204 205 void (*set_new_content)( 206 struct dwbc *dwbc, 207 bool is_new_content); 208 209 210 void (*set_warmup)( 211 struct dwbc *dwbc, 212 struct dwb_warmup_params *warmup_params); 213 214 bool (*dwb_get_mcifbuf_line)( 215 struct dwbc *dwbc, unsigned int *buf_idx, 216 unsigned int *cur_line, 217 unsigned int *over_run); 218 #if defined(CONFIG_DRM_AMD_DC_FP) 219 void (*dwb_program_output_csc)( 220 struct dwbc *dwbc, 221 enum dc_color_space color_space, 222 enum dwb_output_csc_mode mode); 223 224 bool (*dwb_ogam_set_output_transfer_func)( 225 struct dwbc *dwbc, 226 const struct dc_transfer_func *in_transfer_func_dwb_ogam); 227 #endif 228 //TODO: merge with output_transfer_func? 229 bool (*dwb_ogam_set_input_transfer_func)( 230 struct dwbc *dwbc, 231 const struct dc_transfer_func *in_transfer_func_dwb_ogam); 232 233 void (*get_drr_time_stamp)( 234 struct dwbc *dwbc, uint32_t *time_stamp); 235 236 bool (*get_dwb_status)( 237 struct dwbc *dwbc); 238 }; 239 240 #endif 241