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Searched refs:indirect (Results 1 – 25 of 111) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_2.c382 bool indirect) in vcn_v5_0_2_mc_resume_dpg_mode() argument
394 if (!indirect) { in vcn_v5_0_2_mc_resume_dpg_mode()
398 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
402 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
404 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
407 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
409 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
411 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
417 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
420 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
[all …]
H A Dvcn_v4_0_5.c461 bool indirect) in vcn_v4_0_5_mc_resume_dpg_mode() argument
473 if (!indirect) { in vcn_v4_0_5_mc_resume_dpg_mode()
477 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
481 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
483 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
490 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
496 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
499 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_0.c425 bool indirect) in vcn_v5_0_0_mc_resume_dpg_mode() argument
437 if (!indirect) { in vcn_v5_0_0_mc_resume_dpg_mode()
440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
452 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
458 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
461 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
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H A Dvcn_v4_0_3.c99 int inst_idx, bool indirect);
546 bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
558 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
562 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
566 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
568 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
571 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
573 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
575 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
581 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_0.c439 bool indirect) in vcn_v2_0_mc_resume_dpg_mode() argument
447 if (!indirect) { in vcn_v2_0_mc_resume_dpg_mode()
450 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
455 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
460 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
462 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
471 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_5.c645 bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
654 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
657 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
660 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
662 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
665 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
667 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
669 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
675 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
678 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
[all …]
H A Djpeg_v5_3_0.c287 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
300 if (indirect) { in jpeg_engine_5_0_0_dpg_clock_gating_mode()
301 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
305 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
307 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
311 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 static int jpeg_v5_3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_3_0_start_dpg_mode() argument
336 if (indirect) in jpeg_v5_3_0_start_dpg_mode()
340 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v5_3_0_start_dpg_mode()
343 if (indirect) in jpeg_v5_3_0_start_dpg_mode()
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H A Dvcn_v4_0.c510 bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
521 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
524 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
527 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
529 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
532 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
534 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
536 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
542 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
545 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
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H A Djpeg_v5_0_0.c304 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
317 if (indirect) { in jpeg_engine_5_0_0_dpg_clock_gating_mode()
318 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
322 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
328 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
341 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_0_0_start_dpg_mode() argument
353 if (indirect) in jpeg_v5_0_0_start_dpg_mode()
357 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v5_0_0_start_dpg_mode()
360 if (indirect) in jpeg_v5_0_0_start_dpg_mode()
[all …]
H A Dvcn_v3_0.c573 bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
582 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
585 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
588 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
590 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
593 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
595 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
597 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
606 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_1.c485 bool indirect) in vcn_v5_0_1_mc_resume_dpg_mode() argument
497 if (!indirect) { in vcn_v5_0_1_mc_resume_dpg_mode()
501 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
505 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
507 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
510 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
512 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
514 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
520 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
523 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
[all …]
H A Djpeg_v4_0_5.c356 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
367 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regJPEG_CGC_CTRL_INTERNAL_OFFSET, data, indirect); in jpeg_engine_4_0_5_dpg_clock_gating_mode()
371 data, indirect); in jpeg_engine_4_0_5_dpg_clock_gating_mode()
421 static void jpeg_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v4_0_5_start_dpg_mode() argument
444 if (indirect) in jpeg_v4_0_5_start_dpg_mode()
448 jpeg_engine_4_0_5_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v4_0_5_start_dpg_mode()
452 adev->gfx.config.gb_addr_config, indirect); in jpeg_v4_0_5_start_dpg_mode()
455 JPEG_SYS_INT_EN__DJRBC_MASK, indirect); in jpeg_v4_0_5_start_dpg_mode()
458 WREG32_SOC15_JPEG_DPG_MODE(inst_idx, regUVD_NO_OP_INTERNAL_OFFSET, 0, indirect); in jpeg_v4_0_5_start_dpg_mode()
460 if (indirect) in jpeg_v4_0_5_start_dpg_mode()
/linux/Documentation/arch/riscv/
H A Dzicfilp.rst7 Tracking indirect control transfers on RISC-V Linux
11 to enable indirect branch tracking for user mode applications on RISC-V.
28 restriction on such indirect control transfers:
42 This form of indirect control transfer is immutable and doesn't
72 dependencies have been compiled with indirect branch support. Thus
73 it's left to the dynamic loader to enable indirect branch tracking for
79 Per-task indirect branch tracking state can be monitored and
91 ``zicfilp``, then the kernel will enable indirect branch tracking for
94 indirect branch tracking.
98 setting the bit :c:macro:`PR_CFI_LOCK` in arg. Either indirect branch
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/linux/arch/x86/kernel/
H A Dksysfs.c95 struct setup_indirect *indirect; in get_setup_data_size() local
114 indirect = (struct setup_indirect *)data->data; in get_setup_data_size()
116 if (indirect->type != SETUP_INDIRECT) in get_setup_data_size()
117 *size = indirect->len; in get_setup_data_size()
138 struct setup_indirect *indirect; in type_show() local
162 indirect = (struct setup_indirect *)data->data; in type_show()
164 ret = sprintf(buf, "0x%x\n", indirect->type); in type_show()
179 struct setup_indirect *indirect; in setup_data_data_read() local
203 indirect = (struct setup_indirect *)data->data; in setup_data_data_read()
205 if (indirect->type != SETUP_INDIRECT) { in setup_data_data_read()
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H A Dkdebugfs.c91 struct setup_indirect *indirect; in create_setup_data_nodes() local
129 indirect = (struct setup_indirect *)data->data; in create_setup_data_nodes()
131 if (indirect->type != SETUP_INDIRECT) { in create_setup_data_nodes()
132 node->paddr = indirect->addr; in create_setup_data_nodes()
133 node->type = indirect->type; in create_setup_data_nodes()
134 node->len = indirect->len; in create_setup_data_nodes()
/linux/drivers/net/ethernet/intel/idpf/
H A Didpf_controlq.c80 desc->params.indirect.addr_high = in idpf_ctlq_init_rxq_bufs()
82 desc->params.indirect.addr_low = in idpf_ctlq_init_rxq_bufs()
84 desc->params.indirect.param0 = 0; in idpf_ctlq_init_rxq_bufs()
85 desc->params.indirect.sw_cookie = 0; in idpf_ctlq_init_rxq_bufs()
86 desc->params.indirect.v_flags = 0; in idpf_ctlq_init_rxq_bufs()
295 struct idpf_dma_mem *buff = msg->ctx.indirect.payload; in idpf_ctlq_send()
304 desc->params.indirect.addr_high = in idpf_ctlq_send()
306 desc->params.indirect.addr_low = in idpf_ctlq_send()
309 memcpy(&desc->params, msg->ctx.indirect.context, in idpf_ctlq_send()
497 desc->params.indirect.addr_high = in idpf_ctlq_post_rx_buffs()
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/linux/Documentation/filesystems/ext4/
H A Dblockmap.rst16 | 13 | Double-indirect block: (file blocks ``$block_size``/4 + 12 to (``$block_siz…
21 | | | 0 to (``$block_size`` / 4) | Map to (``$block_size`` / 4) indirect bl…
30 | 14 | Triple-indirect block: (file blocks (``$block_size`` / 4) ^ 2 + (``$block_s…
35 … | 0 to (``$block_size`` / 4) | Map to (``$block_size`` / 4) double indirect blocks (1024 if 4…
40 … | | 0 to (``$block_size`` / 4) | Map to (``$block_size`` / 4) indirect blocks (1024 if 4…
/linux/arch/arm64/kvm/hyp/
H A Dhyp-entry.S216 .macro hyp_ventry indirect, spectrev2
226 .if \indirect != 0
249 .macro generate_vectors indirect, spectrev2
252 hyp_ventry \indirect, \spectrev2
259 generate_vectors indirect = 0, spectrev2 = 1 // HYP_VECTOR_SPECTRE_DIRECT
260 generate_vectors indirect = 1, spectrev2 = 0 // HYP_VECTOR_INDIRECT
261 generate_vectors indirect = 1, spectrev2 = 1 // HYP_VECTOR_SPECTRE_INDIRECT
/linux/drivers/block/xen-blkback/
H A Dblkback.c927 pages[i]->gref = req->u.indirect.indirect_grefs[i]; in xen_blkbk_parse_indirect()
1104 dst->u.indirect.indirect_op = src->u.indirect.indirect_op; in blkif_get_x86_32_req()
1105 dst->u.indirect.nr_segments = in blkif_get_x86_32_req()
1106 READ_ONCE(src->u.indirect.nr_segments); in blkif_get_x86_32_req()
1107 dst->u.indirect.handle = src->u.indirect.handle; in blkif_get_x86_32_req()
1108 dst->u.indirect.id = src->u.indirect.id; in blkif_get_x86_32_req()
1109 dst->u.indirect.sector_number = src->u.indirect.sector_number; in blkif_get_x86_32_req()
1111 INDIRECT_PAGES(dst->u.indirect.nr_segments)); in blkif_get_x86_32_req()
1113 dst->u.indirect.indirect_grefs[i] = in blkif_get_x86_32_req()
1114 src->u.indirect.indirect_grefs[i]; in blkif_get_x86_32_req()
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/linux/Documentation/admin-guide/hw-vuln/
H A Dspectre.rst62 execution of indirect branches to leak privileged memory.
93 execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
95 indirect branches can be influenced by an attacker, causing gadget code
102 In Spectre variant 2 attacks, the attacker can steer speculative indirect
104 buffer of a CPU used for predicting indirect branch addresses. Such
105 poisoning could be done by indirect branching into existing code,
106 with the address offset of the indirect branch under the attacker's
109 this could cause privileged code's indirect branch to jump to a gadget
130 steer its indirect branch speculations to gadget code, and measure the
135 Branch History Buffer (BHB) to speculatively steer an indirect branch
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H A Dindirect-target-selection.rst8 of indirect branches and RETs located in the lower half of a cacheline.
20 - **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
57 As only the indirect branches and RETs that have their last byte of instruction
59 the mitigation is to not allow indirect branches in the lower half.
63 added ITS-safe thunks. These safe thunks consists of indirect branch in the
66 indirect branch.
75 Note, for simplicity, indirect branches in eBPF programs are always replaced
82 thunks. But, RETs significantly outnumber indirect branches, and any benefit
88 Retpoline sequence also mitigates ITS-unsafe indirect branches. For this
119 indirect branches.
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/linux/tools/testing/selftests/bpf/progs/
H A Dmap_ptr_kern.c50 static inline int check_bpf_map_ptr(struct bpf_map *indirect, in check_bpf_map_ptr() argument
53 VERIFY(indirect->map_type == direct->map_type); in check_bpf_map_ptr()
54 VERIFY(indirect->key_size == direct->key_size); in check_bpf_map_ptr()
55 VERIFY(indirect->value_size == direct->value_size); in check_bpf_map_ptr()
56 VERIFY(indirect->max_entries == direct->max_entries); in check_bpf_map_ptr()
57 VERIFY(indirect->id == direct->id); in check_bpf_map_ptr()
62 static inline int check(struct bpf_map *indirect, struct bpf_map *direct, in check() argument
65 VERIFY(check_bpf_map_ptr(indirect, direct)); in check()
66 VERIFY(check_bpf_map_fields(indirect, key_size, value_size, in check()
71 static inline int check_default(struct bpf_map *indirect, in check_default() argument
80 check_default_noinline(struct bpf_map * indirect,struct bpf_map * direct) check_default_noinline() argument
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/linux/drivers/net/can/sja1000/
H A Dsja1000_isa.c37 static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1}; variable
46 module_param_hw_array(indirect, int, ioport, NULL, 0444);
47 MODULE_PARM_DESC(indirect, "Indirect access via address and data port");
139 if (indirect[idx] > 0 || in sja1000_isa_probe()
140 (indirect[idx] == -1 && indirect[0] > 0)) in sja1000_isa_probe()
/linux/arch/m68k/math-emu/
H A Dfp_decode.h196 | test if %pc is the base register for the indirect addr mode
220 | addressing mode: address register indirect
244 | addressing mode: address register indirect with postincrement
263 | addressing mode: address register indirect with predecrement
289 | addressing mode: address register/programm counter indirect
331 | all other indirect addressing modes will finally end up here
345 | addressing mode: address register/programm counter indirect
355 3: | addressing mode: address register/programm counter memory indirect
/linux/drivers/net/can/cc770/
H A Dcc770_isa.c75 static int indirect[MAXDEV] = {[0 ... (MAXDEV - 1)] = -1}; variable
83 module_param_hw_array(indirect, int, ioport, NULL, 0444);
84 MODULE_PARM_DESC(indirect, "Indirect access via address and data port");
184 if (indirect[idx] > 0 || in cc770_isa_probe()
185 (indirect[idx] == -1 && indirect[0] > 0)) in cc770_isa_probe()

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