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Searched refs:imu_reg_val (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c120 u32 imu_reg_val = 0; in imu_v12_0_wait_for_reset_status() local
124 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v12_0_wait_for_reset_status()
125 if ((imu_reg_val & 0x1f) == 0x1f) in imu_v12_0_wait_for_reset_status()
140 u32 imu_reg_val; in imu_v12_0_setup() local
146 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v12_0_setup()
147 imu_reg_val |= 0x1; in imu_v12_0_setup()
148 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v12_0_setup()
150 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v12_0_setup()
151 imu_reg_val |= 0x20010007; in imu_v12_0_setup()
152 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); in imu_v12_0_setup()
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H A Dimu_v11_0.c125 int i, imu_reg_val = 0; in imu_v11_0_wait_for_reset_status() local
128 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); in imu_v11_0_wait_for_reset_status()
129 if ((imu_reg_val & 0x1f) == 0x1f) in imu_v11_0_wait_for_reset_status()
144 int imu_reg_val; in imu_v11_0_setup() local
151 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16); in imu_v11_0_setup()
152 imu_reg_val |= 0x1; in imu_v11_0_setup()
153 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); in imu_v11_0_setup()
157 imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); in imu_v11_0_setup()
158 imu_reg_val |= 0x10007; in imu_v11_0_setup()
159 WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); in imu_v11_0_setup()
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