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Searched refs:idiv (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c26 unsigned int idiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
104 idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
144 i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv); in i2s_pll_set_rate()
H A Dpll_clock.c68 u32 idiv; member
139 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
142 idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV)); in axs10x_pll_recalc_rate()
147 do_div(rate, idiv * odiv); in axs10x_pll_recalc_rate()
185 axs10x_encode_div(pll_cfg[i].idiv, 0)); in axs10x_pll_set_rate()
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c46 u64 idiv; member
102 static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv, in sja1105_cgu_idiv_packing() argument
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
118 struct sja1105_cgu_idiv idiv; in sja1105_cgu_idiv_config() local
130 idiv.clksrc = 0x0A; /* 25MHz */ in sja1105_cgu_idiv_config()
131 idiv.autoblock = 1; /* Block clk automatically */ in sja1105_cgu_idiv_config()
132 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ in sja1105_cgu_idiv_config()
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/linux/drivers/clk/
H A Dclk-hsdk-pll.c48 u32 idiv; member
141 val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; in hsdk_pll_set_cfg()
172 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
188 idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT); in hsdk_pll_recalc_rate()
195 do_div(rate, idiv * odiv); in hsdk_pll_recalc_rate()
H A Dclk-versaclock5.c368 unsigned long idiv; in vc5_pfd_determine_rate() local
381 idiv = DIV_ROUND_UP(req->best_parent_rate, req->rate); in vc5_pfd_determine_rate()
382 if (idiv > 127) in vc5_pfd_determine_rate()
385 req->rate = req->best_parent_rate / idiv; in vc5_pfd_determine_rate()
395 unsigned long idiv; in vc5_pfd_set_rate() local
409 idiv = DIV_ROUND_UP(parent_rate, rate); in vc5_pfd_set_rate()
412 if (idiv == 2) in vc5_pfd_set_rate()
415 div = VC5_REF_DIVIDER_REF_DIV(idiv); in vc5_pfd_set_rate()
H A Dclk-si5351.c271 unsigned char idiv; in si5351_clkin_recalc_rate() local
275 idiv = SI5351_CLKIN_DIV_8; in si5351_clkin_recalc_rate()
278 idiv = SI5351_CLKIN_DIV_4; in si5351_clkin_recalc_rate()
281 idiv = SI5351_CLKIN_DIV_2; in si5351_clkin_recalc_rate()
284 idiv = SI5351_CLKIN_DIV_1; in si5351_clkin_recalc_rate()
288 SI5351_CLKIN_DIV_MASK, idiv); in si5351_clkin_recalc_rate()
291 __func__, (1 << (idiv >> 6)), rate); in si5351_clkin_recalc_rate()
/linux/drivers/clk/microchip/
H A Dclk-pic32.c580 u32 idiv; /* PLL iclk divider, treated fixed */ member
603 parent_rate /= pll->idiv; in spll_calc_mult_div()
655 pll_in_rate = parent_rate / pll->idiv; in spll_clk_recalc_rate()
747 spll->idiv = (readl(spll->ctrl_reg) >> PLL_IDIV_SHIFT) & PLL_IDIV_MASK; in pic32_spll_clk_register()
748 spll->idiv += 1; in pic32_spll_clk_register()