xref: /linux/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h (revision 06d07429858317ded2db7986113a9e0129cd599b)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3 
4 #ifndef _I40E_ADMINQ_CMD_H_
5 #define _I40E_ADMINQ_CMD_H_
6 
7 #include <linux/bits.h>
8 #include <linux/types.h>
9 
10 /* This header file defines the i40e Admin Queue commands and is shared between
11  * i40e Firmware and Software.
12  *
13  * This file needs to comply with the Linux Kernel coding style.
14  */
15 
16 #define I40E_FW_API_VERSION_MAJOR	0x0001
17 #define I40E_FW_API_VERSION_MINOR_X722	0x000C
18 #define I40E_FW_API_VERSION_MINOR_X710	0x000F
19 
20 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
21 					I40E_FW_API_VERSION_MINOR_X710 : \
22 					I40E_FW_API_VERSION_MINOR_X722)
23 
24 /* API version 1.7 implements additional link and PHY-specific APIs  */
25 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
26 /* API version 1.9 for X722 implements additional link and PHY-specific APIs */
27 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
28 /* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
29 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
30 /* API version 1.10 for X722 devices adds ability to request FEC encoding */
31 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
32 
33 struct i40e_aq_desc {
34 	__le16 flags;
35 	__le16 opcode;
36 	__le16 datalen;
37 	__le16 retval;
38 	__le32 cookie_high;
39 	__le32 cookie_low;
40 	union {
41 		struct {
42 			__le32 param0;
43 			__le32 param1;
44 			__le32 param2;
45 			__le32 param3;
46 		} internal;
47 		struct {
48 			__le32 param0;
49 			__le32 param1;
50 			__le32 addr_high;
51 			__le32 addr_low;
52 		} external;
53 		u8 raw[16];
54 	} params;
55 };
56 
57 /* Flags sub-structure
58  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
59  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
60  */
61 
62 /* command flags and offsets*/
63 #define I40E_AQ_FLAG_ERR_SHIFT	2
64 #define I40E_AQ_FLAG_LB_SHIFT	9
65 #define I40E_AQ_FLAG_RD_SHIFT	10
66 #define I40E_AQ_FLAG_BUF_SHIFT	12
67 #define I40E_AQ_FLAG_SI_SHIFT	13
68 
69 #define I40E_AQ_FLAG_ERR	BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
70 #define I40E_AQ_FLAG_LB		BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
71 #define I40E_AQ_FLAG_RD		BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
72 #define I40E_AQ_FLAG_BUF	BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
73 #define I40E_AQ_FLAG_SI		BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
74 
75 /* error codes */
76 enum i40e_admin_queue_err {
77 	I40E_AQ_RC_OK		= 0,  /* success */
78 	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */
79 	I40E_AQ_RC_ENOENT	= 2,  /* No such element */
80 	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */
81 	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */
82 	I40E_AQ_RC_EIO		= 5,  /* I/O error */
83 	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */
84 	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */
85 	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */
86 	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */
87 	I40E_AQ_RC_EACCES	= 10, /* Permission denied */
88 	I40E_AQ_RC_EFAULT	= 11, /* Bad address */
89 	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */
90 	I40E_AQ_RC_EEXIST	= 13, /* object already exists */
91 	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */
92 	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
93 	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */
94 	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */
95 	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */
96 	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
97 	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
98 	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */
99 	I40E_AQ_RC_EFBIG	= 22, /* File too large */
100 };
101 
102 /* Admin Queue command opcodes */
103 enum i40e_admin_queue_opc {
104 	/* aq commands */
105 	i40e_aqc_opc_get_version	= 0x0001,
106 	i40e_aqc_opc_driver_version	= 0x0002,
107 	i40e_aqc_opc_queue_shutdown	= 0x0003,
108 	i40e_aqc_opc_set_pf_context	= 0x0004,
109 
110 	/* resource ownership */
111 	i40e_aqc_opc_request_resource	= 0x0008,
112 	i40e_aqc_opc_release_resource	= 0x0009,
113 
114 	i40e_aqc_opc_list_func_capabilities	= 0x000A,
115 	i40e_aqc_opc_list_dev_capabilities	= 0x000B,
116 
117 	/* Proxy commands */
118 	i40e_aqc_opc_set_proxy_config		= 0x0104,
119 	i40e_aqc_opc_set_ns_proxy_table_entry	= 0x0105,
120 
121 	/* LAA */
122 	i40e_aqc_opc_mac_address_read	= 0x0107,
123 	i40e_aqc_opc_mac_address_write	= 0x0108,
124 
125 	/* PXE */
126 	i40e_aqc_opc_clear_pxe_mode	= 0x0110,
127 
128 	/* WoL commands */
129 	i40e_aqc_opc_set_wol_filter	= 0x0120,
130 	i40e_aqc_opc_get_wake_reason	= 0x0121,
131 
132 	/* internal switch commands */
133 	i40e_aqc_opc_get_switch_config		= 0x0200,
134 	i40e_aqc_opc_add_statistics		= 0x0201,
135 	i40e_aqc_opc_remove_statistics		= 0x0202,
136 	i40e_aqc_opc_set_port_parameters	= 0x0203,
137 	i40e_aqc_opc_get_switch_resource_alloc	= 0x0204,
138 	i40e_aqc_opc_set_switch_config		= 0x0205,
139 	i40e_aqc_opc_rx_ctl_reg_read		= 0x0206,
140 	i40e_aqc_opc_rx_ctl_reg_write		= 0x0207,
141 
142 	i40e_aqc_opc_add_vsi			= 0x0210,
143 	i40e_aqc_opc_update_vsi_parameters	= 0x0211,
144 	i40e_aqc_opc_get_vsi_parameters		= 0x0212,
145 
146 	i40e_aqc_opc_add_pv			= 0x0220,
147 	i40e_aqc_opc_update_pv_parameters	= 0x0221,
148 	i40e_aqc_opc_get_pv_parameters		= 0x0222,
149 
150 	i40e_aqc_opc_add_veb			= 0x0230,
151 	i40e_aqc_opc_update_veb_parameters	= 0x0231,
152 	i40e_aqc_opc_get_veb_parameters		= 0x0232,
153 
154 	i40e_aqc_opc_delete_element		= 0x0243,
155 
156 	i40e_aqc_opc_add_macvlan		= 0x0250,
157 	i40e_aqc_opc_remove_macvlan		= 0x0251,
158 	i40e_aqc_opc_add_vlan			= 0x0252,
159 	i40e_aqc_opc_remove_vlan		= 0x0253,
160 	i40e_aqc_opc_set_vsi_promiscuous_modes	= 0x0254,
161 	i40e_aqc_opc_add_tag			= 0x0255,
162 	i40e_aqc_opc_remove_tag			= 0x0256,
163 	i40e_aqc_opc_add_multicast_etag		= 0x0257,
164 	i40e_aqc_opc_remove_multicast_etag	= 0x0258,
165 	i40e_aqc_opc_update_tag			= 0x0259,
166 	i40e_aqc_opc_add_control_packet_filter	= 0x025A,
167 	i40e_aqc_opc_remove_control_packet_filter	= 0x025B,
168 	i40e_aqc_opc_add_cloud_filters		= 0x025C,
169 	i40e_aqc_opc_remove_cloud_filters	= 0x025D,
170 	i40e_aqc_opc_clear_wol_switch_filters	= 0x025E,
171 
172 	i40e_aqc_opc_add_mirror_rule	= 0x0260,
173 	i40e_aqc_opc_delete_mirror_rule	= 0x0261,
174 
175 	/* Dynamic Device Personalization */
176 	i40e_aqc_opc_write_personalization_profile	= 0x0270,
177 	i40e_aqc_opc_get_personalization_profile_list	= 0x0271,
178 
179 	/* DCB commands */
180 	i40e_aqc_opc_dcb_ignore_pfc	= 0x0301,
181 	i40e_aqc_opc_dcb_updated	= 0x0302,
182 	i40e_aqc_opc_set_dcb_parameters = 0x0303,
183 
184 	/* TX scheduler */
185 	i40e_aqc_opc_configure_vsi_bw_limit		= 0x0400,
186 	i40e_aqc_opc_configure_vsi_ets_sla_bw_limit	= 0x0406,
187 	i40e_aqc_opc_configure_vsi_tc_bw		= 0x0407,
188 	i40e_aqc_opc_query_vsi_bw_config		= 0x0408,
189 	i40e_aqc_opc_query_vsi_ets_sla_config		= 0x040A,
190 	i40e_aqc_opc_configure_switching_comp_bw_limit	= 0x0410,
191 
192 	i40e_aqc_opc_enable_switching_comp_ets			= 0x0413,
193 	i40e_aqc_opc_modify_switching_comp_ets			= 0x0414,
194 	i40e_aqc_opc_disable_switching_comp_ets			= 0x0415,
195 	i40e_aqc_opc_configure_switching_comp_ets_bw_limit	= 0x0416,
196 	i40e_aqc_opc_configure_switching_comp_bw_config		= 0x0417,
197 	i40e_aqc_opc_query_switching_comp_ets_config		= 0x0418,
198 	i40e_aqc_opc_query_port_ets_config			= 0x0419,
199 	i40e_aqc_opc_query_switching_comp_bw_config		= 0x041A,
200 	i40e_aqc_opc_suspend_port_tx				= 0x041B,
201 	i40e_aqc_opc_resume_port_tx				= 0x041C,
202 	i40e_aqc_opc_configure_partition_bw			= 0x041D,
203 	/* hmc */
204 	i40e_aqc_opc_query_hmc_resource_profile	= 0x0500,
205 	i40e_aqc_opc_set_hmc_resource_profile	= 0x0501,
206 
207 	/* phy commands*/
208 	i40e_aqc_opc_get_phy_abilities		= 0x0600,
209 	i40e_aqc_opc_set_phy_config		= 0x0601,
210 	i40e_aqc_opc_set_mac_config		= 0x0603,
211 	i40e_aqc_opc_set_link_restart_an	= 0x0605,
212 	i40e_aqc_opc_get_link_status		= 0x0607,
213 	i40e_aqc_opc_set_phy_int_mask		= 0x0613,
214 	i40e_aqc_opc_get_local_advt_reg		= 0x0614,
215 	i40e_aqc_opc_set_local_advt_reg		= 0x0615,
216 	i40e_aqc_opc_get_partner_advt		= 0x0616,
217 	i40e_aqc_opc_set_lb_modes		= 0x0618,
218 	i40e_aqc_opc_get_phy_wol_caps		= 0x0621,
219 	i40e_aqc_opc_set_phy_debug		= 0x0622,
220 	i40e_aqc_opc_upload_ext_phy_fm		= 0x0625,
221 	i40e_aqc_opc_run_phy_activity		= 0x0626,
222 	i40e_aqc_opc_set_phy_register		= 0x0628,
223 	i40e_aqc_opc_get_phy_register		= 0x0629,
224 
225 	/* NVM commands */
226 	i40e_aqc_opc_nvm_read			= 0x0701,
227 	i40e_aqc_opc_nvm_erase			= 0x0702,
228 	i40e_aqc_opc_nvm_update			= 0x0703,
229 	i40e_aqc_opc_nvm_config_read		= 0x0704,
230 	i40e_aqc_opc_nvm_config_write		= 0x0705,
231 	i40e_aqc_opc_oem_post_update		= 0x0720,
232 	i40e_aqc_opc_thermal_sensor		= 0x0721,
233 
234 	/* virtualization commands */
235 	i40e_aqc_opc_send_msg_to_pf		= 0x0801,
236 	i40e_aqc_opc_send_msg_to_vf		= 0x0802,
237 	i40e_aqc_opc_send_msg_to_peer		= 0x0803,
238 
239 	/* alternate structure */
240 	i40e_aqc_opc_alternate_write		= 0x0900,
241 	i40e_aqc_opc_alternate_write_indirect	= 0x0901,
242 	i40e_aqc_opc_alternate_read		= 0x0902,
243 	i40e_aqc_opc_alternate_read_indirect	= 0x0903,
244 	i40e_aqc_opc_alternate_write_done	= 0x0904,
245 	i40e_aqc_opc_alternate_set_mode		= 0x0905,
246 	i40e_aqc_opc_alternate_clear_port	= 0x0906,
247 
248 	/* LLDP commands */
249 	i40e_aqc_opc_lldp_get_mib	= 0x0A00,
250 	i40e_aqc_opc_lldp_update_mib	= 0x0A01,
251 	i40e_aqc_opc_lldp_add_tlv	= 0x0A02,
252 	i40e_aqc_opc_lldp_update_tlv	= 0x0A03,
253 	i40e_aqc_opc_lldp_delete_tlv	= 0x0A04,
254 	i40e_aqc_opc_lldp_stop		= 0x0A05,
255 	i40e_aqc_opc_lldp_start		= 0x0A06,
256 	i40e_aqc_opc_get_cee_dcb_cfg	= 0x0A07,
257 	i40e_aqc_opc_lldp_set_local_mib	= 0x0A08,
258 	i40e_aqc_opc_lldp_stop_start_spec_agent	= 0x0A09,
259 	i40e_aqc_opc_lldp_restore		= 0x0A0A,
260 
261 	/* Tunnel commands */
262 	i40e_aqc_opc_add_udp_tunnel	= 0x0B00,
263 	i40e_aqc_opc_del_udp_tunnel	= 0x0B01,
264 	i40e_aqc_opc_set_rss_key	= 0x0B02,
265 	i40e_aqc_opc_set_rss_lut	= 0x0B03,
266 	i40e_aqc_opc_get_rss_key	= 0x0B04,
267 	i40e_aqc_opc_get_rss_lut	= 0x0B05,
268 
269 	/* Async Events */
270 	i40e_aqc_opc_event_lan_overflow		= 0x1001,
271 
272 	/* OEM commands */
273 	i40e_aqc_opc_oem_parameter_change	= 0xFE00,
274 	i40e_aqc_opc_oem_device_status_change	= 0xFE01,
275 	i40e_aqc_opc_oem_ocsd_initialize	= 0xFE02,
276 	i40e_aqc_opc_oem_ocbb_initialize	= 0xFE03,
277 
278 	/* debug commands */
279 	i40e_aqc_opc_debug_read_reg		= 0xFF03,
280 	i40e_aqc_opc_debug_write_reg		= 0xFF04,
281 	i40e_aqc_opc_debug_modify_reg		= 0xFF07,
282 	i40e_aqc_opc_debug_dump_internals	= 0xFF08,
283 };
284 
285 /* command structures and indirect data structures */
286 
287 /* Structure naming conventions:
288  * - no suffix for direct command descriptor structures
289  * - _data for indirect sent data
290  * - _resp for indirect return data (data which is both will use _data)
291  * - _completion for direct return data
292  * - _element_ for repeated elements (may also be _data or _resp)
293  *
294  * Command structures are expected to overlay the params.raw member of the basic
295  * descriptor, and as such cannot exceed 16 bytes in length.
296  */
297 
298 /* This macro is used to generate a compilation error if a structure
299  * is not exactly the correct length. It gives a divide by zero error if the
300  * structure is not of the correct size, otherwise it creates an enum that is
301  * never used.
302  */
303 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
304 	{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
305 
306 /* This macro is used extensively to ensure that command structures are 16
307  * bytes in length as they have to map to the raw array of that size.
308  */
309 #define I40E_CHECK_CMD_LENGTH(X)	I40E_CHECK_STRUCT_LEN(16, X)
310 
311 /* internal (0x00XX) commands */
312 
313 /* Get version (direct 0x0001) */
314 struct i40e_aqc_get_version {
315 	__le32 rom_ver;
316 	__le32 fw_build;
317 	__le16 fw_major;
318 	__le16 fw_minor;
319 	__le16 api_major;
320 	__le16 api_minor;
321 };
322 
323 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
324 
325 /* Send driver version (indirect 0x0002) */
326 struct i40e_aqc_driver_version {
327 	u8	driver_major_ver;
328 	u8	driver_minor_ver;
329 	u8	driver_build_ver;
330 	u8	driver_subbuild_ver;
331 	u8	reserved[4];
332 	__le32	address_high;
333 	__le32	address_low;
334 };
335 
336 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
337 
338 /* Queue Shutdown (direct 0x0003) */
339 struct i40e_aqc_queue_shutdown {
340 	__le32	driver_unloading;
341 #define I40E_AQ_DRIVER_UNLOADING	0x1
342 	u8	reserved[12];
343 };
344 
345 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
346 
347 /* Set PF context (0x0004, direct) */
348 struct i40e_aqc_set_pf_context {
349 	u8	pf_id;
350 	u8	reserved[15];
351 };
352 
353 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
354 
355 /* Request resource ownership (direct 0x0008)
356  * Release resource ownership (direct 0x0009)
357  */
358 struct i40e_aqc_request_resource {
359 	__le16	resource_id;
360 	__le16	access_type;
361 	__le32	timeout;
362 	__le32	resource_number;
363 	u8	reserved[4];
364 };
365 
366 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
367 
368 /* Get function capabilities (indirect 0x000A)
369  * Get device capabilities (indirect 0x000B)
370  */
371 struct i40e_aqc_list_capabilites {
372 	u8 command_flags;
373 	u8 pf_index;
374 	u8 reserved[2];
375 	__le32 count;
376 	__le32 addr_high;
377 	__le32 addr_low;
378 };
379 
380 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
381 
382 struct i40e_aqc_list_capabilities_element_resp {
383 	__le16	id;
384 	u8	major_rev;
385 	u8	minor_rev;
386 	__le32	number;
387 	__le32	logical_id;
388 	__le32	phys_id;
389 	u8	reserved[16];
390 };
391 
392 /* list of caps */
393 
394 #define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001
395 #define I40E_AQ_CAP_ID_MNG_MODE		0x0002
396 #define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003
397 #define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004
398 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005
399 #define I40E_AQ_CAP_ID_SRIOV		0x0012
400 #define I40E_AQ_CAP_ID_VF		0x0013
401 #define I40E_AQ_CAP_ID_VMDQ		0x0014
402 #define I40E_AQ_CAP_ID_8021QBG		0x0015
403 #define I40E_AQ_CAP_ID_8021QBR		0x0016
404 #define I40E_AQ_CAP_ID_VSI		0x0017
405 #define I40E_AQ_CAP_ID_DCB		0x0018
406 #define I40E_AQ_CAP_ID_FCOE		0x0021
407 #define I40E_AQ_CAP_ID_ISCSI		0x0022
408 #define I40E_AQ_CAP_ID_RSS		0x0040
409 #define I40E_AQ_CAP_ID_RXQ		0x0041
410 #define I40E_AQ_CAP_ID_TXQ		0x0042
411 #define I40E_AQ_CAP_ID_MSIX		0x0043
412 #define I40E_AQ_CAP_ID_VF_MSIX		0x0044
413 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045
414 #define I40E_AQ_CAP_ID_1588		0x0046
415 #define I40E_AQ_CAP_ID_IWARP		0x0051
416 #define I40E_AQ_CAP_ID_LED		0x0061
417 #define I40E_AQ_CAP_ID_SDP		0x0062
418 #define I40E_AQ_CAP_ID_MDIO		0x0063
419 #define I40E_AQ_CAP_ID_WSR_PROT		0x0064
420 #define I40E_AQ_CAP_ID_NVM_MGMT		0x0080
421 #define I40E_AQ_CAP_ID_FLEX10		0x00F1
422 #define I40E_AQ_CAP_ID_CEM		0x00F2
423 
424 /* Set CPPM Configuration (direct 0x0103) */
425 struct i40e_aqc_cppm_configuration {
426 	__le16	command_flags;
427 	__le16	ttlx;
428 	__le32	dmacr;
429 	__le16	dmcth;
430 	u8	hptc;
431 	u8	reserved;
432 	__le32	pfltrc;
433 };
434 
435 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
436 
437 /* Set ARP Proxy command / response (indirect 0x0104) */
438 struct i40e_aqc_arp_proxy_data {
439 	__le16	command_flags;
440 	__le16	table_id;
441 	__le32	enabled_offloads;
442 	__le32	ip_addr;
443 	u8	mac_addr[6];
444 	u8	reserved[2];
445 };
446 
447 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
448 
449 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
450 struct i40e_aqc_ns_proxy_data {
451 	__le16	table_idx_mac_addr_0;
452 	__le16	table_idx_mac_addr_1;
453 	__le16	table_idx_ipv6_0;
454 	__le16	table_idx_ipv6_1;
455 	__le16	control;
456 	u8	mac_addr_0[6];
457 	u8	mac_addr_1[6];
458 	u8	local_mac_addr[6];
459 	u8	ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
460 	u8	ipv6_addr_1[16];
461 };
462 
463 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
464 
465 /* Manage LAA Command (0x0106) - obsolete */
466 struct i40e_aqc_mng_laa {
467 	__le16	command_flags;
468 	u8	reserved[2];
469 	__le32	sal;
470 	__le16	sah;
471 	u8	reserved2[6];
472 };
473 
474 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
475 
476 /* Manage MAC Address Read Command (indirect 0x0107) */
477 struct i40e_aqc_mac_address_read {
478 	__le16	command_flags;
479 #define I40E_AQC_LAN_ADDR_VALID		0x10
480 #define I40E_AQC_PORT_ADDR_VALID	0x40
481 	u8	reserved[6];
482 	__le32	addr_high;
483 	__le32	addr_low;
484 };
485 
486 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
487 
488 struct i40e_aqc_mac_address_read_data {
489 	u8 pf_lan_mac[6];
490 	u8 pf_san_mac[6];
491 	u8 port_mac[6];
492 	u8 pf_wol_mac[6];
493 };
494 
495 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
496 
497 /* Manage MAC Address Write Command (0x0108) */
498 struct i40e_aqc_mac_address_write {
499 	__le16	command_flags;
500 #define I40E_AQC_MC_MAG_EN		0x0100
501 #define I40E_AQC_WOL_PRESERVE_ON_PFR	0x0200
502 #define I40E_AQC_WRITE_TYPE_LAA_ONLY	0x0000
503 #define I40E_AQC_WRITE_TYPE_LAA_WOL	0x4000
504 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG	0xC000
505 
506 	__le16	mac_sah;
507 	__le32	mac_sal;
508 	u8	reserved[8];
509 };
510 
511 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
512 
513 /* PXE commands (0x011x) */
514 
515 /* Clear PXE Command and response  (direct 0x0110) */
516 struct i40e_aqc_clear_pxe {
517 	u8	rx_cnt;
518 	u8	reserved[15];
519 };
520 
521 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
522 
523 /* Set WoL Filter (0x0120) */
524 
525 struct i40e_aqc_set_wol_filter {
526 	__le16 filter_index;
527 
528 	__le16 cmd_flags;
529 	__le16 valid_flags;
530 	u8 reserved[2];
531 	__le32	address_high;
532 	__le32	address_low;
533 };
534 
535 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
536 
537 struct i40e_aqc_set_wol_filter_data {
538 	u8 filter[128];
539 	u8 mask[16];
540 };
541 
542 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
543 
544 /* Get Wake Reason (0x0121) */
545 
546 struct i40e_aqc_get_wake_reason_completion {
547 	u8 reserved_1[2];
548 	__le16 wake_reason;
549 	u8 reserved_2[12];
550 };
551 
552 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
553 
554 /* Switch configuration commands (0x02xx) */
555 
556 /* Used by many indirect commands that only pass an seid and a buffer in the
557  * command
558  */
559 struct i40e_aqc_switch_seid {
560 	__le16	seid;
561 	u8	reserved[6];
562 	__le32	addr_high;
563 	__le32	addr_low;
564 };
565 
566 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
567 
568 /* Get Switch Configuration command (indirect 0x0200)
569  * uses i40e_aqc_switch_seid for the descriptor
570  */
571 struct i40e_aqc_get_switch_config_header_resp {
572 	__le16	num_reported;
573 	__le16	num_total;
574 	u8	reserved[12];
575 };
576 
577 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
578 
579 struct i40e_aqc_switch_config_element_resp {
580 	u8	element_type;
581 	u8	revision;
582 	__le16	seid;
583 	__le16	uplink_seid;
584 	__le16	downlink_seid;
585 	u8	reserved[3];
586 	u8	connection_type;
587 	__le16	scheduler_id;
588 	__le16	element_info;
589 };
590 
591 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
592 
593 /* Get Switch Configuration (indirect 0x0200)
594  *    an array of elements are returned in the response buffer
595  *    the first in the array is the header, remainder are elements
596  */
597 struct i40e_aqc_get_switch_config_resp {
598 	struct i40e_aqc_get_switch_config_header_resp	header;
599 	struct i40e_aqc_switch_config_element_resp	element[1];
600 };
601 
602 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
603 
604 /* Add Statistics (direct 0x0201)
605  * Remove Statistics (direct 0x0202)
606  */
607 struct i40e_aqc_add_remove_statistics {
608 	__le16	seid;
609 	__le16	vlan;
610 	__le16	stat_index;
611 	u8	reserved[10];
612 };
613 
614 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
615 
616 /* Set Port Parameters command (direct 0x0203) */
617 struct i40e_aqc_set_port_parameters {
618 	__le16	command_flags;
619 	__le16	bad_frame_vsi;
620 	__le16	default_seid;        /* reserved for command */
621 	u8	reserved[10];
622 };
623 
624 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
625 
626 /* Get Switch Resource Allocation (indirect 0x0204) */
627 struct i40e_aqc_get_switch_resource_alloc {
628 	u8	num_entries;         /* reserved for command */
629 	u8	reserved[7];
630 	__le32	addr_high;
631 	__le32	addr_low;
632 };
633 
634 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
635 
636 /* expect an array of these structs in the response buffer */
637 struct i40e_aqc_switch_resource_alloc_element_resp {
638 	u8	resource_type;
639 	u8	reserved1;
640 	__le16	guaranteed;
641 	__le16	total;
642 	__le16	used;
643 	__le16	total_unalloced;
644 	u8	reserved2[6];
645 };
646 
647 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
648 
649 /* Set Switch Configuration (direct 0x0205) */
650 struct i40e_aqc_set_switch_config {
651 	__le16	flags;
652 /* flags used for both fields below */
653 #define I40E_AQ_SET_SWITCH_CFG_PROMISC		0x0001
654 	__le16	valid_flags;
655 	/* The ethertype in switch_tag is dropped on ingress and used
656 	 * internally by the switch. Set this to zero for the default
657 	 * of 0x88a8 (802.1ad). Should be zero for firmware API
658 	 * versions lower than 1.7.
659 	 */
660 	__le16	switch_tag;
661 	/* The ethertypes in first_tag and second_tag are used to
662 	 * match the outer and inner VLAN tags (respectively) when HW
663 	 * double VLAN tagging is enabled via the set port parameters
664 	 * AQ command. Otherwise these are both ignored. Set them to
665 	 * zero for their defaults of 0x8100 (802.1Q). Should be zero
666 	 * for firmware API versions lower than 1.7.
667 	 */
668 	__le16	first_tag;
669 	__le16	second_tag;
670 	/* Next byte is split into following:
671 	 * Bit 7    : 0 : No action, 1: Switch to mode defined by bits 6:0
672 	 * Bit 6    : 0 : Destination Port, 1: source port
673 	 * Bit 5..4 : L4 type
674 	 * 0: rsvd
675 	 * 1: TCP
676 	 * 2: UDP
677 	 * 3: Both TCP and UDP
678 	 * Bits 3:0 Mode
679 	 * 0: default mode
680 	 * 1: L4 port only mode
681 	 * 2: non-tunneled mode
682 	 * 3: tunneled mode
683 	 */
684 #define I40E_AQ_SET_SWITCH_BIT7_VALID		0x80
685 
686 
687 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP		0x10
688 
689 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL	0x02
690 	u8	mode;
691 	u8	rsvd5[5];
692 };
693 
694 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
695 
696 /* Read Receive control registers  (direct 0x0206)
697  * Write Receive control registers (direct 0x0207)
698  *     used for accessing Rx control registers that can be
699  *     slow and need special handling when under high Rx load
700  */
701 struct i40e_aqc_rx_ctl_reg_read_write {
702 	__le32 reserved1;
703 	__le32 address;
704 	__le32 reserved2;
705 	__le32 value;
706 };
707 
708 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
709 
710 /* Add VSI (indirect 0x0210)
711  *    this indirect command uses struct i40e_aqc_vsi_properties_data
712  *    as the indirect buffer (128 bytes)
713  *
714  * Update VSI (indirect 0x211)
715  *     uses the same data structure as Add VSI
716  *
717  * Get VSI (indirect 0x0212)
718  *     uses the same completion and data structure as Add VSI
719  */
720 struct i40e_aqc_add_get_update_vsi {
721 	__le16	uplink_seid;
722 	u8	connection_type;
723 #define I40E_AQ_VSI_CONN_TYPE_NORMAL	0x1
724 	u8	reserved1;
725 	u8	vf_id;
726 	u8	reserved2;
727 	__le16	vsi_flags;
728 #define I40E_AQ_VSI_TYPE_VF		0x0
729 #define I40E_AQ_VSI_TYPE_VMDQ2		0x1
730 #define I40E_AQ_VSI_TYPE_PF		0x2
731 	__le32	addr_high;
732 	__le32	addr_low;
733 };
734 
735 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
736 
737 struct i40e_aqc_add_get_update_vsi_completion {
738 	__le16 seid;
739 	__le16 vsi_number;
740 	__le16 vsi_used;
741 	__le16 vsi_free;
742 	__le32 addr_high;
743 	__le32 addr_low;
744 };
745 
746 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
747 
748 struct i40e_aqc_vsi_properties_data {
749 	/* first 96 byte are written by SW */
750 	__le16	valid_sections;
751 #define I40E_AQ_VSI_PROP_SWITCH_VALID		0x0001
752 #define I40E_AQ_VSI_PROP_SECURITY_VALID		0x0002
753 #define I40E_AQ_VSI_PROP_VLAN_VALID		0x0004
754 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID	0x0040
755 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID	0x0080
756 #define I40E_AQ_VSI_PROP_SCHED_VALID		0x0200
757 	/* switch section */
758 	__le16	switch_id; /* 12bit id combined with flags below */
759 #define I40E_AQ_VSI_SW_ID_SHIFT		0x0000
760 #define I40E_AQ_VSI_SW_ID_MASK		(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
761 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB	0x2000
762 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB	0x4000
763 	u8	sw_reserved[2];
764 	/* security section */
765 	u8	sec_flags;
766 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK	0x02
767 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK	0x04
768 	u8	sec_reserved;
769 	/* VLAN section */
770 	__le16	pvid; /* VLANS include priority bits */
771 	__le16	fcoe_pvid;
772 	u8	port_vlan_flags;
773 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
774 #define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
775 					 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
776 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED	0x01
777 #define I40E_AQ_VSI_PVLAN_MODE_ALL	0x03
778 #define I40E_AQ_VSI_PVLAN_INSERT_PVID	0x04
779 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT	0x03
780 #define I40E_AQ_VSI_PVLAN_EMOD_MASK	(0x3 << \
781 					 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
782 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH	0x0
783 #define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
784 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
785 	u8	pvlan_reserved[3];
786 	/* ingress egress up sections */
787 	__le32	ingress_table; /* bitmap, 3 bits per up */
788 	__le32	egress_table;   /* same defines as for ingress table */
789 	/* cascaded PV section */
790 	__le16	cas_pv_tag;
791 	u8	cas_pv_flags;
792 	u8	cas_pv_reserved;
793 	/* queue mapping section */
794 	__le16	mapping_flags;
795 #define I40E_AQ_VSI_QUE_MAP_CONTIG	0x0
796 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG	0x1
797 	__le16	queue_mapping[16];
798 	__le16	tc_mapping[8];
799 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT	0
800 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT	9
801 	/* queueing option section */
802 	u8	queueing_opt_flags;
803 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA	0x10
804 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI	0x40
805 	u8	queueing_opt_reserved[3];
806 	/* scheduler section */
807 	u8	up_enable_bits;
808 	u8	sched_reserved;
809 	/* outer up section */
810 	__le32	outer_up_table; /* same structure and defines as ingress tbl */
811 	u8	cmd_reserved[8];
812 	/* last 32 bytes are written by FW */
813 	__le16	qs_handle[8];
814 #define I40E_AQ_VSI_QS_HANDLE_INVALID	0xFFFF
815 	__le16	stat_counter_idx;
816 	__le16	sched_id;
817 	u8	resp_reserved[12];
818 };
819 
820 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
821 
822 /* Add Port Virtualizer (direct 0x0220)
823  * also used for update PV (direct 0x0221) but only flags are used
824  * (IS_CTRL_PORT only works on add PV)
825  */
826 struct i40e_aqc_add_update_pv {
827 	__le16	command_flags;
828 	__le16	uplink_seid;
829 	__le16	connected_seid;
830 	u8	reserved[10];
831 };
832 
833 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
834 
835 struct i40e_aqc_add_update_pv_completion {
836 	/* reserved for update; for add also encodes error if rc == ENOSPC */
837 	__le16	pv_seid;
838 	u8	reserved[14];
839 };
840 
841 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
842 
843 /* Get PV Params (direct 0x0222)
844  * uses i40e_aqc_switch_seid for the descriptor
845  */
846 
847 struct i40e_aqc_get_pv_params_completion {
848 	__le16	seid;
849 	__le16	default_stag;
850 	__le16	pv_flags; /* same flags as add_pv */
851 	u8	reserved[8];
852 	__le16	default_port_seid;
853 };
854 
855 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
856 
857 /* Add VEB (direct 0x0230) */
858 struct i40e_aqc_add_veb {
859 	__le16	uplink_seid;
860 	__le16	downlink_seid;
861 	__le16	veb_flags;
862 #define I40E_AQC_ADD_VEB_FLOATING		0x1
863 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT	0x2
864 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA		0x4
865 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS	0x10
866 	u8	enable_tcs;
867 	u8	reserved[9];
868 };
869 
870 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
871 
872 struct i40e_aqc_add_veb_completion {
873 	u8	reserved[6];
874 	__le16	switch_seid;
875 	/* also encodes error if rc == ENOSPC; codes are the same as add_pv */
876 	__le16	veb_seid;
877 	__le16	statistic_index;
878 	__le16	vebs_used;
879 	__le16	vebs_free;
880 };
881 
882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
883 
884 /* Get VEB Parameters (direct 0x0232)
885  * uses i40e_aqc_switch_seid for the descriptor
886  */
887 struct i40e_aqc_get_veb_parameters_completion {
888 	__le16	seid;
889 	__le16	switch_id;
890 	__le16	veb_flags; /* only the first/last flags from 0x0230 is valid */
891 	__le16	statistic_index;
892 	__le16	vebs_used;
893 	__le16	vebs_free;
894 	u8	reserved[4];
895 };
896 
897 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
898 
899 /* Delete Element (direct 0x0243)
900  * uses the generic i40e_aqc_switch_seid
901  */
902 
903 /* Add MAC-VLAN (indirect 0x0250) */
904 
905 /* used for the command for most vlan commands */
906 struct i40e_aqc_macvlan {
907 	__le16	num_addresses;
908 	__le16	seid[3];
909 #define I40E_AQC_MACVLAN_CMD_SEID_VALID		0x8000
910 	__le32	addr_high;
911 	__le32	addr_low;
912 };
913 
914 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
915 
916 /* indirect data for command and response */
917 struct i40e_aqc_add_macvlan_element_data {
918 	u8	mac_addr[6];
919 	__le16	vlan_tag;
920 	__le16	flags;
921 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH	0x0001
922 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN	0x0004
923 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC	0x0010
924 	__le16	queue_number;
925 	/* response section */
926 	u8	match_method;
927 #define I40E_AQC_MM_ERR_NO_RES		0xFF
928 	u8	reserved1[3];
929 };
930 
931 struct i40e_aqc_add_remove_macvlan_completion {
932 	__le16 perfect_mac_used;
933 	__le16 perfect_mac_free;
934 	__le16 unicast_hash_free;
935 	__le16 multicast_hash_free;
936 	__le32 addr_high;
937 	__le32 addr_low;
938 };
939 
940 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
941 
942 /* Remove MAC-VLAN (indirect 0x0251)
943  * uses i40e_aqc_macvlan for the descriptor
944  * data points to an array of num_addresses of elements
945  */
946 
947 struct i40e_aqc_remove_macvlan_element_data {
948 	u8	mac_addr[6];
949 	__le16	vlan_tag;
950 	u8	flags;
951 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH	0x01
952 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN	0x08
953 	u8	reserved[3];
954 	/* reply section */
955 	u8	error_code;
956 	u8	reply_reserved[3];
957 };
958 
959 /* Add VLAN (indirect 0x0252)
960  * Remove VLAN (indirect 0x0253)
961  * use the generic i40e_aqc_macvlan for the command
962  */
963 struct i40e_aqc_add_remove_vlan_element_data {
964 	__le16	vlan_tag;
965 	u8	vlan_flags;
966 	u8	reserved;
967 	u8	result;
968 	u8	reserved1[3];
969 };
970 
971 struct i40e_aqc_add_remove_vlan_completion {
972 	u8	reserved[4];
973 	__le16	vlans_used;
974 	__le16	vlans_free;
975 	__le32	addr_high;
976 	__le32	addr_low;
977 };
978 
979 /* Set VSI Promiscuous Modes (direct 0x0254) */
980 struct i40e_aqc_set_vsi_promiscuous_modes {
981 	__le16	promiscuous_flags;
982 	__le16	valid_flags;
983 /* flags used for both fields above */
984 #define I40E_AQC_SET_VSI_PROMISC_UNICAST	0x01
985 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST	0x02
986 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
987 #define I40E_AQC_SET_VSI_DEFAULT		0x08
988 #define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
989 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY	0x8000
990 	__le16	seid;
991 	__le16	vlan_tag;
992 #define I40E_AQC_SET_VSI_VLAN_VALID		0x8000
993 	u8	reserved[8];
994 };
995 
996 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
997 
998 /* Add S/E-tag command (direct 0x0255)
999  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1000  */
1001 struct i40e_aqc_add_tag {
1002 	__le16	flags;
1003 	__le16	seid;
1004 	__le16	tag;
1005 	__le16	queue_number;
1006 	u8	reserved[8];
1007 };
1008 
1009 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1010 
1011 struct i40e_aqc_add_remove_tag_completion {
1012 	u8	reserved[12];
1013 	__le16	tags_used;
1014 	__le16	tags_free;
1015 };
1016 
1017 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1018 
1019 /* Remove S/E-tag command (direct 0x0256)
1020  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1021  */
1022 struct i40e_aqc_remove_tag {
1023 	__le16	seid;
1024 	__le16	tag;
1025 	u8	reserved[12];
1026 };
1027 
1028 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1029 
1030 /* Add multicast E-Tag (direct 0x0257)
1031  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1032  * and no external data
1033  */
1034 struct i40e_aqc_add_remove_mcast_etag {
1035 	__le16	pv_seid;
1036 	__le16	etag;
1037 	u8	num_unicast_etags;
1038 	u8	reserved[3];
1039 	__le32	addr_high;          /* address of array of 2-byte s-tags */
1040 	__le32	addr_low;
1041 };
1042 
1043 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1044 
1045 struct i40e_aqc_add_remove_mcast_etag_completion {
1046 	u8	reserved[4];
1047 	__le16	mcast_etags_used;
1048 	__le16	mcast_etags_free;
1049 	__le32	addr_high;
1050 	__le32	addr_low;
1051 
1052 };
1053 
1054 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1055 
1056 /* Update S/E-Tag (direct 0x0259) */
1057 struct i40e_aqc_update_tag {
1058 	__le16	seid;
1059 	__le16	old_tag;
1060 	__le16	new_tag;
1061 	u8	reserved[10];
1062 };
1063 
1064 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1065 
1066 struct i40e_aqc_update_tag_completion {
1067 	u8	reserved[12];
1068 	__le16	tags_used;
1069 	__le16	tags_free;
1070 };
1071 
1072 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1073 
1074 /* Add Control Packet filter (direct 0x025A)
1075  * Remove Control Packet filter (direct 0x025B)
1076  * uses the i40e_aqc_add_oveb_cloud,
1077  * and the generic direct completion structure
1078  */
1079 struct i40e_aqc_add_remove_control_packet_filter {
1080 	u8	mac[6];
1081 	__le16	etype;
1082 	__le16	flags;
1083 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC	0x0001
1084 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP		0x0002
1085 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX		0x0008
1086 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX		0x0000
1087 	__le16	seid;
1088 	__le16	queue;
1089 	u8	reserved[2];
1090 };
1091 
1092 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1093 
1094 struct i40e_aqc_add_remove_control_packet_filter_completion {
1095 	__le16	mac_etype_used;
1096 	__le16	etype_used;
1097 	__le16	mac_etype_free;
1098 	__le16	etype_free;
1099 	u8	reserved[8];
1100 };
1101 
1102 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1103 
1104 /* Add Cloud filters (indirect 0x025C)
1105  * Remove Cloud filters (indirect 0x025D)
1106  * uses the i40e_aqc_add_remove_cloud_filters,
1107  * and the generic indirect completion structure
1108  */
1109 struct i40e_aqc_add_remove_cloud_filters {
1110 	u8	num_filters;
1111 	u8	reserved;
1112 	__le16	seid;
1113 	u8	big_buffer_flag;
1114 #define I40E_AQC_ADD_CLOUD_CMD_BB	1
1115 	u8	reserved2[3];
1116 	__le32	addr_high;
1117 	__le32	addr_low;
1118 };
1119 
1120 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1121 
1122 struct i40e_aqc_cloud_filters_element_data {
1123 	u8	outer_mac[6];
1124 	u8	inner_mac[6];
1125 	__le16	inner_vlan;
1126 	union {
1127 		struct {
1128 			u8 reserved[12];
1129 			u8 data[4];
1130 		} v4;
1131 		struct {
1132 			u8 data[16];
1133 		} v6;
1134 		struct {
1135 			__le16 data[8];
1136 		} raw_v6;
1137 	} ipaddr;
1138 	__le16	flags;
1139 /* 0x0000 reserved */
1140 /* 0x0001 reserved */
1141 /* 0x0002 reserved */
1142 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN		0x0003
1143 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID	0x0004
1144 /* 0x0005 reserved */
1145 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID		0x0006
1146 /* 0x0007 reserved */
1147 /* 0x0008 reserved */
1148 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC			0x0009
1149 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A
1150 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B
1151 #define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C
1152 /* 0x000D reserved */
1153 /* 0x000E reserved */
1154 /* 0x000F reserved */
1155 /* 0x0010 to 0x0017 is for custom filters */
1156 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT		0x0010 /* Dest IP + L4 Port */
1157 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT		0x0011 /* Dest MAC + L4 Port */
1158 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT		0x0012 /* Dest MAC + VLAN + L4 Port */
1159 
1160 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4			0
1161 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6			0x0100
1162 
1163 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT		9
1164 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK		0x1E00
1165 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE		2
1166 
1167 
1168 	__le32	tenant_id;
1169 	u8	reserved[4];
1170 	__le16	queue_number;
1171 	u8	reserved2[14];
1172 	/* response section */
1173 	u8	allocation_result;
1174 	u8	response_reserved[7];
1175 };
1176 
1177 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1178 
1179 /* i40e_aqc_cloud_filters_element_bb is used when
1180  * I40E_AQC_CLOUD_CMD_BB flag is set.
1181  */
1182 struct i40e_aqc_cloud_filters_element_bb {
1183 	struct i40e_aqc_cloud_filters_element_data element;
1184 	u16     general_fields[32];
1185 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0	15
1186 };
1187 
1188 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1189 
1190 struct i40e_aqc_remove_cloud_filters_completion {
1191 	__le16 perfect_ovlan_used;
1192 	__le16 perfect_ovlan_free;
1193 	__le16 vlan_used;
1194 	__le16 vlan_free;
1195 	__le32 addr_high;
1196 	__le32 addr_low;
1197 };
1198 
1199 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1200 
1201 /* Replace filter Command 0x025F
1202  * uses the i40e_aqc_replace_cloud_filters,
1203  * and the generic indirect completion structure
1204  */
1205 struct i40e_filter_data {
1206 	u8 filter_type;
1207 	u8 input[3];
1208 };
1209 
1210 I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1211 
1212 struct i40e_aqc_replace_cloud_filters_cmd {
1213 	u8      valid_flags;
1214 	u8      old_filter_type;
1215 	u8      new_filter_type;
1216 	u8      tr_bit;
1217 	u8      reserved[4];
1218 	__le32 addr_high;
1219 	__le32 addr_low;
1220 };
1221 
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1223 
1224 struct i40e_aqc_replace_cloud_filters_cmd_buf {
1225 	u8      data[32];
1226 	struct i40e_filter_data filters[8];
1227 };
1228 
1229 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1230 
1231 /* Add Mirror Rule (indirect or direct 0x0260)
1232  * Delete Mirror Rule (indirect or direct 0x0261)
1233  * note: some rule types (4,5) do not use an external buffer.
1234  *       take care to set the flags correctly.
1235  */
1236 struct i40e_aqc_add_delete_mirror_rule {
1237 	__le16 seid;
1238 	__le16 rule_type;
1239 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT		0
1240 #define I40E_AQC_MIRROR_RULE_TYPE_MASK		(0x7 << \
1241 						I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1242 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN		3
1243 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS	4
1244 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS	5
1245 	__le16 num_entries;
1246 	__le16 destination;  /* VSI for add, rule id for delete */
1247 	__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1248 	__le32 addr_low;
1249 };
1250 
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1252 
1253 struct i40e_aqc_add_delete_mirror_rule_completion {
1254 	u8	reserved[2];
1255 	__le16	rule_id;  /* only used on add */
1256 	__le16	mirror_rules_used;
1257 	__le16	mirror_rules_free;
1258 	__le32	addr_high;
1259 	__le32	addr_low;
1260 };
1261 
1262 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1263 
1264 /* Dynamic Device Personalization */
1265 struct i40e_aqc_write_personalization_profile {
1266 	u8      flags;
1267 	u8      reserved[3];
1268 	__le32  profile_track_id;
1269 	__le32  addr_high;
1270 	__le32  addr_low;
1271 };
1272 
1273 I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1274 
1275 struct i40e_aqc_write_ddp_resp {
1276 	__le32 error_offset;
1277 	__le32 error_info;
1278 	__le32 addr_high;
1279 	__le32 addr_low;
1280 };
1281 
1282 struct i40e_aqc_get_applied_profiles {
1283 	u8      flags;
1284 	u8      rsv[3];
1285 	__le32  reserved;
1286 	__le32  addr_high;
1287 	__le32  addr_low;
1288 };
1289 
1290 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1291 
1292 /* DCB 0x03xx*/
1293 
1294 /* PFC Ignore (direct 0x0301)
1295  *    the command and response use the same descriptor structure
1296  */
1297 struct i40e_aqc_pfc_ignore {
1298 	u8	tc_bitmap;
1299 	u8	command_flags; /* unused on response */
1300 	u8	reserved[14];
1301 };
1302 
1303 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1304 
1305 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1306  * with no parameters
1307  */
1308 
1309 /* TX scheduler 0x04xx */
1310 
1311 /* Almost all the indirect commands use
1312  * this generic struct to pass the SEID in param0
1313  */
1314 struct i40e_aqc_tx_sched_ind {
1315 	__le16	vsi_seid;
1316 	u8	reserved[6];
1317 	__le32	addr_high;
1318 	__le32	addr_low;
1319 };
1320 
1321 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1322 
1323 /* Several commands respond with a set of queue set handles */
1324 struct i40e_aqc_qs_handles_resp {
1325 	__le16 qs_handles[8];
1326 };
1327 
1328 /* Configure VSI BW limits (direct 0x0400) */
1329 struct i40e_aqc_configure_vsi_bw_limit {
1330 	__le16	vsi_seid;
1331 	u8	reserved[2];
1332 	__le16	credit;
1333 	u8	reserved1[2];
1334 	u8	max_credit; /* 0-3, limit = 2^max */
1335 	u8	reserved2[7];
1336 };
1337 
1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1339 
1340 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1341  *    responds with i40e_aqc_qs_handles_resp
1342  */
1343 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1344 	u8	tc_valid_bits;
1345 	u8	reserved[15];
1346 	__le16	tc_bw_credits[8]; /* FW writesback QS handles here */
1347 
1348 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1349 	__le16	tc_bw_max[2];
1350 	u8	reserved1[28];
1351 };
1352 
1353 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1354 
1355 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1356  *    responds with i40e_aqc_qs_handles_resp
1357  */
1358 struct i40e_aqc_configure_vsi_tc_bw_data {
1359 	u8	tc_valid_bits;
1360 	u8	reserved[3];
1361 	u8	tc_bw_credits[8];
1362 	u8	reserved1[4];
1363 	__le16	qs_handles[8];
1364 };
1365 
1366 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1367 
1368 /* Query vsi bw configuration (indirect 0x0408) */
1369 struct i40e_aqc_query_vsi_bw_config_resp {
1370 	u8	tc_valid_bits;
1371 	u8	tc_suspended_bits;
1372 	u8	reserved[14];
1373 	__le16	qs_handles[8];
1374 	u8	reserved1[4];
1375 	__le16	port_bw_limit;
1376 	u8	reserved2[2];
1377 	u8	max_bw; /* 0-3, limit = 2^max */
1378 	u8	reserved3[23];
1379 };
1380 
1381 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1382 
1383 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1384 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1385 	u8	tc_valid_bits;
1386 	u8	reserved[3];
1387 	u8	share_credits[8];
1388 	__le16	credits[8];
1389 
1390 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1391 	__le16	tc_bw_max[2];
1392 };
1393 
1394 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1395 
1396 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1397 struct i40e_aqc_configure_switching_comp_bw_limit {
1398 	__le16	seid;
1399 	u8	reserved[2];
1400 	__le16	credit;
1401 	u8	reserved1[2];
1402 	u8	max_bw; /* 0-3, limit = 2^max */
1403 	u8	reserved2[7];
1404 };
1405 
1406 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1407 
1408 /* Enable  Physical Port ETS (indirect 0x0413)
1409  * Modify  Physical Port ETS (indirect 0x0414)
1410  * Disable Physical Port ETS (indirect 0x0415)
1411  */
1412 struct i40e_aqc_configure_switching_comp_ets_data {
1413 	u8	reserved[4];
1414 	u8	tc_valid_bits;
1415 	u8	seepage;
1416 	u8	tc_strict_priority_flags;
1417 	u8	reserved1[17];
1418 	u8	tc_bw_share_credits[8];
1419 	u8	reserved2[96];
1420 };
1421 
1422 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1423 
1424 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1425 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1426 	u8	tc_valid_bits;
1427 	u8	reserved[15];
1428 	__le16	tc_bw_credit[8];
1429 
1430 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1431 	__le16	tc_bw_max[2];
1432 	u8	reserved1[28];
1433 };
1434 
1435 I40E_CHECK_STRUCT_LEN(0x40,
1436 		      i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1437 
1438 /* Configure Switching Component Bandwidth Allocation per Tc
1439  * (indirect 0x0417)
1440  */
1441 struct i40e_aqc_configure_switching_comp_bw_config_data {
1442 	u8	tc_valid_bits;
1443 	u8	reserved[2];
1444 	u8	absolute_credits; /* bool */
1445 	u8	tc_bw_share_credits[8];
1446 	u8	reserved1[20];
1447 };
1448 
1449 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1450 
1451 /* Query Switching Component Configuration (indirect 0x0418) */
1452 struct i40e_aqc_query_switching_comp_ets_config_resp {
1453 	u8	tc_valid_bits;
1454 	u8	reserved[35];
1455 	__le16	port_bw_limit;
1456 	u8	reserved1[2];
1457 	u8	tc_bw_max; /* 0-3, limit = 2^max */
1458 	u8	reserved2[23];
1459 };
1460 
1461 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1462 
1463 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1464 struct i40e_aqc_query_port_ets_config_resp {
1465 	u8	reserved[4];
1466 	u8	tc_valid_bits;
1467 	u8	reserved1;
1468 	u8	tc_strict_priority_bits;
1469 	u8	reserved2;
1470 	u8	tc_bw_share_credits[8];
1471 	__le16	tc_bw_limits[8];
1472 
1473 	/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1474 	__le16	tc_bw_max[2];
1475 	u8	reserved3[32];
1476 };
1477 
1478 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1479 
1480 /* Query Switching Component Bandwidth Allocation per Traffic Type
1481  * (indirect 0x041A)
1482  */
1483 struct i40e_aqc_query_switching_comp_bw_config_resp {
1484 	u8	tc_valid_bits;
1485 	u8	reserved[2];
1486 	u8	absolute_credits_enable; /* bool */
1487 	u8	tc_bw_share_credits[8];
1488 	__le16	tc_bw_limits[8];
1489 
1490 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1491 	__le16	tc_bw_max[2];
1492 };
1493 
1494 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1495 
1496 /* Suspend/resume port TX traffic
1497  * (direct 0x041B and 0x041C) uses the generic SEID struct
1498  */
1499 
1500 /* Configure partition BW
1501  * (indirect 0x041D)
1502  */
1503 struct i40e_aqc_configure_partition_bw_data {
1504 	__le16	pf_valid_bits;
1505 	u8	min_bw[16];      /* guaranteed bandwidth */
1506 	u8	max_bw[16];      /* bandwidth limit */
1507 };
1508 
1509 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1510 
1511 /* Get and set the active HMC resource profile and status.
1512  * (direct 0x0500) and (direct 0x0501)
1513  */
1514 struct i40e_aq_get_set_hmc_resource_profile {
1515 	u8	pm_profile;
1516 	u8	pe_vf_enabled;
1517 	u8	reserved[14];
1518 };
1519 
1520 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1521 
1522 enum i40e_aq_hmc_profile {
1523 	/* I40E_HMC_PROFILE_NO_CHANGE	= 0, reserved */
1524 	I40E_HMC_PROFILE_DEFAULT	= 1,
1525 	I40E_HMC_PROFILE_FAVOR_VF	= 2,
1526 	I40E_HMC_PROFILE_EQUAL		= 3,
1527 };
1528 
1529 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1530 
1531 /* set in param0 for get phy abilities to report qualified modules */
1532 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES	0x0001
1533 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES	0x0002
1534 
1535 enum i40e_aq_phy_type {
1536 	I40E_PHY_TYPE_SGMII			= 0x0,
1537 	I40E_PHY_TYPE_1000BASE_KX		= 0x1,
1538 	I40E_PHY_TYPE_10GBASE_KX4		= 0x2,
1539 	I40E_PHY_TYPE_10GBASE_KR		= 0x3,
1540 	I40E_PHY_TYPE_40GBASE_KR4		= 0x4,
1541 	I40E_PHY_TYPE_XAUI			= 0x5,
1542 	I40E_PHY_TYPE_XFI			= 0x6,
1543 	I40E_PHY_TYPE_SFI			= 0x7,
1544 	I40E_PHY_TYPE_XLAUI			= 0x8,
1545 	I40E_PHY_TYPE_XLPPI			= 0x9,
1546 	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,
1547 	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,
1548 	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,
1549 	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,
1550 	I40E_PHY_TYPE_UNRECOGNIZED		= 0xE,
1551 	I40E_PHY_TYPE_UNSUPPORTED		= 0xF,
1552 	I40E_PHY_TYPE_100BASE_TX		= 0x11,
1553 	I40E_PHY_TYPE_1000BASE_T		= 0x12,
1554 	I40E_PHY_TYPE_10GBASE_T			= 0x13,
1555 	I40E_PHY_TYPE_10GBASE_SR		= 0x14,
1556 	I40E_PHY_TYPE_10GBASE_LR		= 0x15,
1557 	I40E_PHY_TYPE_10GBASE_SFPP_CU		= 0x16,
1558 	I40E_PHY_TYPE_10GBASE_CR1		= 0x17,
1559 	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,
1560 	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,
1561 	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,
1562 	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,
1563 	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
1564 	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
1565 	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
1566 	I40E_PHY_TYPE_25GBASE_KR		= 0x1F,
1567 	I40E_PHY_TYPE_25GBASE_CR		= 0x20,
1568 	I40E_PHY_TYPE_25GBASE_SR		= 0x21,
1569 	I40E_PHY_TYPE_25GBASE_LR		= 0x22,
1570 	I40E_PHY_TYPE_25GBASE_AOC		= 0x23,
1571 	I40E_PHY_TYPE_25GBASE_ACC		= 0x24,
1572 	I40E_PHY_TYPE_2_5GBASE_T		= 0x26,
1573 	I40E_PHY_TYPE_5GBASE_T			= 0x27,
1574 	I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS	= 0x30,
1575 	I40E_PHY_TYPE_5GBASE_T_LINK_STATUS	= 0x31,
1576 	I40E_PHY_TYPE_MAX,
1577 	I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP	= 0xFD,
1578 	I40E_PHY_TYPE_EMPTY			= 0xFE,
1579 	I40E_PHY_TYPE_DEFAULT			= 0xFF,
1580 };
1581 
1582 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
1583 				BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
1584 				BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
1585 				BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
1586 				BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
1587 				BIT_ULL(I40E_PHY_TYPE_XAUI) | \
1588 				BIT_ULL(I40E_PHY_TYPE_XFI) | \
1589 				BIT_ULL(I40E_PHY_TYPE_SFI) | \
1590 				BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
1591 				BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
1592 				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
1593 				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
1594 				BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
1595 				BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
1596 				BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
1597 				BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
1598 				BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
1599 				BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
1600 				BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
1601 				BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
1602 				BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
1603 				BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
1604 				BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
1605 				BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
1606 				BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
1607 				BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
1608 				BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
1609 				BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
1610 				BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
1611 				BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
1612 				BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
1613 				BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
1614 				BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
1615 				BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
1616 				BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
1617 				BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
1618 				BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
1619 				BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
1620 
1621 #define I40E_LINK_SPEED_2_5GB_SHIFT	0x0
1622 #define I40E_LINK_SPEED_100MB_SHIFT	0x1
1623 #define I40E_LINK_SPEED_1000MB_SHIFT	0x2
1624 #define I40E_LINK_SPEED_10GB_SHIFT	0x3
1625 #define I40E_LINK_SPEED_40GB_SHIFT	0x4
1626 #define I40E_LINK_SPEED_20GB_SHIFT	0x5
1627 #define I40E_LINK_SPEED_25GB_SHIFT	0x6
1628 #define I40E_LINK_SPEED_5GB_SHIFT	0x7
1629 
1630 enum i40e_aq_link_speed {
1631 	I40E_LINK_SPEED_UNKNOWN	= 0,
1632 	I40E_LINK_SPEED_100MB	= BIT(I40E_LINK_SPEED_100MB_SHIFT),
1633 	I40E_LINK_SPEED_1GB	= BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1634 	I40E_LINK_SPEED_2_5GB	= (1 << I40E_LINK_SPEED_2_5GB_SHIFT),
1635 	I40E_LINK_SPEED_5GB	= (1 << I40E_LINK_SPEED_5GB_SHIFT),
1636 	I40E_LINK_SPEED_10GB	= BIT(I40E_LINK_SPEED_10GB_SHIFT),
1637 	I40E_LINK_SPEED_40GB	= BIT(I40E_LINK_SPEED_40GB_SHIFT),
1638 	I40E_LINK_SPEED_20GB	= BIT(I40E_LINK_SPEED_20GB_SHIFT),
1639 	I40E_LINK_SPEED_25GB	= BIT(I40E_LINK_SPEED_25GB_SHIFT),
1640 };
1641 
1642 struct i40e_aqc_module_desc {
1643 	u8 oui[3];
1644 	u8 reserved1;
1645 	u8 part_number[16];
1646 	u8 revision[4];
1647 	u8 reserved2[8];
1648 };
1649 
1650 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1651 
1652 struct i40e_aq_get_phy_abilities_resp {
1653 	__le32	phy_type;       /* bitmap using the above enum for offsets */
1654 	u8	link_speed;     /* bitmap using the above enum bit patterns */
1655 	u8	abilities;
1656 #define I40E_AQ_PHY_FLAG_PAUSE_TX	0x01
1657 #define I40E_AQ_PHY_FLAG_PAUSE_RX	0x02
1658 	__le16	eee_capability;
1659 	__le32	eeer_val;
1660 	u8	d3_lpan;
1661 	u8	phy_type_ext;
1662 #define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
1663 #define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
1664 #define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
1665 #define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
1666 	u8	fec_cfg_curr_mod_ext_info;
1667 #define I40E_AQ_REQUEST_FEC_KR		0x04
1668 #define I40E_AQ_REQUEST_FEC_RS		0x08
1669 #define I40E_AQ_ENABLE_FEC_AUTO		0x10
1670 
1671 	u8	ext_comp_code;
1672 	u8	phy_id[4];
1673 	u8	module_type[3];
1674 	u8	qualified_module_count;
1675 #define I40E_AQ_PHY_MAX_QMS		16
1676 	struct i40e_aqc_module_desc	qualified_module[I40E_AQ_PHY_MAX_QMS];
1677 };
1678 
1679 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1680 
1681 /* Set PHY Config (direct 0x0601) */
1682 struct i40e_aq_set_phy_config { /* same bits as above in all */
1683 	__le32	phy_type;
1684 	u8	link_speed;
1685 	u8	abilities;
1686 /* bits 0-2 use the values from get_phy_abilities_resp */
1687 #define I40E_AQ_PHY_ENABLE_LINK		0x08
1688 #define I40E_AQ_PHY_ENABLE_AN		0x10
1689 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK	0x20
1690 	__le16	eee_capability;
1691 	__le32	eeer;
1692 	u8	low_power_ctrl;
1693 	u8	phy_type_ext;
1694 #define I40E_AQ_PHY_TYPE_EXT_25G_KR	0X01
1695 #define I40E_AQ_PHY_TYPE_EXT_25G_CR	0X02
1696 #define I40E_AQ_PHY_TYPE_EXT_25G_SR	0x04
1697 #define I40E_AQ_PHY_TYPE_EXT_25G_LR	0x08
1698 	u8	fec_config;
1699 #define I40E_AQ_SET_FEC_ABILITY_KR	BIT(0)
1700 #define I40E_AQ_SET_FEC_ABILITY_RS	BIT(1)
1701 #define I40E_AQ_SET_FEC_REQUEST_KR	BIT(2)
1702 #define I40E_AQ_SET_FEC_REQUEST_RS	BIT(3)
1703 #define I40E_AQ_SET_FEC_AUTO		BIT(4)
1704 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT	0x0
1705 #define I40E_AQ_PHY_FEC_CONFIG_MASK	(0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1706 	u8	reserved;
1707 };
1708 
1709 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1710 
1711 /* Set MAC Config command data structure (direct 0x0603) */
1712 struct i40e_aq_set_mac_config {
1713 	__le16	max_frame_size;
1714 	u8	params;
1715 	u8	tx_timer_priority; /* bitmap */
1716 	__le16	tx_timer_value;
1717 	__le16	fc_refresh_threshold;
1718 	u8	reserved[8];
1719 };
1720 
1721 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1722 
1723 /* Restart Auto-Negotiation (direct 0x605) */
1724 struct i40e_aqc_set_link_restart_an {
1725 	u8	command;
1726 #define I40E_AQ_PHY_RESTART_AN	0x02
1727 #define I40E_AQ_PHY_LINK_ENABLE	0x04
1728 	u8	reserved[15];
1729 };
1730 
1731 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1732 
1733 /* Get Link Status cmd & response data structure (direct 0x0607) */
1734 struct i40e_aqc_get_link_status {
1735 	__le16	command_flags; /* only field set on command */
1736 #define I40E_AQ_LSE_DISABLE		0x2
1737 #define I40E_AQ_LSE_ENABLE		0x3
1738 /* only response uses this flag */
1739 #define I40E_AQ_LSE_IS_ENABLED		0x1
1740 	u8	phy_type;    /* i40e_aq_phy_type   */
1741 	u8	link_speed;  /* i40e_aq_link_speed */
1742 	u8	link_info;
1743 #define I40E_AQ_LINK_UP			0x01    /* obsolete */
1744 #define I40E_AQ_MEDIA_AVAILABLE		0x40
1745 	u8	an_info;
1746 #define I40E_AQ_AN_COMPLETED		0x01
1747 #define I40E_AQ_LINK_PAUSE_TX		0x20
1748 #define I40E_AQ_LINK_PAUSE_RX		0x40
1749 #define I40E_AQ_QUALIFIED_MODULE	0x80
1750 	u8	ext_info;
1751 	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
1752 /* Since firmware API 1.7 loopback field keeps power class info as well */
1753 #define I40E_AQ_LOOPBACK_MASK		0x07
1754 	__le16	max_frame_size;
1755 	u8	config;
1756 #define I40E_AQ_CONFIG_FEC_KR_ENA	0x01
1757 #define I40E_AQ_CONFIG_FEC_RS_ENA	0x02
1758 #define I40E_AQ_CONFIG_CRC_ENA		0x04
1759 #define I40E_AQ_CONFIG_PACING_MASK	0x78
1760 	union {
1761 		struct {
1762 			u8	power_desc;
1763 			u8	reserved[4];
1764 		};
1765 		struct {
1766 			u8	link_type[4];
1767 			u8	link_type_ext;
1768 		};
1769 	};
1770 };
1771 
1772 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1773 
1774 /* Set event mask command (direct 0x613) */
1775 struct i40e_aqc_set_phy_int_mask {
1776 	u8	reserved[8];
1777 	__le16	event_mask;
1778 #define I40E_AQ_EVENT_LINK_UPDOWN	0x0002
1779 #define I40E_AQ_EVENT_MEDIA_NA		0x0004
1780 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL	0x0100
1781 	u8	reserved1[6];
1782 };
1783 
1784 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1785 
1786 /* Get Local AN advt register (direct 0x0614)
1787  * Set Local AN advt register (direct 0x0615)
1788  * Get Link Partner AN advt register (direct 0x0616)
1789  */
1790 struct i40e_aqc_an_advt_reg {
1791 	__le32	local_an_reg0;
1792 	__le16	local_an_reg1;
1793 	u8	reserved[10];
1794 };
1795 
1796 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1797 
1798 /* Set Loopback mode (0x0618) */
1799 struct i40e_aqc_set_lb_mode {
1800 	__le16	lb_mode;
1801 #define I40E_LEGACY_LOOPBACK_NVM_VER	0x6000
1802 #define I40E_AQ_LB_MAC_LOCAL		0x01
1803 #define I40E_AQ_LB_PHY_LOCAL		0x05
1804 #define I40E_AQ_LB_PHY_REMOTE		0x06
1805 #define I40E_AQ_LB_MAC_LOCAL_LEGACY	0x04
1806 	u8	reserved[14];
1807 };
1808 
1809 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1810 
1811 /* Set PHY Debug command (0x0622) */
1812 struct i40e_aqc_set_phy_debug {
1813 	u8	command_flags;
1814 /* Disable link manageability on a single port */
1815 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10
1816 /* Disable link manageability on all ports */
1817 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW	0x20
1818 	u8	reserved[15];
1819 };
1820 
1821 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1822 
1823 enum i40e_aq_phy_reg_type {
1824 	I40E_AQC_PHY_REG_INTERNAL	= 0x1,
1825 	I40E_AQC_PHY_REG_EXERNAL_BASET	= 0x2,
1826 	I40E_AQC_PHY_REG_EXERNAL_MODULE	= 0x3
1827 };
1828 
1829 /* Run PHY Activity (0x0626) */
1830 struct i40e_aqc_run_phy_activity {
1831 	__le16  activity_id;
1832 	u8      flags;
1833 	u8      reserved1;
1834 	__le32  control;
1835 	__le32  data;
1836 	u8      reserved2[4];
1837 };
1838 
1839 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1840 
1841 /* Set PHY Register command (0x0628) */
1842 /* Get PHY Register command (0x0629) */
1843 struct i40e_aqc_phy_register_access {
1844 	u8	phy_interface;
1845 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL	1
1846 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE	2
1847 	u8	dev_address;
1848 	u8	cmd_flags;
1849 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE	0x01
1850 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER	0x02
1851 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT	2
1852 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK	(0x3 << \
1853 		I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT)
1854 	u8	reserved1;
1855 	__le32	reg_address;
1856 	__le32	reg_value;
1857 	u8	reserved2[4];
1858 };
1859 
1860 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
1861 
1862 /* NVM Read command (indirect 0x0701)
1863  * NVM Erase commands (direct 0x0702)
1864  * NVM Update commands (indirect 0x0703)
1865  */
1866 struct i40e_aqc_nvm_update {
1867 	u8	command_flags;
1868 #define I40E_AQ_NVM_LAST_CMD			0x01
1869 #define I40E_AQ_NVM_REARRANGE_TO_FLAT		0x20
1870 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT		0x40
1871 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT	1
1872 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED	0x03
1873 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL	0x01
1874 	u8	module_pointer;
1875 	__le16	length;
1876 	__le32	offset;
1877 	__le32	addr_high;
1878 	__le32	addr_low;
1879 };
1880 
1881 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1882 
1883 /* NVM Config Read (indirect 0x0704) */
1884 struct i40e_aqc_nvm_config_read {
1885 	__le16	cmd_flags;
1886 	__le16	element_count;
1887 	__le16	element_id;	/* Feature/field ID */
1888 	__le16	element_id_msw;	/* MSWord of field ID */
1889 	__le32	address_high;
1890 	__le32	address_low;
1891 };
1892 
1893 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1894 
1895 /* NVM Config Write (indirect 0x0705) */
1896 struct i40e_aqc_nvm_config_write {
1897 	__le16	cmd_flags;
1898 	__le16	element_count;
1899 	u8	reserved[4];
1900 	__le32	address_high;
1901 	__le32	address_low;
1902 };
1903 
1904 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1905 
1906 /* Used for 0x0704 as well as for 0x0705 commands */
1907 struct i40e_aqc_nvm_config_data_feature {
1908 	__le16 feature_id;
1909 	__le16 feature_options;
1910 	__le16 feature_selection;
1911 };
1912 
1913 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1914 
1915 struct i40e_aqc_nvm_config_data_immediate_field {
1916 	__le32 field_id;
1917 	__le32 field_value;
1918 	__le16 field_options;
1919 	__le16 reserved;
1920 };
1921 
1922 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1923 
1924 /* OEM Post Update (indirect 0x0720)
1925  * no command data struct used
1926  */
1927 struct i40e_aqc_nvm_oem_post_update {
1928 	u8 sel_data;
1929 	u8 reserved[7];
1930 };
1931 
1932 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1933 
1934 struct i40e_aqc_nvm_oem_post_update_buffer {
1935 	u8 str_len;
1936 	u8 dev_addr;
1937 	__le16 eeprom_addr;
1938 	u8 data[36];
1939 };
1940 
1941 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1942 
1943 /* Thermal Sensor (indirect 0x0721)
1944  *     read or set thermal sensor configs and values
1945  *     takes a sensor and command specific data buffer, not detailed here
1946  */
1947 struct i40e_aqc_thermal_sensor {
1948 	u8 sensor_action;
1949 	u8 reserved[7];
1950 	__le32	addr_high;
1951 	__le32	addr_low;
1952 };
1953 
1954 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1955 
1956 /* Send to PF command (indirect 0x0801) id is only used by PF
1957  * Send to VF command (indirect 0x0802) id is only used by PF
1958  * Send to Peer PF command (indirect 0x0803)
1959  */
1960 struct i40e_aqc_pf_vf_message {
1961 	__le32	id;
1962 	u8	reserved[4];
1963 	__le32	addr_high;
1964 	__le32	addr_low;
1965 };
1966 
1967 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1968 
1969 /* Alternate structure */
1970 
1971 /* Direct write (direct 0x0900)
1972  * Direct read (direct 0x0902)
1973  */
1974 struct i40e_aqc_alternate_write {
1975 	__le32 address0;
1976 	__le32 data0;
1977 	__le32 address1;
1978 	__le32 data1;
1979 };
1980 
1981 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1982 
1983 /* Indirect write (indirect 0x0901)
1984  * Indirect read (indirect 0x0903)
1985  */
1986 
1987 struct i40e_aqc_alternate_ind_write {
1988 	__le32 address;
1989 	__le32 length;
1990 	__le32 addr_high;
1991 	__le32 addr_low;
1992 };
1993 
1994 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1995 
1996 /* Done alternate write (direct 0x0904)
1997  * uses i40e_aq_desc
1998  */
1999 struct i40e_aqc_alternate_write_done {
2000 	__le16	cmd_flags;
2001 	u8	reserved[14];
2002 };
2003 
2004 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2005 
2006 /* Set OEM mode (direct 0x0905) */
2007 struct i40e_aqc_alternate_set_mode {
2008 	__le32	mode;
2009 	u8	reserved[12];
2010 };
2011 
2012 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2013 
2014 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2015 
2016 /* async events 0x10xx */
2017 
2018 /* Lan Queue Overflow Event (direct, 0x1001) */
2019 struct i40e_aqc_lan_overflow {
2020 	__le32	prtdcb_rupto;
2021 	__le32	otx_ctl;
2022 	u8	reserved[8];
2023 };
2024 
2025 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2026 
2027 /* Get LLDP MIB (indirect 0x0A00) */
2028 struct i40e_aqc_lldp_get_mib {
2029 	u8	type;
2030 	u8	reserved1;
2031 #define I40E_AQ_LLDP_MIB_TYPE_MASK		0x3
2032 #define I40E_AQ_LLDP_MIB_LOCAL			0x0
2033 #define I40E_AQ_LLDP_MIB_REMOTE			0x1
2034 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK		0xC
2035 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT		0x2
2036 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE	0x0
2037 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2038 	__le16	local_len;
2039 	__le16	remote_len;
2040 	u8	reserved2[2];
2041 	__le32	addr_high;
2042 	__le32	addr_low;
2043 };
2044 
2045 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2046 
2047 /* Configure LLDP MIB Change Event (direct 0x0A01)
2048  * also used for the event (with type in the command field)
2049  */
2050 struct i40e_aqc_lldp_update_mib {
2051 	u8	command;
2052 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE	0x1
2053 	u8	reserved[7];
2054 	__le32	addr_high;
2055 	__le32	addr_low;
2056 };
2057 
2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2059 
2060 /* Add LLDP TLV (indirect 0x0A02)
2061  * Delete LLDP TLV (indirect 0x0A04)
2062  */
2063 struct i40e_aqc_lldp_add_tlv {
2064 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2065 	u8	reserved1[1];
2066 	__le16	len;
2067 	u8	reserved2[4];
2068 	__le32	addr_high;
2069 	__le32	addr_low;
2070 };
2071 
2072 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2073 
2074 /* Update LLDP TLV (indirect 0x0A03) */
2075 struct i40e_aqc_lldp_update_tlv {
2076 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2077 	u8	reserved;
2078 	__le16	old_len;
2079 	__le16	new_offset;
2080 	__le16	new_len;
2081 	__le32	addr_high;
2082 	__le32	addr_low;
2083 };
2084 
2085 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2086 
2087 /* Stop LLDP (direct 0x0A05) */
2088 struct i40e_aqc_lldp_stop {
2089 	u8	command;
2090 #define I40E_AQ_LLDP_AGENT_SHUTDOWN		0x1
2091 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST		0x2
2092 	u8	reserved[15];
2093 };
2094 
2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2096 
2097 /* Start LLDP (direct 0x0A06) */
2098 struct i40e_aqc_lldp_start {
2099 	u8	command;
2100 #define I40E_AQ_LLDP_AGENT_START		0x1
2101 #define I40E_AQ_LLDP_AGENT_START_PERSIST	0x2
2102 	u8	reserved[15];
2103 };
2104 
2105 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2106 
2107 /* Set DCB (direct 0x0303) */
2108 struct i40e_aqc_set_dcb_parameters {
2109 	u8 command;
2110 #define I40E_AQ_DCB_SET_AGENT	0x1
2111 #define I40E_DCB_VALID		0x1
2112 	u8 valid_flags;
2113 	u8 reserved[14];
2114 };
2115 
2116 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2117 
2118 /* Get CEE DCBX Oper Config (0x0A07)
2119  * uses the generic descriptor struct
2120  * returns below as indirect response
2121  */
2122 
2123 #define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2124 #define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2125 #define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2126 #define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2127 #define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2128 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2129 
2130 #define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2131 #define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2132 #define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2133 #define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2134 #define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2135 #define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2136 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT	0x8
2137 #define I40E_AQC_CEE_FCOE_STATUS_MASK	(0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2138 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT	0xB
2139 #define I40E_AQC_CEE_ISCSI_STATUS_MASK	(0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2140 #define I40E_AQC_CEE_FIP_STATUS_SHIFT	0x10
2141 #define I40E_AQC_CEE_FIP_STATUS_MASK	(0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2142 
2143 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2144  * word boundary layout issues, which the Linux compilers silently deal
2145  * with by adding padding, making the actual struct larger than designed.
2146  * However, the FW compiler for the NIC is less lenient and complains
2147  * about the struct.  Hence, the struct defined here has an extra byte in
2148  * fields reserved3 and reserved4 to directly acknowledge that padding,
2149  * and the new length is used in the length check macro.
2150  */
2151 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2152 	u8	reserved1;
2153 	u8	oper_num_tc;
2154 	u8	oper_prio_tc[4];
2155 	u8	reserved2;
2156 	u8	oper_tc_bw[8];
2157 	u8	oper_pfc_en;
2158 	u8	reserved3[2];
2159 	__le16	oper_app_prio;
2160 	u8	reserved4[2];
2161 	__le16	tlv_status;
2162 };
2163 
2164 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2165 
2166 struct i40e_aqc_get_cee_dcb_cfg_resp {
2167 	u8	oper_num_tc;
2168 	u8	oper_prio_tc[4];
2169 	u8	oper_tc_bw[8];
2170 	u8	oper_pfc_en;
2171 	__le16	oper_app_prio;
2172 #define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2173 #define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2174 #define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2175 #define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2176 #define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2177 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2178 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2179 	__le32	tlv_status;
2180 #define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2181 #define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2182 #define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2183 #define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2184 #define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2185 #define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2186 	u8	reserved[12];
2187 };
2188 
2189 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2190 
2191 /*	Set Local LLDP MIB (indirect 0x0A08)
2192  *	Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2193  */
2194 struct i40e_aqc_lldp_set_local_mib {
2195 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT	0
2196 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK	(1 << \
2197 					SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2198 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB	0x0
2199 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT	(1)
2200 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK	(1 << \
2201 				SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2202 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS		0x1
2203 	u8	type;
2204 	u8	reserved0;
2205 	__le16	length;
2206 	u8	reserved1[4];
2207 	__le32	address_high;
2208 	__le32	address_low;
2209 };
2210 
2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2212 
2213 /*	Stop/Start LLDP Agent (direct 0x0A09)
2214  *	Used for stopping/starting specific LLDP agent. e.g. DCBx
2215  */
2216 struct i40e_aqc_lldp_stop_start_specific_agent {
2217 	u8	command;
2218 	u8	reserved[15];
2219 };
2220 
2221 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2222 
2223 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2224 struct i40e_aqc_lldp_restore {
2225 	u8	command;
2226 #define I40E_AQ_LLDP_AGENT_RESTORE		0x1
2227 	u8	reserved[15];
2228 };
2229 
2230 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_restore);
2231 
2232 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2233 struct i40e_aqc_add_udp_tunnel {
2234 	__le16	udp_port;
2235 	u8	reserved0[3];
2236 	u8	protocol_type;
2237 #define I40E_AQC_TUNNEL_TYPE_VXLAN	0x00
2238 #define I40E_AQC_TUNNEL_TYPE_NGE	0x01
2239 	u8	reserved1[10];
2240 };
2241 
2242 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2243 
2244 struct i40e_aqc_add_udp_tunnel_completion {
2245 	__le16	udp_port;
2246 	u8	filter_entry_index;
2247 	u8	multiple_pfs;
2248 	u8	total_filters;
2249 	u8	reserved[11];
2250 };
2251 
2252 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2253 
2254 /* remove UDP Tunnel command (0x0B01) */
2255 struct i40e_aqc_remove_udp_tunnel {
2256 	u8	reserved[2];
2257 	u8	index; /* 0 to 15 */
2258 	u8	reserved2[13];
2259 };
2260 
2261 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2262 
2263 struct i40e_aqc_del_udp_tunnel_completion {
2264 	__le16	udp_port;
2265 	u8	index; /* 0 to 15 */
2266 	u8	multiple_pfs;
2267 	u8	total_filters_used;
2268 	u8	reserved1[11];
2269 };
2270 
2271 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2272 
2273 struct i40e_aqc_get_set_rss_key {
2274 #define I40E_AQC_SET_RSS_KEY_VSI_VALID		BIT(15)
2275 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT	0
2276 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK	(0x3FF << \
2277 					I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2278 	__le16	vsi_id;
2279 	u8	reserved[6];
2280 	__le32	addr_high;
2281 	__le32	addr_low;
2282 };
2283 
2284 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2285 
2286 struct i40e_aqc_get_set_rss_key_data {
2287 	u8 standard_rss_key[0x28];
2288 	u8 extended_hash_key[0xc];
2289 };
2290 
2291 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2292 
2293 struct  i40e_aqc_get_set_rss_lut {
2294 #define I40E_AQC_SET_RSS_LUT_VSI_VALID		BIT(15)
2295 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT	0
2296 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK	(0x3FF << \
2297 					I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2298 	__le16	vsi_id;
2299 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT	0
2300 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK	BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2301 
2302 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI	0
2303 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF	1
2304 	__le16	flags;
2305 	u8	reserved[4];
2306 	__le32	addr_high;
2307 	__le32	addr_low;
2308 };
2309 
2310 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2311 
2312 /* tunnel key structure 0x0B10 */
2313 
2314 struct i40e_aqc_tunnel_key_structure {
2315 	u8	key1_off;
2316 	u8	key2_off;
2317 	u8	key1_len;  /* 0 to 15 */
2318 	u8	key2_len;  /* 0 to 15 */
2319 	u8	flags;
2320 	u8	network_key_index;
2321 	u8	reserved[10];
2322 };
2323 
2324 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2325 
2326 /* OEM mode commands (direct 0xFE0x) */
2327 struct i40e_aqc_oem_param_change {
2328 	__le32	param_type;
2329 	__le32	param_value1;
2330 	__le16	param_value2;
2331 	u8	reserved[6];
2332 };
2333 
2334 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2335 
2336 struct i40e_aqc_oem_state_change {
2337 	__le32	state;
2338 	u8	reserved[12];
2339 };
2340 
2341 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2342 
2343 /* Initialize OCSD (0xFE02, direct) */
2344 struct i40e_aqc_opc_oem_ocsd_initialize {
2345 	u8 type_status;
2346 	u8 reserved1[3];
2347 	__le32 ocsd_memory_block_addr_high;
2348 	__le32 ocsd_memory_block_addr_low;
2349 	__le32 requested_update_interval;
2350 };
2351 
2352 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2353 
2354 /* Initialize OCBB  (0xFE03, direct) */
2355 struct i40e_aqc_opc_oem_ocbb_initialize {
2356 	u8 type_status;
2357 	u8 reserved1[3];
2358 	__le32 ocbb_memory_block_addr_high;
2359 	__le32 ocbb_memory_block_addr_low;
2360 	u8 reserved2[4];
2361 };
2362 
2363 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2364 
2365 /* debug commands */
2366 
2367 /* get device id (0xFF00) uses the generic structure */
2368 
2369 /* set test more (0xFF01, internal) */
2370 
2371 struct i40e_acq_set_test_mode {
2372 	u8	mode;
2373 	u8	reserved[3];
2374 	u8	command;
2375 	u8	reserved2[3];
2376 	__le32	address_high;
2377 	__le32	address_low;
2378 };
2379 
2380 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2381 
2382 /* Debug Read Register command (0xFF03)
2383  * Debug Write Register command (0xFF04)
2384  */
2385 struct i40e_aqc_debug_reg_read_write {
2386 	__le32 reserved;
2387 	__le32 address;
2388 	__le32 value_high;
2389 	__le32 value_low;
2390 };
2391 
2392 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2393 
2394 /* Scatter/gather Reg Read  (indirect 0xFF05)
2395  * Scatter/gather Reg Write (indirect 0xFF06)
2396  */
2397 
2398 /* i40e_aq_desc is used for the command */
2399 struct i40e_aqc_debug_reg_sg_element_data {
2400 	__le32 address;
2401 	__le32 value;
2402 };
2403 
2404 /* Debug Modify register (direct 0xFF07) */
2405 struct i40e_aqc_debug_modify_reg {
2406 	__le32 address;
2407 	__le32 value;
2408 	__le32 clear_mask;
2409 	__le32 set_mask;
2410 };
2411 
2412 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2413 
2414 /* dump internal data (0xFF08, indirect) */
2415 struct i40e_aqc_debug_dump_internals {
2416 	u8	cluster_id;
2417 	u8	table_id;
2418 	__le16	data_size;
2419 	__le32	idx;
2420 	__le32	address_high;
2421 	__le32	address_low;
2422 };
2423 
2424 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2425 
2426 struct i40e_aqc_debug_modify_internals {
2427 	u8	cluster_id;
2428 	u8	cluster_specific_params[7];
2429 	__le32	address_high;
2430 	__le32	address_low;
2431 };
2432 
2433 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2434 
2435 #endif /* _I40E_ADMINQ_CMD_H_ */
2436