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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrIntrinsicVL.gen.td1 def : Pat<(int_ve_vl_vld_vssl i64:$sy, i64:$sz, i32:$vl), (VLDrrl i64:$sy, i64:$sz, i32:$vl)>;
2 …Pat<(int_ve_vl_vld_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDrrl_v i64:$sy, i64:$sz, i32:…
3 def : Pat<(int_ve_vl_vld_vssl simm7:$I, i64:$sz, i32:$vl), (VLDirl (LO7 $I), i64:$sz, i32:$vl)>;
4 …t<(int_ve_vl_vld_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDirl_v (LO7 $I), i64:$sz, i32:…
5 def : Pat<(int_ve_vl_vldnc_vssl i64:$sy, i64:$sz, i32:$vl), (VLDNCrrl i64:$sy, i64:$sz, i32:$vl)>;
6 …<(int_ve_vl_vldnc_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCrrl_v i64:$sy, i64:$sz, i32…
7 def : Pat<(int_ve_vl_vldnc_vssl simm7:$I, i64:$sz, i32:$vl), (VLDNCirl (LO7 $I), i64:$sz, i32:$vl)>;
8 …int_ve_vl_vldnc_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCirl_v (LO7 $I), i64:$sz, i32…
9 def : Pat<(int_ve_vl_vldu_vssl i64:$sy, i64:$sz, i32:$vl), (VLDUrrl i64:$sy, i64:$sz, i32:$vl)>;
10 …t<(int_ve_vl_vldu_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDUrrl_v i64:$sy, i64:$sz, i32:…
[all …]
H A DVEInstrIntrinsicVL.td31 def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl),
32 (VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>;
33 def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm,
34 v256f64:$pt, i32:$vl),
35 (VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl,
39 def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl),
40 (VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>;
41 def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl),
42 (VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>;
43 def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt,
[all …]
H A DVVPInstrPatternsVec.td26 (i64 simm7:$stride), (MaskVT true_mask), i32:$avl),
32 i64:$stride, (MaskVT true_mask), i32:$avl),
38 (i64 simm7:$stride), MaskVT:$mask, i32:$avl),
44 i64:$stride, MaskVT:$mask, i32:$avl),
60 (MaskVT true_mask), i32:$avl)),
66 (MaskVT true_mask), i32:$avl)),
72 MaskVT:$mask, i32:$avl)),
82 PtrVT:$addr, i64:$stride, MaskVT:$mask, i32:$avl)),
103 PtrVT:$addr, (MaskVT true_mask), i32:$avl)),
106 def : Pat<(DataVT (vvp_gather PtrVT:$addr, MaskVT:$mask, i32:$avl)),
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsVEVL.gen.td1 …ultAttrsIntrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrReadMem]>;
2 …LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<v256f64>, LLVMType<i32>], [IntrReadMem]>;
3 …ultAttrsIntrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrReadMem]>;
4 …LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<v256f64>, LLVMType<i32>], [IntrReadMem]>;
5 …ultAttrsIntrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrReadMem]>;
6 …LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<v256f64>, LLVMType<i32>], [IntrReadMem]>;
7 …ultAttrsIntrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrReadMem]>;
8 …LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<v256f64>, LLVMType<i32>], [IntrReadMem]>;
9 …ultAttrsIntrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrReadMem]>;
10 …LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVMType<v256f64>, LLVMType<i32>], [IntrReadMem]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td33 def IMMZeroBasedBitfieldMask : ImmLeaf <i32, [{
39 MVT::i32);
65 (i32 imm:$rat_id))]>;
70 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)]
147 [(store_global i32:$rw_gpr, i32:$index_gpr)]
154 [(store_global v2i32:$rw_gpr, i32:$index_gpr)]
161 [(store_global v4i32:$rw_gpr, i32:$index_gpr)]
260 def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)),
262 def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)),
264 def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
[all …]
H A DSIInstructions.td51 (i32 timm:$attrchan), (i32 timm:$attr), M0))]
78 (i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
87 [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
88 (i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
115 [(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))],
238 [(set i1:$sdst, (int_amdgcn_inverse_ballot i32:$mask))]
251 (S_INVERSE_BALLOT_U32 (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)))
279 def : GCNPat <(f16 (fptrunc_round f32:$src0, (i32 SupportedRoundMode:$round))),
283 def : GCNPat <(f16 (fptrunc_round f32:$src0, (i32 SupportedRoundMode:$round))),
287 def : GCNPat <(f16 (fptrunc_round (f32 (VOP3OpSelMods f32:$src0, i32:$src0_modifiers)), (i32 Suppor…
[all …]
H A DVOP3Instructions.td9 def BITOP3_32 : ComplexPattern<i32, 4, "SelectBITOP3", [and, or, xor]>;
39 def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
72 def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
81 def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
276 (i32 (int_amdgcn_alignbyte (i32 (VOP3OpSelMods i32:$src0, i32:$src0_modifiers)),
277 (i32 (VOP3OpSelMods i32:$src1, i32:$src1_modifiers)),
278 (i32 (VOP3OpSelMods i32:$src2, i32:$src2_modifiers)))),
279 (V_ALIGNBYTE_B32_fake16_e64 i32:$src0_modifiers, VSrc_b32:$src0,
280 i32:$src1_modifiers, VSrc_b32:$src1,
281 i32:$src2_modifiers, VGPR_32:$src2)
[all …]
H A DAMDGPUCallingConv.td25 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
29 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
33 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>>
37 CCIfType<[i1], CCPromoteToType<i32>>,
38 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
40 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
47 CCIfType<[i1], CCPromoteToType<i32>>,
49 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
54 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16, bf16, v2bf16] , CCAssignToReg<
60 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
[all …]
H A DR600Instructions.td41 : OperandWithDefaultOps <i32, (ops (i32 Default))> {
46 def SEL : OperandWithDefaultOps <i32, (ops (i32 -1))>;
47 def BANK_SWIZZLE : OperandWithDefaultOps <i32, (ops (i32 0))> {
66 def RSel : Operand<i32> {
69 def CT: Operand<i32> {
77 def ADDRVTX_READ : ComplexPattern<i32, 2, "SelectADDRVTX_READ", [], []>;
78 def ADDRGA_CONST_OFFSET : ComplexPattern<i32,
[all...]
/freebsd/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
H A Dtst.signedkeyspos.d82 @i32["mouse", -2] = sum(-2);
83 @i32["bear", -2] = sum(-22);
84 @i32["cat", -2] = sum(-222);
85 @i32["mouse", -1] = sum(-1);
86 @i32["bear", -1] = sum(-11);
87 @i32["cat", -1] = sum(-111);
88 @i32["mouse", 0] = sum(0);
89 @i32["bear", 0] = sum(10);
90 @i32["cat", 0] = sum(100);
91 @i32["mouse", 1] = sum(1);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaOperators.td12 def SDT_XtensaCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
13 def SDT_XtensaCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
21 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
26 SDTCisVT<5, i32>]>;
32 SDTCisVT<5, i32>, SDTCisVT<6, i32>]>;
34 def SDT_XtensaSRC : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
35 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
37 def SDT_XtensaEXTUI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
38 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
40 def SDT_XtensaMOVSP : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
[all …]
H A DXtensaISelLowering.cpp57 MVT PtrVT = MVT::i32; in XtensaTargetLowering()
59 addRegisterClass(MVT::i32, &Xtensa::ARRegClass); in XtensaTargetLowering()
76 setOperationAction(ISD::Constant, MVT::i32, Custom); in XtensaTargetLowering()
87 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in XtensaTargetLowering()
89 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
90 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in XtensaTargetLowering()
91 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in XtensaTargetLowering()
92 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in XtensaTargetLowering()
112 setOperationAction(ISD::BR_CC, MVT::i32, Legal); in XtensaTargetLowering()
115 setOperationAction(ISD::SELECT, MVT::i32, Expand); in XtensaTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64r6InstrInfo.td213 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
217 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
221 def : MipsPat<(select (i32 (seteq i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
225 def : MipsPat<(select (i32 (setne i64:$cond, immZExt16_64:$imm)), i64:$t, i64:$f),
230 (select (i32 (setgt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
239 (select (i32 (setugt i64:$cond, immSExt16Plus1:$imm)), i64:$t, i64:$f),
248 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, immz),
250 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, immz),
252 def : MipsPat<(select (i32 (setne i64:$cond, immz)), immz, i64:$f),
254 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), immz, i64:$f),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrAtomics.td81 Pat<(i32 (int_wasm_memory_atomic_notify (AddrOps32 offset32_op:$offset, I32:$addr), I32:$count)),
85 Pat<(i32 (int_wasm_memory_atomic_notify (AddrOps64 offset64_op:$offset, I64:$addr), I32:$count)),
92 Pat<(i32 (kind (AddrOps32 offset32_op:$offset, I32:$addr), ty:$exp, I64:$timeout)),
96 Pat<(i32 (kind (AddrOps64 offset64_op:$offset, I64:$addr), ty:$exp, I64:$timeout)),
101 defm : WaitPat<i32, int_wasm_memory_atomic_wait32, "MEMORY_ATOMIC_WAIT32">;
126 defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
130 defm : LoadPat<i32, atomic_load_nonext_32, "ATOMIC_LOAD_I32">;
135 defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
136 defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
146 // Unlike regular loads, extension to i64 is handled differently than i32.
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp48 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
62 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
63 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
68 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
69 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
70 setOperationAction(ISD::MULHS, MVT::i32, Expand); in XCoreTargetLowering()
71 setOperationAction(ISD::MULHU, MVT::i32, Expand); in XCoreTargetLowering()
72 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in XCoreTargetLowering()
73 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in XCoreTargetLowering()
74 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in XCoreTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepOperands.td11 multiclass ImmOpPred<code pred, ValueType vt = i32> {
17 def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDec…
20 def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0Imm…
23 def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsigned…
26 def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsigned…
29 def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsigned…
38 def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtarget…
44 def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1Imm…
47 def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2Imm…
50 def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3Imm…
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp86 DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0)); in ReplaceNodeResults()
101 addRegisterClass(MVT::i32, &ARC::GPR32RegClass); in ARCTargetLowering()
115 setOperationAction(Opc, MVT::i32, Expand); in ARCTargetLowering()
119 setOperationAction(ISD::ADD, MVT::i32, Legal); in ARCTargetLowering()
120 setOperationAction(ISD::SUB, MVT::i32, Legal); in ARCTargetLowering()
121 setOperationAction(ISD::AND, MVT::i32, Legal); in ARCTargetLowering()
122 setOperationAction(ISD::SMAX, MVT::i32, Legal); in ARCTargetLowering()
123 setOperationAction(ISD::SMIN, MVT::i32, Legal); in ARCTargetLowering()
125 setOperationAction(ISD::ADDC, MVT::i32, Legal); in ARCTargetLowering()
126 setOperationAction(ISD::ADDE, MVT::i32, Legal); in ARCTargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp75 addRegisterClass(MVT::i32, &Lanai::GPRRegClass); in LanaiTargetLowering()
83 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in LanaiTargetLowering()
86 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
87 setOperationAction(ISD::SELECT, MVT::i32, Expand); in LanaiTargetLowering()
88 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in LanaiTargetLowering()
90 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in LanaiTargetLowering()
91 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in LanaiTargetLowering()
92 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in LanaiTargetLowering()
93 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in LanaiTargetLowering()
95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in LanaiTargetLowering()
[all …]
H A DLanaiInstrInfo.td24 def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
25 SDTCisVT<1, i32>]>;
26 def SDT_LanaiCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
27 SDTCisVT<1, i32>]>;
28 def SDT_LanaiCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
32 def SDT_LanaiSetCC : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
33 SDTCisVT<1, i32>]>;
35 SDTCisVT<1, i32>]>;
36 def SDT_LanaiAdjDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
37 SDTCisVT<1, i32>]>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td39 def CvtNONE : PatLeaf<(i32 0x0)>;
40 def CvtRNI : PatLeaf<(i32 0x1)>;
41 def CvtRZI : PatLeaf<(i32 0x2)>;
42 def CvtRMI : PatLeaf<(i32 0x3)>;
43 def CvtRPI : PatLeaf<(i32 0x4)>;
44 def CvtRN : PatLeaf<(i32 0x5)>;
45 def CvtRZ : PatLeaf<(i32 0x6)>;
46 def CvtRM : PatLeaf<(i32 0x7)>;
47 def CvtRP : PatLeaf<(i32 0x8)>;
48 def CvtRNA : PatLeaf<(i32 0x9)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td617 [(set i32:$CR, (PPCftsqrt f64:$XB))]>;
628 [(set i32:$CR, (PPCftsqrt v2f64:$XB))]>;
632 [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>;
1305 [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64;
1323 [(set f64:$XT, (PPCmtvsra i32:$RA))]>;
1331 [(set f64:$XT, (PPCmtvsrz i32:$RA))]>;
1812 // Output dag used to bitcast f32 to i32 and f64 to i64
1814 dag FltToInt = (i32 (MFVSRWZ (EXTRACT_SUBREG (XSCVDPSPN $A), sub_64)));
1828 dag Li8 = (i32 (extloadi8 ForceXForm:$src));
1829 dag ZELi8 = (i32 (zextloadi8 ForceXForm:$src));
[all …]
H A DPPCInstrHTM.td97 def : Pat<(int_ppc_tbegin i32:$R),
100 def : Pat<(int_ppc_tend i32:$R),
103 def : Pat<(int_ppc_tabort i32:$R),
106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_treclaim i32:$RA),
127 def : Pat<(int_ppc_tsr i32:$L),
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZOperators.td18 [SDTCisVT<0, i32>,
21 [SDTCisVT<0, i32>,
23 SDTCisVT<3, i32>]>;
25 [SDTCisVT<0, i32>,
26 SDTCisVT<1, i32>,
28 SDTCisVT<3, i32>]>;
32 SDTCisVT<3, i32>,
33 SDTCisVT<4, i32>,
34 SDTCisVT<5, i32>]>;
53 SDTCisVT<1, i32>,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td13 def regseq_f2 : Operand<i32> {
21 def regseq_d2 : Operand<i32> {
250 def : Pat<(i32 (fp_to_sint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
251 def : Pat<(i32 (fp_to_uint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
252 def : Pat<(i32 (fp_to_sint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
253 def : Pat<(i32 (fp_to_uint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
254 def : Pat<(i32 (fp_to_sint (ffloor FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
255 def : Pat<(i32 (fp_to_uint (ffloor FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
256 def : Pat<(i32 (fp_to_sint (ftrunc FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
257 def : Pat<(i32 (fp_to_uin
[all...]
/freebsd/sys/i386/i386/
H A Dbpf_jit_machdep.h109 #define MOVid(i32, r32) do { \ argument
111 emitm(&stream, i32, 4); \
196 #define ADD_EAXi(i32) do { \ argument
198 emitm(&stream, i32, 4); \
216 #define SUB_EAXi(i32) do { \ argument
218 emitm(&stream, i32, 4); \
252 #define ANDid(i32, r32) do { \ argument
259 emitm(&stream, i32, 4); \
270 #define TESTid(i32, r32) do { \ argument
277 emitm(&stream, i32, 4); \
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