1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include "pp_debug.h"
25 #include <linux/delay.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29 #include <linux/pci.h>
30 #include <drm/amdgpu_drm.h>
31 #include "power_state.h"
32 #include "hwmgr.h"
33 #include "ppsmc.h"
34 #include "amd_acpi.h"
35 #include "pp_psm.h"
36 #include "vega10_hwmgr.h"
37
38 extern const struct pp_smumgr_func ci_smu_funcs;
39 extern const struct pp_smumgr_func smu8_smu_funcs;
40 extern const struct pp_smumgr_func iceland_smu_funcs;
41 extern const struct pp_smumgr_func tonga_smu_funcs;
42 extern const struct pp_smumgr_func fiji_smu_funcs;
43 extern const struct pp_smumgr_func polaris10_smu_funcs;
44 extern const struct pp_smumgr_func vegam_smu_funcs;
45 extern const struct pp_smumgr_func vega10_smu_funcs;
46 extern const struct pp_smumgr_func vega12_smu_funcs;
47 extern const struct pp_smumgr_func smu10_smu_funcs;
48 extern const struct pp_smumgr_func vega20_smu_funcs;
49
50 extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
51
52 static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
53 static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
54 static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
55 static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
56 static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
57 static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
58 static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
59
60
hwmgr_init_workload_prority(struct pp_hwmgr * hwmgr)61 static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
62 {
63 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
64 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
65 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
66 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
67 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
68 hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
69
70 hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
71 hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
72 hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
73 hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
74 hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
75 hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
76 }
77
hwmgr_early_init(struct pp_hwmgr * hwmgr)78 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
79 {
80 struct amdgpu_device *adev;
81
82 if (!hwmgr)
83 return -EINVAL;
84
85 hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
86 hwmgr->pp_table_version = PP_TABLE_V1;
87 hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
88 hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
89 hwmgr_init_default_caps(hwmgr);
90 hwmgr_set_user_specify_caps(hwmgr);
91 hwmgr->fan_ctrl_is_in_default_mode = true;
92 hwmgr_init_workload_prority(hwmgr);
93 hwmgr->gfxoff_state_changed_by_workload = false;
94
95 adev = hwmgr->adev;
96
97 switch (hwmgr->chip_family) {
98 case AMDGPU_FAMILY_CI:
99 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
100 hwmgr->smumgr_funcs = &ci_smu_funcs;
101 ci_set_asic_special_caps(hwmgr);
102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
103 PP_ENABLE_GFX_CG_THRU_SMU |
104 PP_GFXOFF_MASK);
105 hwmgr->pp_table_version = PP_TABLE_V0;
106 hwmgr->od_enabled = false;
107 switch (hwmgr->chip_id) {
108 case CHIP_BONAIRE:
109 /* R9 M380 in iMac 2015: SMU hangs when enabling MCLK DPM */
110 if (adev->pdev->subsystem_vendor == 0x106B) {
111 dev_info(adev->dev, "disabling MCLK DPM on quirky ASIC");
112 adev->pm.pp_feature &= ~PP_MCLK_DPM_MASK;
113 hwmgr->feature_mask &= ~PP_MCLK_DPM_MASK;
114 }
115 break;
116 default:
117 break;
118 }
119 smu7_init_function_pointers(hwmgr);
120 break;
121 case AMDGPU_FAMILY_CZ:
122 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
123 hwmgr->od_enabled = false;
124 hwmgr->smumgr_funcs = &smu8_smu_funcs;
125 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
126 smu8_init_function_pointers(hwmgr);
127 break;
128 case AMDGPU_FAMILY_VI:
129 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
130 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
131 switch (hwmgr->chip_id) {
132 case CHIP_TOPAZ:
133 hwmgr->smumgr_funcs = &iceland_smu_funcs;
134 topaz_set_asic_special_caps(hwmgr);
135 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
136 PP_ENABLE_GFX_CG_THRU_SMU);
137 hwmgr->pp_table_version = PP_TABLE_V0;
138 hwmgr->od_enabled = false;
139 break;
140 case CHIP_TONGA:
141 hwmgr->smumgr_funcs = &tonga_smu_funcs;
142 tonga_set_asic_special_caps(hwmgr);
143 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
144 break;
145 case CHIP_FIJI:
146 hwmgr->smumgr_funcs = &fiji_smu_funcs;
147 fiji_set_asic_special_caps(hwmgr);
148 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
149 PP_ENABLE_GFX_CG_THRU_SMU);
150 break;
151 case CHIP_POLARIS11:
152 case CHIP_POLARIS10:
153 case CHIP_POLARIS12:
154 hwmgr->smumgr_funcs = &polaris10_smu_funcs;
155 polaris_set_asic_special_caps(hwmgr);
156 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
157 break;
158 case CHIP_VEGAM:
159 hwmgr->smumgr_funcs = &vegam_smu_funcs;
160 polaris_set_asic_special_caps(hwmgr);
161 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
162 break;
163 default:
164 return -EINVAL;
165 }
166 smu7_init_function_pointers(hwmgr);
167 break;
168 case AMDGPU_FAMILY_AI:
169 switch (hwmgr->chip_id) {
170 case CHIP_VEGA10:
171 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
172 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
173 hwmgr->smumgr_funcs = &vega10_smu_funcs;
174 vega10_hwmgr_init(hwmgr);
175 break;
176 case CHIP_VEGA12:
177 hwmgr->smumgr_funcs = &vega12_smu_funcs;
178 vega12_hwmgr_init(hwmgr);
179 break;
180 case CHIP_VEGA20:
181 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
182 hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
183 hwmgr->smumgr_funcs = &vega20_smu_funcs;
184 vega20_hwmgr_init(hwmgr);
185 break;
186 default:
187 return -EINVAL;
188 }
189 break;
190 case AMDGPU_FAMILY_RV:
191 switch (hwmgr->chip_id) {
192 case CHIP_RAVEN:
193 hwmgr->od_enabled = false;
194 hwmgr->smumgr_funcs = &smu10_smu_funcs;
195 smu10_init_function_pointers(hwmgr);
196 break;
197 default:
198 return -EINVAL;
199 }
200 break;
201 default:
202 return -EINVAL;
203 }
204
205 return 0;
206 }
207
hwmgr_sw_init(struct pp_hwmgr * hwmgr)208 int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
209 {
210 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
211 return -EINVAL;
212
213 phm_register_irq_handlers(hwmgr);
214 pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name);
215
216 return hwmgr->smumgr_funcs->smu_init(hwmgr);
217 }
218
219
hwmgr_sw_fini(struct pp_hwmgr * hwmgr)220 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
221 {
222 if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
223 hwmgr->smumgr_funcs->smu_fini(hwmgr);
224
225 return 0;
226 }
227
hwmgr_hw_init(struct pp_hwmgr * hwmgr)228 int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
229 {
230 int ret = 0;
231
232 hwmgr->pp_one_vf = amdgpu_sriov_is_pp_one_vf((struct amdgpu_device *)hwmgr->adev);
233 hwmgr->pm_en = (amdgpu_dpm && (hwmgr->not_vf || hwmgr->pp_one_vf))
234 ? true : false;
235 if (!hwmgr->pm_en)
236 return 0;
237
238 if (!hwmgr->pptable_func ||
239 !hwmgr->pptable_func->pptable_init ||
240 !hwmgr->hwmgr_func->backend_init) {
241 hwmgr->pm_en = false;
242 pr_info("dpm not supported \n");
243 return 0;
244 }
245
246 ret = hwmgr->pptable_func->pptable_init(hwmgr);
247 if (ret)
248 goto err;
249
250 ((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
251 hwmgr->thermal_controller.fanInfo.bNoFan;
252
253 ret = hwmgr->hwmgr_func->backend_init(hwmgr);
254 if (ret)
255 goto err1;
256 /* make sure dc limits are valid */
257 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
258 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
259 hwmgr->dyn_state.max_clock_voltage_on_dc =
260 hwmgr->dyn_state.max_clock_voltage_on_ac;
261
262 ret = psm_init_power_state_table(hwmgr);
263 if (ret)
264 goto err2;
265
266 ret = phm_setup_asic(hwmgr);
267 if (ret)
268 goto err2;
269
270 ret = phm_enable_dynamic_state_management(hwmgr);
271 if (ret)
272 goto err2;
273 ret = phm_start_thermal_controller(hwmgr);
274 ret |= psm_set_performance_states(hwmgr);
275 if (ret)
276 goto err2;
277
278 ((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
279
280 return 0;
281 err2:
282 if (hwmgr->hwmgr_func->backend_fini)
283 hwmgr->hwmgr_func->backend_fini(hwmgr);
284 err1:
285 if (hwmgr->pptable_func->pptable_fini)
286 hwmgr->pptable_func->pptable_fini(hwmgr);
287 err:
288 return ret;
289 }
290
hwmgr_hw_fini(struct pp_hwmgr * hwmgr)291 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
292 {
293 if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
294 return 0;
295
296 phm_stop_thermal_controller(hwmgr);
297 psm_set_boot_states(hwmgr);
298 psm_adjust_power_state_dynamic(hwmgr, true, NULL);
299 phm_disable_dynamic_state_management(hwmgr);
300 phm_disable_clock_power_gatings(hwmgr);
301
302 if (hwmgr->hwmgr_func->backend_fini)
303 hwmgr->hwmgr_func->backend_fini(hwmgr);
304 if (hwmgr->pptable_func->pptable_fini)
305 hwmgr->pptable_func->pptable_fini(hwmgr);
306 return psm_fini_power_state_table(hwmgr);
307 }
308
hwmgr_suspend(struct pp_hwmgr * hwmgr)309 int hwmgr_suspend(struct pp_hwmgr *hwmgr)
310 {
311 int ret = 0;
312
313 if (!hwmgr || !hwmgr->pm_en || !hwmgr->not_vf)
314 return 0;
315
316 phm_disable_smc_firmware_ctf(hwmgr);
317 ret = psm_set_boot_states(hwmgr);
318 if (ret)
319 return ret;
320 ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
321 if (ret)
322 return ret;
323 ret = phm_power_down_asic(hwmgr);
324
325 return ret;
326 }
327
hwmgr_resume(struct pp_hwmgr * hwmgr)328 int hwmgr_resume(struct pp_hwmgr *hwmgr)
329 {
330 int ret = 0;
331
332 if (!hwmgr)
333 return -EINVAL;
334
335 if (!hwmgr->not_vf || !hwmgr->pm_en)
336 return 0;
337
338 ret = phm_setup_asic(hwmgr);
339 if (ret)
340 return ret;
341
342 ret = phm_enable_dynamic_state_management(hwmgr);
343 if (ret)
344 return ret;
345 ret = phm_start_thermal_controller(hwmgr);
346 ret |= psm_set_performance_states(hwmgr);
347 if (ret)
348 return ret;
349
350 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
351
352 return ret;
353 }
354
power_state_convert(enum amd_pm_state_type state)355 static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state)
356 {
357 switch (state) {
358 case POWER_STATE_TYPE_BATTERY:
359 return PP_StateUILabel_Battery;
360 case POWER_STATE_TYPE_BALANCED:
361 return PP_StateUILabel_Balanced;
362 case POWER_STATE_TYPE_PERFORMANCE:
363 return PP_StateUILabel_Performance;
364 default:
365 return PP_StateUILabel_None;
366 }
367 }
368
hwmgr_handle_task(struct pp_hwmgr * hwmgr,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)369 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
370 enum amd_pm_state_type *user_state)
371 {
372 int ret = 0;
373
374 if (hwmgr == NULL)
375 return -EINVAL;
376
377 switch (task_id) {
378 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
379 if (!hwmgr->not_vf)
380 return ret;
381 ret = phm_pre_display_configuration_changed(hwmgr);
382 if (ret)
383 return ret;
384 ret = phm_set_cpu_power_state(hwmgr);
385 if (ret)
386 return ret;
387 ret = psm_set_performance_states(hwmgr);
388 if (ret)
389 return ret;
390 ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
391 break;
392 case AMD_PP_TASK_ENABLE_USER_STATE:
393 {
394 enum PP_StateUILabel requested_ui_label;
395 struct pp_power_state *requested_ps = NULL;
396
397 if (!hwmgr->not_vf)
398 return ret;
399 if (user_state == NULL) {
400 ret = -EINVAL;
401 break;
402 }
403
404 requested_ui_label = power_state_convert(*user_state);
405 ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
406 if (ret)
407 return ret;
408 ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);
409 break;
410 }
411 case AMD_PP_TASK_COMPLETE_INIT:
412 case AMD_PP_TASK_READJUST_POWER_STATE:
413 ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
414 break;
415 default:
416 break;
417 }
418 return ret;
419 }
420
hwmgr_init_default_caps(struct pp_hwmgr * hwmgr)421 void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
422 {
423 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
424
425 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
426 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
427
428 #if defined(CONFIG_ACPI)
429 if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
430 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
431 #endif
432
433 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
434 PHM_PlatformCaps_DynamicPatchPowerState);
435
436 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
437 PHM_PlatformCaps_EnableSMU7ThermalManagement);
438
439 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
440 PHM_PlatformCaps_DynamicPowerManagement);
441
442 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
443 PHM_PlatformCaps_SMC);
444
445 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
446 PHM_PlatformCaps_DynamicUVDState);
447
448 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
449 PHM_PlatformCaps_FanSpeedInTableIsRPM);
450 return;
451 }
452
hwmgr_set_user_specify_caps(struct pp_hwmgr * hwmgr)453 int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
454 {
455 if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
456 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
457 PHM_PlatformCaps_SclkDeepSleep);
458 else
459 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
460 PHM_PlatformCaps_SclkDeepSleep);
461
462 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
463 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
464 PHM_PlatformCaps_PowerContainment);
465 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
466 PHM_PlatformCaps_CAC);
467 } else {
468 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
469 PHM_PlatformCaps_PowerContainment);
470 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
471 PHM_PlatformCaps_CAC);
472 }
473
474 if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
475 hwmgr->od_enabled = true;
476
477 return 0;
478 }
479
polaris_set_asic_special_caps(struct pp_hwmgr * hwmgr)480 int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
481 {
482 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
483 PHM_PlatformCaps_EVV);
484 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
485 PHM_PlatformCaps_SQRamping);
486 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
487 PHM_PlatformCaps_RegulatorHot);
488
489 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
490 PHM_PlatformCaps_MemorySpreadSpectrumSupport);
491 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
492 PHM_PlatformCaps_EngineSpreadSpectrumSupport);
493
494 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
495 PHM_PlatformCaps_AutomaticDCTransition);
496
497 if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
498 (hwmgr->chip_id == CHIP_POLARIS12))
499 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
500 PHM_PlatformCaps_SPLLShutdownSupport);
501
502 if (hwmgr->chip_id != CHIP_POLARIS11) {
503 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
504 PHM_PlatformCaps_DBRamping);
505 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
506 PHM_PlatformCaps_TDRamping);
507 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
508 PHM_PlatformCaps_TCPRamping);
509 }
510 return 0;
511 }
512
fiji_set_asic_special_caps(struct pp_hwmgr * hwmgr)513 int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
514 {
515 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
516 PHM_PlatformCaps_EVV);
517 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
518 PHM_PlatformCaps_SQRamping);
519 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
520 PHM_PlatformCaps_DBRamping);
521 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
522 PHM_PlatformCaps_TDRamping);
523 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
524 PHM_PlatformCaps_TCPRamping);
525 return 0;
526 }
527
tonga_set_asic_special_caps(struct pp_hwmgr * hwmgr)528 int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
529 {
530 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
531 PHM_PlatformCaps_EVV);
532 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
533 PHM_PlatformCaps_SQRamping);
534 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
535 PHM_PlatformCaps_DBRamping);
536 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
537 PHM_PlatformCaps_TDRamping);
538 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
539 PHM_PlatformCaps_TCPRamping);
540
541 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
542 PHM_PlatformCaps_UVDPowerGating);
543 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
544 PHM_PlatformCaps_VCEPowerGating);
545 return 0;
546 }
547
topaz_set_asic_special_caps(struct pp_hwmgr * hwmgr)548 int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
549 {
550 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
551 PHM_PlatformCaps_EVV);
552 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
553 PHM_PlatformCaps_SQRamping);
554 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
555 PHM_PlatformCaps_DBRamping);
556 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
557 PHM_PlatformCaps_TDRamping);
558 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
559 PHM_PlatformCaps_TCPRamping);
560 return 0;
561 }
562
ci_set_asic_special_caps(struct pp_hwmgr * hwmgr)563 int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
564 {
565 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
566 PHM_PlatformCaps_SQRamping);
567 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
568 PHM_PlatformCaps_DBRamping);
569 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
570 PHM_PlatformCaps_TDRamping);
571 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
572 PHM_PlatformCaps_TCPRamping);
573 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
574 PHM_PlatformCaps_MemorySpreadSpectrumSupport);
575 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
576 PHM_PlatformCaps_EngineSpreadSpectrumSupport);
577 return 0;
578 }
579