Home
last modified time | relevance | path

Searched refs:hwmgr (Results 1 – 25 of 64) sorted by relevance

123

/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmumgr.c57 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr) in smum_thermal_avfs_enable() argument
59 if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable) in smum_thermal_avfs_enable()
60 return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr); in smum_thermal_avfs_enable()
65 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) in smum_thermal_setup_fan_table() argument
67 if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table) in smum_thermal_setup_fan_table()
68 return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr); in smum_thermal_setup_fan_table()
73 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr) in smum_update_sclk_threshold() argument
76 if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold) in smum_update_sclk_threshold()
77 return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr); in smum_update_sclk_threshold()
82 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) in smum_update_smc_table() argument
[all …]
H A Dsmu8_smumgr.c56 static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr) in smu8_get_argument() argument
58 if (hwmgr == NULL || hwmgr->device == NULL) in smu8_get_argument()
61 return cgs_read_register(hwmgr->device, in smu8_get_argument()
66 static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, in smu8_send_msg_to_smc_with_parameter() argument
73 if (hwmgr == NULL || hwmgr->device == NULL) in smu8_send_msg_to_smc_with_parameter()
76 result = PHM_WAIT_FIELD_UNEQUAL(hwmgr, in smu8_send_msg_to_smc_with_parameter()
80 uint32_t val = cgs_read_register(hwmgr->device, in smu8_send_msg_to_smc_with_parameter()
88 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter); in smu8_send_msg_to_smc_with_parameter()
90 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0); in smu8_send_msg_to_smc_with_parameter()
91 cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg); in smu8_send_msg_to_smc_with_parameter()
[all …]
H A Dsmu7_smumgr.c38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) in smu7_set_smc_sram_address() argument
43 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr); in smu7_set_smc_sram_address()
44 …PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_A… in smu7_set_smc_sram_address()
49 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in smu7_copy_bytes_to_smc() argument
67 result = smu7_set_smc_sram_address(hwmgr, addr, limit); in smu7_copy_bytes_to_smc()
72 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data); in smu7_copy_bytes_to_smc()
83 result = smu7_set_smc_sram_address(hwmgr, addr, limit); in smu7_copy_bytes_to_smc()
89 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11); in smu7_copy_bytes_to_smc()
103 result = smu7_set_smc_sram_address(hwmgr, addr, limit); in smu7_copy_bytes_to_smc()
108 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data); in smu7_copy_bytes_to_smc()
[all …]
H A Dci_smumgr.c94 static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr, in ci_set_smc_sram_address() argument
103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
108 static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, in ci_copy_bytes_to_smc() argument
129 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
145 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
165 result = ci_set_smc_sram_address(hwmgr, addr, limit); in ci_copy_bytes_to_smc()
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
[all …]
H A Diceland_smumgr.c109 static int iceland_start_smc(struct pp_hwmgr *hwmgr) in iceland_start_smc() argument
111 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_start_smc()
117 static void iceland_reset_smc(struct pp_hwmgr *hwmgr) in iceland_reset_smc() argument
119 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_reset_smc()
125 static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr) in iceland_stop_smc_clock() argument
127 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_stop_smc_clock()
132 static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr) in iceland_start_smc_clock() argument
134 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in iceland_start_smc_clock()
139 static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr) in iceland_smu_start_smc() argument
142 smu7_program_jump_on_start(hwmgr); in iceland_smu_start_smc()
[all …]
H A Dpolaris10_smumgr.c96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) in polaris10_perform_btc() argument
99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); in polaris10_perform_btc()
102 …if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, in polaris10_perform_btc()
111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); in polaris10_perform_btc()
113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); in polaris10_perform_btc()
114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); in polaris10_perform_btc()
120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) in polaris10_setup_graphics_level_structure() argument
131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, in polaris10_setup_graphics_level_structure()
142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, in polaris10_setup_graphics_level_structure()
149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, in polaris10_setup_graphics_level_structure()
[all …]
H A Dfiji_smumgr.c99 static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) in fiji_start_smu_in_protection_mode() argument
107 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
110 result = smu7_upload_smu_firmware_image(hwmgr); in fiji_start_smu_in_protection_mode()
115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
130 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
134 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in fiji_start_smu_in_protection_mode()
137 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, in fiji_start_smu_in_protection_mode()
140 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000, NULL); in fiji_start_smu_in_protection_mode()
[all …]
H A Dsmu9_smumgr.c39 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr) in smu9_is_smc_ram_running() argument
41 struct amdgpu_device *adev = hwmgr->adev; in smu9_is_smc_ram_running()
59 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr) in smu9_wait_for_response() argument
61 struct amdgpu_device *adev = hwmgr->adev; in smu9_wait_for_response()
65 if (hwmgr->pp_one_vf) { in smu9_wait_for_response()
68 ret = phm_wait_for_register_unequal(hwmgr, reg, in smu9_wait_for_response()
78 ret = phm_wait_for_register_unequal(hwmgr, reg, in smu9_wait_for_response()
93 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, in smu9_send_msg_to_smc_without_waiting() argument
96 struct amdgpu_device *adev = hwmgr->adev; in smu9_send_msg_to_smc_without_waiting()
98 if (hwmgr->pp_one_vf) { in smu9_send_msg_to_smc_without_waiting()
[all …]
H A Dsmu10_smumgr.c49 static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr) in smu10_wait_for_response() argument
51 struct amdgpu_device *adev = hwmgr->adev; in smu10_wait_for_response()
56 phm_wait_for_register_unequal(hwmgr, reg, in smu10_wait_for_response()
62 static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, in smu10_send_msg_to_smc_without_waiting() argument
65 struct amdgpu_device *adev = hwmgr->adev; in smu10_send_msg_to_smc_without_waiting()
72 static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr) in smu10_read_arg_from_smc() argument
74 struct amdgpu_device *adev = hwmgr->adev; in smu10_read_arg_from_smc()
79 static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) in smu10_send_msg_to_smc() argument
81 struct amdgpu_device *adev = hwmgr->adev; in smu10_send_msg_to_smc()
83 smu10_wait_for_response(hwmgr); in smu10_send_msg_to_smc()
[all …]
H A Dvegam_smumgr.c82 static int vegam_smu_init(struct pp_hwmgr *hwmgr) in vegam_smu_init() argument
90 hwmgr->smu_backend = smu_data; in vegam_smu_init()
92 if (smu7_init(hwmgr)) { in vegam_smu_init()
100 static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) in vegam_start_smu_in_protection_mode() argument
108 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
111 result = smu7_upload_smu_firmware_image(hwmgr); in vegam_start_smu_in_protection_mode()
116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); in vegam_start_smu_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in vegam_start_smu_in_protection_mode()
126 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); in vegam_start_smu_in_protection_mode()
[all …]
H A Dvega20_smumgr.c49 bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr) in vega20_is_smc_ram_running() argument
51 struct amdgpu_device *adev = hwmgr->adev; in vega20_is_smc_ram_running()
70 static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr) in vega20_wait_for_response() argument
72 struct amdgpu_device *adev = hwmgr->adev; in vega20_wait_for_response()
77 phm_wait_for_register_unequal(hwmgr, reg, in vega20_wait_for_response()
89 static int vega20_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, in vega20_send_msg_to_smc_without_waiting() argument
92 struct amdgpu_device *adev = hwmgr->adev; in vega20_send_msg_to_smc_without_waiting()
105 static int vega20_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) in vega20_send_msg_to_smc() argument
107 struct amdgpu_device *adev = hwmgr->adev; in vega20_send_msg_to_smc()
110 vega20_wait_for_response(hwmgr); in vega20_send_msg_to_smc()
[all …]
H A Dtonga_smumgr.c97 static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr) in tonga_start_in_protection_mode() argument
102 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
105 result = smu7_upload_smu_firmware_image(hwmgr); in tonga_start_in_protection_mode()
110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
114 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
129 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, in tonga_start_in_protection_mode()
135 smu7_send_msg_to_smc_offset(hwmgr); in tonga_start_in_protection_mode()
[all …]
H A Dvega10_smumgr.c38 static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, in vega10_copy_table_from_smc() argument
41 struct vega10_smumgr *priv = hwmgr->smu_backend; in vega10_copy_table_from_smc()
42 struct amdgpu_device *adev = hwmgr->adev; in vega10_copy_table_from_smc()
50 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_copy_table_from_smc()
54 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_copy_table_from_smc()
58 smum_send_msg_to_smc_with_parameter(hwmgr, in vega10_copy_table_from_smc()
71 static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, in vega10_copy_table_to_smc() argument
74 struct vega10_smumgr *priv = hwmgr->smu_backend; in vega10_copy_table_to_smc()
75 struct amdgpu_device *adev = hwmgr->adev; in vega10_copy_table_to_smc()
80 if (!hwmgr->not_vf) in vega10_copy_table_to_smc()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dpp_psm.c29 int psm_init_power_state_table(struct pp_hwmgr *hwmgr) in psm_init_power_state_table() argument
36 if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL) in psm_init_power_state_table()
39 if (hwmgr->hwmgr_func->get_power_state_size == NULL) in psm_init_power_state_table()
42 table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr); in psm_init_power_state_table()
44 size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) + in psm_init_power_state_table()
49 hwmgr->num_ps = 0; in psm_init_power_state_table()
50 hwmgr->ps_size = 0; in psm_init_power_state_table()
53 hwmgr->num_ps = table_entries; in psm_init_power_state_table()
54 hwmgr->ps_size = size; in psm_init_power_state_table()
56 hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL); in psm_init_power_state_table()
[all …]
H A Dvega12_thermal.c32 static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) in vega12_get_current_rpm() argument
34 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, in vega12_get_current_rpm()
43 int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, in vega12_fan_ctrl_get_fan_speed_info() argument
55 int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) in vega12_fan_ctrl_get_fan_speed_rpm() argument
59 return vega12_get_current_rpm(hwmgr, speed); in vega12_fan_ctrl_get_fan_speed_rpm()
68 static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega12_enable_fan_control_feature() argument
71 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_enable_fan_control_feature()
75 hwmgr, true, in vega12_enable_fan_control_feature()
86 static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr) in vega12_disable_fan_control_feature() argument
89 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); in vega12_disable_fan_control_feature()
[all …]
H A Dprocess_pptables_v1_0.c40 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap) in set_hw_cap() argument
43 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
45 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
55 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
69 hwmgr, in set_platform_caps()
75 hwmgr, in set_platform_caps()
81 hwmgr, in set_platform_caps()
87 hwmgr, in set_platform_caps()
93 hwmgr, in set_platform_caps()
99 hwmgr, in set_platform_caps()
[all …]
H A Dvega12_processpptables.c34 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, in set_hw_cap() argument
38 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
40 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
43 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) in get_powerplay_table() argument
49 const void *table_address = hwmgr->soft_pp_table; in get_powerplay_table()
53 smu_atom_get_data_table(hwmgr->adev, index, in get_powerplay_table()
56 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ in get_powerplay_table()
57 hwmgr->soft_pp_table_size = size; in get_powerplay_table()
64 struct pp_hwmgr *hwmgr, in check_powerplay_tables() argument
76 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
[all …]
H A Dvega10_processpptables.c37 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, in set_hw_cap() argument
41 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
43 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
46 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) in get_powerplay_table() argument
52 const void *table_address = hwmgr->soft_pp_table; in get_powerplay_table()
56 smu_atom_get_data_table(hwmgr->adev, index, in get_powerplay_table()
59 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ in get_powerplay_table()
60 hwmgr->soft_pp_table_size = size; in get_powerplay_table()
67 struct pp_hwmgr *hwmgr, in check_powerplay_tables() argument
88 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
[all …]
H A Dsmu7_thermal.h41 extern int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr);
42 extern int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
43 extern int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_…
44 extern int smu7_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t *speed);
45 extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
46 extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
47 extern int smu7_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr, uint32_t speed);
48 extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
49 extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
50 extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
[all …]
H A Dvega10_powertune.c749 static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_co… in vega10_program_didt_config_registers() argument
758 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); in vega10_program_didt_config_registers()
761 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); in vega10_program_didt_config_registers()
764 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); in vega10_program_didt_config_registers()
767 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); in vega10_program_didt_config_registers()
770 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); in vega10_program_didt_config_registers()
773 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); in vega10_program_didt_config_registers()
785 static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt… in vega10_program_gc_didt_config_registers() argument
790 data = cgs_read_register(hwmgr->device, config_regs->offset); in vega10_program_gc_didt_config_registers()
793 cgs_write_register(hwmgr->device, config_regs->offset, data); in vega10_program_gc_didt_config_registers()
[all …]
H A Dvega10_thermal.h53 extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
54 extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
55 extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
57 extern int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
59 extern int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
60 extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
62 extern int vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
64 extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
66 struct pp_hwmgr *hwmgr);
67 extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
[all …]
H A Dvega20_processpptables.c36 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, in set_hw_cap() argument
40 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
42 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); in set_hw_cap()
45 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) in get_powerplay_table() argument
51 const void *table_address = hwmgr->soft_pp_table; in get_powerplay_table()
55 smu_atom_get_data_table(hwmgr->adev, index, in get_powerplay_table()
58 hwmgr->soft_pp_table = table_address; in get_powerplay_table()
59 hwmgr->soft_pp_table_size = size; in get_powerplay_table()
66 struct pp_hwmgr *hwmgr, in check_powerplay_tables() argument
86 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) in set_platform_caps() argument
[all …]
H A Dvega20_powertune.c32 int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) in vega20_set_power_limit() argument
35 (struct vega20_hwmgr *)(hwmgr->backend); in vega20_set_power_limit()
38 return smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_set_power_limit()
45 int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr, in vega20_validate_power_level_request() argument
48 return (tdp_percentage_adjustment > hwmgr->platform_descriptor.TDPLimit) ? -1 : 0; in vega20_validate_power_level_request()
51 static int vega20_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, in vega20_set_overdrive_target_percentage() argument
54 return smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_set_overdrive_target_percentage()
59 int vega20_power_control_set_level(struct pp_hwmgr *hwmgr) in vega20_power_control_set_level() argument
65 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? in vega20_power_control_set_level()
66 hwmgr->platform_descriptor.TDPAdjustment : in vega20_power_control_set_level()
[all …]
H A Dvega20_baco.c39 int vega20_get_bamaco_support(struct pp_hwmgr *hwmgr) in vega20_get_bamaco_support() argument
41 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); in vega20_get_bamaco_support()
44 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) in vega20_get_bamaco_support()
57 int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) in vega20_baco_get_state() argument
59 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); in vega20_baco_get_state()
72 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) in vega20_baco_set_state() argument
74 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); in vega20_baco_set_state()
79 vega20_baco_get_state(hwmgr, &cur_state); in vega20_baco_set_state()
91 if (smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_baco_set_state()
95 if (smum_send_msg_to_smc_with_parameter(hwmgr, in vega20_baco_set_state()
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmumgr.h84 extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
86 extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
88 extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp);
90 extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
94 extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
96 extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
97 extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
98 extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
99 extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
100 extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
[all …]

123