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Searched refs:hw_cap (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2_dma.c366 u32 hw_cap; in dwxgmac2_get_hw_feature() local
371 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); in dwxgmac2_get_hw_feature()
372 dma_cap->edma = (hw_cap & XGMAC_HWFEAT_EDMA) >> 31; in dwxgmac2_get_hw_feature()
373 dma_cap->ediffc = (hw_cap & XGMAC_HWFEAT_EDIFFC) >> 30; in dwxgmac2_get_hw_feature()
374 dma_cap->vxn = (hw_cap & XGMAC_HWFEAT_VXN) >> 29; in dwxgmac2_get_hw_feature()
375 dma_cap->vlins = (hw_cap & XGMAC_HWFEAT_SAVLANINS) >> 27; in dwxgmac2_get_hw_feature()
376 dma_cap->tssrc = (hw_cap & XGMAC_HWFEAT_TSSTSSEL) >> 25; in dwxgmac2_get_hw_feature()
377 dma_cap->actphyif = FIELD_GET(XGMAC_HWFEAT_PHYSEL, hw_cap); in dwxgmac2_get_hw_feature()
378 dma_cap->multi_addr = (hw_cap & XGMAC_HWFEAT_ADDMACADRSEL) >> 18; in dwxgmac2_get_hw_feature()
379 dma_cap->rx_coe = (hw_cap & XGMAC_HWFEAT_RXCOESEL) >> 16; in dwxgmac2_get_hw_feature()
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H A Ddwmac4_dma.c383 u32 hw_cap = readl(ioaddr + GMAC_HW_FEATURE0); in dwmac4_get_hw_feature() local
386 dma_cap->mbps_10_100 = (hw_cap & GMAC_HW_FEAT_MIISEL); in dwmac4_get_hw_feature()
387 dma_cap->mbps_1000 = (hw_cap & GMAC_HW_FEAT_GMIISEL) >> 1; in dwmac4_get_hw_feature()
388 dma_cap->half_duplex = (hw_cap & GMAC_HW_FEAT_HDSEL) >> 2; in dwmac4_get_hw_feature()
389 dma_cap->vlhash = (hw_cap & GMAC_HW_FEAT_VLHASH) >> 4; in dwmac4_get_hw_feature()
390 dma_cap->multi_addr = (hw_cap & GMAC_HW_FEAT_ADDMAC) >> 18; in dwmac4_get_hw_feature()
391 dma_cap->pcs = (hw_cap & GMAC_HW_FEAT_PCSSEL) >> 3; in dwmac4_get_hw_feature()
392 dma_cap->sma_mdio = (hw_cap & GMAC_HW_FEAT_SMASEL) >> 5; in dwmac4_get_hw_feature()
393 dma_cap->pmt_remote_wake_up = (hw_cap & GMAC_HW_FEAT_RWKSEL) >> 6; in dwmac4_get_hw_feature()
394 dma_cap->pmt_magic_frame = (hw_cap & GMAC_HW_FEAT_MGKSEL) >> 7; in dwmac4_get_hw_feature()
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/linux/drivers/net/wireless/realtek/rtw88/
H A Defuse.h15 #define GET_EFUSE_HW_CAP_HCI(hw_cap) \ argument
16 le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(3, 0))
17 #define GET_EFUSE_HW_CAP_BW(hw_cap) \ argument
18 le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(18, 16))
19 #define GET_EFUSE_HW_CAP_NSS(hw_cap) \ argument
20 le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(20, 19))
21 #define GET_EFUSE_HW_CAP_ANT_NUM(hw_cap) \ argument
22 le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(23, 21))
23 #define GET_EFUSE_HW_CAP_PTCL(hw_cap) \ argument
24 le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(27, 26))
H A Drtw88xxa.c132 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | in rtw88xxa_read_usb_type()
135 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT; in rtw88xxa_read_usb_type()
138 efuse->hw_cap.nss = 1; in rtw88xxa_read_usb_type()
140 efuse->hw_cap.nss = 2; in rtw88xxa_read_usb_type()
167 efuse->hw_cap.nss = 1; in rtw88xxa_read_usb_type()
175 efuse->hw_cap.nss = 2; in rtw88xxa_read_usb_type()
188 efuse->hw_cap.ptcl = 1; in rtw88xxa_read_usb_type()
189 efuse->hw_cap.bw &= ~BIT(RTW_CHANNEL_WIDTH_80); in rtw88xxa_read_usb_type()
196 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, in rtw88xxa_read_usb_type()
197 efuse->hw_cap.ant_num, efuse->hw_cap.nss); in rtw88xxa_read_usb_type()
H A Drtw8814a.c113 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | in rtw8814a_init_hwcap()
116 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT; in rtw8814a_init_hwcap()
119 efuse->hw_cap.nss = 3; in rtw8814a_init_hwcap()
121 efuse->hw_cap.nss = 2; in rtw8814a_init_hwcap()
125 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, in rtw8814a_init_hwcap()
126 efuse->hw_cap.ant_num, efuse->hw_cap.nss); in rtw8814a_init_hwcap()
H A Dtx.c133 if (efuse->hw_cap.nss == 1) { in get_highest_vht_tx_rate()
146 } else if (efuse->hw_cap.nss >= 2) { in get_highest_vht_tx_rate()
H A Ddebug.c697 u8 nss = rtwdev->efuse.hw_cap.nss; in rtw_debugfs_get_tx_pwr_tbl()
828 for (ss = 0; ss < efuse->hw_cap.nss; ss++) { in rtw_debugfs_get_phy_info()
842 for (ss = 0; ss < efuse->hw_cap.nss; ss++) { in rtw_debugfs_get_phy_info()
H A Dregd.c287 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_80)) in rtw_regd_apply_hw_cap_flags()
H A Dmain.h1840 } hw_cap; member
/linux/drivers/net/ethernet/hisilicon/
H A Dhix5hd2_gmac.c196 #define HAS_CAP_TSO(hw_cap) ((hw_cap) & HW_CAP_TSO) argument
261 unsigned long hw_cap; member
684 static u32 hix5hd2_get_desc_cmd(struct sk_buff *skb, unsigned long hw_cap) in hix5hd2_get_desc_cmd() argument
688 if (HAS_CAP_TSO(hw_cap)) { in hix5hd2_get_desc_cmd()
756 cmd = hix5hd2_get_desc_cmd(skb, priv->hw_cap); in hix5hd2_net_xmit()
1113 priv->hw_cap = (unsigned long)device_get_match_data(dev); in hix5hd2_dev_probe()
1230 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_probe()
1242 if (HAS_CAP_TSO(priv->hw_cap)) { in hix5hd2_dev_probe()
1260 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_probe()
1289 if (HAS_CAP_TSO(priv->hw_cap)) in hix5hd2_dev_remove()
/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c129 if (priv->hw_cap.eee) { in sxgbe_eee_init()
703 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) in sxgbe_mtl_operation_mode()
709 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) in sxgbe_mtl_operation_mode()
715 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num) in sxgbe_mtl_operation_mode()
719 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num) in sxgbe_mtl_operation_mode()
873 struct sxgbe_hw_features *features = &priv->hw_cap; in sxgbe_get_hw_features()
985 priv->hw_cap.tx_mtl_qsize); in sxgbe_init_mtl_engine()
2028 if (priv->hw_cap.tx_csum_offload) in sxgbe_hw_init()
2031 if (priv->hw_cap.rx_csum_offload) in sxgbe_hw_init()
2126 if (priv->hw_cap.tcpseg_offload) { in sxgbe_drv_probe()
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H A Dsxgbe_common.h484 struct sxgbe_hw_features hw_cap; member
H A Dsxgbe_ethtool.c140 if (!priv->hw_cap.eee) in sxgbe_get_eee()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu.h415 struct hw_cap { struct
461 struct hw_cap cap;
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c6093 u32 hw_cap; in gaudi2_is_hmmu_enabled() local
6095 hw_cap = HW_CAP_DCORE0_DMMU0 << (NUM_OF_HMMU_PER_DCORE * dcore_id + hmmu_id); in gaudi2_is_hmmu_enabled()
6097 if (gaudi2->hw_cap_initialized & hw_cap) in gaudi2_is_hmmu_enabled()
6405 u32 offset, mmu_base, stlb_base, hw_cap; in gaudi2_dcore_hmmu_init() local
6410 hw_cap = HW_CAP_DCORE0_DMMU0 << dmmu_seq; in gaudi2_dcore_hmmu_init()
6416 if ((gaudi2->hw_cap_initialized & hw_cap) || !(prop->hmmu_hif_enabled_mask & BIT(dmmu_seq))) in gaudi2_dcore_hmmu_init()
6447 gaudi2->hw_cap_initialized |= hw_cap; in gaudi2_dcore_hmmu_init()