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Searched refs:hubp (Results 1 – 25 of 38) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dhubp.h101 struct hubp { struct
141 struct hubp *hubp,
148 struct hubp *hubp,
152 void (*dcc_control)(struct hubp *hubp, bool enable,
156 struct hubp *hubp,
161 struct hubp *hubp,
166 struct hubp *hubp,
172 struct hubp *hubp,
176 struct hubp *hubp,
180 struct hubp *hubp,
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.h31 #define TO_DCN20_HUBP(hubp)\ argument
32 container_of(hubp, struct dcn20_hubp, base)
300 struct hubp base;
316 struct hubp *hubp,
320 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
324 struct hubp *hubp,
327 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
335 struct hubp *hubp,
339 struct hubp *hubp,
343 bool hubp2_dmdata_status_done(struct hubp *hubp);
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H A Ddcn20_hubp.c47 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, in hubp2_set_vm_system_aperture_settings() argument
50 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_set_vm_system_aperture_settings()
82 struct hubp *hubp, in hubp2_program_deadline() argument
86 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_program_deadline()
172 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, in hubp2_vready_at_or_After_vsync() argument
176 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_vready_at_or_After_vsync()
197 static void hubp2_program_requestor(struct hubp *hubp, in hubp2_program_requestor() argument
200 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_program_requestor()
230 struct hubp *hubp, in hubp2_setup() argument
240 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); in hubp2_setup()
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c43 static void hubp401_program_3dlut_fl_addr(struct hubp *hubp, in hubp401_program_3dlut_fl_addr() argument
46 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp401_program_3dlut_fl_addr()
52 static void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) in hubp401_program_3dlut_fl_dlg_param() argument
54 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp401_program_3dlut_fl_dlg_param()
59 static void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable) in hubp401_enable_3dlut_fl() argument
61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp401_enable_3dlut_fl()
66 int hubp401_get_3dlut_fl_done(struct hubp *hubp) in hubp401_get_3dlut_fl_done() argument
68 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp401_get_3dlut_fl_done()
75 static void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressi… in hubp401_program_3dlut_fl_addressing_mode() argument
77 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp401_program_3dlut_fl_addressing_mode()
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H A Ddcn401_hubp.h257 void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
259 void hubp401_vready_at_or_After_vsync(struct hubp *hubp,
263 struct hubp *hubp,
267 struct hubp *hubp,
272 struct hubp *hubp,
279 struct hubp *hubp,
284 struct hubp *hubp,
288 void hubp401_dcc_control(struct hubp *hubp,
297 struct hubp *hubp,
303 struct hubp *hubp,
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c41 void hubp1_set_blank(struct hubp *hubp, bool blank) in hubp1_set_blank() argument
43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_set_blank()
65 hubp->mpcc_id = 0xf; in hubp1_set_blank()
66 hubp->opp_id = OPP_ID_INVALID; in hubp1_set_blank()
70 static void hubp1_disconnect(struct hubp *hubp) in hubp1_disconnect() argument
72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_disconnect()
81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) in hubp1_disable_control() argument
83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_disable_control()
90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) in hubp1_get_underflow_status() argument
93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_get_underflow_status()
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H A Ddcn10_hubp.h30 #define TO_DCN10_HUBP(hubp)\ argument
31 container_of(hubp, struct dcn10_hubp, base)
699 struct hubp base;
707 struct hubp *hubp,
717 struct hubp *hubp,
722 struct hubp *hubp,
726 struct hubp *hubp,
730 struct hubp *hubp,
736 struct hubp *hubp,
741 struct hubp *hubp,
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn32/
H A Ddcn32_hubp.c42 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow) in hubp32_update_force_pstate_disallow() argument
44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_update_force_pstate_disallow()
50 void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow) in hubp32_update_force_cursor_pstate_disallow() argument
52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_update_force_cursor_pstate_disallow()
59 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) in hubp32_update_mall_sel() argument
61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_update_mall_sel()
68 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable) in hubp32_prepare_subvp_buffering() argument
70 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_prepare_subvp_buffering()
86 void hubp32_phantom_hubp_post_enable(struct hubp *hubp) in hubp32_phantom_hubp_post_enable() argument
89 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_phantom_hubp_post_enable()
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H A Ddcn32_hubp.h47 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
49 void hubp32_update_force_cursor_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
51 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
53 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
55 void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
57 void hubp32_cursor_set_attributes(struct hubp *hubp,
60 void hubp32_init(struct hubp *hubp);
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c45 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, in hubp3_set_vm_system_aperture_settings() argument
48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_set_vm_system_aperture_settings()
69 struct hubp *hubp, in hubp3_program_surface_flip_and_addr() argument
73 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_program_surface_flip_and_addr()
314 hubp->request_address = *address; in hubp3_program_surface_flip_and_addr()
337 void hubp3_dcc_control(struct hubp *hubp, bool enable, in hubp3_dcc_control() argument
341 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_dcc_control()
350 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp, in hubp3_dcc_control_sienna_cichlid() argument
353 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_dcc_control_sienna_cichlid()
365 struct hubp *hubp, in hubp3_dmdata_set_attributes() argument
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H A Ddcn30_hubp.h256 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
260 struct hubp *hubp,
265 struct hubp *hubp,
275 struct hubp *hubp,
286 void hubp3_dcc_control(struct hubp *hubp, bool enable,
289 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
293 struct hubp *hubp,
296 void hubp3_read_state(struct hubp *hubp);
298 void hubp3_init(struct hubp *hubp);
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c43 struct hubp *hubp, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
55 hubp1_program_pixel_format(hubp, format); in hubp201_program_surface_config()
59 struct hubp *hubp, in hubp201_program_deadline() argument
63 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); in hubp201_program_deadline()
66 static void hubp201_program_requestor(struct hubp *hubp, in hubp201_program_requestor() argument
69 struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp); in hubp201_program_requestor()
97 struct hubp *hubp, in hubp201_setup() argument
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H A Ddcn201_hubp.h32 #define TO_DCN201_HUBP(hubp)\ argument
33 container_of(hubp, struct dcn201_hubp, base)
117 struct hubp base;
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn35/
H A Ddcn35_hubp.c41 void hubp35_set_fgcg(struct hubp *hubp, bool enable) in hubp35_set_fgcg() argument
43 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp35_set_fgcg()
48 static void hubp35_init(struct hubp *hubp) in hubp35_init() argument
50 hubp3_init(hubp); in hubp35_init()
52 hubp35_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub); in hubp35_init()
58 struct hubp *hubp, in hubp35_program_pixel_format() argument
61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp35_program_pixel_format()
173 struct hubp *hubp, in hubp35_program_surface_config() argument
182 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp35_program_surface_config()
184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp35_program_surface_config()
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H A Ddcn35_hubp.h59 void hubp35_set_fgcg(struct hubp *hubp, bool enable);
62 struct hubp *hubp,
66 struct hubp *hubp,
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn31/
H A Ddcn31_hubp.c42 void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable) in hubp31_set_unbounded_requesting() argument
44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_set_unbounded_requesting()
50 void hubp31_soft_reset(struct hubp *hubp, bool reset) in hubp31_soft_reset() argument
52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_soft_reset()
57 static void hubp31_program_extended_blank(struct hubp *hubp, in hubp31_program_extended_blank() argument
60 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_program_extended_blank()
66 struct hubp *hubp, unsigned int min_dst_y_next_start_optimized) in hubp31_program_extended_blank_value() argument
68 hubp31_program_extended_blank(hubp, min_dst_y_next_start_optimized); in hubp31_program_extended_blank_value()
H A Ddcn31_hubp.h242 void hubp31_soft_reset(struct hubp *hubp, bool reset);
244 void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
247 struct hubp *hubp, unsigned int min_dst_y_next_start_optimized);
/linux/drivers/gpu/drm/amd/display/dc/hubp/
H A DMakefile31 AMD_DAL_HUBP_DCN10 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn10/,$(HUBP_DCN10))
38 AMD_DAL_HUBP_DCN20 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn20/,$(HUBP_DCN20))
46 AMD_DAL_HUBP_DCN201 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn201/,$(HUBP_DCN201))
54 AMD_DAL_HUBP_DCN21 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn21/,$(HUBP_DCN21))
61 AMD_DAL_HUBP_DCN30 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn30/,$(HUBP_DCN30))
69 AMD_DAL_HUBP_DCN31 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn31/,$(HUBP_DCN31))
77 AMD_DAL_HUBP_DCN32 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn32/,$(HUBP_DCN32))
85 AMD_DAL_HUBP_DCN35 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn35/,$(HUBP_DCN35))
93 AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401))
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c149 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
150 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
307 struct hubp *hubp = res_pool->hubps[i]; in dcn201_init_hw() local
313 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
316 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
317 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw()
318 hubp->power_gated = false; in dcn201_init_hw()
321 hubp->funcs->hubp_init(hubp); in dcn201_init_hw()
346 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
380 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect() local
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/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c80 struct hubp *hubp, in apply_DEDCN21_142_wa_for_hostvm_deadline() argument
83 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); in apply_DEDCN21_142_wa_for_hostvm_deadline()
130 struct hubp *hubp, in hubp21_program_deadline() argument
134 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); in hubp21_program_deadline()
136 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); in hubp21_program_deadline()
140 struct hubp *hubp, in hubp21_program_requestor() argument
143 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); in hubp21_program_requestor()
172 struct hubp *hubp, in hubp21_setup() argument
182 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); in hubp21_setup()
183 hubp21_program_requestor(hubp, rq_regs); in hubp21_setup()
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H A Ddcn21_hubp.h32 #define TO_DCN21_HUBP(hubp)\ argument
33 container_of(hubp, struct dcn21_hubp, base)
106 struct hubp base;
123 struct hubp *hubp,
127 struct hubp *hubp,
132 struct hubp *hubp,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c181 struct hubp *hubp = pool->hubps[i]; in dcn10_log_hubp_states() local
182 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); in dcn10_log_hubp_states()
184 hubp->funcs->hubp_read_state(hubp); in dcn10_log_hubp_states()
188 hubp->inst, in dcn10_log_hubp_states()
598 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur() local
606 if (hubp->funcs->hubp_get_underflow_status(hubp)) { in dcn10_did_underflow_occur()
607 hubp->funcs->hubp_clear_underflow(hubp); in dcn10_did_underflow_occur()
819 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa() local
824 hubp->funcs->set_blank(hubp, true); in undo_DEGVIDCN10_253_wa()
839 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa() local
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c738 struct hubp *hubp = dc->res_pool->hubps[i]; in dcn35_init_pipes() local
744 if (hubbub && hubp) { in dcn35_init_pipes()
746 hubbub->funcs->program_det_size(hubbub, hubp->inst, 0); in dcn35_init_pipes()
748 hubbub->funcs->program_det_segments(hubbub, hubp->inst, 0); in dcn35_init_pipes()
766 struct hubp *hubp = dc->res_pool->hubps[i]; in dcn35_init_pipes() local
783 hubp->power_gated = true; in dcn35_init_pipes()
796 pipe_ctx->plane_res.hubp = hubp; in dcn35_init_pipes()
799 hubp->mpcc_id = dpp->inst; in dcn35_init_pipes()
800 hubp->opp_id = OPP_ID_INVALID; in dcn35_init_pipes()
801 hubp->power_gated = false; in dcn35_init_pipes()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c413 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
418 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
835 …>pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
837 …ipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst; in populate_subvp_cmd_pipe_info()
1063 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0() local
1066 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, in dc_build_cursor_update_payload0()
1073 payload->cursor_rect.x = hubp->cur_rect.x; in dc_build_cursor_update_payload0()
1074 payload->cursor_rect.y = hubp->cur_rect.y; in dc_build_cursor_update_payload0()
1076 payload->cursor_rect.width = hubp->cur_rect.w; in dc_build_cursor_update_payload0()
1077 payload->cursor_rect.height = hubp->cur_rect.h; in dc_build_cursor_update_payload0()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer_private.h65 struct hubp;
113 struct hubp *hubp);

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