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Searched refs:gvt (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A DMakefile4 gvt/aperture_gm.o \
5 gvt/cfg_space.o \
6 gvt/cmd_parser.o \
7 gvt/debugfs.o \
8 gvt/display.o \
9 gvt/dmabuf.o \
10 gvt/edid.o \
11 gvt/execlist.o \
12 gvt/fb_decoder.o \
13 gvt/firmware.o \
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H A Dsched_policy.c43 for_each_engine(engine, vgpu->gvt->gt, i) { in vgpu_has_pending_workload()
69 struct intel_gvt *gvt; member
81 if (!vgpu || vgpu == vgpu->gvt->idle_vgpu) in vgpu_update_timeslice()
133 static void try_to_schedule_next_vgpu(struct intel_gvt *gvt) in try_to_schedule_next_vgpu() argument
135 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in try_to_schedule_next_vgpu()
156 for_each_engine(engine, gvt->gt, i) { in try_to_schedule_next_vgpu()
173 for_each_engine(engine, gvt->gt, i) in try_to_schedule_next_vgpu()
214 struct intel_gvt *gvt = sched_data->gvt; in tbs_sched_func() local
215 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler; in tbs_sched_func()
234 scheduler->next_vgpu = gvt->idle_vgpu; in tbs_sched_func()
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H A Dvgpu.c45 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in populate_pvinfo_page()
109 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) in intel_gvt_init_vgpu_types() argument
111 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
112 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
116 gvt->types = kzalloc_objs(struct intel_vgpu_type, num_types); in intel_gvt_init_vgpu_types()
117 if (!gvt->types) in intel_gvt_init_vgpu_types()
120 gvt->mdev_types = kzalloc_objs(*gvt->mdev_types, num_types); in intel_gvt_init_vgpu_types()
121 if (!gvt->mdev_types) in intel_gvt_init_vgpu_types()
132 sprintf(gvt->types[i].name, "GVTg_V%u_%s", in intel_gvt_init_vgpu_types()
133 GRAPHICS_VER(gvt->gt->i915) == 8 ? 4 : 5, conf->name); in intel_gvt_init_vgpu_types()
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H A Ddebugfs.c60 static inline int mmio_diff_handler(struct intel_gvt *gvt, in mmio_diff_handler() argument
67 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset)); in mmio_diff_handler()
89 struct intel_gvt *gvt = vgpu->gvt; in vgpu_mmio_diff_show() local
100 mutex_lock(&gvt->lock); in vgpu_mmio_diff_show()
101 spin_lock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
103 wakeref = mmio_hw_access_pre(gvt->gt); in vgpu_mmio_diff_show()
105 intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, &param); in vgpu_mmio_diff_show()
106 mmio_hw_access_post(gvt->gt, wakeref); in vgpu_mmio_diff_show()
108 spin_unlock_bh(&gvt->scheduler.mmio_context_lock); in vgpu_mmio_diff_show()
109 mutex_unlock(&gvt->lock); in vgpu_mmio_diff_show()
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H A Dkvmgt.c181 struct device *dev = vgpu->gvt->gt->i915->drm.dev; in gvt_dma_map_page()
204 struct device *dev = vgpu->gvt->gt->i915->drm.dev; in gvt_dma_unmap_page()
648 mutex_lock(&vgpu->gvt->lock); in __kvmgt_vgpu_exist()
649 for_each_active_vgpu(vgpu->gvt, itr, id) { in __kvmgt_vgpu_exist()
659 mutex_unlock(&vgpu->gvt->lock); in __kvmgt_vgpu_exist()
784 aperture_va = io_mapping_map_wc(&vgpu->gvt->gt->ggtt->iomap, in intel_vgpu_aperture_rw()
851 struct intel_gvt *gvt = vgpu->gvt; in gtt_entry() local
861 return (offset >= gvt->device_info.gtt_start_offset && in gtt_entry()
862 offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ? in gtt_entry()
1047 pgoff = (gvt_aperture_pa_base(vgpu->gvt) >> PAGE_SHIFT) + pgoff; in intel_vgpu_mmap()
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H A Dgtt.c245 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_get_entry64()
258 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index); in gtt_get_entry64()
270 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info; in gtt_set_entry64()
283 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64); in gtt_set_entry64()
493 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in _ppgtt_get_root_entry()
520 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in _ppgtt_set_root_entry()
536 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in ggtt_get_guest_entry()
548 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in ggtt_set_guest_entry()
559 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in ggtt_get_host_entry()
569 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops; in ggtt_set_host_entry()
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H A Dsched_policy.h41 int (*init)(struct intel_gvt *gvt);
42 void (*clean)(struct intel_gvt *gvt);
49 void intel_gvt_schedule(struct intel_gvt *gvt);
51 int intel_gvt_init_sched_policy(struct intel_gvt *gvt);
53 void intel_gvt_clean_sched_policy(struct intel_gvt *gvt);
63 void intel_gvt_kick_schedule(struct intel_gvt *gvt);
H A Dhandlers.c82 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt) in intel_gvt_get_device_type() argument
84 struct drm_i915_private *i915 = gvt->gt->i915; in intel_gvt_get_device_type()
100 static bool intel_gvt_match_device(struct intel_gvt *gvt, in intel_gvt_match_device() argument
103 return intel_gvt_get_device_type(gvt) & device; in intel_gvt_match_device()
118 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, in intel_gvt_find_mmio_info() argument
123 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) { in intel_gvt_find_mmio_info()
130 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size, in setup_mmio_info() argument
137 if (!intel_gvt_match_device(gvt, device)) in setup_mmio_info()
147 p = intel_gvt_find_mmio_info(gvt, i); in setup_mmio_info()
154 gvt->mmio.mmio_attribute[i / 4] = flags; in setup_mmio_info()
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H A Dcmd_parser.c526 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
672 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode, in find_cmd_entry() argument
677 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) { in find_cmd_entry()
686 get_cmd_info(struct intel_gvt *gvt, u32 cmd, in get_cmd_info() argument
695 return find_cmd_entry(gvt, opcode, engine); in get_cmd_info()
902 struct intel_gvt *gvt = vgpu->gvt; in cmd_reg_handler() local
906 if (offset + 4 > gvt->device_info.mmio_size) { in cmd_reg_handler()
915 intel_gvt_mmio_set_cmd_accessible(gvt, offset); in cmd_reg_handler()
916 mmio_info = intel_gvt_find_mmio_info(gvt, offset); in cmd_reg_handler()
918 intel_gvt_mmio_set_cmd_write_patch(gvt, offset); in cmd_reg_handler()
[all …]
H A Dcmd_parser.h46 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt);
48 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt);
H A Ddisplay.c75 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in edp_pipe_is_enabled()
88 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in pipe_is_enabled()
189 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_monitor_status_change()
549 intel_gvt_request_service(vgpu->gvt, in vblank_timer_fn()
558 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in setup_virtual_dp_monitor()
640 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in emulate_vblank_on_pipe()
670 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_vblank()
690 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in intel_vgpu_emulate_hotplug()
779 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_clean_display()
805 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; in intel_vgpu_init_display()
H A Dgtt.h223 int intel_gvt_init_gtt(struct intel_gvt *gvt);
224 void intel_gvt_clean_gtt(struct intel_gvt *gvt);
291 void intel_gvt_restore_ggtt(struct intel_gvt *gvt);
H A Dscheduler.h139 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
141 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
H A Dinterrupt.h193 int intel_gvt_init_irq(struct intel_gvt *gvt);
H A Ddmabuf.c406 struct drm_device *dev = &vgpu->gvt->gt->i915->drm; in intel_vgpu_query_plane()
503 struct drm_device *dev = &vgpu->gvt->gt->i915->drm; in intel_vgpu_get_dmabuf()
/linux/
H A DMAINTAINERS12857 W: https://github.com/intel/gvt-linux/wiki
12858 F: drivers/gpu/drm/i915/gvt/