Home
last modified time | relevance | path

Searched refs:gpu_write64 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da8xx_gpu.c522 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); in hw_init()
531 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, gmem_range_min); in hw_init()
532 gpu_write64(gpu, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, gmem_range_min); in hw_init()
535 gpu_write64(gpu, REG_A8XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); in hw_init()
536 gpu_write64(gpu, REG_A8XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); in hw_init()
537 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_TRAP_BASE, adreno_gpu->uche_trap_base); in hw_init()
538 gpu_write64(gpu, REG_A8XX_UCHE_CCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); in hw_init()
625 gpu_write64(gpu, REG_A8XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); in hw_init()
627 gpu_write64(gpu, REG_A8XX_CP_AQE_INSTR_BASE_0, a6xx_gpu->aqe_iova); in hw_init()
630 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
[all …]
H A Da6xx_gpu.c1288 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE, 0x00000000); in hw_init()
1339 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); in hw_init()
1340 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); in hw_init()
1342 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX, adreno_gpu->uche_trap_base + 0xfc0); in hw_init()
1343 gpu_write64(gpu, REG_A6XX_UCHE_TRAP_BASE, adreno_gpu->uche_trap_base); in hw_init()
1344 gpu_write64(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE, adreno_gpu->uche_trap_base); in hw_init()
1353 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, gmem_range_min); in hw_init()
1355 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, in hw_init()
1509 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE, a6xx_gpu->sqe_iova); in hw_init()
1512 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, gpu->rb[0]->iova); in hw_init()
[all …]
H A Da5xx_preempt.c153 gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO, in a5xx_preempt_trigger()
240 gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO, 0); in a5xx_preempt_hw_init()
H A Da5xx_gpu.c896 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000); in a5xx_hw_init()
930 gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, a5xx_gpu->pm4_iova); in a5xx_hw_init()
931 gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, a5xx_gpu->pfp_iova); in a5xx_hw_init()
934 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
947 gpu_write64(gpu, REG_A5XX_CP_RB_RPTR_ADDR, in a5xx_hw_init()
1477 gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova); in a5xx_crashdumper_run()
H A Da6xx_preempt.c227 gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0); in a6xx_preempt_hw_init()
H A Da6xx_gpu_state.c161 gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova); in a6xx_crashdumper_run()
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_gpu.c188 gpu_write64(ptdev, pwroff_reg, mask); in panthor_gpu_block_power_off()
231 gpu_write64(ptdev, pwron_reg, mask); in panthor_gpu_block_power_on()
H A Dpanthor_mmu.c555 gpu_write64(ptdev, AS_LOCKADDR(as_nr), region); in lock_region()
632 gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab); in panthor_mmu_as_enable()
633 gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr); in panthor_mmu_as_enable()
634 gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg); in panthor_mmu_as_enable()
647 gpu_write64(ptdev, AS_TRANSTAB(as_nr), 0); in panthor_mmu_as_disable()
648 gpu_write64(ptdev, AS_MEMATTR(as_nr), 0); in panthor_mmu_as_disable()
649 gpu_write64(ptdev, AS_TRANSCFG(as_nr), AS_TRANSCFG_ADRMODE_UNMAPPED); in panthor_mmu_as_disable()
H A Dpanthor_device.h492 static inline void gpu_write64(struct panthor_device *ptdev, u32 reg, u64 data) in gpu_write64() function
H A Dpanthor_pwr.c77 gpu_write64(ptdev, PWR_CMDARG, args); in panthor_pwr_write_command()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h639 static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val) in gpu_write64() function